Subversion Repositories openrisc

/* Print i386 instructions for GDB, the GNU debugger.

   Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,

   2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)

   July 1988

    modified by John Hassey (hassey@dg-rtp.dg.com)

    x86-64 support added by Jan Hubicka (jh@suse.cz)

    VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */

/* The main tables describing the instructions is essentially a copy

   of the "Opcode Map" chapter (Appendix A) of the Intel 80386

   Programmers Manual.  Usually, there is a capital letter, followed

   by a small letter.  The capital letter tell the addressing mode,

   and the small letter tells about the operand size.  Refer to

   the Intel manual for details.  */

#include "sysdep.h"

#include "dis-asm.h"

#include "opintl.h"

#include "opcode/i386.h"

#include "libiberty.h"

#include <setjmp.h>

static int fetch_data (struct disassemble_info *, bfd_byte *);

static void ckprefix (void);

static const char *prefix_name (int, int);

static int print_insn (bfd_vma, disassemble_info *);

static void dofloat (int);

static void OP_ST (int, int);

static void OP_STi (int, int);

static int putop (const char *, int);

static void oappend (const char *);

static void append_seg (void);

static void OP_indirE (int, int);

static void print_operand_value (char *, int, bfd_vma);

static void OP_E_register (int, int);

static void OP_E_memory (int, int, int);

static void OP_E_extended (int, int, int);

static void print_displacement (char *, bfd_vma);

static void OP_E (int, int);

static void OP_G (int, int);

static bfd_vma get64 (void);

static bfd_signed_vma get32 (void);

static bfd_signed_vma get32s (void);

static int get16 (void);

static void set_op (bfd_vma, int);

static void OP_Skip_MODRM (int, int);

static void OP_REG (int, int);

static void OP_IMREG (int, int);

static void OP_I (int, int);

static void OP_I64 (int, int);

static void OP_sI (int, int);

static void OP_J (int, int);

static void OP_SEG (int, int);

static void OP_DIR (int, int);

static void OP_OFF (int, int);

static void OP_OFF64 (int, int);

static void ptr_reg (int, int);

static void OP_ESreg (int, int);

static void OP_DSreg (int, int);

static void OP_C (int, int);

static void OP_D (int, int);

static void OP_T (int, int);

static void OP_R (int, int);

static void OP_MMX (int, int);

static void OP_XMM (int, int);

static void OP_EM (int, int);

static void OP_EX (int, int);

static void OP_EMC (int,int);

static void OP_MXC (int,int);

static void OP_MS (int, int);

static void OP_XS (int, int);

static void OP_M (int, int);

static void OP_VEX (int, int);

static void OP_VEX_FMA (int, int);

static void OP_EX_Vex (int, int);

static void OP_EX_VexW (int, int);

static void OP_EX_VexImmW (int, int);

static void OP_XMM_Vex (int, int);

static void OP_XMM_VexW (int, int);

static void OP_REG_VexI4 (int, int);

static void PCLMUL_Fixup (int, int);

static void VEXI4_Fixup (int, int);

static void VZERO_Fixup (int, int);

static void VCMP_Fixup (int, int);

static void VPERMIL2_Fixup (int, int);

static void OP_0f07 (int, int);

static void OP_Monitor (int, int);

static void OP_Mwait (int, int);

static void NOP_Fixup1 (int, int);

static void NOP_Fixup2 (int, int);

static void OP_3DNowSuffix (int, int);

static void CMP_Fixup (int, int);

static void BadOp (void);

static void REP_Fixup (int, int);

static void CMPXCHG8B_Fixup (int, int);

static void XMM_Fixup (int, int);

static void CRC32_Fixup (int, int);

static void print_drex_arg (unsigned int, int, int);

static void OP_DREX4 (int, int);

static void OP_DREX3 (int, int);

static void OP_DREX_ICMP (int, int);

static void OP_DREX_FCMP (int, int);

static void MOVBE_Fixup (int, int);

struct dis_private {

  /* Points to first byte not fetched.  */

  bfd_byte *max_fetched;

  bfd_byte the_buffer[MAX_MNEM_SIZE];

  bfd_vma insn_start;

  int orig_sizeflag;

  jmp_buf bailout;

};

enum address_mode

{

  mode_16bit,

  mode_32bit,

  mode_64bit

};

enum address_mode address_mode;

/* Flags for the prefixes for the current instruction.  See below.  */

static int prefixes;

/* REX prefix the current instruction.  See below.  */

static int rex;

/* Bits of REX we've already used.  */

static int rex_used;

/* Original REX prefix.  */

static int rex_original;

/* REX bits in original REX prefix ignored.  It may not be the same

   as rex_original since some bits may not be ignored.  */

static int rex_ignored;

/* Mark parts used in the REX prefix.  When we are testing for

   empty prefix (for 8bit register REX extension), just mask it

   out.  Otherwise test for REX bit is excuse for existence of REX

   only in case value is nonzero.  */

#define USED_REX(value)                                 \

  {                                                     \

    if (value)                                          \

      {                                                 \

        if ((rex & value))                              \

          rex_used |= (value) | REX_OPCODE;             \

      }                                                 \

    else                                                \

      rex_used |= REX_OPCODE;                           \

  }

/* Special 'registers' for DREX handling */

#define DREX_REG_UNKNOWN        1000    /* not initialized */

#define DREX_REG_MEMORY         1001    /* use MODRM/SIB/OFFSET memory */

/* The DREX byte has the following fields:

   Bits 7-4 -- DREX.Dest, xmm destination register

   Bit 3    -- DREX.OC0, operand config bit defines operand order

   Bit 2    -- DREX.R, equivalent to REX_R bit, to extend ModRM register

   Bit 1    -- DREX.X, equivalent to REX_X bit, to extend SIB index field

   Bit 0    -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,

               SIB base field, or opcode reg field.  */

#define DREX_XMM(drex) ((drex >> 4) & 0xf)

#define DREX_OC0(drex) ((drex >> 3) & 0x1)

/* Flags for prefixes which we somehow handled when printing the

   current instruction.  */

static int used_prefixes;

/* Flags stored in PREFIXES.  */

#define PREFIX_REPZ 1

#define PREFIX_REPNZ 2

#define PREFIX_LOCK 4

#define PREFIX_CS 8

#define PREFIX_SS 0x10

#define PREFIX_DS 0x20

#define PREFIX_ES 0x40

#define PREFIX_FS 0x80

#define PREFIX_GS 0x100

#define PREFIX_DATA 0x200

#define PREFIX_ADDR 0x400

#define PREFIX_FWAIT 0x800

/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)

   to ADDR (exclusive) are valid.  Returns 1 for success, longjmps

   on error.  */

#define FETCH_DATA(info, addr) \

  ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \

   ? 1 : fetch_data ((info), (addr)))

static int

fetch_data (struct disassemble_info *info, bfd_byte *addr)

{

  int status;

  struct dis_private *priv = (struct dis_private *) info->private_data;

  bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);

  if (addr <= priv->the_buffer + MAX_MNEM_SIZE)

    status = (*info->read_memory_func) (start,

                                        priv->max_fetched,

                                        addr - priv->max_fetched,

                                        info);

  else

    status = -1;

  if (status != 0)

    {

      /* If we did manage to read at least one byte, then

         print_insn_i386 will do something sensible.  Otherwise, print

         an error.  We do that here because this is where we know

         STATUS.  */

      if (priv->max_fetched == priv->the_buffer)

        (*info->memory_error_func) (status, start, info);

      longjmp (priv->bailout, 1);

    }

  else

    priv->max_fetched = addr;

  return 1;

}

#define XX { NULL, 0 }

#define Eb { OP_E, b_mode }

#define Ev { OP_E, v_mode }

#define Ed { OP_E, d_mode }

#define Edq { OP_E, dq_mode }

#define Edqw { OP_E, dqw_mode }

#define Edqb { OP_E, dqb_mode }

#define Edqd { OP_E, dqd_mode }

#define Eq { OP_E, q_mode }

#define indirEv { OP_indirE, stack_v_mode }

#define indirEp { OP_indirE, f_mode }

#define stackEv { OP_E, stack_v_mode }

#define Em { OP_E, m_mode }

#define Ew { OP_E, w_mode }

#define M { OP_M, 0 }           /* lea, lgdt, etc. */

#define Ma { OP_M, a_mode }

#define Mb { OP_M, b_mode }

#define Md { OP_M, d_mode }

#define Mo { OP_M, o_mode }

#define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */

#define Mq { OP_M, q_mode }

#define Mx { OP_M, x_mode }

#define Mxmm { OP_M, xmm_mode }

#define Gb { OP_G, b_mode }

#define Gv { OP_G, v_mode }

#define Gd { OP_G, d_mode }

#define Gdq { OP_G, dq_mode }

#define Gm { OP_G, m_mode }

#define Gw { OP_G, w_mode }

#define Rd { OP_R, d_mode }

#define Rm { OP_R, m_mode }

#define Ib { OP_I, b_mode }

#define sIb { OP_sI, b_mode }   /* sign extened byte */

#define Iv { OP_I, v_mode }

#define Iq { OP_I, q_mode }

#define Iv64 { OP_I64, v_mode }

#define Iw { OP_I, w_mode }

#define I1 { OP_I, const_1_mode }

#define Jb { OP_J, b_mode }

#define Jv { OP_J, v_mode }

#define Cm { OP_C, m_mode }

#define Dm { OP_D, m_mode }

#define Td { OP_T, d_mode }

#define Skip_MODRM { OP_Skip_MODRM, 0 }

#define RMeAX { OP_REG, eAX_reg }

#define RMeBX { OP_REG, eBX_reg }

#define RMeCX { OP_REG, eCX_reg }

#define RMeDX { OP_REG, eDX_reg }

#define RMeSP { OP_REG, eSP_reg }

#define RMeBP { OP_REG, eBP_reg }

#define RMeSI { OP_REG, eSI_reg }

#define RMeDI { OP_REG, eDI_reg }

#define RMrAX { OP_REG, rAX_reg }

#define RMrBX { OP_REG, rBX_reg }

#define RMrCX { OP_REG, rCX_reg }

#define RMrDX { OP_REG, rDX_reg }

#define RMrSP { OP_REG, rSP_reg }

#define RMrBP { OP_REG, rBP_reg }

#define RMrSI { OP_REG, rSI_reg }

#define RMrDI { OP_REG, rDI_reg }

#define RMAL { OP_REG, al_reg }

#define RMAL { OP_REG, al_reg }

#define RMCL { OP_REG, cl_reg }

#define RMDL { OP_REG, dl_reg }

#define RMBL { OP_REG, bl_reg }

#define RMAH { OP_REG, ah_reg }

#define RMCH { OP_REG, ch_reg }

#define RMDH { OP_REG, dh_reg }

#define RMBH { OP_REG, bh_reg }

#define RMAX { OP_REG, ax_reg }

#define RMDX { OP_REG, dx_reg }

#define eAX { OP_IMREG, eAX_reg }

#define eBX { OP_IMREG, eBX_reg }

#define eCX { OP_IMREG, eCX_reg }

#define eDX { OP_IMREG, eDX_reg }

#define eSP { OP_IMREG, eSP_reg }

#define eBP { OP_IMREG, eBP_reg }

#define eSI { OP_IMREG, eSI_reg }

#define eDI { OP_IMREG, eDI_reg }

#define AL { OP_IMREG, al_reg }

#define CL { OP_IMREG, cl_reg }

#define DL { OP_IMREG, dl_reg }

#define BL { OP_IMREG, bl_reg }

#define AH { OP_IMREG, ah_reg }

#define CH { OP_IMREG, ch_reg }

#define DH { OP_IMREG, dh_reg }

#define BH { OP_IMREG, bh_reg }

#define AX { OP_IMREG, ax_reg }

#define DX { OP_IMREG, dx_reg }

#define zAX { OP_IMREG, z_mode_ax_reg }

#define indirDX { OP_IMREG, indir_dx_reg }

#define Sw { OP_SEG, w_mode }

#define Sv { OP_SEG, v_mode }

#define Ap { OP_DIR, 0 }

#define Ob { OP_OFF64, b_mode }

#define Ov { OP_OFF64, v_mode }

#define Xb { OP_DSreg, eSI_reg }

#define Xv { OP_DSreg, eSI_reg }

#define Xz { OP_DSreg, eSI_reg }

#define Yb { OP_ESreg, eDI_reg }

#define Yv { OP_ESreg, eDI_reg }

#define DSBX { OP_DSreg, eBX_reg }

#define es { OP_REG, es_reg }

#define ss { OP_REG, ss_reg }

#define cs { OP_REG, cs_reg }

#define ds { OP_REG, ds_reg }

#define fs { OP_REG, fs_reg }

#define gs { OP_REG, gs_reg }

#define MX { OP_MMX, 0 }

#define XM { OP_XMM, 0 }

#define XMM { OP_XMM, xmm_mode }

#define EM { OP_EM, v_mode }

#define EMd { OP_EM, d_mode }

#define EMx { OP_EM, x_mode }

#define EXw { OP_EX, w_mode }

#define EXd { OP_EX, d_mode }

#define EXq { OP_EX, q_mode }

#define EXx { OP_EX, x_mode }

#define EXxmm { OP_EX, xmm_mode }

#define EXxmmq { OP_EX, xmmq_mode }

#define EXymmq { OP_EX, ymmq_mode }

#define MS { OP_MS, v_mode }

#define XS { OP_XS, v_mode }

#define EMCq { OP_EMC, q_mode }

#define MXC { OP_MXC, 0 }

#define OPSUF { OP_3DNowSuffix, 0 }

#define CMP { CMP_Fixup, 0 }

#define XMM0 { XMM_Fixup, 0 }

#define Vex { OP_VEX, vex_mode }

#define Vex128 { OP_VEX, vex128_mode }

#define Vex256 { OP_VEX, vex256_mode }

#define VexI4 { VEXI4_Fixup, 0}

#define VexFMA { OP_VEX_FMA, vex_mode }

#define Vex128FMA { OP_VEX_FMA, vex128_mode }

#define EXdVex { OP_EX_Vex, d_mode }

#define EXqVex { OP_EX_Vex, q_mode }

#define EXVexW { OP_EX_VexW, x_mode }

#define EXdVexW { OP_EX_VexW, d_mode }

#define EXqVexW { OP_EX_VexW, q_mode }

#define EXVexImmW { OP_EX_VexImmW, x_mode }

#define XMVex { OP_XMM_Vex, 0 }

#define XMVexW { OP_XMM_VexW, 0 }

#define XMVexI4 { OP_REG_VexI4, x_mode }

#define PCLMUL { PCLMUL_Fixup, 0 }

#define VZERO { VZERO_Fixup, 0 }

#define VCMP { VCMP_Fixup, 0 }

#define VPERMIL2 { VPERMIL2_Fixup, 0 }

/* Used handle "rep" prefix for string instructions.  */

#define Xbr { REP_Fixup, eSI_reg }

#define Xvr { REP_Fixup, eSI_reg }

#define Ybr { REP_Fixup, eDI_reg }

#define Yvr { REP_Fixup, eDI_reg }

#define Yzr { REP_Fixup, eDI_reg }

#define indirDXr { REP_Fixup, indir_dx_reg }

#define ALr { REP_Fixup, al_reg }

#define eAXr { REP_Fixup, eAX_reg }

#define cond_jump_flag { NULL, cond_jump_mode }

#define loop_jcxz_flag { NULL, loop_jcxz_mode }

/* bits in sizeflag */

#define SUFFIX_ALWAYS 4

#define AFLAG 2

#define DFLAG 1

/* byte operand */

#define b_mode                  1

/* operand size depends on prefixes */

#define v_mode                  (b_mode + 1)

/* word operand */

#define w_mode                  (v_mode + 1)

/* double word operand  */

#define d_mode                  (w_mode + 1)

/* quad word operand */

#define q_mode                  (d_mode + 1)

/* ten-byte operand */

#define t_mode                  (q_mode + 1)

/* 16-byte XMM or 32-byte YMM operand */

#define x_mode                  (t_mode + 1)

/* 16-byte XMM operand */

#define xmm_mode                (x_mode + 1)

/* 16-byte XMM or quad word operand */

#define xmmq_mode               (xmm_mode + 1)

/* 32-byte YMM or quad word operand */

#define ymmq_mode               (xmmq_mode + 1)

/* d_mode in 32bit, q_mode in 64bit mode.  */

#define m_mode                  (ymmq_mode + 1)

/* pair of v_mode operands */

#define a_mode                  (m_mode + 1)

#define cond_jump_mode          (a_mode + 1)

#define loop_jcxz_mode          (cond_jump_mode + 1)

/* operand size depends on REX prefixes.  */

#define dq_mode                 (loop_jcxz_mode + 1)

/* registers like dq_mode, memory like w_mode.  */

#define dqw_mode                (dq_mode + 1)

/* 4- or 6-byte pointer operand */

#define f_mode                  (dqw_mode + 1)

#define const_1_mode            (f_mode + 1)

/* v_mode for stack-related opcodes.  */

#define stack_v_mode            (const_1_mode + 1)

/* non-quad operand size depends on prefixes */

#define z_mode                  (stack_v_mode + 1)

/* 16-byte operand */

#define o_mode                  (z_mode + 1)

/* registers like dq_mode, memory like b_mode.  */

#define dqb_mode                (o_mode + 1)

/* registers like dq_mode, memory like d_mode.  */

#define dqd_mode                (dqb_mode + 1)

/* normal vex mode */

#define vex_mode                (dqd_mode + 1)

/* 128bit vex mode */

#define vex128_mode             (vex_mode + 1)

/* 256bit vex mode */

#define vex256_mode             (vex128_mode + 1)

#define es_reg                  (vex256_mode + 1)

#define cs_reg                  (es_reg + 1)

#define ss_reg                  (cs_reg + 1)

#define ds_reg                  (ss_reg + 1)

#define fs_reg                  (ds_reg + 1)

#define gs_reg                  (fs_reg + 1)

#define eAX_reg                 (gs_reg + 1)

#define eCX_reg                 (eAX_reg + 1)

#define eDX_reg                 (eCX_reg + 1)

#define eBX_reg                 (eDX_reg + 1)

#define eSP_reg                 (eBX_reg + 1)

#define eBP_reg                 (eSP_reg + 1)

#define eSI_reg                 (eBP_reg + 1)

#define eDI_reg                 (eSI_reg + 1)

#define al_reg                  (eDI_reg + 1)

#define cl_reg                  (al_reg + 1)

#define dl_reg                  (cl_reg + 1)

#define bl_reg                  (dl_reg + 1)

#define ah_reg                  (bl_reg + 1)

#define ch_reg                  (ah_reg + 1)

#define dh_reg                  (ch_reg + 1)

#define bh_reg                  (dh_reg + 1)

#define ax_reg                  (bh_reg + 1)

#define cx_reg                  (ax_reg + 1)

#define dx_reg                  (cx_reg + 1)

#define bx_reg                  (dx_reg + 1)

#define sp_reg                  (bx_reg + 1)

#define bp_reg                  (sp_reg + 1)

#define si_reg                  (bp_reg + 1)

#define di_reg                  (si_reg + 1)

#define rAX_reg                 (di_reg + 1)

#define rCX_reg                 (rAX_reg + 1)

#define rDX_reg                 (rCX_reg + 1)

#define rBX_reg                 (rDX_reg + 1)

#define rSP_reg                 (rBX_reg + 1)

#define rBP_reg                 (rSP_reg + 1)

#define rSI_reg                 (rBP_reg + 1)

#define rDI_reg                 (rSI_reg + 1)

#define z_mode_ax_reg           (rDI_reg + 1)

#define indir_dx_reg            (z_mode_ax_reg + 1)

#define MAX_BYTEMODE    indir_dx_reg

/* Flags that are OR'ed into the bytemode field to pass extra

   information.  */

#define DREX_OC1                0x10000 /* OC1 bit set */

#define DREX_NO_OC0             0x20000 /* OC0 bit not used */

#define DREX_MASK               0x40000 /* mask to delete */

#if MAX_BYTEMODE >= DREX_OC1

#error MAX_BYTEMODE must be less than DREX_OC1

#endif

#define FLOATCODE               1

#define USE_REG_TABLE           (FLOATCODE + 1)

#define USE_MOD_TABLE           (USE_REG_TABLE + 1)

#define USE_RM_TABLE            (USE_MOD_TABLE + 1)

#define USE_PREFIX_TABLE        (USE_RM_TABLE + 1)

#define USE_X86_64_TABLE        (USE_PREFIX_TABLE + 1)

#define USE_3BYTE_TABLE         (USE_X86_64_TABLE + 1)

#define USE_VEX_C4_TABLE        (USE_3BYTE_TABLE + 1)

#define USE_VEX_C5_TABLE        (USE_VEX_C4_TABLE + 1)

#define USE_VEX_LEN_TABLE       (USE_VEX_C5_TABLE + 1)

#define FLOAT                   NULL, { { NULL, FLOATCODE } }

#define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }

#define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))

#define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))

#define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))

#define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))

#define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))

#define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))

#define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))

#define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))

#define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))

#define REG_80                  0

#define REG_81                  (REG_80 + 1)

#define REG_82                  (REG_81 + 1)

#define REG_8F                  (REG_82 + 1)

#define REG_C0                  (REG_8F + 1)

#define REG_C1                  (REG_C0 + 1)

#define REG_C6                  (REG_C1 + 1)

#define REG_C7                  (REG_C6 + 1)

#define REG_D0                  (REG_C7 + 1)

#define REG_D1                  (REG_D0 + 1)

#define REG_D2                  (REG_D1 + 1)

#define REG_D3                  (REG_D2 + 1)

#define REG_F6                  (REG_D3 + 1)

#define REG_F7                  (REG_F6 + 1)

#define REG_FE                  (REG_F7 + 1)

#define REG_FF                  (REG_FE + 1)

#define REG_0F00                (REG_FF + 1)

#define REG_0F01                (REG_0F00 + 1)

#define REG_0F0D                (REG_0F01 + 1)

#define REG_0F18                (REG_0F0D + 1)

#define REG_0F71                (REG_0F18 + 1)

#define REG_0F72                (REG_0F71 + 1)

#define REG_0F73                (REG_0F72 + 1)

#define REG_0FA6                (REG_0F73 + 1)

#define REG_0FA7                (REG_0FA6 + 1)

#define REG_0FAE                (REG_0FA7 + 1)

#define REG_0FBA                (REG_0FAE + 1)

#define REG_0FC7                (REG_0FBA + 1)

#define REG_VEX_71              (REG_0FC7 + 1)

#define REG_VEX_72              (REG_VEX_71 + 1)

#define REG_VEX_73              (REG_VEX_72 + 1)

#define REG_VEX_AE              (REG_VEX_73 + 1)

#define MOD_8D                  0

#define MOD_0F01_REG_0          (MOD_8D + 1)

#define MOD_0F01_REG_1          (MOD_0F01_REG_0 + 1)

#define MOD_0F01_REG_2          (MOD_0F01_REG_1 + 1)

#define MOD_0F01_REG_3          (MOD_0F01_REG_2 + 1)

#define MOD_0F01_REG_7          (MOD_0F01_REG_3 + 1)

#define MOD_0F12_PREFIX_0       (MOD_0F01_REG_7 + 1)

#define MOD_0F13                (MOD_0F12_PREFIX_0 + 1)

#define MOD_0F16_PREFIX_0       (MOD_0F13 + 1)

#define MOD_0F17                (MOD_0F16_PREFIX_0 + 1)

#define MOD_0F18_REG_0          (MOD_0F17 + 1)

#define MOD_0F18_REG_1          (MOD_0F18_REG_0 + 1)

#define MOD_0F18_REG_2          (MOD_0F18_REG_1 + 1)

#define MOD_0F18_REG_3          (MOD_0F18_REG_2 + 1)

#define MOD_0F20                (MOD_0F18_REG_3 + 1)

#define MOD_0F21                (MOD_0F20 + 1)

#define MOD_0F22                (MOD_0F21 + 1)

#define MOD_0F23                (MOD_0F22 + 1)

#define MOD_0F24                (MOD_0F23 + 1)

#define MOD_0F26                (MOD_0F24 + 1)

#define MOD_0F2B_PREFIX_0       (MOD_0F26 + 1)

#define MOD_0F2B_PREFIX_1       (MOD_0F2B_PREFIX_0 + 1)

#define MOD_0F2B_PREFIX_2       (MOD_0F2B_PREFIX_1 + 1)

#define MOD_0F2B_PREFIX_3       (MOD_0F2B_PREFIX_2 + 1)

#define MOD_0F51                (MOD_0F2B_PREFIX_3 + 1)

#define MOD_0F71_REG_2          (MOD_0F51 + 1)

#define MOD_0F71_REG_4          (MOD_0F71_REG_2 + 1)

#define MOD_0F71_REG_6          (MOD_0F71_REG_4 + 1)

#define MOD_0F72_REG_2          (MOD_0F71_REG_6 + 1)

#define MOD_0F72_REG_4          (MOD_0F72_REG_2 + 1)

#define MOD_0F72_REG_6          (MOD_0F72_REG_4 + 1)

#define MOD_0F73_REG_2          (MOD_0F72_REG_6 + 1)

#define MOD_0F73_REG_3          (MOD_0F73_REG_2 + 1)

#define MOD_0F73_REG_6          (MOD_0F73_REG_3 + 1)

#define MOD_0F73_REG_7          (MOD_0F73_REG_6 + 1)

#define MOD_0FAE_REG_0          (MOD_0F73_REG_7 + 1)

#define MOD_0FAE_REG_1          (MOD_0FAE_REG_0 + 1)

#define MOD_0FAE_REG_2          (MOD_0FAE_REG_1 + 1)

#define MOD_0FAE_REG_3          (MOD_0FAE_REG_2 + 1)

#define MOD_0FAE_REG_4          (MOD_0FAE_REG_3 + 1)

#define MOD_0FAE_REG_5          (MOD_0FAE_REG_4 + 1)

#define MOD_0FAE_REG_6          (MOD_0FAE_REG_5 + 1)

#define MOD_0FAE_REG_7          (MOD_0FAE_REG_6 + 1)

#define MOD_0FB2                (MOD_0FAE_REG_7 + 1)

#define MOD_0FB4                (MOD_0FB2 + 1)

#define MOD_0FB5                (MOD_0FB4 + 1)

#define MOD_0FC7_REG_6          (MOD_0FB5 + 1)

#define MOD_0FC7_REG_7          (MOD_0FC7_REG_6 + 1)

#define MOD_0FD7                (MOD_0FC7_REG_7 + 1)

#define MOD_0FE7_PREFIX_2       (MOD_0FD7 + 1)

#define MOD_0FF0_PREFIX_3       (MOD_0FE7_PREFIX_2 + 1)

#define MOD_0F382A_PREFIX_2     (MOD_0FF0_PREFIX_3 + 1)

#define MOD_62_32BIT            (MOD_0F382A_PREFIX_2 + 1)

#define MOD_C4_32BIT            (MOD_62_32BIT + 1)

#define MOD_C5_32BIT            (MOD_C4_32BIT + 1)

#define MOD_VEX_12_PREFIX_0     (MOD_C5_32BIT + 1)

#define MOD_VEX_13              (MOD_VEX_12_PREFIX_0 + 1)

#define MOD_VEX_16_PREFIX_0     (MOD_VEX_13 + 1)

#define MOD_VEX_17              (MOD_VEX_16_PREFIX_0 + 1)

#define MOD_VEX_2B              (MOD_VEX_17 + 1)

#define MOD_VEX_51              (MOD_VEX_2B + 1)

#define MOD_VEX_71_REG_2        (MOD_VEX_51 + 1)

#define MOD_VEX_71_REG_4        (MOD_VEX_71_REG_2 + 1)

#define MOD_VEX_71_REG_6        (MOD_VEX_71_REG_4 + 1)

#define MOD_VEX_72_REG_2        (MOD_VEX_71_REG_6 + 1)

#define MOD_VEX_72_REG_4        (MOD_VEX_72_REG_2 + 1)

#define MOD_VEX_72_REG_6        (MOD_VEX_72_REG_4 + 1)

#define MOD_VEX_73_REG_2        (MOD_VEX_72_REG_6 + 1)

#define MOD_VEX_73_REG_3        (MOD_VEX_73_REG_2 + 1)

#define MOD_VEX_73_REG_6        (MOD_VEX_73_REG_3 + 1)

#define MOD_VEX_73_REG_7        (MOD_VEX_73_REG_6 + 1)

#define MOD_VEX_AE_REG_2        (MOD_VEX_73_REG_7 + 1)

#define MOD_VEX_AE_REG_3        (MOD_VEX_AE_REG_2 + 1)

#define MOD_VEX_D7_PREFIX_2     (MOD_VEX_AE_REG_3 + 1)

#define MOD_VEX_E7_PREFIX_2     (MOD_VEX_D7_PREFIX_2 + 1)

#define MOD_VEX_F0_PREFIX_3     (MOD_VEX_E7_PREFIX_2 + 1)

#define MOD_VEX_3818_PREFIX_2   (MOD_VEX_F0_PREFIX_3 + 1)

#define MOD_VEX_3819_PREFIX_2   (MOD_VEX_3818_PREFIX_2 + 1)

#define MOD_VEX_381A_PREFIX_2   (MOD_VEX_3819_PREFIX_2 + 1)

#define MOD_VEX_382A_PREFIX_2   (MOD_VEX_381A_PREFIX_2 + 1)

#define MOD_VEX_382C_PREFIX_2   (MOD_VEX_382A_PREFIX_2 + 1)

#define MOD_VEX_382D_PREFIX_2   (MOD_VEX_382C_PREFIX_2 + 1)

#define MOD_VEX_382E_PREFIX_2   (MOD_VEX_382D_PREFIX_2 + 1)

#define MOD_VEX_382F_PREFIX_2   (MOD_VEX_382E_PREFIX_2 + 1)

#define RM_0F01_REG_0           0

#define RM_0F01_REG_1           (RM_0F01_REG_0 + 1)

#define RM_0F01_REG_2           (RM_0F01_REG_1 + 1)

#define RM_0F01_REG_3           (RM_0F01_REG_2 + 1)

#define RM_0F01_REG_7           (RM_0F01_REG_3 + 1)

#define RM_0FAE_REG_5           (RM_0F01_REG_7 + 1)

#define RM_0FAE_REG_6           (RM_0FAE_REG_5 + 1)

#define RM_0FAE_REG_7           (RM_0FAE_REG_6 + 1)

#define PREFIX_90               0

#define PREFIX_0F10             (PREFIX_90 + 1)

#define PREFIX_0F11             (PREFIX_0F10 + 1)

#define PREFIX_0F12             (PREFIX_0F11 + 1)

#define PREFIX_0F16             (PREFIX_0F12 + 1)

#define PREFIX_0F2A             (PREFIX_0F16 + 1)

#define PREFIX_0F2B             (PREFIX_0F2A + 1)

#define PREFIX_0F2C             (PREFIX_0F2B + 1)

#define PREFIX_0F2D             (PREFIX_0F2C + 1)

#define PREFIX_0F2E             (PREFIX_0F2D + 1)

#define PREFIX_0F2F             (PREFIX_0F2E + 1)

#define PREFIX_0F51             (PREFIX_0F2F + 1)

#define PREFIX_0F52             (PREFIX_0F51 + 1)

#define PREFIX_0F53             (PREFIX_0F52 + 1)

#define PREFIX_0F58             (PREFIX_0F53 + 1)

#define PREFIX_0F59             (PREFIX_0F58 + 1)

#define PREFIX_0F5A             (PREFIX_0F59 + 1)

#define PREFIX_0F5B             (PREFIX_0F5A + 1)

#define PREFIX_0F5C             (PREFIX_0F5B + 1)

#define PREFIX_0F5D             (PREFIX_0F5C + 1)

#define PREFIX_0F5E             (PREFIX_0F5D + 1)

#define PREFIX_0F5F             (PREFIX_0F5E + 1)

#define PREFIX_0F60             (PREFIX_0F5F + 1)

#define PREFIX_0F61             (PREFIX_0F60 + 1)

#define PREFIX_0F62             (PREFIX_0F61 + 1)

#define PREFIX_0F6C             (PREFIX_0F62 + 1)

#define PREFIX_0F6D             (PREFIX_0F6C + 1)

#define PREFIX_0F6F             (PREFIX_0F6D + 1)

#define PREFIX_0F70             (PREFIX_0F6F + 1)

#define PREFIX_0F73_REG_3       (PREFIX_0F70 + 1)

#define PREFIX_0F73_REG_7       (PREFIX_0F73_REG_3 + 1)

#define PREFIX_0F78             (PREFIX_0F73_REG_7 + 1)

#define PREFIX_0F79             (PREFIX_0F78 + 1)

#define PREFIX_0F7C             (PREFIX_0F79 + 1)

#define PREFIX_0F7D             (PREFIX_0F7C + 1)

#define PREFIX_0F7E             (PREFIX_0F7D + 1)

#define PREFIX_0F7F             (PREFIX_0F7E + 1)

#define PREFIX_0FB8             (PREFIX_0F7F + 1)

#define PREFIX_0FBD             (PREFIX_0FB8 + 1)

#define PREFIX_0FC2             (PREFIX_0FBD + 1)

#define PREFIX_0FC3             (PREFIX_0FC2 + 1)

#define PREFIX_0FC7_REG_6       (PREFIX_0FC3 + 1)

#define PREFIX_0FD0             (PREFIX_0FC7_REG_6 + 1)

#define PREFIX_0FD6             (PREFIX_0FD0 + 1)

#define PREFIX_0FE6             (PREFIX_0FD6 + 1)

#define PREFIX_0FE7             (PREFIX_0FE6 + 1)

#define PREFIX_0FF0             (PREFIX_0FE7 + 1)

#define PREFIX_0FF7             (PREFIX_0FF0 + 1)

#define PREFIX_0F3810           (PREFIX_0FF7 + 1)

#define PREFIX_0F3814           (PREFIX_0F3810 + 1)

#define PREFIX_0F3815           (PREFIX_0F3814 + 1)

#define PREFIX_0F3817           (PREFIX_0F3815 + 1)

#define PREFIX_0F3820           (PREFIX_0F3817 + 1)

#define PREFIX_0F3821           (PREFIX_0F3820 + 1)

#define PREFIX_0F3822           (PREFIX_0F3821 + 1)

#define PREFIX_0F3823           (PREFIX_0F3822 + 1)

#define PREFIX_0F3824           (PREFIX_0F3823 + 1)

#define PREFIX_0F3825           (PREFIX_0F3824 + 1)

#define PREFIX_0F3828           (PREFIX_0F3825 + 1)

#define PREFIX_0F3829           (PREFIX_0F3828 + 1)

#define PREFIX_0F382A           (PREFIX_0F3829 + 1)

#define PREFIX_0F382B           (PREFIX_0F382A + 1)

#define PREFIX_0F3830           (PREFIX_0F382B + 1)

#define PREFIX_0F3831           (PREFIX_0F3830 + 1)

#define PREFIX_0F3832           (PREFIX_0F3831 + 1)

#define PREFIX_0F3833           (PREFIX_0F3832 + 1)

#define PREFIX_0F3834           (PREFIX_0F3833 + 1)

#define PREFIX_0F3835           (PREFIX_0F3834 + 1)

#define PREFIX_0F3837           (PREFIX_0F3835 + 1)

#define PREFIX_0F3838           (PREFIX_0F3837 + 1)

#define PREFIX_0F3839           (PREFIX_0F3838 + 1)

#define PREFIX_0F383A           (PREFIX_0F3839 + 1)

#define PREFIX_0F383B           (PREFIX_0F383A + 1)

#define PREFIX_0F383C           (PREFIX_0F383B + 1)

#define PREFIX_0F383D           (PREFIX_0F383C + 1)

#define PREFIX_0F383E           (PREFIX_0F383D + 1)

#define PREFIX_0F383F           (PREFIX_0F383E + 1)

#define PREFIX_0F3840           (PREFIX_0F383F + 1)