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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [opcodes/] [iq2000-dis.c] - Blame information for rev 826

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1 38 julius
/* Disassembler interface for targets using CGEN. -*- C -*-
2
   CGEN: Cpu tools GENerator
3
 
4
   THIS FILE IS MACHINE GENERATED WITH CGEN.
5
   - the resultant file is machine generated, cgen-dis.in isn't
6
 
7
   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007
8
   Free Software Foundation, Inc.
9
 
10
   This file is part of libopcodes.
11
 
12
   This library is free software; you can redistribute it and/or modify
13
   it under the terms of the GNU General Public License as published by
14
   the Free Software Foundation; either version 3, or (at your option)
15
   any later version.
16
 
17
   It is distributed in the hope that it will be useful, but WITHOUT
18
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
20
   License for more details.
21
 
22
   You should have received a copy of the GNU General Public License
23
   along with this program; if not, write to the Free Software Foundation, Inc.,
24
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
25
 
26
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
27
   Keep that in mind.  */
28
 
29
#include "sysdep.h"
30
#include <stdio.h>
31
#include "ansidecl.h"
32
#include "dis-asm.h"
33
#include "bfd.h"
34
#include "symcat.h"
35
#include "libiberty.h"
36
#include "iq2000-desc.h"
37
#include "iq2000-opc.h"
38
#include "opintl.h"
39
 
40
/* Default text to print if an instruction isn't recognized.  */
41
#define UNKNOWN_INSN_MSG _("*unknown*")
42
 
43
static void print_normal
44
  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
45
static void print_address
46
  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
47
static void print_keyword
48
  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
49
static void print_insn_normal
50
  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
51
static int print_insn
52
  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
53
static int default_print_insn
54
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
55
static int read_insn
56
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
57
   unsigned long *);
58
 
59
/* -- disassembler routines inserted here.  */
60
 
61
 
62
void iq2000_cgen_print_operand
63
  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
64
 
65
/* Main entry point for printing operands.
66
   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
67
   of dis-asm.h on cgen.h.
68
 
69
   This function is basically just a big switch statement.  Earlier versions
70
   used tables to look up the function to use, but
71
   - if the table contains both assembler and disassembler functions then
72
     the disassembler contains much of the assembler and vice-versa,
73
   - there's a lot of inlining possibilities as things grow,
74
   - using a switch statement avoids the function call overhead.
75
 
76
   This function could be moved into `print_insn_normal', but keeping it
77
   separate makes clear the interface between `print_insn_normal' and each of
78
   the handlers.  */
79
 
80
void
81
iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
82
                           int opindex,
83
                           void * xinfo,
84
                           CGEN_FIELDS *fields,
85
                           void const *attrs ATTRIBUTE_UNUSED,
86
                           bfd_vma pc,
87
                           int length)
88
{
89
  disassemble_info *info = (disassemble_info *) xinfo;
90
 
91
  switch (opindex)
92
    {
93
    case IQ2000_OPERAND__INDEX :
94
      print_normal (cd, info, fields->f_index, 0, pc, length);
95
      break;
96
    case IQ2000_OPERAND_BASE :
97
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
98
      break;
99
    case IQ2000_OPERAND_BASEOFF :
100
      print_address (cd, info, fields->f_imm, 0, pc, length);
101
      break;
102
    case IQ2000_OPERAND_BITNUM :
103
      print_normal (cd, info, fields->f_rt, 0, pc, length);
104
      break;
105
    case IQ2000_OPERAND_BYTECOUNT :
106
      print_normal (cd, info, fields->f_bytecount, 0, pc, length);
107
      break;
108
    case IQ2000_OPERAND_CAM_Y :
109
      print_normal (cd, info, fields->f_cam_y, 0, pc, length);
110
      break;
111
    case IQ2000_OPERAND_CAM_Z :
112
      print_normal (cd, info, fields->f_cam_z, 0, pc, length);
113
      break;
114
    case IQ2000_OPERAND_CM_3FUNC :
115
      print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
116
      break;
117
    case IQ2000_OPERAND_CM_3Z :
118
      print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
119
      break;
120
    case IQ2000_OPERAND_CM_4FUNC :
121
      print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
122
      break;
123
    case IQ2000_OPERAND_CM_4Z :
124
      print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
125
      break;
126
    case IQ2000_OPERAND_COUNT :
127
      print_normal (cd, info, fields->f_count, 0, pc, length);
128
      break;
129
    case IQ2000_OPERAND_EXECODE :
130
      print_normal (cd, info, fields->f_excode, 0, pc, length);
131
      break;
132
    case IQ2000_OPERAND_HI16 :
133
      print_normal (cd, info, fields->f_imm, 0, pc, length);
134
      break;
135
    case IQ2000_OPERAND_IMM :
136
      print_normal (cd, info, fields->f_imm, 0, pc, length);
137
      break;
138
    case IQ2000_OPERAND_JMPTARG :
139
      print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
140
      break;
141
    case IQ2000_OPERAND_JMPTARGQ10 :
142
      print_address (cd, info, fields->f_jtargq10, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
143
      break;
144
    case IQ2000_OPERAND_LO16 :
145
      print_normal (cd, info, fields->f_imm, 0, pc, length);
146
      break;
147
    case IQ2000_OPERAND_MASK :
148
      print_normal (cd, info, fields->f_mask, 0, pc, length);
149
      break;
150
    case IQ2000_OPERAND_MASKL :
151
      print_normal (cd, info, fields->f_maskl, 0, pc, length);
152
      break;
153
    case IQ2000_OPERAND_MASKQ10 :
154
      print_normal (cd, info, fields->f_maskq10, 0, pc, length);
155
      break;
156
    case IQ2000_OPERAND_MASKR :
157
      print_normal (cd, info, fields->f_rs, 0, pc, length);
158
      break;
159
    case IQ2000_OPERAND_MLO16 :
160
      print_normal (cd, info, fields->f_imm, 0, pc, length);
161
      break;
162
    case IQ2000_OPERAND_OFFSET :
163
      print_address (cd, info, fields->f_offset, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
164
      break;
165
    case IQ2000_OPERAND_RD :
166
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
167
      break;
168
    case IQ2000_OPERAND_RD_RS :
169
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
170
      break;
171
    case IQ2000_OPERAND_RD_RT :
172
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0|(1<<CGEN_OPERAND_VIRTUAL));
173
      break;
174
    case IQ2000_OPERAND_RS :
175
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
176
      break;
177
    case IQ2000_OPERAND_RT :
178
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
179
      break;
180
    case IQ2000_OPERAND_RT_RS :
181
      print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
182
      break;
183
    case IQ2000_OPERAND_SHAMT :
184
      print_normal (cd, info, fields->f_shamt, 0, pc, length);
185
      break;
186
 
187
    default :
188
      /* xgettext:c-format */
189
      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
190
               opindex);
191
    abort ();
192
  }
193
}
194
 
195
cgen_print_fn * const iq2000_cgen_print_handlers[] =
196
{
197
  print_insn_normal,
198
};
199
 
200
 
201
void
202
iq2000_cgen_init_dis (CGEN_CPU_DESC cd)
203
{
204
  iq2000_cgen_init_opcode_table (cd);
205
  iq2000_cgen_init_ibld_table (cd);
206
  cd->print_handlers = & iq2000_cgen_print_handlers[0];
207
  cd->print_operand = iq2000_cgen_print_operand;
208
}
209
 
210
 
211
/* Default print handler.  */
212
 
213
static void
214
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
215
              void *dis_info,
216
              long value,
217
              unsigned int attrs,
218
              bfd_vma pc ATTRIBUTE_UNUSED,
219
              int length ATTRIBUTE_UNUSED)
220
{
221
  disassemble_info *info = (disassemble_info *) dis_info;
222
 
223
#ifdef CGEN_PRINT_NORMAL
224
  CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
225
#endif
226
 
227
  /* Print the operand as directed by the attributes.  */
228
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
229
    ; /* nothing to do */
230
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
231
    (*info->fprintf_func) (info->stream, "%ld", value);
232
  else
233
    (*info->fprintf_func) (info->stream, "0x%lx", value);
234
}
235
 
236
/* Default address handler.  */
237
 
238
static void
239
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
240
               void *dis_info,
241
               bfd_vma value,
242
               unsigned int attrs,
243
               bfd_vma pc ATTRIBUTE_UNUSED,
244
               int length ATTRIBUTE_UNUSED)
245
{
246
  disassemble_info *info = (disassemble_info *) dis_info;
247
 
248
#ifdef CGEN_PRINT_ADDRESS
249
  CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
250
#endif
251
 
252
  /* Print the operand as directed by the attributes.  */
253
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
254
    ; /* Nothing to do.  */
255
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
256
    (*info->print_address_func) (value, info);
257
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
258
    (*info->print_address_func) (value, info);
259
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
260
    (*info->fprintf_func) (info->stream, "%ld", (long) value);
261
  else
262
    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
263
}
264
 
265
/* Keyword print handler.  */
266
 
267
static void
268
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
269
               void *dis_info,
270
               CGEN_KEYWORD *keyword_table,
271
               long value,
272
               unsigned int attrs ATTRIBUTE_UNUSED)
273
{
274
  disassemble_info *info = (disassemble_info *) dis_info;
275
  const CGEN_KEYWORD_ENTRY *ke;
276
 
277
  ke = cgen_keyword_lookup_value (keyword_table, value);
278
  if (ke != NULL)
279
    (*info->fprintf_func) (info->stream, "%s", ke->name);
280
  else
281
    (*info->fprintf_func) (info->stream, "???");
282
}
283
 
284
/* Default insn printer.
285
 
286
   DIS_INFO is defined as `void *' so the disassembler needn't know anything
287
   about disassemble_info.  */
288
 
289
static void
290
print_insn_normal (CGEN_CPU_DESC cd,
291
                   void *dis_info,
292
                   const CGEN_INSN *insn,
293
                   CGEN_FIELDS *fields,
294
                   bfd_vma pc,
295
                   int length)
296
{
297
  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
298
  disassemble_info *info = (disassemble_info *) dis_info;
299
  const CGEN_SYNTAX_CHAR_TYPE *syn;
300
 
301
  CGEN_INIT_PRINT (cd);
302
 
303
  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
304
    {
305
      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
306
        {
307
          (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
308
          continue;
309
        }
310
      if (CGEN_SYNTAX_CHAR_P (*syn))
311
        {
312
          (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
313
          continue;
314
        }
315
 
316
      /* We have an operand.  */
317
      iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
318
                                 fields, CGEN_INSN_ATTRS (insn), pc, length);
319
    }
320
}
321
 
322
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
323
   the extract info.
324
   Returns 0 if all is well, non-zero otherwise.  */
325
 
326
static int
327
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
328
           bfd_vma pc,
329
           disassemble_info *info,
330
           bfd_byte *buf,
331
           int buflen,
332
           CGEN_EXTRACT_INFO *ex_info,
333
           unsigned long *insn_value)
334
{
335
  int status = (*info->read_memory_func) (pc, buf, buflen, info);
336
 
337
  if (status != 0)
338
    {
339
      (*info->memory_error_func) (status, pc, info);
340
      return -1;
341
    }
342
 
343
  ex_info->dis_info = info;
344
  ex_info->valid = (1 << buflen) - 1;
345
  ex_info->insn_bytes = buf;
346
 
347
  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
348
  return 0;
349
}
350
 
351
/* Utility to print an insn.
352
   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
353
   The result is the size of the insn in bytes or zero for an unknown insn
354
   or -1 if an error occurs fetching data (memory_error_func will have
355
   been called).  */
356
 
357
static int
358
print_insn (CGEN_CPU_DESC cd,
359
            bfd_vma pc,
360
            disassemble_info *info,
361
            bfd_byte *buf,
362
            unsigned int buflen)
363
{
364
  CGEN_INSN_INT insn_value;
365
  const CGEN_INSN_LIST *insn_list;
366
  CGEN_EXTRACT_INFO ex_info;
367
  int basesize;
368
 
369
  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
370
  basesize = cd->base_insn_bitsize < buflen * 8 ?
371
                                     cd->base_insn_bitsize : buflen * 8;
372
  insn_value = cgen_get_insn_value (cd, buf, basesize);
373
 
374
 
375
  /* Fill in ex_info fields like read_insn would.  Don't actually call
376
     read_insn, since the incoming buffer is already read (and possibly
377
     modified a la m32r).  */
378
  ex_info.valid = (1 << buflen) - 1;
379
  ex_info.dis_info = info;
380
  ex_info.insn_bytes = buf;
381
 
382
  /* The instructions are stored in hash lists.
383
     Pick the first one and keep trying until we find the right one.  */
384
 
385
  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
386
  while (insn_list != NULL)
387
    {
388
      const CGEN_INSN *insn = insn_list->insn;
389
      CGEN_FIELDS fields;
390
      int length;
391
      unsigned long insn_value_cropped;
392
 
393
#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
394
      /* Not needed as insn shouldn't be in hash lists if not supported.  */
395
      /* Supported by this cpu?  */
396
      if (! iq2000_cgen_insn_supported (cd, insn))
397
        {
398
          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
399
          continue;
400
        }
401
#endif
402
 
403
      /* Basic bit mask must be correct.  */
404
      /* ??? May wish to allow target to defer this check until the extract
405
         handler.  */
406
 
407
      /* Base size may exceed this instruction's size.  Extract the
408
         relevant part from the buffer. */
409
      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
410
          (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
411
        insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
412
                                           info->endian == BFD_ENDIAN_BIG);
413
      else
414
        insn_value_cropped = insn_value;
415
 
416
      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
417
          == CGEN_INSN_BASE_VALUE (insn))
418
        {
419
          /* Printing is handled in two passes.  The first pass parses the
420
             machine insn and extracts the fields.  The second pass prints
421
             them.  */
422
 
423
          /* Make sure the entire insn is loaded into insn_value, if it
424
             can fit.  */
425
          if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
426
              (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
427
            {
428
              unsigned long full_insn_value;
429
              int rc = read_insn (cd, pc, info, buf,
430
                                  CGEN_INSN_BITSIZE (insn) / 8,
431
                                  & ex_info, & full_insn_value);
432
              if (rc != 0)
433
                return rc;
434
              length = CGEN_EXTRACT_FN (cd, insn)
435
                (cd, insn, &ex_info, full_insn_value, &fields, pc);
436
            }
437
          else
438
            length = CGEN_EXTRACT_FN (cd, insn)
439
              (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
440
 
441
          /* Length < 0 -> error.  */
442
          if (length < 0)
443
            return length;
444
          if (length > 0)
445
            {
446
              CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
447
              /* Length is in bits, result is in bytes.  */
448
              return length / 8;
449
            }
450
        }
451
 
452
      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
453
    }
454
 
455
  return 0;
456
}
457
 
458
/* Default value for CGEN_PRINT_INSN.
459
   The result is the size of the insn in bytes or zero for an unknown insn
460
   or -1 if an error occured fetching bytes.  */
461
 
462
#ifndef CGEN_PRINT_INSN
463
#define CGEN_PRINT_INSN default_print_insn
464
#endif
465
 
466
static int
467
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
468
{
469
  bfd_byte buf[CGEN_MAX_INSN_SIZE];
470
  int buflen;
471
  int status;
472
 
473
  /* Attempt to read the base part of the insn.  */
474
  buflen = cd->base_insn_bitsize / 8;
475
  status = (*info->read_memory_func) (pc, buf, buflen, info);
476
 
477
  /* Try again with the minimum part, if min < base.  */
478
  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
479
    {
480
      buflen = cd->min_insn_bitsize / 8;
481
      status = (*info->read_memory_func) (pc, buf, buflen, info);
482
    }
483
 
484
  if (status != 0)
485
    {
486
      (*info->memory_error_func) (status, pc, info);
487
      return -1;
488
    }
489
 
490
  return print_insn (cd, pc, info, buf, buflen);
491
}
492
 
493
/* Main entry point.
494
   Print one instruction from PC on INFO->STREAM.
495
   Return the size of the instruction (in bytes).  */
496
 
497
typedef struct cpu_desc_list
498
{
499
  struct cpu_desc_list *next;
500
  CGEN_BITSET *isa;
501
  int mach;
502
  int endian;
503
  CGEN_CPU_DESC cd;
504
} cpu_desc_list;
505
 
506
int
507
print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
508
{
509
  static cpu_desc_list *cd_list = 0;
510
  cpu_desc_list *cl = 0;
511
  static CGEN_CPU_DESC cd = 0;
512
  static CGEN_BITSET *prev_isa;
513
  static int prev_mach;
514
  static int prev_endian;
515
  int length;
516
  CGEN_BITSET *isa;
517
  int mach;
518
  int endian = (info->endian == BFD_ENDIAN_BIG
519
                ? CGEN_ENDIAN_BIG
520
                : CGEN_ENDIAN_LITTLE);
521
  enum bfd_architecture arch;
522
 
523
  /* ??? gdb will set mach but leave the architecture as "unknown" */
524
#ifndef CGEN_BFD_ARCH
525
#define CGEN_BFD_ARCH bfd_arch_iq2000
526
#endif
527
  arch = info->arch;
528
  if (arch == bfd_arch_unknown)
529
    arch = CGEN_BFD_ARCH;
530
 
531
  /* There's no standard way to compute the machine or isa number
532
     so we leave it to the target.  */
533
#ifdef CGEN_COMPUTE_MACH
534
  mach = CGEN_COMPUTE_MACH (info);
535
#else
536
  mach = info->mach;
537
#endif
538
 
539
#ifdef CGEN_COMPUTE_ISA
540
  {
541
    static CGEN_BITSET *permanent_isa;
542
 
543
    if (!permanent_isa)
544
      permanent_isa = cgen_bitset_create (MAX_ISAS);
545
    isa = permanent_isa;
546
    cgen_bitset_clear (isa);
547
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
548
  }
549
#else
550
  isa = info->insn_sets;
551
#endif
552
 
553
  /* If we've switched cpu's, try to find a handle we've used before */
554
  if (cd
555
      && (cgen_bitset_compare (isa, prev_isa) != 0
556
          || mach != prev_mach
557
          || endian != prev_endian))
558
    {
559
      cd = 0;
560
      for (cl = cd_list; cl; cl = cl->next)
561
        {
562
          if (cgen_bitset_compare (cl->isa, isa) == 0 &&
563
              cl->mach == mach &&
564
              cl->endian == endian)
565
            {
566
              cd = cl->cd;
567
              prev_isa = cd->isas;
568
              break;
569
            }
570
        }
571
    }
572
 
573
  /* If we haven't initialized yet, initialize the opcode table.  */
574
  if (! cd)
575
    {
576
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
577
      const char *mach_name;
578
 
579
      if (!arch_type)
580
        abort ();
581
      mach_name = arch_type->printable_name;
582
 
583
      prev_isa = cgen_bitset_copy (isa);
584
      prev_mach = mach;
585
      prev_endian = endian;
586
      cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
587
                                 CGEN_CPU_OPEN_BFDMACH, mach_name,
588
                                 CGEN_CPU_OPEN_ENDIAN, prev_endian,
589
                                 CGEN_CPU_OPEN_END);
590
      if (!cd)
591
        abort ();
592
 
593
      /* Save this away for future reference.  */
594
      cl = xmalloc (sizeof (struct cpu_desc_list));
595
      cl->cd = cd;
596
      cl->isa = prev_isa;
597
      cl->mach = mach;
598
      cl->endian = endian;
599
      cl->next = cd_list;
600
      cd_list = cl;
601
 
602
      iq2000_cgen_init_dis (cd);
603
    }
604
 
605
  /* We try to have as much common code as possible.
606
     But at this point some targets need to take over.  */
607
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
608
     but if not possible try to move this hook elsewhere rather than
609
     have two hooks.  */
610
  length = CGEN_PRINT_INSN (cd, pc, info);
611
  if (length > 0)
612
    return length;
613
  if (length < 0)
614
    return -1;
615
 
616
  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
617
  return cd->default_insn_bitsize / 8;
618
}

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