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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [opcodes/] [m10300-opc.c] - Blame information for rev 830

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1 38 julius
/* Assemble Matsushita MN10300 instructions.
2
   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2007
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of the GNU opcodes library.
6
 
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program; if not, write to the Free Software
19
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
 
22
/* This file is formatted at > 80 columns.  Attempting to read it
23
   on a screeen with less than 80 columns will be difficult.  */
24
#include "sysdep.h"
25
#include "opcode/mn10300.h"
26
 
27
 
28
const struct mn10300_operand mn10300_operands[] = {
29
#define UNUSED  0
30
  {0, 0, 0},
31
 
32
/* dn register in the first register operand position.  */
33
#define DN0      (UNUSED+1)
34
  {2, 0, MN10300_OPERAND_DREG},
35
 
36
/* dn register in the second register operand position.  */
37
#define DN1      (DN0+1)
38
  {2, 2, MN10300_OPERAND_DREG},
39
 
40
/* dn register in the third register operand position.  */
41
#define DN2      (DN1+1)
42
  {2, 4, MN10300_OPERAND_DREG},
43
 
44
/* dm register in the first register operand position.  */
45
#define DM0      (DN2+1)
46
  {2, 0, MN10300_OPERAND_DREG},
47
 
48
/* dm register in the second register operand position.  */
49
#define DM1      (DM0+1)
50
  {2, 2, MN10300_OPERAND_DREG},
51
 
52
/* dm register in the third register operand position.  */
53
#define DM2      (DM1+1)
54
  {2, 4, MN10300_OPERAND_DREG},
55
 
56
/* an register in the first register operand position.  */
57
#define AN0      (DM2+1)
58
  {2, 0, MN10300_OPERAND_AREG},
59
 
60
/* an register in the second register operand position.  */
61
#define AN1      (AN0+1)
62
  {2, 2, MN10300_OPERAND_AREG},
63
 
64
/* an register in the third register operand position.  */
65
#define AN2      (AN1+1)
66
  {2, 4, MN10300_OPERAND_AREG},
67
 
68
/* am register in the first register operand position.  */
69
#define AM0      (AN2+1)
70
  {2, 0, MN10300_OPERAND_AREG},
71
 
72
/* am register in the second register operand position.  */
73
#define AM1      (AM0+1)
74
  {2, 2, MN10300_OPERAND_AREG},
75
 
76
/* am register in the third register operand position.  */
77
#define AM2      (AM1+1)
78
  {2, 4, MN10300_OPERAND_AREG},
79
 
80
/* 8 bit unsigned immediate which may promote to a 16bit
81
   unsigned immediate.  */
82
#define IMM8    (AM2+1)
83
  {8, 0, MN10300_OPERAND_PROMOTE},
84
 
85
/* 16 bit unsigned immediate which may promote to a 32bit
86
   unsigned immediate.  */
87
#define IMM16    (IMM8+1)
88
  {16, 0, MN10300_OPERAND_PROMOTE},
89
 
90
/* 16 bit pc-relative immediate which may promote to a 16bit
91
   pc-relative immediate.  */
92
#define IMM16_PCREL    (IMM16+1)
93
  {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
94
 
95
/* 16bit unsigned displacement in a memory operation which
96
   may promote to a 32bit displacement.  */
97
#define IMM16_MEM    (IMM16_PCREL+1)
98
  {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
99
 
100
/* 32bit immediate, high 16 bits in the main instruction
101
   word, 16bits in the extension word.
102
 
103
   The "bits" field indicates how many bits are in the
104
   main instruction word for MN10300_OPERAND_SPLIT!  */
105
#define IMM32    (IMM16_MEM+1)
106
  {16, 0, MN10300_OPERAND_SPLIT},
107
 
108
/* 32bit pc-relative offset.  */
109
#define IMM32_PCREL    (IMM32+1)
110
  {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
111
 
112
/* 32bit memory offset.  */
113
#define IMM32_MEM    (IMM32_PCREL+1)
114
  {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
115
 
116
/* 32bit immediate, high 16 bits in the main instruction
117
   word, 16bits in the extension word, low 16bits are left
118
   shifted 8 places.
119
 
120
   The "bits" field indicates how many bits are in the
121
   main instruction word for MN10300_OPERAND_SPLIT!  */
122
#define IMM32_LOWSHIFT8    (IMM32_MEM+1)
123
  {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
124
 
125
/* 32bit immediate, high 24 bits in the main instruction
126
   word, 8 in the extension word.
127
 
128
   The "bits" field indicates how many bits are in the
129
   main instruction word for MN10300_OPERAND_SPLIT!  */
130
#define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
131
  {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
132
 
133
/* 32bit immediate, high 24 bits in the main instruction
134
   word, 8 in the extension word, low 8 bits are left
135
   shifted 16 places.
136
 
137
   The "bits" field indicates how many bits are in the
138
   main instruction word for MN10300_OPERAND_SPLIT!  */
139
#define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
140
  {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
141
 
142
/* Stack pointer.  */
143
#define SP    (IMM32_HIGH24_LOWSHIFT16+1)
144
  {8, 0, MN10300_OPERAND_SP},
145
 
146
/* Processor status word.  */
147
#define PSW    (SP+1)
148
  {0, 0, MN10300_OPERAND_PSW},
149
 
150
/* MDR register.  */
151
#define MDR    (PSW+1)
152
  {0, 0, MN10300_OPERAND_MDR},
153
 
154
/* Index register.  */
155
#define DI (MDR+1)
156
  {2, 2, MN10300_OPERAND_DREG},
157
 
158
/* 8 bit signed displacement, may promote to 16bit signed displacement.  */
159
#define SD8    (DI+1)
160
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
161
 
162
/* 16 bit signed displacement, may promote to 32bit displacement.  */
163
#define SD16    (SD8+1)
164
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
165
 
166
/* 8 bit signed displacement that can not promote.  */
167
#define SD8N    (SD16+1)
168
  {8, 0, MN10300_OPERAND_SIGNED},
169
 
170
/* 8 bit pc-relative displacement.  */
171
#define SD8N_PCREL    (SD8N+1)
172
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
173
 
174
/* 8 bit signed displacement shifted left 8 bits in the instruction.  */
175
#define SD8N_SHIFT8    (SD8N_PCREL+1)
176
  {8, 8, MN10300_OPERAND_SIGNED},
177
 
178
/* 8 bit signed immediate which may promote to 16bit signed immediate.  */
179
#define SIMM8    (SD8N_SHIFT8+1)
180
  {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
181
 
182
/* 16 bit signed immediate which may promote to 32bit  immediate.  */
183
#define SIMM16    (SIMM8+1)
184
  {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
185
 
186
/* Either an open paren or close paren.  */
187
#define PAREN   (SIMM16+1)
188
  {0, 0, MN10300_OPERAND_PAREN},
189
 
190
/* dn register that appears in the first and second register positions.  */
191
#define DN01     (PAREN+1)
192
  {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
193
 
194
/* an register that appears in the first and second register positions.  */
195
#define AN01     (DN01+1)
196
  {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
197
 
198
/* 16bit pc-relative displacement which may promote to 32bit pc-relative
199
   displacement.  */
200
#define D16_SHIFT (AN01+1)
201
  {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
202
 
203
/* 8 bit immediate found in the extension word.  */
204
#define IMM8E    (D16_SHIFT+1)
205
  {8, 0, MN10300_OPERAND_EXTENDED},
206
 
207
/* Register list found in the extension word shifted 8 bits left.  */
208
#define REGSE_SHIFT8    (IMM8E+1)
209
  {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
210
 
211
/* Register list shifted 8 bits left.  */
212
#define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
213
  {8, 8, MN10300_OPERAND_REG_LIST},
214
 
215
/* Reigster list.  */
216
#define REGS    (REGS_SHIFT8+1)
217
  {8, 0, MN10300_OPERAND_REG_LIST},
218
 
219
/* UStack pointer.  */
220
#define USP    (REGS+1)
221
  {0, 0, MN10300_OPERAND_USP},
222
 
223
/* SStack pointer.  */
224
#define SSP    (USP+1)
225
  {0, 0, MN10300_OPERAND_SSP},
226
 
227
/* MStack pointer.  */
228
#define MSP    (SSP+1)
229
  {0, 0, MN10300_OPERAND_MSP},
230
 
231
/* PC .  */
232
#define PC    (MSP+1)
233
  {0, 0, MN10300_OPERAND_PC},
234
 
235
/* 4 bit immediate for syscall.  */
236
#define IMM4    (PC+1)
237
  {4, 0, 0},
238
 
239
/* Processor status word.  */
240
#define EPSW    (IMM4+1)
241
  {0, 0, MN10300_OPERAND_EPSW},
242
 
243
/* rn register in the first register operand position.  */
244
#define RN0      (EPSW+1)
245
  {4, 0, MN10300_OPERAND_RREG},
246
 
247
/* rn register in the fourth register operand position.  */
248
#define RN2      (RN0+1)
249
  {4, 4, MN10300_OPERAND_RREG},
250
 
251
/* rm register in the first register operand position.  */
252
#define RM0      (RN2+1)
253
  {4, 0, MN10300_OPERAND_RREG},
254
 
255
/* rm register in the second register operand position.  */
256
#define RM1      (RM0+1)
257
  {4, 2, MN10300_OPERAND_RREG},
258
 
259
/* rm register in the third register operand position.  */
260
#define RM2      (RM1+1)
261
  {4, 4, MN10300_OPERAND_RREG},
262
 
263
#define RN02      (RM2+1)
264
  {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
265
 
266
#define XRN0      (RN02+1)
267
  {4, 0, MN10300_OPERAND_XRREG},
268
 
269
#define XRM2      (XRN0+1)
270
  {4, 4, MN10300_OPERAND_XRREG},
271
 
272
/* + for autoincrement */
273
#define PLUS    (XRM2+1)
274
  {0, 0, MN10300_OPERAND_PLUS},
275
 
276
#define XRN02      (PLUS+1)
277
  {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
278
 
279
/* Ick */
280
#define RD0      (XRN02+1)
281
  {4, -8, MN10300_OPERAND_RREG},
282
 
283
#define RD2      (RD0+1)
284
  {4, -4, MN10300_OPERAND_RREG},
285
 
286
/* 8 unsigned displacement in a memory operation which
287
   may promote to a 32bit displacement.  */
288
#define IMM8_MEM    (RD2+1)
289
  {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
290
 
291
/* Index register.  */
292
#define RI (IMM8_MEM+1)
293
  {4, 4, MN10300_OPERAND_RREG},
294
 
295
/* 24 bit signed displacement, may promote to 32bit displacement.  */
296
#define SD24    (RI+1)
297
  {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
298
 
299
/* 24 bit unsigned immediate which may promote to a 32bit
300
   unsigned immediate.  */
301
#define IMM24    (SD24+1)
302
  {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
303
 
304
/* 24 bit signed immediate which may promote to a 32bit
305
   signed immediate.  */
306
#define SIMM24    (IMM24+1)
307
  {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
308
 
309
/* 24bit unsigned displacement in a memory operation which
310
   may promote to a 32bit displacement.  */
311
#define IMM24_MEM    (SIMM24+1)
312
  {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
313
/* 32bit immediate, high 8 bits in the main instruction
314
   word, 24 in the extension word.
315
 
316
   The "bits" field indicates how many bits are in the
317
   main instruction word for MN10300_OPERAND_SPLIT!  */
318
#define IMM32_HIGH8    (IMM24_MEM+1)
319
  {8, 0, MN10300_OPERAND_SPLIT},
320
 
321
/* Similarly, but a memory address.  */
322
#define IMM32_HIGH8_MEM  (IMM32_HIGH8+1)
323
  {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
324
 
325
/* rm register in the seventh register operand position.  */
326
#define RM6      (IMM32_HIGH8_MEM+1)
327
  {4, 12, MN10300_OPERAND_RREG},
328
 
329
/* rm register in the fifth register operand position.  */
330
#define RN4      (RM6+1)
331
  {4, 8, MN10300_OPERAND_RREG},
332
 
333
/* 4 bit immediate for dsp instructions.  */
334
#define IMM4_2    (RN4+1)
335
  {4, 4, 0},
336
 
337
/* 4 bit immediate for dsp instructions.  */
338
#define SIMM4_2    (IMM4_2+1)
339
  {4, 4, MN10300_OPERAND_SIGNED},
340
 
341
/* 4 bit immediate for dsp instructions.  */
342
#define SIMM4_6    (SIMM4_2+1)
343
  {4, 12, MN10300_OPERAND_SIGNED},
344
 
345
#define FPCR      (SIMM4_6+1)
346
  {0, 0, MN10300_OPERAND_FPCR},
347
 
348
/* We call f[sd]m registers those whose most significant bit is stored
349
 * within the opcode half-word, i.e., in a bit on the left of the 4
350
 * least significant bits, and f[sd]n registers those whose most
351
 * significant bit is stored at the end of the full word, after the 4
352
 * least significant bits.  They're not numbered after their position
353
 * in the mnemonic asm instruction, but after their position in the
354
 * opcode word, i.e., depending on the amount of shift they need.
355
 *
356
 * The additional bit is shifted as follows: for `n' registers, it
357
 * will be shifted by (|shift|/4); for `m' registers, it will be
358
 * shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose
359
 * specifications are only 3-bits long, the two least-significant bits
360
 * are shifted by 16, and the most-significant bit is shifted by -2
361
 * (i.e., it's stored in the least significant bit of the full
362
 * word).  */
363
 
364
/* fsm register in the first register operand position.  */
365
#define FSM0      (FPCR+1)
366
  {5, 0, MN10300_OPERAND_FSREG },
367
 
368
/* fsm register in the second register operand position.  */
369
#define FSM1      (FSM0+1)
370
  {5, 4, MN10300_OPERAND_FSREG },
371
 
372
/* fsm register in the third register operand position.  */
373
#define FSM2      (FSM1+1)
374
  {5, 8, MN10300_OPERAND_FSREG },
375
 
376
/* fsm register in the fourth register operand position.  */
377
#define FSM3      (FSM2+1)
378
  {5, 12, MN10300_OPERAND_FSREG },
379
 
380
/* fsn register in the first register operand position.  */
381
#define FSN1      (FSM3+1)
382
  {5, -4, MN10300_OPERAND_FSREG },
383
 
384
/* fsn register in the second register operand position.  */
385
#define FSN2      (FSN1+1)
386
  {5, -8, MN10300_OPERAND_FSREG },
387
 
388
/* fsm register in the third register operand position.  */
389
#define FSN3      (FSN2+1)
390
  {5, -12, MN10300_OPERAND_FSREG },
391
 
392
/* fsm accumulator, in the fourth register operand position.  */
393
#define FSACC     (FSN3+1)
394
  {3, -16, MN10300_OPERAND_FSREG },
395
 
396
/* fdm register in the first register operand position.  */
397
#define FDM0      (FSACC+1)
398
  {5, 0, MN10300_OPERAND_FDREG },
399
 
400
/* fdm register in the second register operand position.  */
401
#define FDM1      (FDM0+1)
402
  {5, 4, MN10300_OPERAND_FDREG },
403
 
404
/* fdm register in the third register operand position.  */
405
#define FDM2      (FDM1+1)
406
  {5, 8, MN10300_OPERAND_FDREG },
407
 
408
/* fdm register in the fourth register operand position.  */
409
#define FDM3      (FDM2+1)
410
  {5, 12, MN10300_OPERAND_FDREG },
411
 
412
/* fdn register in the first register operand position.  */
413
#define FDN1      (FDM3+1)
414
  {5, -4, MN10300_OPERAND_FDREG },
415
 
416
/* fdn register in the second register operand position.  */
417
#define FDN2      (FDN1+1)
418
  {5, -8, MN10300_OPERAND_FDREG },
419
 
420
/* fdn register in the third register operand position.  */
421
#define FDN3      (FDN2+1)
422
  {5, -12, MN10300_OPERAND_FDREG },
423
 
424
} ;
425
 
426
#define MEM(ADDR) PAREN, ADDR, PAREN 
427
#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN 
428
#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN 
429
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
430
 
431
/* The opcode table.
432
 
433
   The format of the opcode table is:
434
 
435
   NAME         OPCODE          MASK    MATCH_MASK, FORMAT, PROCESSOR   { OPERANDS }
436
 
437
   NAME is the name of the instruction.
438
   OPCODE is the instruction opcode.
439
   MASK is the opcode mask; this is used to tell the disassembler
440
     which bits in the actual opcode must match OPCODE.
441
   OPERANDS is the list of operands.
442
 
443
   The disassembler reads the table in order and prints the first
444
   instruction which matches, so this table is sorted to put more
445
   specific instructions before more general instructions.  It is also
446
   sorted by major opcode.  */
447
 
448
const struct mn10300_opcode mn10300_opcodes[] = {
449
{ "mov",        0x8000,      0xf000,      0,    FMT_S1, 0,        {SIMM8, DN01}},
450
{ "mov",        0x80,        0xf0,        0x3,  FMT_S0, 0,       {DM1, DN0}},
451
{ "mov",        0xf1e0,      0xfff0,      0,    FMT_D0, 0,        {DM1, AN0}},
452
{ "mov",        0xf1d0,      0xfff0,      0,    FMT_D0, 0,        {AM1, DN0}},
453
{ "mov",        0x9000,      0xf000,      0,    FMT_S1, 0,        {IMM8, AN01}},
454
{ "mov",        0x90,        0xf0,        0x3,  FMT_S0, 0,       {AM1, AN0}},
455
{ "mov",        0x3c,        0xfc,        0,    FMT_S0, 0,        {SP, AN0}},
456
{ "mov",        0xf2f0,      0xfff3,      0,    FMT_D0, 0,        {AM1, SP}},
457
{ "mov",        0xf2e4,      0xfffc,      0,    FMT_D0, 0,        {PSW, DN0}},
458
{ "mov",        0xf2f3,      0xfff3,      0,    FMT_D0, 0,        {DM1, PSW}},
459
{ "mov",        0xf2e0,      0xfffc,      0,    FMT_D0, 0,        {MDR, DN0}},
460
{ "mov",        0xf2f2,      0xfff3,      0,    FMT_D0, 0,        {DM1, MDR}},
461
{ "mov",        0x70,        0xf0,        0,    FMT_S0, 0,        {MEM(AM0), DN1}},
462
{ "mov",        0x5800,      0xfcff,      0,    FMT_S1, 0,        {MEM(SP), DN0}},
463
{ "mov",        0x300000,    0xfc0000,    0,    FMT_S2, 0,        {MEM(IMM16_MEM), DN0}},
464
{ "mov",        0xf000,      0xfff0,      0,    FMT_D0, 0,        {MEM(AM0), AN1}},
465
{ "mov",        0x5c00,      0xfcff,      0,    FMT_S1, 0,        {MEM(SP), AN0}},
466
{ "mov",        0xfaa00000,  0xfffc0000,  0,    FMT_D2, 0,        {MEM(IMM16_MEM), AN0}},
467
{ "mov",        0x60,        0xf0,        0,    FMT_S0, 0,        {DM1, MEM(AN0)}},
468
{ "mov",        0x4200,      0xf3ff,      0,    FMT_S1, 0,        {DM1, MEM(SP)}},
469
{ "mov",        0x010000,    0xf30000,    0,    FMT_S2, 0,        {DM1, MEM(IMM16_MEM)}},
470
{ "mov",        0xf010,      0xfff0,      0,    FMT_D0, 0,        {AM1, MEM(AN0)}},
471
{ "mov",        0x4300,      0xf3ff,      0,    FMT_S1, 0,        {AM1, MEM(SP)}},
472
{ "mov",        0xfa800000,  0xfff30000,  0,    FMT_D2, 0,        {AM1, MEM(IMM16_MEM)}},
473
{ "mov",        0x5c00,      0xfc00,      0,    FMT_S1, 0,        {MEM2(IMM8, SP), AN0}},
474
{ "mov",        0xf80000,    0xfff000,    0,    FMT_D1, 0,        {MEM2(SD8, AM0), DN1}},
475
{ "mov",        0xfa000000,  0xfff00000,  0,    FMT_D2, 0,        {MEM2(SD16, AM0), DN1}},
476
{ "mov",        0x5800,      0xfc00,      0,    FMT_S1, 0,        {MEM2(IMM8, SP), DN0}},
477
{ "mov",        0xfab40000,  0xfffc0000,  0,    FMT_D2, 0,        {MEM2(IMM16, SP), DN0}},
478
{ "mov",        0xf300,      0xffc0,      0,    FMT_D0, 0,        {MEM2(DI, AM0), DN2}},
479
{ "mov",        0xf82000,    0xfff000,    0,    FMT_D1, 0,        {MEM2(SD8,AM0), AN1}},
480
{ "mov",        0xfa200000,  0xfff00000,  0,    FMT_D2, 0,        {MEM2(SD16, AM0), AN1}},
481
{ "mov",        0xfab00000,  0xfffc0000,  0,    FMT_D2, 0,        {MEM2(IMM16, SP), AN0}},
482
{ "mov",        0xf380,      0xffc0,      0,    FMT_D0, 0,        {MEM2(DI, AM0), AN2}},
483
{ "mov",        0x4300,      0xf300,      0,    FMT_S1, 0,        {AM1, MEM2(IMM8, SP)}},
484
{ "mov",        0xf81000,    0xfff000,    0,    FMT_D1, 0,        {DM1, MEM2(SD8, AN0)}},
485
{ "mov",        0xfa100000,  0xfff00000,  0,    FMT_D2, 0,        {DM1, MEM2(SD16, AN0)}},
486
{ "mov",        0x4200,      0xf300,      0,    FMT_S1, 0,        {DM1, MEM2(IMM8, SP)}},
487
{ "mov",        0xfa910000,  0xfff30000,  0,    FMT_D2, 0,        {DM1, MEM2(IMM16, SP)}},
488
{ "mov",        0xf340,      0xffc0,      0,    FMT_D0, 0,        {DM2, MEM2(DI, AN0)}},
489
{ "mov",        0xf83000,    0xfff000,    0,    FMT_D1, 0,        {AM1, MEM2(SD8, AN0)}},
490
{ "mov",        0xfa300000,  0xfff00000,  0,    FMT_D2, 0,        {AM1, MEM2(SD16, AN0)}},
491
{ "mov",        0xfa900000,  0xfff30000,  0,    FMT_D2, 0,        {AM1, MEM2(IMM16, SP)}},
492
{ "mov",        0xf3c0,      0xffc0,      0,    FMT_D0, 0,        {AM2, MEM2(DI, AN0)}},
493
 
494
{ "mov",        0xf020,      0xfffc,      0,    FMT_D0, AM33,    {USP, AN0}},
495
{ "mov",        0xf024,      0xfffc,      0,    FMT_D0, AM33,    {SSP, AN0}},
496
{ "mov",        0xf028,      0xfffc,      0,    FMT_D0, AM33,    {MSP, AN0}},
497
{ "mov",        0xf02c,      0xfffc,      0,    FMT_D0, AM33,    {PC, AN0}},
498
{ "mov",        0xf030,      0xfff3,      0,    FMT_D0, AM33,    {AN1, USP}},
499
{ "mov",        0xf031,      0xfff3,      0,    FMT_D0, AM33,    {AN1, SSP}},
500
{ "mov",        0xf032,      0xfff3,      0,    FMT_D0, AM33,    {AN1, MSP}},
501
{ "mov",        0xf2ec,      0xfffc,      0,    FMT_D0, AM33,    {EPSW, DN0}},
502
{ "mov",        0xf2f1,      0xfff3,      0,    FMT_D0, AM33,    {DM1, EPSW}},
503
{ "mov",        0xf500,      0xffc0,      0,    FMT_D0, AM33,    {AM2, RN0}},
504
{ "mov",        0xf540,      0xffc0,      0,    FMT_D0, AM33,    {DM2, RN0}},
505
{ "mov",        0xf580,      0xffc0,      0,    FMT_D0, AM33,    {RM1, AN0}},
506
{ "mov",        0xf5c0,      0xffc0,      0,    FMT_D0, AM33,    {RM1, DN0}},
507
{ "mov",        0xf90800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
508
{ "mov",        0xf9e800,    0xffff00,    0,    FMT_D6, AM33,    {XRM2, RN0}},
509
{ "mov",        0xf9f800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, XRN0}},
510
{ "mov",        0xf90a00,    0xffff00,    0,    FMT_D6, AM33,    {MEM(RM0), RN2}},
511
{ "mov",        0xf98a00,    0xffff0f,    0,    FMT_D6, AM33,    {MEM(SP), RN2}},
512
{ "mov",        0xf96a00,    0xffff00,    0x12, FMT_D6, AM33,   {MEMINC(RM0), RN2}},
513
{ "mov",        0xfb0e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM(IMM8_MEM), RN2}},
514
{ "mov",        0xfd0e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM(IMM24_MEM), RN2}},
515
{ "mov",        0xf91a00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, MEM(RN0)}},
516
{ "mov",        0xf99a00,    0xffff0f,    0,    FMT_D6, AM33,    {RM2, MEM(SP)}},
517
{ "mov",        0xf97a00,    0xffff00,    0,     FMT_D6, AM33,   {RM2, MEMINC(RN0)}},
518
{ "mov",        0xfb1e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM(IMM8_MEM)}},
519
{ "mov",        0xfd1e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM(IMM24_MEM)}},
520
{ "mov",        0xfb0a0000,  0xffff0000,  0,    FMT_D7, AM33,    {MEM2(SD8, RM0), RN2}},
521
{ "mov",        0xfd0a0000,  0xffff0000,  0,    FMT_D8, AM33,    {MEM2(SD24, RM0), RN2}},
522
{ "mov",        0xfb8e0000,  0xffff000f,  0,    FMT_D7, AM33,    {MEM2(RI, RM0), RD2}},
523
{ "mov",        0xfb1a0000,  0xffff0000,  0,    FMT_D7, AM33,    {RM2, MEM2(SD8, RN0)}},
524
{ "mov",        0xfd1a0000,  0xffff0000,  0,    FMT_D8, AM33,    {RM2, MEM2(SD24, RN0)}},
525
{ "mov",        0xfb8a0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM2(IMM8, SP), RN2}},
526
{ "mov",        0xfd8a0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM2(IMM24, SP), RN2}},
527
{ "mov",        0xfb9a0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM2(IMM8, SP)}},
528
{ "mov",        0xfd9a0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM2(IMM24, SP)}},
529
{ "mov",        0xfb9e0000,  0xffff000f,  0,    FMT_D7, AM33,    {RD2, MEM2(RI, RN0)}},
530
{ "mov",        0xfb6a0000,  0xffff0000,  0x22, FMT_D7, AM33,   {MEMINC2 (RM0, SIMM8), RN2}},
531
{ "mov",        0xfb7a0000,  0xffff0000,  0,     FMT_D7, AM33,   {RM2, MEMINC2 (RN0, SIMM8)}},
532
{ "mov",        0xfd6a0000,  0xffff0000,  0x22, FMT_D8, AM33,   {MEMINC2 (RM0, IMM24), RN2}},
533
{ "mov",        0xfd7a0000,  0xffff0000,  0,     FMT_D8, AM33,   {RM2, MEMINC2 (RN0, IMM24)}},
534
{ "mov",        0xfe6a0000,  0xffff0000,  0x22, FMT_D9, AM33,   {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
535
{ "mov",        0xfe7a0000,  0xffff0000,  0,     FMT_D9, AM33,   {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
536
/* These must come after most of the other move instructions to avoid matching
537
   a symbolic name with IMMxx operands.  Ugh.  */
538
{ "mov",        0x2c0000,    0xfc0000,    0,    FMT_S2, 0,        {SIMM16, DN0}},
539
{ "mov",        0xfccc0000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
540
{ "mov",        0x240000,    0xfc0000,    0,    FMT_S2, 0,        {IMM16, AN0}},
541
{ "mov",        0xfcdc0000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, AN0}},
542
{ "mov",        0xfca40000,  0xfffc0000,  0,    FMT_D4, 0,        {MEM(IMM32_MEM), DN0}},
543
{ "mov",        0xfca00000,  0xfffc0000,  0,    FMT_D4, 0,        {MEM(IMM32_MEM), AN0}},
544
{ "mov",        0xfc810000,  0xfff30000,  0,    FMT_D4, 0,        {DM1, MEM(IMM32_MEM)}},
545
{ "mov",        0xfc800000,  0xfff30000,  0,    FMT_D4, 0,        {AM1, MEM(IMM32_MEM)}},
546
{ "mov",        0xfc000000,  0xfff00000,  0,    FMT_D4, 0,        {MEM2(IMM32,AM0), DN1}},
547
{ "mov",        0xfcb40000,  0xfffc0000,  0,    FMT_D4, 0,        {MEM2(IMM32, SP), DN0}},
548
{ "mov",        0xfc200000,  0xfff00000,  0,    FMT_D4, 0,        {MEM2(IMM32,AM0), AN1}},
549
{ "mov",        0xfcb00000,  0xfffc0000,  0,    FMT_D4, 0,        {MEM2(IMM32, SP), AN0}},
550
{ "mov",        0xfc100000,  0xfff00000,  0,    FMT_D4, 0,        {DM1, MEM2(IMM32,AN0)}},
551
{ "mov",        0xfc910000,  0xfff30000,  0,    FMT_D4, 0,        {DM1, MEM2(IMM32, SP)}},
552
{ "mov",        0xfc300000,  0xfff00000,  0,    FMT_D4, 0,        {AM1, MEM2(IMM32,AN0)}},
553
{ "mov",        0xfc900000,  0xfff30000,  0,    FMT_D4, 0,        {AM1, MEM2(IMM32, SP)}},
554
/* These non-promoting variants need to come after all the other memory
555
   moves.  */
556
{ "mov",        0xf8f000,    0xfffc00,    0,    FMT_D1, AM30,    {MEM2(SD8N, AM0), SP}},
557
{ "mov",        0xf8f400,    0xfffc00,    0,    FMT_D1, AM30,    {SP, MEM2(SD8N, AN0)}},
558
/* These are the same as the previous non-promoting versions.  The am33
559
   does not have restrictions on the offsets used to load/store the stack
560
   pointer.  */
561
{ "mov",        0xf8f000,    0xfffc00,    0,    FMT_D1, AM33,    {MEM2(SD8, AM0), SP}},
562
{ "mov",        0xf8f400,    0xfffc00,    0,    FMT_D1, AM33,    {SP, MEM2(SD8, AN0)}},
563
/* These must come last so that we favor shorter move instructions for
564
   loading immediates into d0-d3/a0-a3.  */
565
{ "mov",        0xfb080000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
566
{ "mov",        0xfd080000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
567
{ "mov",        0xfe080000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
568
{ "mov",        0xfbf80000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, XRN02}},
569
{ "mov",        0xfdf80000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, XRN02}},
570
{ "mov",        0xfef80000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, XRN02}},
571
{ "mov",        0xfe0e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM(IMM32_HIGH8_MEM), RN2}},
572
{ "mov",        0xfe1e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM(IMM32_HIGH8_MEM)}},
573
{ "mov",        0xfe0a0000,  0xffff0000,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8,RM0), RN2}},
574
{ "mov",        0xfe1a0000,  0xffff0000,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, RN0)}},
575
{ "mov",        0xfe8a0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8, SP), RN2}},
576
{ "mov",        0xfe9a0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, SP)}},
577
 
578
{ "movu",       0xfb180000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
579
{ "movu",       0xfd180000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
580
{ "movu",       0xfe180000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
581
 
582
{ "mcst9",      0xf630,      0xfff0,      0,    FMT_D0, AM33,    {DN01}},
583
{ "mcst48",     0xf660,      0xfff0,      0,    FMT_D0, AM33,    {DN01}},
584
{ "swap",       0xf680,      0xfff0,      0,    FMT_D0, AM33,    {DM1, DN0}},
585
{ "swap",       0xf9cb00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
586
{ "swaph",      0xf690,      0xfff0,      0,    FMT_D0, AM33,    {DM1, DN0}},
587
{ "swaph",      0xf9db00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
588
{ "getchx",     0xf6c0,      0xfff0,      0,    FMT_D0, AM33,    {DN01}},
589
{ "getclx",     0xf6d0,      0xfff0,      0,    FMT_D0, AM33,    {DN01}},
590
{ "mac",        0xfb0f0000,  0xffff0000,  0xc,  FMT_D7, AM33,   {RM2, RN0, RD2, RD0}},
591
{ "mac",        0xf90b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
592
{ "mac",        0xfb0b0000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
593
{ "mac",        0xfd0b0000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
594
{ "mac",        0xfe0b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
595
{ "macu",       0xfb1f0000,  0xffff0000,  0xc,  FMT_D7, AM33,   {RM2, RN0, RD2, RD0}},
596
{ "macu",       0xf91b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
597
{ "macu",       0xfb1b0000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
598
{ "macu",       0xfd1b0000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
599
{ "macu",       0xfe1b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
600
{ "macb",       0xfb2f0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
601
{ "macb",       0xf92b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
602
{ "macb",       0xfb2b0000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
603
{ "macb",       0xfd2b0000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
604
{ "macb",       0xfe2b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
605
{ "macbu",      0xfb3f0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
606
{ "macbu",      0xf93b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
607
{ "macbu",      0xfb3b0000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
608
{ "macbu",      0xfd3b0000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
609
{ "macbu",      0xfe3b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
610
{ "mach",       0xfb4f0000,  0xffff0000,  0xc,  FMT_D7, AM33,   {RM2, RN0, RD2, RD0}},
611
{ "mach",       0xf94b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
612
{ "mach",       0xfb4b0000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
613
{ "mach",       0xfd4b0000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
614
{ "mach",       0xfe4b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
615
{ "machu",      0xfb5f0000,  0xffff0000,  0xc,  FMT_D7, AM33,   {RM2, RN0, RD2, RD0}},
616
{ "machu",      0xf95b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
617
{ "machu",      0xfb5b0000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
618
{ "machu",      0xfd5b0000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
619
{ "machu",      0xfe5b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
620
{ "dmach",      0xfb6f0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
621
{ "dmach",      0xf96b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
622
{ "dmach",      0xfe6b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
623
{ "dmachu",     0xfb7f0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
624
{ "dmachu",     0xf97b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
625
{ "dmachu",     0xfe7b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
626
{ "dmulh",      0xfb8f0000,  0xffff0000,  0xc,  FMT_D7, AM33,   {RM2, RN0, RD2, RD0}},
627
{ "dmulh",      0xf98b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
628
{ "dmulh",      0xfe8b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
629
{ "dmulhu",     0xfb9f0000,  0xffff0000,  0xc,  FMT_D7, AM33,   {RM2, RN0, RD2, RD0}},
630
{ "dmulhu",     0xf99b00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
631
{ "dmulhu",     0xfe9b0000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
632
{ "mcste",      0xf9bb00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
633
{ "mcste",      0xfbbb0000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
634
{ "swhw",       0xf9eb00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
635
 
636
{ "movbu",      0xf040,      0xfff0,      0,    FMT_D0, 0,        {MEM(AM0), DN1}},
637
{ "movbu",      0xf84000,    0xfff000,    0,    FMT_D1, 0,        {MEM2(SD8, AM0), DN1}},
638
{ "movbu",      0xfa400000,  0xfff00000,  0,    FMT_D2, 0,        {MEM2(SD16, AM0), DN1}},
639
{ "movbu",      0xf8b800,    0xfffcff,    0,    FMT_D1, 0,        {MEM(SP), DN0}},
640
{ "movbu",      0xf8b800,    0xfffc00,    0,    FMT_D1, 0,        {MEM2(IMM8, SP), DN0}},
641
{ "movbu",      0xfab80000,  0xfffc0000,  0,    FMT_D2, 0,        {MEM2(IMM16, SP), DN0}},
642
{ "movbu",      0xf400,      0xffc0,      0,    FMT_D0, 0,        {MEM2(DI, AM0), DN2}},
643
{ "movbu",      0x340000,    0xfc0000,    0,    FMT_S2, 0,        {MEM(IMM16_MEM), DN0}},
644
{ "movbu",      0xf050,      0xfff0,      0,    FMT_D0, 0,        {DM1, MEM(AN0)}},
645
{ "movbu",      0xf85000,    0xfff000,    0,    FMT_D1, 0,        {DM1, MEM2(SD8, AN0)}},
646
{ "movbu",      0xfa500000,  0xfff00000,  0,    FMT_D2, 0,        {DM1, MEM2(SD16, AN0)}},
647
{ "movbu",      0xf89200,    0xfff3ff,    0,    FMT_D1, 0,        {DM1, MEM(SP)}},
648
{ "movbu",      0xf89200,    0xfff300,    0,    FMT_D1, 0,        {DM1, MEM2(IMM8, SP)}},
649
{ "movbu",      0xfa920000,  0xfff30000,  0,    FMT_D2, 0,        {DM1, MEM2(IMM16, SP)}},
650
{ "movbu",      0xf440,      0xffc0,      0,    FMT_D0, 0,        {DM2, MEM2(DI, AN0)}},
651
{ "movbu",      0x020000,    0xf30000,    0,    FMT_S2, 0,        {DM1, MEM(IMM16_MEM)}},
652
{ "movbu",      0xf92a00,    0xffff00,    0,    FMT_D6, AM33,    {MEM(RM0), RN2}},
653
{ "movbu",      0xf93a00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, MEM(RN0)}},
654
{ "movbu",      0xf9aa00,    0xffff0f,    0,    FMT_D6, AM33,    {MEM(SP), RN2}},
655
{ "movbu",      0xf9ba00,    0xffff0f,    0,    FMT_D6, AM33,    {RM2, MEM(SP)}},
656
{ "movbu",      0xfb2a0000,  0xffff0000,  0,    FMT_D7, AM33,    {MEM2(SD8, RM0), RN2}},
657
{ "movbu",      0xfd2a0000,  0xffff0000,  0,    FMT_D8, AM33,    {MEM2(SD24, RM0), RN2}},
658
{ "movbu",      0xfb3a0000,  0xffff0000,  0,    FMT_D7, AM33,    {RM2, MEM2(SD8, RN0)}},
659
{ "movbu",      0xfd3a0000,  0xffff0000,  0,    FMT_D8, AM33,    {RM2, MEM2(SD24, RN0)}},
660
{ "movbu",      0xfbaa0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM2(IMM8, SP), RN2}},
661
{ "movbu",      0xfdaa0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM2(IMM24, SP), RN2}},
662
{ "movbu",      0xfbba0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM2(IMM8, SP)}},
663
{ "movbu",      0xfdba0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM2(IMM24, SP)}},
664
{ "movbu",      0xfb2e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM(IMM8_MEM), RN2}},
665
{ "movbu",      0xfd2e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM(IMM24_MEM), RN2}},
666
{ "movbu",      0xfb3e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM(IMM8_MEM)}},
667
{ "movbu",      0xfd3e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM(IMM24_MEM)}},
668
{ "movbu",      0xfbae0000,  0xffff000f,  0,    FMT_D7, AM33,    {MEM2(RI, RM0), RD2}},
669
{ "movbu",      0xfbbe0000,  0xffff000f,  0,    FMT_D7, AM33,    {RD2, MEM2(RI, RN0)}},
670
{ "movbu",      0xfc400000,  0xfff00000,  0,    FMT_D4, 0,        {MEM2(IMM32,AM0), DN1}},
671
{ "movbu",      0xfcb80000,  0xfffc0000,  0,    FMT_D4, 0,        {MEM2(IMM32, SP), DN0}},
672
{ "movbu",      0xfca80000,  0xfffc0000,  0,    FMT_D4, 0,        {MEM(IMM32_MEM), DN0}},
673
{ "movbu",      0xfc500000,  0xfff00000,  0,    FMT_D4, 0,        {DM1, MEM2(IMM32,AN0)}},
674
{ "movbu",      0xfc920000,  0xfff30000,  0,    FMT_D4, 0,        {DM1, MEM2(IMM32, SP)}},
675
{ "movbu",      0xfc820000,  0xfff30000,  0,    FMT_D4, 0,        {DM1, MEM(IMM32_MEM)}},
676
{ "movbu",      0xfe2a0000,  0xffff0000,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8,RM0), RN2}},
677
{ "movbu",      0xfe3a0000,  0xffff0000,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, RN0)}},
678
{ "movbu",      0xfeaa0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8,SP), RN2}},
679
{ "movbu",      0xfeba0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, SP)}},
680
{ "movbu",      0xfe2e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM(IMM32_HIGH8_MEM), RN2}},
681
{ "movbu",      0xfe3e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM(IMM32_HIGH8_MEM)}},
682
 
683
{ "movhu",      0xf060,      0xfff0,      0,    FMT_D0, 0,        {MEM(AM0), DN1}},
684
{ "movhu",      0xf86000,    0xfff000,    0,    FMT_D1, 0,        {MEM2(SD8, AM0), DN1}},
685
{ "movhu",      0xfa600000,  0xfff00000,  0,    FMT_D2, 0,        {MEM2(SD16, AM0), DN1}},
686
{ "movhu",      0xf8bc00,    0xfffcff,    0,    FMT_D1, 0,        {MEM(SP), DN0}},
687
{ "movhu",      0xf8bc00,    0xfffc00,    0,    FMT_D1, 0,        {MEM2(IMM8, SP), DN0}},
688
{ "movhu",      0xfabc0000,  0xfffc0000,  0,    FMT_D2, 0,        {MEM2(IMM16, SP), DN0}},
689
{ "movhu",      0xf480,      0xffc0,      0,    FMT_D0, 0,        {MEM2(DI, AM0), DN2}},
690
{ "movhu",      0x380000,    0xfc0000,    0,    FMT_S2, 0,        {MEM(IMM16_MEM), DN0}},
691
{ "movhu",      0xf070,      0xfff0,      0,    FMT_D0, 0,        {DM1, MEM(AN0)}},
692
{ "movhu",      0xf87000,    0xfff000,    0,    FMT_D1, 0,        {DM1, MEM2(SD8, AN0)}},
693
{ "movhu",      0xfa700000,  0xfff00000,  0,    FMT_D2, 0,        {DM1, MEM2(SD16, AN0)}},
694
{ "movhu",      0xf89300,    0xfff3ff,    0,    FMT_D1, 0,        {DM1, MEM(SP)}},
695
{ "movhu",      0xf89300,    0xfff300,    0,    FMT_D1, 0,        {DM1, MEM2(IMM8, SP)}},
696
{ "movhu",      0xfa930000,  0xfff30000,  0,    FMT_D2, 0,        {DM1, MEM2(IMM16, SP)}},
697
{ "movhu",      0xf4c0,      0xffc0,      0,    FMT_D0, 0,        {DM2, MEM2(DI, AN0)}},
698
{ "movhu",      0x030000,    0xf30000,    0,    FMT_S2, 0,        {DM1, MEM(IMM16_MEM)}},
699
{ "movhu",      0xf94a00,    0xffff00,    0,    FMT_D6, AM33,    {MEM(RM0), RN2}},
700
{ "movhu",      0xf95a00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, MEM(RN0)}},
701
{ "movhu",      0xf9ca00,    0xffff0f,    0,    FMT_D6, AM33,    {MEM(SP), RN2}},
702
{ "movhu",      0xf9da00,    0xffff0f,    0,    FMT_D6, AM33,    {RM2, MEM(SP)}},
703
{ "movhu",      0xf9ea00,    0xffff00,    0x12, FMT_D6, AM33,   {MEMINC(RM0), RN2}},
704
{ "movhu",      0xf9fa00,    0xffff00,    0,     FMT_D6, AM33,   {RM2, MEMINC(RN0)}},
705
{ "movhu",      0xfb4a0000,  0xffff0000,  0,    FMT_D7, AM33,    {MEM2(SD8, RM0), RN2}},
706
{ "movhu",      0xfd4a0000,  0xffff0000,  0,    FMT_D8, AM33,    {MEM2(SD24, RM0), RN2}},
707
{ "movhu",      0xfb5a0000,  0xffff0000,  0,    FMT_D7, AM33,    {RM2, MEM2(SD8, RN0)}},
708
{ "movhu",      0xfd5a0000,  0xffff0000,  0,    FMT_D8, AM33,    {RM2, MEM2(SD24, RN0)}},
709
{ "movhu",      0xfbca0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM2(IMM8, SP), RN2}},
710
{ "movhu",      0xfdca0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM2(IMM24, SP), RN2}},
711
{ "movhu",      0xfbda0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM2(IMM8, SP)}},
712
{ "movhu",      0xfdda0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM2(IMM24, SP)}},
713
{ "movhu",      0xfb4e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {MEM(IMM8_MEM), RN2}},
714
{ "movhu",      0xfd4e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {MEM(IMM24_MEM), RN2}},
715
{ "movhu",      0xfbce0000,  0xffff000f,  0,    FMT_D7, AM33,    {MEM2(RI, RM0), RD2}},
716
{ "movhu",      0xfbde0000,  0xffff000f,  0,    FMT_D7, AM33,    {RD2, MEM2(RI, RN0)}},
717
{ "movhu",      0xfc600000,  0xfff00000,  0,    FMT_D4, 0,        {MEM2(IMM32,AM0), DN1}},
718
{ "movhu",      0xfcbc0000,  0xfffc0000,  0,    FMT_D4, 0,        {MEM2(IMM32, SP), DN0}},
719
{ "movhu",      0xfcac0000,  0xfffc0000,  0,    FMT_D4, 0,        {MEM(IMM32_MEM), DN0}},
720
{ "movhu",      0xfc700000,  0xfff00000,  0,    FMT_D4, 0,        {DM1, MEM2(IMM32,AN0)}},
721
{ "movhu",      0xfc930000,  0xfff30000,  0,    FMT_D4, 0,        {DM1, MEM2(IMM32, SP)}},
722
{ "movhu",      0xfc830000,  0xfff30000,  0,    FMT_D4, 0,        {DM1, MEM(IMM32_MEM)}},
723
{ "movhu",      0xfe4a0000,  0xffff0000,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8,RM0), RN2}},
724
{ "movhu",      0xfe5a0000,  0xffff0000,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, RN0)}},
725
{ "movhu",      0xfeca0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM2(IMM32_HIGH8, SP), RN2}},
726
{ "movhu",      0xfeda0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM2(IMM32_HIGH8, SP)}},
727
{ "movhu",      0xfe4e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {MEM(IMM32_HIGH8_MEM), RN2}},
728
{ "movhu",      0xfb5e0000,  0xffff0f00,  0,    FMT_D7, AM33,    {RM2, MEM(IMM8_MEM)}},
729
{ "movhu",      0xfd5e0000,  0xffff0f00,  0,    FMT_D8, AM33,    {RM2, MEM(IMM24_MEM)}},
730
{ "movhu",      0xfe5e0000,  0xffff0f00,  0,    FMT_D9, AM33,    {RM2, MEM(IMM32_HIGH8_MEM)}},
731
{ "movhu",      0xfbea0000,  0xffff0000,  0x22, FMT_D7, AM33,   {MEMINC2 (RM0, SIMM8), RN2}},
732
{ "movhu",      0xfbfa0000,  0xffff0000,  0,     FMT_D7, AM33,   {RM2, MEMINC2 (RN0, SIMM8)}},
733
{ "movhu",      0xfdea0000,  0xffff0000,  0x22, FMT_D8, AM33,   {MEMINC2 (RM0, IMM24), RN2}},
734
{ "movhu",      0xfdfa0000,  0xffff0000,  0,     FMT_D8, AM33,   {RM2, MEMINC2 (RN0, IMM24)}},
735
{ "movhu",      0xfeea0000,  0xffff0000,  0x22, FMT_D9, AM33,   {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
736
{ "movhu",      0xfefa0000,  0xffff0000,  0,     FMT_D9, AM33,   {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
737
 
738
{ "ext",        0xf2d0,      0xfffc,      0,    FMT_D0, 0,        {DN0}},
739
{ "ext",        0xf91800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
740
 
741
{ "extb",       0xf92800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
742
{ "extb",       0x10,        0xfc,        0,    FMT_S0, 0,        {DN0}},
743
{ "extb",       0xf92800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
744
 
745
{ "extbu",      0xf93800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
746
{ "extbu",      0x14,        0xfc,        0,    FMT_S0, 0,        {DN0}},
747
{ "extbu",      0xf93800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
748
 
749
{ "exth",       0xf94800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
750
{ "exth",       0x18,        0xfc,        0,    FMT_S0, 0,        {DN0}},
751
{ "exth",       0xf94800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
752
 
753
{ "exthu",      0xf95800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
754
{ "exthu",      0x1c,        0xfc,        0,    FMT_S0, 0,        {DN0}},
755
{ "exthu",      0xf95800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
756
 
757
{ "movm",       0xce00,      0xff00,      0,    FMT_S1, 0,        {MEM(SP), REGS}},
758
{ "movm",       0xcf00,      0xff00,      0,    FMT_S1, 0,        {REGS, MEM(SP)}},
759
{ "movm",       0xf8ce00,    0xffff00,    0,    FMT_D1, AM33,    {MEM(USP), REGS}},
760
{ "movm",       0xf8cf00,    0xffff00,    0,    FMT_D1, AM33,    {REGS, MEM(USP)}},
761
 
762
{ "clr",        0x00,        0xf3,        0,    FMT_S0, 0,        {DN1}},
763
{ "clr",        0xf96800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
764
 
765
{ "add",        0xfb7c0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
766
{ "add",        0xe0,        0xf0,        0,    FMT_S0, 0,        {DM1, DN0}},
767
{ "add",        0xf160,      0xfff0,      0,    FMT_D0, 0,        {DM1, AN0}},
768
{ "add",        0xf150,      0xfff0,      0,    FMT_D0, 0,        {AM1, DN0}},
769
{ "add",        0xf170,      0xfff0,      0,    FMT_D0, 0,        {AM1, AN0}},
770
{ "add",        0x2800,      0xfc00,      0,    FMT_S1, 0,        {SIMM8, DN0}},
771
{ "add",        0xfac00000,  0xfffc0000,  0,    FMT_D2, 0,        {SIMM16, DN0}},
772
{ "add",        0x2000,      0xfc00,      0,    FMT_S1, 0,        {SIMM8, AN0}},
773
{ "add",        0xfad00000,  0xfffc0000,  0,    FMT_D2, 0,        {SIMM16, AN0}},
774
{ "add",        0xf8fe00,    0xffff00,    0,    FMT_D1, 0,        {SIMM8, SP}},
775
{ "add",        0xfafe0000,  0xffff0000,  0,    FMT_D2, 0,        {SIMM16, SP}},
776
{ "add",        0xf97800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
777
{ "add",        0xfcc00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
778
{ "add",        0xfcd00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, AN0}},
779
{ "add",        0xfcfe0000,  0xffff0000,  0,    FMT_D4, 0,        {IMM32, SP}},
780
{ "add",        0xfb780000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
781
{ "add",        0xfd780000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
782
{ "add",        0xfe780000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
783
 
784
{ "addc",       0xfb8c0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
785
{ "addc",       0xf140,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
786
{ "addc",       0xf98800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
787
{ "addc",       0xfb880000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
788
{ "addc",       0xfd880000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
789
{ "addc",       0xfe880000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
790
 
791
{ "sub",        0xfb9c0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
792
{ "sub",        0xf100,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
793
{ "sub",        0xf120,      0xfff0,      0,    FMT_D0, 0,        {DM1, AN0}},
794
{ "sub",        0xf110,      0xfff0,      0,    FMT_D0, 0,        {AM1, DN0}},
795
{ "sub",        0xf130,      0xfff0,      0,    FMT_D0, 0,        {AM1, AN0}},
796
{ "sub",        0xf99800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
797
{ "sub",        0xfcc40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
798
{ "sub",        0xfcd40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, AN0}},
799
{ "sub",        0xfb980000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
800
{ "sub",        0xfd980000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
801
{ "sub",        0xfe980000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
802
 
803
{ "subc",       0xfbac0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
804
{ "subc",       0xf180,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
805
{ "subc",       0xf9a800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
806
{ "subc",       0xfba80000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
807
{ "subc",       0xfda80000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
808
{ "subc",       0xfea80000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
809
 
810
{ "mul",        0xfbad0000,  0xffff0000,  0xc,  FMT_D7, AM33,   {RM2, RN0, RD2, RD0}},
811
{ "mul",        0xf240,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
812
{ "mul",        0xf9a900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
813
{ "mul",        0xfba90000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
814
{ "mul",        0xfda90000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
815
{ "mul",        0xfea90000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
816
 
817
{ "mulu",       0xfbbd0000,  0xffff0000,  0xc,  FMT_D7, AM33,   {RM2, RN0, RD2, RD0}},
818
{ "mulu",       0xf250,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
819
{ "mulu",       0xf9b900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
820
{ "mulu",       0xfbb90000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
821
{ "mulu",       0xfdb90000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
822
{ "mulu",       0xfeb90000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
823
 
824
{ "div",        0xf260,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
825
{ "div",        0xf9c900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
826
 
827
{ "divu",       0xf270,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
828
{ "divu",       0xf9d900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
829
 
830
{ "inc",        0x40,        0xf3,        0,    FMT_S0, 0,        {DN1}},
831
{ "inc",        0x41,        0xf3,        0,    FMT_S0, 0,        {AN1}},
832
{ "inc",        0xf9b800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
833
 
834
{ "inc4",       0x50,        0xfc,        0,    FMT_S0, 0,        {AN0}},
835
{ "inc4",       0xf9c800,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
836
 
837
{ "cmp",        0xa000,      0xf000,      0,    FMT_S1, 0,        {SIMM8, DN01}},
838
{ "cmp",        0xa0,        0xf0,        0x3,  FMT_S0, 0,       {DM1, DN0}},
839
{ "cmp",        0xf1a0,      0xfff0,      0,    FMT_D0, 0,        {DM1, AN0}},
840
{ "cmp",        0xf190,      0xfff0,      0,    FMT_D0, 0,        {AM1, DN0}},
841
{ "cmp",        0xb000,      0xf000,      0,    FMT_S1, 0,        {IMM8, AN01}},
842
{ "cmp",        0xb0,        0xf0,        0x3,  FMT_S0, 0,       {AM1, AN0}},
843
{ "cmp",        0xfac80000,  0xfffc0000,  0,    FMT_D2, 0,        {SIMM16, DN0}},
844
{ "cmp",        0xfad80000,  0xfffc0000,  0,    FMT_D2, 0,        {IMM16, AN0}},
845
{ "cmp",        0xf9d800,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
846
{ "cmp",        0xfcc80000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
847
{ "cmp",        0xfcd80000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, AN0}},
848
{ "cmp",        0xfbd80000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
849
{ "cmp",        0xfdd80000,  0xffff0000,  0,    FMT_D8, AM33,    {SIMM24, RN02}},
850
{ "cmp",        0xfed80000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
851
 
852
{ "and",        0xfb0d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
853
{ "and",        0xf200,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
854
{ "and",        0xf8e000,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
855
{ "and",        0xfae00000,  0xfffc0000,  0,    FMT_D2, 0,        {IMM16, DN0}},
856
{ "and",        0xfafc0000,  0xffff0000,  0,    FMT_D2, 0,        {IMM16, PSW}},
857
{ "and",        0xfcfc0000,  0xffff0000,  0,    FMT_D4, AM33,    {IMM32, EPSW}},
858
{ "and",        0xf90900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
859
{ "and",        0xfce00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
860
{ "and",        0xfb090000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
861
{ "and",        0xfd090000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
862
{ "and",        0xfe090000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
863
 
864
{ "or",         0xfb1d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
865
{ "or",         0xf210,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
866
{ "or",         0xf8e400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
867
{ "or",         0xfae40000,  0xfffc0000,  0,    FMT_D2, 0,        {IMM16, DN0}},
868
{ "or",         0xfafd0000,  0xffff0000,  0,    FMT_D2, 0,        {IMM16, PSW}},
869
{ "or",         0xfcfd0000,  0xffff0000,  0,    FMT_D4, AM33,    {IMM32, EPSW}},
870
{ "or",         0xf91900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
871
{ "or",         0xfce40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
872
{ "or",         0xfb190000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
873
{ "or",         0xfd190000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
874
{ "or",         0xfe190000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
875
 
876
{ "xor",        0xfb2d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
877
{ "xor",        0xf220,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
878
{ "xor",        0xfae80000,  0xfffc0000,  0,    FMT_D2, 0,        {IMM16, DN0}},
879
{ "xor",        0xf92900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
880
{ "xor",        0xfce80000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
881
{ "xor",        0xfb290000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
882
{ "xor",        0xfd290000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
883
{ "xor",        0xfe290000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
884
 
885
{ "not",        0xf230,      0xfffc,      0,    FMT_D0, 0,        {DN0}},
886
{ "not",        0xf93900,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
887
 
888
{ "btst",       0xf8ec00,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
889
{ "btst",       0xfaec0000,  0xfffc0000,  0,    FMT_D2, 0,        {IMM16, DN0}},
890
{ "btst",       0xfcec0000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
891
/* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
892
   them to match last since they do not promote.  */
893
{ "btst",       0xfbe90000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
894
{ "btst",       0xfde90000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
895
{ "btst",       0xfee90000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
896
{ "btst",       0xfe820000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
897
{ "btst",       0xfe020000,  0xffff0000,  0,    FMT_D5, 0,        {IMM8E, MEM(IMM32_LOWSHIFT8)}},
898
{ "btst",       0xfaf80000,  0xfffc0000,  0,    FMT_D2, 0,        {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
899
 
900
{ "bset",       0xf080,      0xfff0,      0,    FMT_D0, 0,        {DM1, MEM(AN0)}},
901
{ "bset",       0xfe800000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
902
{ "bset",       0xfe000000,  0xffff0000,  0,    FMT_D5, 0,        {IMM8E, MEM(IMM32_LOWSHIFT8)}},
903
{ "bset",       0xfaf00000,  0xfffc0000,  0,    FMT_D2, 0,        {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
904
 
905
{ "bclr",       0xf090,      0xfff0,      0,    FMT_D0, 0,        {DM1, MEM(AN0)}},
906
{ "bclr",       0xfe810000,  0xffff0000,  0,    FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
907
{ "bclr",       0xfe010000,  0xffff0000,  0,    FMT_D5, 0,        {IMM8E, MEM(IMM32_LOWSHIFT8)}},
908
{ "bclr",       0xfaf40000,  0xfffc0000,  0,    FMT_D2, 0,        {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
909
 
910
{ "asr",        0xfb4d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
911
{ "asr",        0xf2b0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
912
{ "asr",        0xf8c800,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
913
{ "asr",        0xf94900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
914
{ "asr",        0xfb490000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
915
{ "asr",        0xfd490000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
916
{ "asr",        0xfe490000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
917
{ "asr",        0xf8c801,    0xfffcff,    0,    FMT_D1, 0,        {DN0}},
918
{ "asr",        0xfb490001,  0xffff00ff,  0,    FMT_D7, AM33,    {RN02}},
919
 
920
{ "lsr",        0xfb5d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
921
{ "lsr",        0xf2a0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
922
{ "lsr",        0xf8c400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
923
{ "lsr",        0xf95900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
924
{ "lsr",        0xfb590000,  0xffff0000,  0,    FMT_D7, AM33,    {IMM8, RN02}},
925
{ "lsr",        0xfd590000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
926
{ "lsr",        0xfe590000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
927
{ "lsr",        0xf8c401,    0xfffcff,    0,    FMT_D1, 0,        {DN0}},
928
{ "lsr",        0xfb590001,  0xffff00ff,  0,    FMT_D7, AM33,    {RN02}},
929
 
930
{ "asl",        0xfb6d0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
931
{ "asl",        0xf290,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
932
{ "asl",        0xf8c000,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
933
{ "asl",        0xf96900,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
934
{ "asl",        0xfb690000,  0xffff0000,  0,    FMT_D7, AM33,    {SIMM8, RN02}},
935
{ "asl",        0xfd690000,  0xffff0000,  0,    FMT_D8, AM33,    {IMM24, RN02}},
936
{ "asl",        0xfe690000,  0xffff0000,  0,    FMT_D9, AM33,    {IMM32_HIGH8, RN02}},
937
{ "asl",        0xf8c001,    0xfffcff,    0,    FMT_D1, 0,        {DN0}},
938
{ "asl",        0xfb690001,  0xffff00ff,  0,    FMT_D7, AM33,    {RN02}},
939
 
940
{ "asl2",       0x54,        0xfc,        0,    FMT_S0, 0,        {DN0}},
941
{ "asl2",       0xf97900,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
942
 
943
{ "ror",        0xf284,      0xfffc,      0,    FMT_D0, 0,        {DN0}},
944
{ "ror",        0xf98900,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
945
 
946
{ "rol",        0xf280,      0xfffc,      0,    FMT_D0, 0,        {DN0}},
947
{ "rol",        0xf99900,    0xffff00,    0,    FMT_D6, AM33,    {RN02}},
948
 
949
{ "beq",        0xc800,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
950
{ "bne",        0xc900,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
951
{ "bgt",        0xc100,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
952
{ "bge",        0xc200,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
953
{ "ble",        0xc300,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
954
{ "blt",        0xc000,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
955
{ "bhi",        0xc500,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
956
{ "bcc",        0xc600,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
957
{ "bls",        0xc700,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
958
{ "bcs",        0xc400,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
959
{ "bvc",        0xf8e800,    0xffff00,    0,    FMT_D1, 0,        {SD8N_PCREL}},
960
{ "bvs",        0xf8e900,    0xffff00,    0,    FMT_D1, 0,        {SD8N_PCREL}},
961
{ "bnc",        0xf8ea00,    0xffff00,    0,    FMT_D1, 0,        {SD8N_PCREL}},
962
{ "bns",        0xf8eb00,    0xffff00,    0,    FMT_D1, 0,        {SD8N_PCREL}},
963
{ "bra",        0xca00,      0xff00,      0,    FMT_S1, 0,        {SD8N_PCREL}},
964
 
965
{ "leq",        0xd8,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
966
{ "lne",        0xd9,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
967
{ "lgt",        0xd1,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
968
{ "lge",        0xd2,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
969
{ "lle",        0xd3,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
970
{ "llt",        0xd0,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
971
{ "lhi",        0xd5,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
972
{ "lcc",        0xd6,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
973
{ "lls",        0xd7,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
974
{ "lcs",        0xd4,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
975
{ "lra",        0xda,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
976
{ "setlb",      0xdb,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
977
 
978
{ "fbeq",       0xf8d000,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
979
{ "fbne",       0xf8d100,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
980
{ "fbgt",       0xf8d200,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
981
{ "fbge",       0xf8d300,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
982
{ "fblt",       0xf8d400,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
983
{ "fble",       0xf8d500,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
984
{ "fbuo",       0xf8d600,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
985
{ "fblg",       0xf8d700,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
986
{ "fbleg",      0xf8d800,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
987
{ "fbug",       0xf8d900,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
988
{ "fbuge",      0xf8da00,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
989
{ "fbul",       0xf8db00,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
990
{ "fbule",      0xf8dc00,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
991
{ "fbue",       0xf8dd00,    0xffff00,    0,    FMT_D1, AM33_2,  {SD8N_PCREL}},
992
 
993
{ "fleq",       0xf0d0,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
994
{ "flne",       0xf0d1,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
995
{ "flgt",       0xf0d2,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
996
{ "flge",       0xf0d3,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
997
{ "fllt",       0xf0d4,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
998
{ "flle",       0xf0d5,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
999
{ "fluo",       0xf0d6,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
1000
{ "fllg",       0xf0d7,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
1001
{ "flleg",      0xf0d8,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
1002
{ "flug",       0xf0d9,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
1003
{ "fluge",      0xf0da,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
1004
{ "flul",       0xf0db,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
1005
{ "flule",      0xf0dc,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
1006
{ "flue",       0xf0dd,      0xffff,      0,    FMT_D0, AM33_2,  {UNUSED}},
1007
 
1008
{ "jmp",        0xf0f4,      0xfffc,      0,    FMT_D0, 0,        {PAREN,AN0,PAREN}},
1009
{ "jmp",        0xcc0000,    0xff0000,    0,    FMT_S2, 0,        {IMM16_PCREL}},
1010
{ "jmp",        0xdc000000,  0xff000000,  0,    FMT_S4, 0,        {IMM32_HIGH24}},
1011
{ "call",       0xcd000000,  0xff000000,  0,    FMT_S4, 0,        {D16_SHIFT,REGS,IMM8E}},
1012
{ "call",       0xdd000000,  0xff000000,  0,    FMT_S6, 0,        {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
1013
{ "calls",      0xf0f0,      0xfffc,      0,    FMT_D0, 0,        {PAREN,AN0,PAREN}},
1014
{ "calls",      0xfaff0000,  0xffff0000,  0,    FMT_D2, 0,        {IMM16_PCREL}},
1015
{ "calls",      0xfcff0000,  0xffff0000,  0,    FMT_D4, 0,        {IMM32_PCREL}},
1016
 
1017
{ "ret",        0xdf0000,    0xff0000,    0,    FMT_S2, 0,        {REGS_SHIFT8, IMM8}},
1018
{ "retf",       0xde0000,    0xff0000,    0,    FMT_S2, 0,        {REGS_SHIFT8, IMM8}},
1019
{ "rets",       0xf0fc,      0xffff,      0,    FMT_D0, 0,        {UNUSED}},
1020
{ "rti",        0xf0fd,      0xffff,      0,    FMT_D0, 0,        {UNUSED}},
1021
{ "trap",       0xf0fe,      0xffff,      0,    FMT_D0, 0,        {UNUSED}},
1022
{ "rtm",        0xf0ff,      0xffff,      0,    FMT_D0, 0,        {UNUSED}},
1023
{ "nop",        0xcb,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
1024
 
1025
{ "dcpf",       0xf9a600,    0xffff0f,    0,     FMT_D6, AM33_2,  {MEM (RM2)}},
1026
{ "dcpf",       0xf9a700,    0xffffff,    0,     FMT_D6, AM33_2,  {MEM (SP)}},
1027
{ "dcpf",       0xfba60000,  0xffff00ff,  0,     FMT_D7, AM33_2,  {MEM2 (RI,RM0)}},
1028
{ "dcpf",       0xfba70000,  0xffff0f00,  0,     FMT_D7, AM33_2,  {MEM2 (SD8,RM2)}},
1029
{ "dcpf",       0xfda70000,  0xffff0f00,  0,    FMT_D8, AM33_2,  {MEM2 (SD24,RM2)}},
1030
{ "dcpf",       0xfe460000,  0xffff0f00,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8,RM2)}},
1031
 
1032
{ "fmov",       0xf92000,    0xfffe00,    0,    FMT_D6, AM33_2,  {MEM (RM2), FSM0}},
1033
{ "fmov",       0xf92200,    0xfffe00,    0,    FMT_D6, AM33_2,  {MEMINC (RM2), FSM0}},
1034
{ "fmov",       0xf92400,    0xfffef0,    0,    FMT_D6, AM33_2,  {MEM (SP), FSM0}},
1035
{ "fmov",       0xf92600,    0xfffe00,    0,    FMT_D6, AM33_2,  {RM2, FSM0}},
1036
{ "fmov",       0xf93000,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, MEM (RM0)}},
1037
{ "fmov",       0xf93100,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, MEMINC (RM0)}},
1038
{ "fmov",       0xf93400,    0xfffd0f,    0,    FMT_D6, AM33_2,  {FSM1, MEM (SP)}},
1039
{ "fmov",       0xf93500,    0xfffd00,    0,    FMT_D6, AM33_2,  {FSM1, RM0}},
1040
{ "fmov",       0xf94000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
1041
{ "fmov",       0xf9a000,    0xfffe01,    0,    FMT_D6, AM33_2,  {MEM (RM2), FDM0}},
1042
{ "fmov",       0xf9a200,    0xfffe01,    0,    FMT_D6, AM33_2,  {MEMINC (RM2), FDM0}},
1043
{ "fmov",       0xf9a400,    0xfffef1,    0,    FMT_D6, AM33_2,  {MEM (SP), FDM0}},
1044
{ "fmov",       0xf9b000,    0xfffd10,    0,    FMT_D6, AM33_2,  {FDM1, MEM (RM0)}},
1045
{ "fmov",       0xf9b100,    0xfffd10,    0,    FMT_D6, AM33_2,  {FDM1, MEMINC (RM0)}},
1046
{ "fmov",       0xf9b400,    0xfffd1f,    0,    FMT_D6, AM33_2,  {FDM1, MEM (SP)}},
1047
{ "fmov",       0xf9b500,    0xffff0f,    0,    FMT_D6, AM33_2,  {RM2, FPCR}},
1048
{ "fmov",       0xf9b700,    0xfffff0,    0,    FMT_D6, AM33_2,  {FPCR, RM0}},
1049
{ "fmov",       0xf9c000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
1050
{ "fmov",       0xfb200000,  0xfffe0000,  0,    FMT_D7, AM33_2,  {MEM2 (SD8, RM2), FSM2}},
1051
{ "fmov",       0xfb220000,  0xfffe0000,  0,    FMT_D7, AM33_2,  {MEMINC2 (RM2, SIMM8), FSM2}},
1052
{ "fmov",       0xfb240000,  0xfffef000,  0,    FMT_D7, AM33_2,  {MEM2 (IMM8, SP), FSM2}},
1053
{ "fmov",       0xfb270000,  0xffff000d,  0,    FMT_D7, AM33_2,  {MEM2 (RI, RM0), FSN1}},
1054
{ "fmov",       0xfb300000,  0xfffd0000,  0,    FMT_D7, AM33_2,  {FSM3, MEM2 (SD8, RM0)}},
1055
{ "fmov",       0xfb310000,  0xfffd0000,  0,    FMT_D7, AM33_2,  {FSM3, MEMINC2 (RM0, SIMM8)}},
1056
{ "fmov",       0xfb340000,  0xfffd0f00,  0,    FMT_D7, AM33_2,  {FSM3, MEM2 (IMM8, SP)}},
1057
{ "fmov",       0xfb370000,  0xffff000d,  0,    FMT_D7, AM33_2,  {FSN1, MEM2(RI, RM0)}},
1058
  /* FIXME: the spec doesn't say the fd register must be even for the
1059
   * next two insns.  Assuming it was a mistake in the spec.  */
1060
{ "fmov",       0xfb470000,  0xffff001d,  0,    FMT_D7, AM33_2,  {MEM2 (RI, RM0), FDN1}},
1061
{ "fmov",       0xfb570000,  0xffff001d,  0,    FMT_D7, AM33_2,  {FDN1, MEM2(RI, RM0)}},
1062
  /* END of FIXME */
1063
{ "fmov",       0xfba00000,  0xfffe0100,  0,    FMT_D7, AM33_2,  {MEM2 (SD8, RM2), FDM2}},
1064
{ "fmov",       0xfba20000,  0xfffe0100,  0,    FMT_D7, AM33_2,  {MEMINC2 (RM2, SIMM8), FDM2}},
1065
{ "fmov",       0xfba40000,  0xfffef100,  0,    FMT_D7, AM33_2,  {MEM2 (IMM8, SP), FDM2}},
1066
{ "fmov",       0xfbb00000,  0xfffd1000,  0,    FMT_D7, AM33_2,  {FDM3, MEM2 (SD8, RM0)}},
1067
{ "fmov",       0xfbb10000,  0xfffd1000,  0,    FMT_D7, AM33_2,  {FDM3, MEMINC2 (RM0, SIMM8)}},
1068
{ "fmov",       0xfbb40000,  0xfffd1f00,  0,    FMT_D7, AM33_2,  {FDM3, MEM2 (IMM8, SP)}},
1069
{ "fmov",       0xfd200000,  0xfffe0000,  0,    FMT_D8, AM33_2,  {MEM2 (SIMM24, RM2), FSM2}},
1070
{ "fmov",       0xfd220000,  0xfffe0000,  0,    FMT_D8, AM33_2,  {MEMINC2 (RM2, SIMM24), FSM2}},
1071
{ "fmov",       0xfd240000,  0xfffef000,  0,    FMT_D8, AM33_2,  {MEM2 (IMM24, SP), FSM2}},
1072
{ "fmov",       0xfd300000,  0xfffd0000,  0,    FMT_D8, AM33_2,  {FSM3, MEM2 (SIMM24, RM0)}},
1073
{ "fmov",       0xfd310000,  0xfffd0000,  0,    FMT_D8, AM33_2,  {FSM3, MEMINC2 (RM0, SIMM24)}},
1074
{ "fmov",       0xfd340000,  0xfffd0f00,  0,    FMT_D8, AM33_2,  {FSM3, MEM2 (IMM24, SP)}},
1075
{ "fmov",       0xfda00000,  0xfffe0100,  0,    FMT_D8, AM33_2,  {MEM2 (SIMM24, RM2), FDM2}},
1076
{ "fmov",       0xfda20000,  0xfffe0100,  0,    FMT_D8, AM33_2,  {MEMINC2 (RM2, SIMM24), FDM2}},
1077
{ "fmov",       0xfda40000,  0xfffef100,  0,    FMT_D8, AM33_2,  {MEM2 (IMM24, SP), FDM2}},
1078
{ "fmov",       0xfdb00000,  0xfffd1000,  0,    FMT_D8, AM33_2,  {FDM3, MEM2 (SIMM24, RM0)}},
1079
{ "fmov",       0xfdb10000,  0xfffd1000,  0,    FMT_D8, AM33_2,  {FDM3, MEMINC2 (RM0, SIMM24)}},
1080
{ "fmov",       0xfdb40000,  0xfffd1f00,  0,    FMT_D8, AM33_2,  {FDM3, MEM2 (IMM24, SP)}},
1081
{ "fmov",       0xfdb50000,  0xffff0000,  0,    FMT_D4, AM33_2,  {IMM32, FPCR}},
1082
{ "fmov",       0xfe200000,  0xfffe0000,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8, RM2), FSM2}},
1083
{ "fmov",       0xfe220000,  0xfffe0000,  0,    FMT_D9, AM33_2,  {MEMINC2 (RM2, IMM32_HIGH8), FSM2}},
1084
{ "fmov",       0xfe240000,  0xfffef000,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8, SP), FSM2}},
1085
{ "fmov",       0xfe260000,  0xfffef000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM2}},
1086
{ "fmov",       0xfe300000,  0xfffd0000,  0,    FMT_D9, AM33_2,  {FSM3, MEM2 (IMM32_HIGH8, RM0)}},
1087
{ "fmov",       0xfe310000,  0xfffd0000,  0,    FMT_D9, AM33_2,  {FSM3, MEMINC2 (RM0, IMM32_HIGH8)}},
1088
{ "fmov",       0xfe340000,  0xfffd0f00,  0,    FMT_D9, AM33_2,  {FSM3, MEM2 (IMM32_HIGH8, SP)}},
1089
{ "fmov",       0xfe400000,  0xfffe0100,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8, RM2), FDM2}},
1090
{ "fmov",       0xfe420000,  0xfffe0100,  0,    FMT_D9, AM33_2,  {MEMINC2 (RM2, IMM32_HIGH8), FDM2}},
1091
{ "fmov",       0xfe440000,  0xfffef100,  0,    FMT_D9, AM33_2,  {MEM2 (IMM32_HIGH8, SP), FDM2}},
1092
{ "fmov",       0xfe500000,  0xfffd1000,  0,    FMT_D9, AM33_2,  {FDM3, MEM2 (IMM32_HIGH8, RM0)}},
1093
{ "fmov",       0xfe510000,  0xfffd1000,  0,    FMT_D9, AM33_2,  {FDM3, MEMINC2 (RM0, IMM32_HIGH8)}},
1094
{ "fmov",       0xfe540000,  0xfffd1f00,  0,    FMT_D9, AM33_2,  {FDM3, MEM2 (IMM32_HIGH8, SP)}},
1095
 
1096
  /* FIXME: these are documented in the instruction bitmap, but not in
1097
   * the instruction manual.  */
1098
{ "ftoi",       0xfb400000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
1099
{ "itof",       0xfb420000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
1100
{ "ftod",       0xfb520000,  0xffff0f15,  0,    FMT_D10,AM33_2,  {FSN3, FDN1}},
1101
{ "dtof",       0xfb560000,  0xffff1f05,  0,    FMT_D10,AM33_2,  {FDN3, FSN1}},
1102
  /* END of FIXME */
1103
 
1104
{ "fabs",       0xfb440000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
1105
{ "fabs",       0xfbc40000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
1106
{ "fabs",       0xf94400,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
1107
{ "fabs",       0xf9c400,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
1108
 
1109
{ "fneg",       0xfb460000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
1110
{ "fneg",       0xfbc60000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
1111
{ "fneg",       0xf94600,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
1112
{ "fneg",       0xf9c600,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
1113
 
1114
{ "frsqrt",     0xfb500000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
1115
{ "frsqrt",     0xfbd00000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
1116
{ "frsqrt",     0xf95000,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
1117
{ "frsqrt",     0xf9d000,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
1118
 
1119
  /* FIXME: this is documented in the instruction bitmap, but not in
1120
   * the instruction manual.  */
1121
{ "fsqrt",      0xfb540000,  0xffff0f05,  0,    FMT_D10,AM33_2,  {FSN3, FSN1}},
1122
{ "fsqrt",      0xfbd40000,  0xffff1f15,  0,    FMT_D10,AM33_2,  {FDN3, FDN1}},
1123
{ "fsqrt",      0xf95200,    0xfffef0,    0,    FMT_D6, AM33_2,  {FSM0}},
1124
{ "fsqrt",      0xf9d200,    0xfffef1,    0,    FMT_D6, AM33_2,  {FDM0}},
1125
  /* END of FIXME */
1126
 
1127
{ "fcmp",       0xf95400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
1128
{ "fcmp",       0xf9d400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
1129
{ "fcmp",       0xfe350000,  0xfffd0f00,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3}},
1130
 
1131
{ "fadd",       0xfb600000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
1132
{ "fadd",       0xfbe00000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
1133
{ "fadd",       0xf96000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
1134
{ "fadd",       0xf9e000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
1135
{ "fadd",       0xfe600000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
1136
 
1137
{ "fsub",       0xfb640000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
1138
{ "fsub",       0xfbe40000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
1139
{ "fsub",       0xf96400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
1140
{ "fsub",       0xf9e400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
1141
{ "fsub",       0xfe640000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
1142
 
1143
{ "fmul",       0xfb700000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
1144
{ "fmul",       0xfbf00000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
1145
{ "fmul",       0xf97000,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
1146
{ "fmul",       0xf9f000,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
1147
{ "fmul",       0xfe700000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
1148
 
1149
{ "fdiv",       0xfb740000,  0xffff0001,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1}},
1150
{ "fdiv",       0xfbf40000,  0xffff1111,  0,    FMT_D10,AM33_2,  {FDN3, FDN2, FDN1}},
1151
{ "fdiv",       0xf97400,    0xfffc00,    0,    FMT_D6, AM33_2,  {FSM1, FSM0}},
1152
{ "fdiv",       0xf9f400,    0xfffc11,    0,    FMT_D6, AM33_2,  {FDM1, FDM0}},
1153
{ "fdiv",       0xfe740000,  0xfffc0000,  0,    FMT_D9, AM33_2,  {IMM32_HIGH8, FSM3, FSM2}},
1154
 
1155
{ "fmadd",      0xfb800000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
1156
{ "fmsub",      0xfb840000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
1157
{ "fnmadd",     0xfb900000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
1158
{ "fnmsub",     0xfb940000,  0xfffc0000,  0,    FMT_D10,AM33_2,  {FSN3, FSN2, FSN1, FSACC}},
1159
 
1160
/* UDF instructions.  */
1161
{ "udf00",      0xf600,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1162
{ "udf00",      0xf90000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1163
{ "udf00",      0xfb000000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1164
{ "udf00",      0xfd000000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1165
{ "udf01",      0xf610,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1166
{ "udf01",      0xf91000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1167
{ "udf01",      0xfb100000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1168
{ "udf01",      0xfd100000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1169
{ "udf02",      0xf620,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1170
{ "udf02",      0xf92000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1171
{ "udf02",      0xfb200000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1172
{ "udf02",      0xfd200000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1173
{ "udf03",      0xf630,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1174
{ "udf03",      0xf93000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1175
{ "udf03",      0xfb300000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1176
{ "udf03",      0xfd300000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1177
{ "udf04",      0xf640,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1178
{ "udf04",      0xf94000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1179
{ "udf04",      0xfb400000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1180
{ "udf04",      0xfd400000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1181
{ "udf05",      0xf650,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1182
{ "udf05",      0xf95000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1183
{ "udf05",      0xfb500000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1184
{ "udf05",      0xfd500000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1185
{ "udf06",      0xf660,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1186
{ "udf06",      0xf96000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1187
{ "udf06",      0xfb600000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1188
{ "udf06",      0xfd600000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1189
{ "udf07",      0xf670,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1190
{ "udf07",      0xf97000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1191
{ "udf07",      0xfb700000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1192
{ "udf07",      0xfd700000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1193
{ "udf08",      0xf680,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1194
{ "udf08",      0xf98000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1195
{ "udf08",      0xfb800000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1196
{ "udf08",      0xfd800000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1197
{ "udf09",      0xf690,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1198
{ "udf09",      0xf99000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1199
{ "udf09",      0xfb900000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1200
{ "udf09",      0xfd900000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1201
{ "udf10",      0xf6a0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1202
{ "udf10",      0xf9a000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1203
{ "udf10",      0xfba00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1204
{ "udf10",      0xfda00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1205
{ "udf11",      0xf6b0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1206
{ "udf11",      0xf9b000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1207
{ "udf11",      0xfbb00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1208
{ "udf11",      0xfdb00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1209
{ "udf12",      0xf6c0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1210
{ "udf12",      0xf9c000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1211
{ "udf12",      0xfbc00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1212
{ "udf12",      0xfdc00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1213
{ "udf13",      0xf6d0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1214
{ "udf13",      0xf9d000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1215
{ "udf13",      0xfbd00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1216
{ "udf13",      0xfdd00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1217
{ "udf14",      0xf6e0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1218
{ "udf14",      0xf9e000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1219
{ "udf14",      0xfbe00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1220
{ "udf14",      0xfde00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1221
{ "udf15",      0xf6f0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1222
{ "udf15",      0xf9f000,    0xfffc00,    0,    FMT_D1, 0,        {SIMM8, DN0}},
1223
{ "udf15",      0xfbf00000,  0xfffc0000,  0,    FMT_D2, 0,      {SIMM16, DN0}},
1224
{ "udf15",      0xfdf00000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1225
{ "udf20",      0xf500,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1226
{ "udf21",      0xf510,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1227
{ "udf22",      0xf520,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1228
{ "udf23",      0xf530,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1229
{ "udf24",      0xf540,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1230
{ "udf25",      0xf550,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1231
{ "udf26",      0xf560,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1232
{ "udf27",      0xf570,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1233
{ "udf28",      0xf580,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1234
{ "udf29",      0xf590,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1235
{ "udf30",      0xf5a0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1236
{ "udf31",      0xf5b0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1237
{ "udf32",      0xf5c0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1238
{ "udf33",      0xf5d0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1239
{ "udf34",      0xf5e0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1240
{ "udf35",      0xf5f0,      0xfff0,      0,    FMT_D0, 0,        {DM1, DN0}},
1241
{ "udfu00",     0xf90400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1242
{ "udfu00",     0xfb040000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1243
{ "udfu00",     0xfd040000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1244
{ "udfu01",     0xf91400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1245
{ "udfu01",     0xfb140000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1246
{ "udfu01",     0xfd140000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1247
{ "udfu02",     0xf92400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1248
{ "udfu02",     0xfb240000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1249
{ "udfu02",     0xfd240000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1250
{ "udfu03",     0xf93400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1251
{ "udfu03",     0xfb340000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1252
{ "udfu03",     0xfd340000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1253
{ "udfu04",     0xf94400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1254
{ "udfu04",     0xfb440000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1255
{ "udfu04",     0xfd440000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1256
{ "udfu05",     0xf95400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1257
{ "udfu05",     0xfb540000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1258
{ "udfu05",     0xfd540000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1259
{ "udfu06",     0xf96400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1260
{ "udfu06",     0xfb640000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1261
{ "udfu06",     0xfd640000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1262
{ "udfu07",     0xf97400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1263
{ "udfu07",     0xfb740000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1264
{ "udfu07",     0xfd740000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1265
{ "udfu08",     0xf98400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1266
{ "udfu08",     0xfb840000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1267
{ "udfu08",     0xfd840000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1268
{ "udfu09",     0xf99400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1269
{ "udfu09",     0xfb940000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1270
{ "udfu09",     0xfd940000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1271
{ "udfu10",     0xf9a400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1272
{ "udfu10",     0xfba40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1273
{ "udfu10",     0xfda40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1274
{ "udfu11",     0xf9b400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1275
{ "udfu11",     0xfbb40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1276
{ "udfu11",     0xfdb40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1277
{ "udfu12",     0xf9c400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1278
{ "udfu12",     0xfbc40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1279
{ "udfu12",     0xfdc40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1280
{ "udfu13",     0xf9d400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1281
{ "udfu13",     0xfbd40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1282
{ "udfu13",     0xfdd40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1283
{ "udfu14",     0xf9e400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1284
{ "udfu14",     0xfbe40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1285
{ "udfu14",     0xfde40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1286
{ "udfu15",     0xf9f400,    0xfffc00,    0,    FMT_D1, 0,        {IMM8, DN0}},
1287
{ "udfu15",     0xfbf40000,  0xfffc0000,  0,    FMT_D2, 0,      {IMM16, DN0}},
1288
{ "udfu15",     0xfdf40000,  0xfffc0000,  0,    FMT_D4, 0,        {IMM32, DN0}},
1289
 
1290
{ "putx",       0xf500,      0xfff0,      0,    FMT_D0, AM30,    {DN01}},
1291
{ "getx",       0xf6f0,      0xfff0,      0,    FMT_D0, AM30,    {DN01}},
1292
{ "mulq",       0xf600,      0xfff0,      0,    FMT_D0, AM30,    {DM1, DN0}},
1293
{ "mulq",       0xf90000,    0xfffc00,    0,    FMT_D1, AM30,    {SIMM8, DN0}},
1294
{ "mulq",       0xfb000000,  0xfffc0000,  0,    FMT_D2, AM30,    {SIMM16, DN0}},
1295
{ "mulq",       0xfd000000,  0xfffc0000,  0,    FMT_D4, AM30,    {IMM32, DN0}},
1296
{ "mulqu",      0xf610,      0xfff0,      0,    FMT_D0, AM30,    {DM1, DN0}},
1297
{ "mulqu",      0xf91400,    0xfffc00,    0,    FMT_D1, AM30,    {SIMM8, DN0}},
1298
{ "mulqu",      0xfb140000,  0xfffc0000,  0,    FMT_D2, AM30,    {SIMM16, DN0}},
1299
{ "mulqu",      0xfd140000,  0xfffc0000,  0,    FMT_D4, AM30,    {IMM32, DN0}},
1300
{ "sat16",      0xf640,      0xfff0,      0,    FMT_D0, AM30,    {DM1, DN0}},
1301
{ "sat16",      0xf9ab00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
1302
 
1303
{ "sat24",      0xf650,      0xfff0,      0,    FMT_D0, AM30,    {DM1, DN0}},
1304
{ "sat24",      0xfbaf0000,  0xffff00ff,  0,    FMT_D7, AM33,    {RM2, RN0}},
1305
 
1306
{ "bsch",       0xfbff0000,  0xffff000f,  0,    FMT_D7, AM33,    {RM2, RN0, RD2}},
1307
{ "bsch",       0xf670,      0xfff0,      0,    FMT_D0, AM30,    {DM1, DN0}},
1308
{ "bsch",       0xf9fb00,    0xffff00,    0,    FMT_D6, AM33,    {RM2, RN0}},
1309
 
1310
/* Extension.  We need some instruction to trigger "emulated syscalls"
1311
   for our simulator.  */
1312
{ "syscall",    0xf0e0,      0xfff0,      0,    FMT_D0, AM33,    {IMM4}},
1313
{ "syscall",    0xf0c0,      0xffff,      0,    FMT_D0, 0,        {UNUSED}},
1314
 
1315
/* Extension.  When talking to the simulator, gdb requires some instruction
1316
   that will trigger a "breakpoint" (really just an instruction that isn't
1317
   otherwise used by the tools.  This instruction must be the same size
1318
   as the smallest instruction on the target machine.  In the case of the
1319
   mn10x00 the "break" instruction must be one byte.  0xff is available on
1320
   both mn10x00 architectures.  */
1321
{ "break",      0xff,        0xff,        0,    FMT_S0, 0,        {UNUSED}},
1322
 
1323
{ "add_add",    0xf7000000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1324
{ "add_add",    0xf7100000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1325
{ "add_add",    0xf7040000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1326
{ "add_add",    0xf7140000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1327
{ "add_sub",    0xf7200000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1328
{ "add_sub",    0xf7300000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1329
{ "add_sub",    0xf7240000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1330
{ "add_sub",    0xf7340000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1331
{ "add_cmp",    0xf7400000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1332
{ "add_cmp",    0xf7500000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1333
{ "add_cmp",    0xf7440000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1334
{ "add_cmp",    0xf7540000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1335
{ "add_mov",    0xf7600000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1336
{ "add_mov",    0xf7700000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1337
{ "add_mov",    0xf7640000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1338
{ "add_mov",    0xf7740000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1339
{ "add_asr",    0xf7800000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1340
{ "add_asr",    0xf7900000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1341
{ "add_asr",    0xf7840000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1342
{ "add_asr",    0xf7940000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1343
{ "add_lsr",    0xf7a00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1344
{ "add_lsr",    0xf7b00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1345
{ "add_lsr",    0xf7a40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1346
{ "add_lsr",    0xf7b40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1347
{ "add_asl",    0xf7c00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1348
{ "add_asl",    0xf7d00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1349
{ "add_asl",    0xf7c40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1350
{ "add_asl",    0xf7d40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1351
{ "cmp_add",    0xf7010000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1352
{ "cmp_add",    0xf7110000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1353
{ "cmp_add",    0xf7050000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1354
{ "cmp_add",    0xf7150000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1355
{ "cmp_sub",    0xf7210000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1356
{ "cmp_sub",    0xf7310000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1357
{ "cmp_sub",    0xf7250000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1358
{ "cmp_sub",    0xf7350000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1359
{ "cmp_mov",    0xf7610000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1360
{ "cmp_mov",    0xf7710000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1361
{ "cmp_mov",    0xf7650000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1362
{ "cmp_mov",    0xf7750000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1363
{ "cmp_asr",    0xf7810000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1364
{ "cmp_asr",    0xf7910000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1365
{ "cmp_asr",    0xf7850000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1366
{ "cmp_asr",    0xf7950000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1367
{ "cmp_lsr",    0xf7a10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1368
{ "cmp_lsr",    0xf7b10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1369
{ "cmp_lsr",    0xf7a50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1370
{ "cmp_lsr",    0xf7b50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1371
{ "cmp_asl",    0xf7c10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1372
{ "cmp_asl",    0xf7d10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1373
{ "cmp_asl",    0xf7c50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1374
{ "cmp_asl",    0xf7d50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1375
{ "sub_add",    0xf7020000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1376
{ "sub_add",    0xf7120000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1377
{ "sub_add",    0xf7060000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1378
{ "sub_add",    0xf7160000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1379
{ "sub_sub",    0xf7220000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1380
{ "sub_sub",    0xf7320000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1381
{ "sub_sub",    0xf7260000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1382
{ "sub_sub",    0xf7360000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1383
{ "sub_cmp",    0xf7420000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1384
{ "sub_cmp",    0xf7520000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1385
{ "sub_cmp",    0xf7460000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1386
{ "sub_cmp",    0xf7560000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1387
{ "sub_mov",    0xf7620000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1388
{ "sub_mov",    0xf7720000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1389
{ "sub_mov",    0xf7660000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1390
{ "sub_mov",    0xf7760000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1391
{ "sub_asr",    0xf7820000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1392
{ "sub_asr",    0xf7920000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1393
{ "sub_asr",    0xf7860000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1394
{ "sub_asr",    0xf7960000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1395
{ "sub_lsr",    0xf7a20000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1396
{ "sub_lsr",    0xf7b20000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1397
{ "sub_lsr",    0xf7a60000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1398
{ "sub_lsr",    0xf7b60000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1399
{ "sub_asl",    0xf7c20000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1400
{ "sub_asl",    0xf7d20000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1401
{ "sub_asl",    0xf7c60000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1402
{ "sub_asl",    0xf7d60000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1403
{ "mov_add",    0xf7030000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1404
{ "mov_add",    0xf7130000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1405
{ "mov_add",    0xf7070000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1406
{ "mov_add",    0xf7170000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1407
{ "mov_sub",    0xf7230000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1408
{ "mov_sub",    0xf7330000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1409
{ "mov_sub",    0xf7270000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1410
{ "mov_sub",    0xf7370000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1411
{ "mov_cmp",    0xf7430000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1412
{ "mov_cmp",    0xf7530000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1413
{ "mov_cmp",    0xf7470000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1414
{ "mov_cmp",    0xf7570000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1415
{ "mov_mov",    0xf7630000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1416
{ "mov_mov",    0xf7730000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1417
{ "mov_mov",    0xf7670000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1418
{ "mov_mov",    0xf7770000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, SIMM4_2, RN0}},
1419
{ "mov_asr",    0xf7830000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1420
{ "mov_asr",    0xf7930000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1421
{ "mov_asr",    0xf7870000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1422
{ "mov_asr",    0xf7970000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1423
{ "mov_lsr",    0xf7a30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1424
{ "mov_lsr",    0xf7b30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1425
{ "mov_lsr",    0xf7a70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1426
{ "mov_lsr",    0xf7b70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1427
{ "mov_asl",    0xf7c30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1428
{ "mov_asl",    0xf7d30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1429
{ "mov_asl",    0xf7c70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, RM2, RN0}},
1430
{ "mov_asl",    0xf7d70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_6, RN4, IMM4_2, RN0}},
1431
{ "and_add",    0xf7080000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1432
{ "and_add",    0xf7180000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1433
{ "and_sub",    0xf7280000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1434
{ "and_sub",    0xf7380000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1435
{ "and_cmp",    0xf7480000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1436
{ "and_cmp",    0xf7580000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1437
{ "and_mov",    0xf7680000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1438
{ "and_mov",    0xf7780000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1439
{ "and_asr",    0xf7880000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1440
{ "and_asr",    0xf7980000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1441
{ "and_lsr",    0xf7a80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1442
{ "and_lsr",    0xf7b80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1443
{ "and_asl",    0xf7c80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1444
{ "and_asl",    0xf7d80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1445
{ "dmach_add",  0xf7090000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1446
{ "dmach_add",  0xf7190000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1447
{ "dmach_sub",  0xf7290000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1448
{ "dmach_sub",  0xf7390000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1449
{ "dmach_cmp",  0xf7490000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1450
{ "dmach_cmp",  0xf7590000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1451
{ "dmach_mov",  0xf7690000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1452
{ "dmach_mov",  0xf7790000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1453
{ "dmach_asr",  0xf7890000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1454
{ "dmach_asr",  0xf7990000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1455
{ "dmach_lsr",  0xf7a90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1456
{ "dmach_lsr",  0xf7b90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1457
{ "dmach_asl",  0xf7c90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1458
{ "dmach_asl",  0xf7d90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1459
{ "xor_add",    0xf70a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1460
{ "xor_add",    0xf71a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1461
{ "xor_sub",    0xf72a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1462
{ "xor_sub",    0xf73a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1463
{ "xor_cmp",    0xf74a0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1464
{ "xor_cmp",    0xf75a0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1465
{ "xor_mov",    0xf76a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1466
{ "xor_mov",    0xf77a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1467
{ "xor_asr",    0xf78a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1468
{ "xor_asr",    0xf79a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1469
{ "xor_lsr",    0xf7aa0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1470
{ "xor_lsr",    0xf7ba0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1471
{ "xor_asl",    0xf7ca0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1472
{ "xor_asl",    0xf7da0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1473
{ "swhw_add",   0xf70b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1474
{ "swhw_add",   0xf71b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1475
{ "swhw_sub",   0xf72b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1476
{ "swhw_sub",   0xf73b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1477
{ "swhw_cmp",   0xf74b0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1478
{ "swhw_cmp",   0xf75b0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1479
{ "swhw_mov",   0xf76b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1480
{ "swhw_mov",   0xf77b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1481
{ "swhw_asr",   0xf78b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1482
{ "swhw_asr",   0xf79b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1483
{ "swhw_lsr",   0xf7ab0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1484
{ "swhw_lsr",   0xf7bb0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1485
{ "swhw_asl",   0xf7cb0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1486
{ "swhw_asl",   0xf7db0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1487
{ "or_add",     0xf70c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1488
{ "or_add",     0xf71c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1489
{ "or_sub",     0xf72c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1490
{ "or_sub",     0xf73c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1491
{ "or_cmp",     0xf74c0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1492
{ "or_cmp",     0xf75c0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1493
{ "or_mov",     0xf76c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1494
{ "or_mov",     0xf77c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1495
{ "or_asr",     0xf78c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1496
{ "or_asr",     0xf79c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1497
{ "or_lsr",     0xf7ac0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1498
{ "or_lsr",     0xf7bc0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1499
{ "or_asl",     0xf7cc0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1500
{ "or_asl",     0xf7dc0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1501
{ "sat16_add",  0xf70d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1502
{ "sat16_add",  0xf71d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1503
{ "sat16_sub",  0xf72d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1504
{ "sat16_sub",  0xf73d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1505
{ "sat16_cmp",  0xf74d0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1506
{ "sat16_cmp",  0xf75d0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1507
{ "sat16_mov",  0xf76d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1508
{ "sat16_mov",  0xf77d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, SIMM4_2, RN0}},
1509
{ "sat16_asr",  0xf78d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1510
{ "sat16_asr",  0xf79d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1511
{ "sat16_lsr",  0xf7ad0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1512
{ "sat16_lsr",  0xf7bd0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1513
{ "sat16_asl",  0xf7cd0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, RM2, RN0}},
1514
{ "sat16_asl",  0xf7dd0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM6, RN4, IMM4_2, RN0}},
1515
/* Ugh.  Synthetic instructions.  */
1516
{ "add_and",    0xf7080000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1517
{ "add_and",    0xf7180000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1518
{ "add_dmach",  0xf7090000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1519
{ "add_dmach",  0xf7190000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1520
{ "add_or",     0xf70c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1521
{ "add_or",     0xf71c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1522
{ "add_sat16",  0xf70d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1523
{ "add_sat16",  0xf71d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1524
{ "add_swhw",   0xf70b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1525
{ "add_swhw",   0xf71b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1526
{ "add_xor",    0xf70a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1527
{ "add_xor",    0xf71a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1528
{ "asl_add",    0xf7c00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1529
{ "asl_add",    0xf7d00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1530
{ "asl_add",    0xf7c40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1531
{ "asl_add",    0xf7d40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1532
{ "asl_and",    0xf7c80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1533
{ "asl_and",    0xf7d80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1534
{ "asl_cmp",    0xf7c10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1535
{ "asl_cmp",    0xf7d10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
1536
{ "asl_cmp",    0xf7c50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1537
{ "asl_cmp",    0xf7d50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1538
{ "asl_dmach",  0xf7c90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1539
{ "asl_dmach",  0xf7d90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1540
{ "asl_mov",    0xf7c30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1541
{ "asl_mov",    0xf7d30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1542
{ "asl_mov",    0xf7c70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1543
{ "asl_mov",    0xf7d70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1544
{ "asl_or",     0xf7cc0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1545
{ "asl_or",     0xf7dc0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1546
{ "asl_sat16",  0xf7cd0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1547
{ "asl_sat16",  0xf7dd0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1548
{ "asl_sub",    0xf7c20000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1549
{ "asl_sub",    0xf7d20000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1550
{ "asl_sub",    0xf7c60000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1551
{ "asl_sub",    0xf7d60000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1552
{ "asl_swhw",   0xf7cb0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1553
{ "asl_swhw",   0xf7db0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1554
{ "asl_xor",    0xf7ca0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1555
{ "asl_xor",    0xf7da0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1556
{ "asr_add",    0xf7800000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1557
{ "asr_add",    0xf7900000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1558
{ "asr_add",    0xf7840000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1559
{ "asr_add",    0xf7940000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1560
{ "asr_and",    0xf7880000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1561
{ "asr_and",    0xf7980000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1562
{ "asr_cmp",    0xf7810000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1563
{ "asr_cmp",    0xf7910000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
1564
{ "asr_cmp",    0xf7850000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1565
{ "asr_cmp",    0xf7950000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1566
{ "asr_dmach",  0xf7890000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1567
{ "asr_dmach",  0xf7990000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1568
{ "asr_mov",    0xf7830000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1569
{ "asr_mov",    0xf7930000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1570
{ "asr_mov",    0xf7870000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1571
{ "asr_mov",    0xf7970000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1572
{ "asr_or",     0xf78c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1573
{ "asr_or",     0xf79c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1574
{ "asr_sat16",  0xf78d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1575
{ "asr_sat16",  0xf79d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1576
{ "asr_sub",    0xf7820000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1577
{ "asr_sub",    0xf7920000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1578
{ "asr_sub",    0xf7860000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1579
{ "asr_sub",    0xf7960000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1580
{ "asr_swhw",   0xf78b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1581
{ "asr_swhw",   0xf79b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1582
{ "asr_xor",    0xf78a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1583
{ "asr_xor",    0xf79a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1584
{ "cmp_and",    0xf7480000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1585
{ "cmp_and",    0xf7580000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1586
{ "cmp_dmach",  0xf7490000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1587
{ "cmp_dmach",  0xf7590000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1588
{ "cmp_or",     0xf74c0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1589
{ "cmp_or",     0xf75c0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1590
{ "cmp_sat16",  0xf74d0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1591
{ "cmp_sat16",  0xf75d0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1592
{ "cmp_swhw",   0xf74b0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1593
{ "cmp_swhw",   0xf75b0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1594
{ "cmp_xor",    0xf74a0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1595
{ "cmp_xor",    0xf75a0000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1596
{ "lsr_add",    0xf7a00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1597
{ "lsr_add",    0xf7b00000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1598
{ "lsr_add",    0xf7a40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1599
{ "lsr_add",    0xf7b40000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1600
{ "lsr_and",    0xf7a80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1601
{ "lsr_and",    0xf7b80000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1602
{ "lsr_cmp",    0xf7a10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1603
{ "lsr_cmp",    0xf7b10000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4, }},
1604
{ "lsr_cmp",    0xf7a50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1605
{ "lsr_cmp",    0xf7b50000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1606
{ "lsr_dmach",  0xf7a90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1607
{ "lsr_dmach",  0xf7b90000,  0xffff0000,  0x0,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1608
{ "lsr_mov",    0xf7a30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1609
{ "lsr_mov",    0xf7b30000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1610
{ "lsr_mov",    0xf7a70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1611
{ "lsr_mov",    0xf7b70000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1612
{ "lsr_or",     0xf7ac0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1613
{ "lsr_or",     0xf7bc0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1614
{ "lsr_sat16",  0xf7ad0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1615
{ "lsr_sat16",  0xf7bd0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1616
{ "lsr_sub",    0xf7a20000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1617
{ "lsr_sub",    0xf7b20000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1618
{ "lsr_sub",    0xf7a60000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, SIMM4_6, RN4}},
1619
{ "lsr_sub",    0xf7b60000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, SIMM4_6, RN4}},
1620
{ "lsr_swhw",   0xf7ab0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1621
{ "lsr_swhw",   0xf7bb0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1622
{ "lsr_xor",    0xf7aa0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1623
{ "lsr_xor",    0xf7ba0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {IMM4_2, RN0, RM6, RN4}},
1624
{ "mov_and",    0xf7680000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1625
{ "mov_and",    0xf7780000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1626
{ "mov_dmach",  0xf7690000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1627
{ "mov_dmach",  0xf7790000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1628
{ "mov_or",     0xf76c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1629
{ "mov_or",     0xf77c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1630
{ "mov_sat16",  0xf76d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1631
{ "mov_sat16",  0xf77d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1632
{ "mov_swhw",   0xf76b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1633
{ "mov_swhw",   0xf77b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1634
{ "mov_xor",    0xf76a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1635
{ "mov_xor",    0xf77a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1636
{ "sub_and",    0xf7280000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1637
{ "sub_and",    0xf7380000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1638
{ "sub_dmach",  0xf7290000,  0xffff0000,  0x0,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1639
{ "sub_dmach",  0xf7390000,  0xffff0000,  0x0,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1640
{ "sub_or",     0xf72c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1641
{ "sub_or",     0xf73c0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1642
{ "sub_sat16",  0xf72d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1643
{ "sub_sat16",  0xf73d0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1644
{ "sub_swhw",   0xf72b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1645
{ "sub_swhw",   0xf73b0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1646
{ "sub_xor",    0xf72a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {RM2, RN0, RM6, RN4}},
1647
{ "sub_xor",    0xf73a0000,  0xffff0000,  0xa,  FMT_D10, AM33,   {SIMM4_2, RN0, RM6, RN4}},
1648
{ "mov_llt",    0xf7e00000,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1649
{ "mov_lgt",    0xf7e00001,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1650
{ "mov_lge",    0xf7e00002,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1651
{ "mov_lle",    0xf7e00003,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1652
{ "mov_lcs",    0xf7e00004,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1653
{ "mov_lhi",    0xf7e00005,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1654
{ "mov_lcc",    0xf7e00006,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1655
{ "mov_lls",    0xf7e00007,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1656
{ "mov_leq",    0xf7e00008,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1657
{ "mov_lne",    0xf7e00009,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1658
{ "mov_lra",    0xf7e0000a,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1659
{ "llt_mov",    0xf7e00000,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1660
{ "lgt_mov",    0xf7e00001,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1661
{ "lge_mov",    0xf7e00002,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1662
{ "lle_mov",    0xf7e00003,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1663
{ "lcs_mov",    0xf7e00004,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1664
{ "lhi_mov",    0xf7e00005,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1665
{ "lcc_mov",    0xf7e00006,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1666
{ "lls_mov",    0xf7e00007,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1667
{ "leq_mov",    0xf7e00008,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1668
{ "lne_mov",    0xf7e00009,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1669
{ "lra_mov",    0xf7e0000a,  0xffff000f,  0x22, FMT_D10, AM33,   {MEMINC2 (RN4,SIMM4_2), RM6}},
1670
 
1671
{ 0, 0, 0, 0, 0, 0, {0}},
1672
 
1673
} ;
1674
 
1675
const int mn10300_num_opcodes =
1676
  sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
1677
 
1678
 

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