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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [opcodes/] [mips-dis.c] - Blame information for rev 816

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1 38 julius
/* Print mips instructions for GDB, the GNU debugger, or for objdump.
2
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3
   2000, 2001, 2002, 2003, 2005, 2007, 2008
4
   Free Software Foundation, Inc.
5
   Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
 
7
   This file is part of the GNU opcodes library.
8
 
9
   This library is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License
20
   along with this program; if not, write to the Free Software
21
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22
   MA 02110-1301, USA.  */
23
 
24
#include "sysdep.h"
25
#include "dis-asm.h"
26
#include "libiberty.h"
27
#include "opcode/mips.h"
28
#include "opintl.h"
29
 
30
/* FIXME: These are needed to figure out if the code is mips16 or
31
   not. The low bit of the address is often a good indicator.  No
32
   symbol table is available when this code runs out in an embedded
33
   system as when it is used for disassembler support in a monitor.  */
34
 
35
#if !defined(EMBEDDED_ENV)
36
#define SYMTAB_AVAILABLE 1
37
#include "elf-bfd.h"
38
#include "elf/mips.h"
39
#endif
40
 
41
/* Mips instructions are at maximum this many bytes long.  */
42
#define INSNLEN 4
43
 
44
 
45
/* FIXME: These should be shared with gdb somehow.  */
46
 
47
struct mips_cp0sel_name
48
{
49
  unsigned int cp0reg;
50
  unsigned int sel;
51
  const char * const name;
52
};
53
 
54
/* The mips16 registers.  */
55
static const unsigned int mips16_to_32_reg_map[] =
56
{
57
  16, 17, 2, 3, 4, 5, 6, 7
58
};
59
 
60
#define mips16_reg_names(rn)    mips_gpr_names[mips16_to_32_reg_map[rn]]
61
 
62
 
63
static const char * const mips_gpr_names_numeric[32] =
64
{
65
  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
66
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
67
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
68
  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
69
};
70
 
71
static const char * const mips_gpr_names_oldabi[32] =
72
{
73
  "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
74
  "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
75
  "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
76
  "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
77
};
78
 
79
static const char * const mips_gpr_names_newabi[32] =
80
{
81
  "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
82
  "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
83
  "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
84
  "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
85
};
86
 
87
static const char * const mips_fpr_names_numeric[32] =
88
{
89
  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
90
  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91
  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92
  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93
};
94
 
95
static const char * const mips_fpr_names_32[32] =
96
{
97
  "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
98
  "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
99
  "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
100
  "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
101
};
102
 
103
static const char * const mips_fpr_names_n32[32] =
104
{
105
  "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
106
  "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
107
  "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
108
  "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
109
};
110
 
111
static const char * const mips_fpr_names_64[32] =
112
{
113
  "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
114
  "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
115
  "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
116
  "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
117
};
118
 
119
static const char * const mips_cp0_names_numeric[32] =
120
{
121
  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
122
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
123
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
124
  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
125
};
126
 
127
static const char * const mips_cp0_names_r3000[32] =
128
{
129
  "c0_index",     "c0_random",    "c0_entrylo",   "$3",
130
  "c0_context",   "$5",           "$6",           "$7",
131
  "c0_badvaddr",  "$9",           "c0_entryhi",   "$11",
132
  "c0_sr",        "c0_cause",     "c0_epc",       "c0_prid",
133
  "$16",          "$17",          "$18",          "$19",
134
  "$20",          "$21",          "$22",          "$23",
135
  "$24",          "$25",          "$26",          "$27",
136
  "$28",          "$29",          "$30",          "$31",
137
};
138
 
139
static const char * const mips_cp0_names_r4000[32] =
140
{
141
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
142
  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
143
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
144
  "c0_sr",        "c0_cause",     "c0_epc",       "c0_prid",
145
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
146
  "c0_xcontext",  "$21",          "$22",          "$23",
147
  "$24",          "$25",          "c0_ecc",       "c0_cacheerr",
148
  "c0_taglo",     "c0_taghi",     "c0_errorepc",  "$31",
149
};
150
 
151
static const char * const mips_cp0_names_mips3264[32] =
152
{
153
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
154
  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
155
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
156
  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
157
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
158
  "c0_xcontext",  "$21",          "$22",          "c0_debug",
159
  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
160
  "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
161
};
162
 
163
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164
{
165
  { 16, 1, "c0_config1"         },
166
  { 16, 2, "c0_config2"         },
167
  { 16, 3, "c0_config3"         },
168
  { 18, 1, "c0_watchlo,1"       },
169
  { 18, 2, "c0_watchlo,2"       },
170
  { 18, 3, "c0_watchlo,3"       },
171
  { 18, 4, "c0_watchlo,4"       },
172
  { 18, 5, "c0_watchlo,5"       },
173
  { 18, 6, "c0_watchlo,6"       },
174
  { 18, 7, "c0_watchlo,7"       },
175
  { 19, 1, "c0_watchhi,1"       },
176
  { 19, 2, "c0_watchhi,2"       },
177
  { 19, 3, "c0_watchhi,3"       },
178
  { 19, 4, "c0_watchhi,4"       },
179
  { 19, 5, "c0_watchhi,5"       },
180
  { 19, 6, "c0_watchhi,6"       },
181
  { 19, 7, "c0_watchhi,7"       },
182
  { 25, 1, "c0_perfcnt,1"       },
183
  { 25, 2, "c0_perfcnt,2"       },
184
  { 25, 3, "c0_perfcnt,3"       },
185
  { 25, 4, "c0_perfcnt,4"       },
186
  { 25, 5, "c0_perfcnt,5"       },
187
  { 25, 6, "c0_perfcnt,6"       },
188
  { 25, 7, "c0_perfcnt,7"       },
189
  { 27, 1, "c0_cacheerr,1"      },
190
  { 27, 2, "c0_cacheerr,2"      },
191
  { 27, 3, "c0_cacheerr,3"      },
192
  { 28, 1, "c0_datalo"          },
193
  { 29, 1, "c0_datahi"          }
194
};
195
 
196
static const char * const mips_cp0_names_mips3264r2[32] =
197
{
198
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
199
  "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
200
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
201
  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
202
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
203
  "c0_xcontext",  "$21",          "$22",          "c0_debug",
204
  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
205
  "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
206
};
207
 
208
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209
{
210
  {  4, 1, "c0_contextconfig"   },
211
  {  0, 1, "c0_mvpcontrol"       },
212
  {  0, 2, "c0_mvpconf0" },
213
  {  0, 3, "c0_mvpconf1" },
214
  {  1, 1, "c0_vpecontrol"      },
215
  {  1, 2, "c0_vpeconf0"        },
216
  {  1, 3, "c0_vpeconf1"        },
217
  {  1, 4, "c0_yqmask"          },
218
  {  1, 5, "c0_vpeschedule"     },
219
  {  1, 6, "c0_vpeschefback"    },
220
  {  2, 1, "c0_tcstatus"        },
221
  {  2, 2, "c0_tcbind"          },
222
  {  2, 3, "c0_tcrestart"       },
223
  {  2, 4, "c0_tchalt"          },
224
  {  2, 5, "c0_tccontext"       },
225
  {  2, 6, "c0_tcschedule"      },
226
  {  2, 7, "c0_tcschefback"     },
227
  {  5, 1, "c0_pagegrain"       },
228
  {  6, 1, "c0_srsconf0"        },
229
  {  6, 2, "c0_srsconf1"        },
230
  {  6, 3, "c0_srsconf2"        },
231
  {  6, 4, "c0_srsconf3"        },
232
  {  6, 5, "c0_srsconf4"        },
233
  { 12, 1, "c0_intctl"          },
234
  { 12, 2, "c0_srsctl"          },
235
  { 12, 3, "c0_srsmap"          },
236
  { 15, 1, "c0_ebase"           },
237
  { 16, 1, "c0_config1"         },
238
  { 16, 2, "c0_config2"         },
239
  { 16, 3, "c0_config3"         },
240
  { 18, 1, "c0_watchlo,1"       },
241
  { 18, 2, "c0_watchlo,2"       },
242
  { 18, 3, "c0_watchlo,3"       },
243
  { 18, 4, "c0_watchlo,4"       },
244
  { 18, 5, "c0_watchlo,5"       },
245
  { 18, 6, "c0_watchlo,6"       },
246
  { 18, 7, "c0_watchlo,7"       },
247
  { 19, 1, "c0_watchhi,1"       },
248
  { 19, 2, "c0_watchhi,2"       },
249
  { 19, 3, "c0_watchhi,3"       },
250
  { 19, 4, "c0_watchhi,4"       },
251
  { 19, 5, "c0_watchhi,5"       },
252
  { 19, 6, "c0_watchhi,6"       },
253
  { 19, 7, "c0_watchhi,7"       },
254
  { 23, 1, "c0_tracecontrol"    },
255
  { 23, 2, "c0_tracecontrol2"   },
256
  { 23, 3, "c0_usertracedata"   },
257
  { 23, 4, "c0_tracebpc"        },
258
  { 25, 1, "c0_perfcnt,1"       },
259
  { 25, 2, "c0_perfcnt,2"       },
260
  { 25, 3, "c0_perfcnt,3"       },
261
  { 25, 4, "c0_perfcnt,4"       },
262
  { 25, 5, "c0_perfcnt,5"       },
263
  { 25, 6, "c0_perfcnt,6"       },
264
  { 25, 7, "c0_perfcnt,7"       },
265
  { 27, 1, "c0_cacheerr,1"      },
266
  { 27, 2, "c0_cacheerr,2"      },
267
  { 27, 3, "c0_cacheerr,3"      },
268
  { 28, 1, "c0_datalo"          },
269
  { 28, 2, "c0_taglo1"          },
270
  { 28, 3, "c0_datalo1"         },
271
  { 28, 4, "c0_taglo2"          },
272
  { 28, 5, "c0_datalo2"         },
273
  { 28, 6, "c0_taglo3"          },
274
  { 28, 7, "c0_datalo3"         },
275
  { 29, 1, "c0_datahi"          },
276
  { 29, 2, "c0_taghi1"          },
277
  { 29, 3, "c0_datahi1"         },
278
  { 29, 4, "c0_taghi2"          },
279
  { 29, 5, "c0_datahi2"         },
280
  { 29, 6, "c0_taghi3"          },
281
  { 29, 7, "c0_datahi3"         },
282
};
283
 
284
/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
285
static const char * const mips_cp0_names_sb1[32] =
286
{
287
  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
288
  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
289
  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
290
  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
291
  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
292
  "c0_xcontext",  "$21",          "$22",          "c0_debug",
293
  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
294
  "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
295
};
296
 
297
static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298
{
299
  { 16, 1, "c0_config1"         },
300
  { 18, 1, "c0_watchlo,1"       },
301
  { 19, 1, "c0_watchhi,1"       },
302
  { 22, 0, "c0_perftrace"        },
303
  { 23, 3, "c0_edebug"          },
304
  { 25, 1, "c0_perfcnt,1"       },
305
  { 25, 2, "c0_perfcnt,2"       },
306
  { 25, 3, "c0_perfcnt,3"       },
307
  { 25, 4, "c0_perfcnt,4"       },
308
  { 25, 5, "c0_perfcnt,5"       },
309
  { 25, 6, "c0_perfcnt,6"       },
310
  { 25, 7, "c0_perfcnt,7"       },
311
  { 26, 1, "c0_buserr_pa"       },
312
  { 27, 1, "c0_cacheerr_d"      },
313
  { 27, 3, "c0_cacheerr_d_pa"   },
314
  { 28, 1, "c0_datalo_i"        },
315
  { 28, 2, "c0_taglo_d"         },
316
  { 28, 3, "c0_datalo_d"        },
317
  { 29, 1, "c0_datahi_i"        },
318
  { 29, 2, "c0_taghi_d"         },
319
  { 29, 3, "c0_datahi_d"        },
320
};
321
 
322
static const char * const mips_hwr_names_numeric[32] =
323
{
324
  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
325
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
326
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
327
  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
328
};
329
 
330
static const char * const mips_hwr_names_mips3264r2[32] =
331
{
332
  "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
333
  "$4",          "$5",            "$6",           "$7",
334
  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
335
  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
336
  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
337
};
338
 
339
struct mips_abi_choice
340
{
341
  const char * name;
342
  const char * const *gpr_names;
343
  const char * const *fpr_names;
344
};
345
 
346
struct mips_abi_choice mips_abi_choices[] =
347
{
348
  { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
349
  { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
350
  { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
351
  { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
352
};
353
 
354
struct mips_arch_choice
355
{
356
  const char *name;
357
  int bfd_mach_valid;
358
  unsigned long bfd_mach;
359
  int processor;
360
  int isa;
361
  const char * const *cp0_names;
362
  const struct mips_cp0sel_name *cp0sel_names;
363
  unsigned int cp0sel_names_len;
364
  const char * const *hwr_names;
365
};
366
 
367
const struct mips_arch_choice mips_arch_choices[] =
368
{
369
  { "numeric",  0, 0, 0, 0,
370
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
371
 
372
  { "r3000",    1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
373
    mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
374
  { "r3900",    1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
375
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376
  { "r4000",    1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
377
    mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
378
  { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
379
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380
  { "vr4100",   1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
381
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382
  { "vr4111",   1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
383
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384
  { "vr4120",   1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
385
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386
  { "r4300",    1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
387
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388
  { "r4400",    1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
389
    mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
390
  { "r4600",    1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
391
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
392
  { "r4650",    1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
393
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
394
  { "r5000",    1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
395
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
396
  { "vr5400",   1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
397
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
398
  { "vr5500",   1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
399
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
400
  { "r6000",    1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
401
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
402
  { "rm7000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
403
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
404
  { "rm9000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
405
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
406
  { "r8000",    1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
407
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
408
  { "r10000",   1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
409
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
410
  { "r12000",   1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
411
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
412
  { "mips5",    1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
413
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
414
 
415
  /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
416
     Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
417
     _MIPS32 Architecture For Programmers Volume I: Introduction to the
418
     MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
419
     page 1.  */
420
  { "mips32",   1, bfd_mach_mipsisa32, CPU_MIPS32,
421
    ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
422
    mips_cp0_names_mips3264,
423
    mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
424
    mips_hwr_names_numeric },
425
 
426
  { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
427
    (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
428
     | INSN_MIPS3D | INSN_MT),
429
    mips_cp0_names_mips3264r2,
430
    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
431
    mips_hwr_names_mips3264r2 },
432
 
433
  /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
434
  { "mips64",   1, bfd_mach_mipsisa64, CPU_MIPS64,
435
    ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
436
    mips_cp0_names_mips3264,
437
    mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
438
    mips_hwr_names_numeric },
439
 
440
  { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
441
    (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
442
     | INSN_DSP64 | INSN_MT | INSN_MDMX),
443
    mips_cp0_names_mips3264r2,
444
    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
445
    mips_hwr_names_mips3264r2 },
446
 
447
  { "sb1",      1, bfd_mach_mips_sb1, CPU_SB1,
448
    ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
449
    mips_cp0_names_sb1,
450
    mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
451
    mips_hwr_names_numeric },
452
 
453
  { "loongson2e",   1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
454
    ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
455
    NULL, 0, mips_hwr_names_numeric },
456
 
457
  { "loongson2f",   1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
458
    ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
459
    NULL, 0, mips_hwr_names_numeric },
460
 
461
  { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
462
    ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
463
    mips_hwr_names_numeric },
464
 
465
  /* This entry, mips16, is here only for ISA/processor selection; do
466
     not print its name.  */
467
  { "",         1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
468
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
469
};
470
 
471
/* ISA and processor type to disassemble for, and register names to use.
472
   set_default_mips_dis_options and parse_mips_dis_options fill in these
473
   values.  */
474
static int mips_processor;
475
static int mips_isa;
476
static const char * const *mips_gpr_names;
477
static const char * const *mips_fpr_names;
478
static const char * const *mips_cp0_names;
479
static const struct mips_cp0sel_name *mips_cp0sel_names;
480
static int mips_cp0sel_names_len;
481
static const char * const *mips_hwr_names;
482
 
483
/* Other options */
484
static int no_aliases;  /* If set disassemble as most general inst.  */
485
 
486
static const struct mips_abi_choice *
487
choose_abi_by_name (const char *name, unsigned int namelen)
488
{
489
  const struct mips_abi_choice *c;
490
  unsigned int i;
491
 
492
  for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
493
    if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
494
        && strlen (mips_abi_choices[i].name) == namelen)
495
      c = &mips_abi_choices[i];
496
 
497
  return c;
498
}
499
 
500
static const struct mips_arch_choice *
501
choose_arch_by_name (const char *name, unsigned int namelen)
502
{
503
  const struct mips_arch_choice *c = NULL;
504
  unsigned int i;
505
 
506
  for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
507
    if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
508
        && strlen (mips_arch_choices[i].name) == namelen)
509
      c = &mips_arch_choices[i];
510
 
511
  return c;
512
}
513
 
514
static const struct mips_arch_choice *
515
choose_arch_by_number (unsigned long mach)
516
{
517
  static unsigned long hint_bfd_mach;
518
  static const struct mips_arch_choice *hint_arch_choice;
519
  const struct mips_arch_choice *c;
520
  unsigned int i;
521
 
522
  /* We optimize this because even if the user specifies no
523
     flags, this will be done for every instruction!  */
524
  if (hint_bfd_mach == mach
525
      && hint_arch_choice != NULL
526
      && hint_arch_choice->bfd_mach == hint_bfd_mach)
527
    return hint_arch_choice;
528
 
529
  for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
530
    {
531
      if (mips_arch_choices[i].bfd_mach_valid
532
          && mips_arch_choices[i].bfd_mach == mach)
533
        {
534
          c = &mips_arch_choices[i];
535
          hint_bfd_mach = mach;
536
          hint_arch_choice = c;
537
        }
538
    }
539
  return c;
540
}
541
 
542
/* Check if the object uses NewABI conventions.  */
543
 
544
static int
545
is_newabi (Elf_Internal_Ehdr *header)
546
{
547
  /* There are no old-style ABIs which use 64-bit ELF.  */
548
  if (header->e_ident[EI_CLASS] == ELFCLASS64)
549
    return 1;
550
 
551
  /* If a 32-bit ELF file, n32 is a new-style ABI.  */
552
  if ((header->e_flags & EF_MIPS_ABI2) != 0)
553
    return 1;
554
 
555
  return 0;
556
}
557
 
558
static void
559
set_default_mips_dis_options (struct disassemble_info *info)
560
{
561
  const struct mips_arch_choice *chosen_arch;
562
 
563
  /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
564
     and numeric FPR, CP0 register, and HWR names.  */
565
  mips_isa = ISA_MIPS3;
566
  mips_processor =  CPU_R3000;
567
  mips_gpr_names = mips_gpr_names_oldabi;
568
  mips_fpr_names = mips_fpr_names_numeric;
569
  mips_cp0_names = mips_cp0_names_numeric;
570
  mips_cp0sel_names = NULL;
571
  mips_cp0sel_names_len = 0;
572
  mips_hwr_names = mips_hwr_names_numeric;
573
  no_aliases = 0;
574
 
575
  /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
576
  if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
577
    {
578
      Elf_Internal_Ehdr *header;
579
 
580
      header = elf_elfheader (info->section->owner);
581
      if (is_newabi (header))
582
        mips_gpr_names = mips_gpr_names_newabi;
583
    }
584
 
585
  /* Set ISA, architecture, and cp0 register names as best we can.  */
586
#if ! SYMTAB_AVAILABLE
587
  /* This is running out on a target machine, not in a host tool.
588
     FIXME: Where does mips_target_info come from?  */
589
  target_processor = mips_target_info.processor;
590
  mips_isa = mips_target_info.isa;
591
#else
592
  chosen_arch = choose_arch_by_number (info->mach);
593
  if (chosen_arch != NULL)
594
    {
595
      mips_processor = chosen_arch->processor;
596
      mips_isa = chosen_arch->isa;
597
      mips_cp0_names = chosen_arch->cp0_names;
598
      mips_cp0sel_names = chosen_arch->cp0sel_names;
599
      mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
600
      mips_hwr_names = chosen_arch->hwr_names;
601
    }
602
#endif
603
}
604
 
605
static void
606
parse_mips_dis_option (const char *option, unsigned int len)
607
{
608
  unsigned int i, optionlen, vallen;
609
  const char *val;
610
  const struct mips_abi_choice *chosen_abi;
611
  const struct mips_arch_choice *chosen_arch;
612
 
613
  /* Try to match options that are simple flags */
614
  if (CONST_STRNEQ (option, "no-aliases"))
615
    {
616
      no_aliases = 1;
617
      return;
618
    }
619
 
620
  /* Look for the = that delimits the end of the option name.  */
621
  for (i = 0; i < len; i++)
622
    if (option[i] == '=')
623
      break;
624
 
625
  if (i == 0)            /* Invalid option: no name before '='.  */
626
    return;
627
  if (i == len)         /* Invalid option: no '='.  */
628
    return;
629
  if (i == (len - 1))   /* Invalid option: no value after '='.  */
630
    return;
631
 
632
  optionlen = i;
633
  val = option + (optionlen + 1);
634
  vallen = len - (optionlen + 1);
635
 
636
  if (strncmp ("gpr-names", option, optionlen) == 0
637
      && strlen ("gpr-names") == optionlen)
638
    {
639
      chosen_abi = choose_abi_by_name (val, vallen);
640
      if (chosen_abi != NULL)
641
        mips_gpr_names = chosen_abi->gpr_names;
642
      return;
643
    }
644
 
645
  if (strncmp ("fpr-names", option, optionlen) == 0
646
      && strlen ("fpr-names") == optionlen)
647
    {
648
      chosen_abi = choose_abi_by_name (val, vallen);
649
      if (chosen_abi != NULL)
650
        mips_fpr_names = chosen_abi->fpr_names;
651
      return;
652
    }
653
 
654
  if (strncmp ("cp0-names", option, optionlen) == 0
655
      && strlen ("cp0-names") == optionlen)
656
    {
657
      chosen_arch = choose_arch_by_name (val, vallen);
658
      if (chosen_arch != NULL)
659
        {
660
          mips_cp0_names = chosen_arch->cp0_names;
661
          mips_cp0sel_names = chosen_arch->cp0sel_names;
662
          mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
663
        }
664
      return;
665
    }
666
 
667
  if (strncmp ("hwr-names", option, optionlen) == 0
668
      && strlen ("hwr-names") == optionlen)
669
    {
670
      chosen_arch = choose_arch_by_name (val, vallen);
671
      if (chosen_arch != NULL)
672
        mips_hwr_names = chosen_arch->hwr_names;
673
      return;
674
    }
675
 
676
  if (strncmp ("reg-names", option, optionlen) == 0
677
      && strlen ("reg-names") == optionlen)
678
    {
679
      /* We check both ABI and ARCH here unconditionally, so
680
         that "numeric" will do the desirable thing: select
681
         numeric register names for all registers.  Other than
682
         that, a given name probably won't match both.  */
683
      chosen_abi = choose_abi_by_name (val, vallen);
684
      if (chosen_abi != NULL)
685
        {
686
          mips_gpr_names = chosen_abi->gpr_names;
687
          mips_fpr_names = chosen_abi->fpr_names;
688
        }
689
      chosen_arch = choose_arch_by_name (val, vallen);
690
      if (chosen_arch != NULL)
691
        {
692
          mips_cp0_names = chosen_arch->cp0_names;
693
          mips_cp0sel_names = chosen_arch->cp0sel_names;
694
          mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
695
          mips_hwr_names = chosen_arch->hwr_names;
696
        }
697
      return;
698
    }
699
 
700
  /* Invalid option.  */
701
}
702
 
703
static void
704
parse_mips_dis_options (const char *options)
705
{
706
  const char *option_end;
707
 
708
  if (options == NULL)
709
    return;
710
 
711
  while (*options != '\0')
712
    {
713
      /* Skip empty options.  */
714
      if (*options == ',')
715
        {
716
          options++;
717
          continue;
718
        }
719
 
720
      /* We know that *options is neither NUL or a comma.  */
721
      option_end = options + 1;
722
      while (*option_end != ',' && *option_end != '\0')
723
        option_end++;
724
 
725
      parse_mips_dis_option (options, option_end - options);
726
 
727
      /* Go on to the next one.  If option_end points to a comma, it
728
         will be skipped above.  */
729
      options = option_end;
730
    }
731
}
732
 
733
static const struct mips_cp0sel_name *
734
lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
735
                         unsigned int len,
736
                         unsigned int cp0reg,
737
                         unsigned int sel)
738
{
739
  unsigned int i;
740
 
741
  for (i = 0; i < len; i++)
742
    if (names[i].cp0reg == cp0reg && names[i].sel == sel)
743
      return &names[i];
744
  return NULL;
745
}
746
 
747
/* Print insn arguments for 32/64-bit code.  */
748
 
749
static void
750
print_insn_args (const char *d,
751
                 register unsigned long int l,
752
                 bfd_vma pc,
753
                 struct disassemble_info *info,
754
                 const struct mips_opcode *opp)
755
{
756
  int op, delta;
757
  unsigned int lsb, msb, msbd;
758
 
759
  lsb = 0;
760
 
761
  for (; *d != '\0'; d++)
762
    {
763
      switch (*d)
764
        {
765
        case ',':
766
        case '(':
767
        case ')':
768
        case '[':
769
        case ']':
770
          (*info->fprintf_func) (info->stream, "%c", *d);
771
          break;
772
 
773
        case '+':
774
          /* Extension character; switch for second char.  */
775
          d++;
776
          switch (*d)
777
            {
778
            case '\0':
779
              /* xgettext:c-format */
780
              (*info->fprintf_func) (info->stream,
781
                                     _("# internal error, incomplete extension sequence (+)"));
782
              return;
783
 
784
            case 'A':
785
              lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
786
              (*info->fprintf_func) (info->stream, "0x%x", lsb);
787
              break;
788
 
789
            case 'B':
790
              msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
791
              (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
792
              break;
793
 
794
            case '1':
795
              (*info->fprintf_func) (info->stream, "0x%lx",
796
                                     (l >> OP_SH_UDI1) & OP_MASK_UDI1);
797
              break;
798
 
799
            case '2':
800
              (*info->fprintf_func) (info->stream, "0x%lx",
801
                                     (l >> OP_SH_UDI2) & OP_MASK_UDI2);
802
              break;
803
 
804
            case '3':
805
              (*info->fprintf_func) (info->stream, "0x%lx",
806
                                     (l >> OP_SH_UDI3) & OP_MASK_UDI3);
807
              break;
808
 
809
            case '4':
810
              (*info->fprintf_func) (info->stream, "0x%lx",
811
                                     (l >> OP_SH_UDI4) & OP_MASK_UDI4);
812
              break;
813
 
814
            case 'C':
815
            case 'H':
816
              msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
817
              (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
818
              break;
819
 
820
            case 'D':
821
              {
822
                const struct mips_cp0sel_name *n;
823
                unsigned int cp0reg, sel;
824
 
825
                cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
826
                sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
827
 
828
                /* CP0 register including 'sel' code for mtcN (et al.), to be
829
                   printed textually if known.  If not known, print both
830
                   CP0 register name and sel numerically since CP0 register
831
                   with sel 0 may have a name unrelated to register being
832
                   printed.  */
833
                n = lookup_mips_cp0sel_name(mips_cp0sel_names,
834
                                            mips_cp0sel_names_len, cp0reg, sel);
835
                if (n != NULL)
836
                  (*info->fprintf_func) (info->stream, "%s", n->name);
837
                else
838
                  (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
839
                break;
840
              }
841
 
842
            case 'E':
843
              lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
844
              (*info->fprintf_func) (info->stream, "0x%x", lsb);
845
              break;
846
 
847
            case 'F':
848
              msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
849
              (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
850
              break;
851
 
852
            case 'G':
853
              msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
854
              (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
855
              break;
856
 
857
            case 't': /* Coprocessor 0 reg name */
858
              (*info->fprintf_func) (info->stream, "%s",
859
                                     mips_cp0_names[(l >> OP_SH_RT) &
860
                                                     OP_MASK_RT]);
861
              break;
862
 
863
            case 'T': /* Coprocessor 0 reg name */
864
              {
865
                const struct mips_cp0sel_name *n;
866
                unsigned int cp0reg, sel;
867
 
868
                cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
869
                sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
870
 
871
                /* CP0 register including 'sel' code for mftc0, to be
872
                   printed textually if known.  If not known, print both
873
                   CP0 register name and sel numerically since CP0 register
874
                   with sel 0 may have a name unrelated to register being
875
                   printed.  */
876
                n = lookup_mips_cp0sel_name(mips_cp0sel_names,
877
                                            mips_cp0sel_names_len, cp0reg, sel);
878
                if (n != NULL)
879
                  (*info->fprintf_func) (info->stream, "%s", n->name);
880
                else
881
                  (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
882
                break;
883
              }
884
 
885
            default:
886
              /* xgettext:c-format */
887
              (*info->fprintf_func) (info->stream,
888
                                     _("# internal error, undefined extension sequence (+%c)"),
889
                                     *d);
890
              return;
891
            }
892
          break;
893
 
894
        case '2':
895
          (*info->fprintf_func) (info->stream, "0x%lx",
896
                                 (l >> OP_SH_BP) & OP_MASK_BP);
897
          break;
898
 
899
        case '3':
900
          (*info->fprintf_func) (info->stream, "0x%lx",
901
                                 (l >> OP_SH_SA3) & OP_MASK_SA3);
902
          break;
903
 
904
        case '4':
905
          (*info->fprintf_func) (info->stream, "0x%lx",
906
                                 (l >> OP_SH_SA4) & OP_MASK_SA4);
907
          break;
908
 
909
        case '5':
910
          (*info->fprintf_func) (info->stream, "0x%lx",
911
                                 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
912
          break;
913
 
914
        case '6':
915
          (*info->fprintf_func) (info->stream, "0x%lx",
916
                                 (l >> OP_SH_RS) & OP_MASK_RS);
917
          break;
918
 
919
        case '7':
920
          (*info->fprintf_func) (info->stream, "$ac%ld",
921
                                 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
922
          break;
923
 
924
        case '8':
925
          (*info->fprintf_func) (info->stream, "0x%lx",
926
                                 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
927
          break;
928
 
929
        case '9':
930
          (*info->fprintf_func) (info->stream, "$ac%ld",
931
                                 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
932
          break;
933
 
934
        case '0': /* dsp 6-bit signed immediate in bit 20 */
935
          delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
936
          if (delta & 0x20) /* test sign bit */
937
            delta |= ~OP_MASK_DSPSFT;
938
          (*info->fprintf_func) (info->stream, "%d", delta);
939
          break;
940
 
941
        case ':': /* dsp 7-bit signed immediate in bit 19 */
942
          delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
943
          if (delta & 0x40) /* test sign bit */
944
            delta |= ~OP_MASK_DSPSFT_7;
945
          (*info->fprintf_func) (info->stream, "%d", delta);
946
          break;
947
 
948
        case '\'':
949
          (*info->fprintf_func) (info->stream, "0x%lx",
950
                                 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
951
          break;
952
 
953
        case '@': /* dsp 10-bit signed immediate in bit 16 */
954
          delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
955
          if (delta & 0x200) /* test sign bit */
956
            delta |= ~OP_MASK_IMM10;
957
          (*info->fprintf_func) (info->stream, "%d", delta);
958
          break;
959
 
960
        case '!':
961
          (*info->fprintf_func) (info->stream, "%ld",
962
                                 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
963
          break;
964
 
965
        case '$':
966
          (*info->fprintf_func) (info->stream, "%ld",
967
                                 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
968
          break;
969
 
970
        case '*':
971
          (*info->fprintf_func) (info->stream, "$ac%ld",
972
                                 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
973
          break;
974
 
975
        case '&':
976
          (*info->fprintf_func) (info->stream, "$ac%ld",
977
                                 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
978
          break;
979
 
980
        case 'g':
981
          /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */
982
          (*info->fprintf_func) (info->stream, "$%ld",
983
                                 (l >> OP_SH_RD) & OP_MASK_RD);
984
          break;
985
 
986
        case 's':
987
        case 'b':
988
        case 'r':
989
        case 'v':
990
          (*info->fprintf_func) (info->stream, "%s",
991
                                 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
992
          break;
993
 
994
        case 't':
995
        case 'w':
996
          (*info->fprintf_func) (info->stream, "%s",
997
                                 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
998
          break;
999
 
1000
        case 'i':
1001
        case 'u':
1002
          (*info->fprintf_func) (info->stream, "0x%lx",
1003
                                 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1004
          break;
1005
 
1006
        case 'j': /* Same as i, but sign-extended.  */
1007
        case 'o':
1008
          delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1009
          if (delta & 0x8000)
1010
            delta |= ~0xffff;
1011
          (*info->fprintf_func) (info->stream, "%d",
1012
                                 delta);
1013
          break;
1014
 
1015
        case 'h':
1016
          (*info->fprintf_func) (info->stream, "0x%x",
1017
                                 (unsigned int) ((l >> OP_SH_PREFX)
1018
                                                 & OP_MASK_PREFX));
1019
          break;
1020
 
1021
        case 'k':
1022
          (*info->fprintf_func) (info->stream, "0x%x",
1023
                                 (unsigned int) ((l >> OP_SH_CACHE)
1024
                                                 & OP_MASK_CACHE));
1025
          break;
1026
 
1027
        case 'a':
1028
          info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1029
                          | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1030
          /* For gdb disassembler, force odd address on jalx.  */
1031
          if (info->flavour == bfd_target_unknown_flavour
1032
              && strcmp (opp->name, "jalx") == 0)
1033
            info->target |= 1;
1034
          (*info->print_address_func) (info->target, info);
1035
          break;
1036
 
1037
        case 'p':
1038
          /* Sign extend the displacement.  */
1039
          delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1040
          if (delta & 0x8000)
1041
            delta |= ~0xffff;
1042
          info->target = (delta << 2) + pc + INSNLEN;
1043
          (*info->print_address_func) (info->target, info);
1044
          break;
1045
 
1046
        case 'd':
1047
          (*info->fprintf_func) (info->stream, "%s",
1048
                                 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1049
          break;
1050
 
1051
        case 'U':
1052
          {
1053
            /* First check for both rd and rt being equal.  */
1054
            unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1055
            if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1056
              (*info->fprintf_func) (info->stream, "%s",
1057
                                     mips_gpr_names[reg]);
1058
            else
1059
              {
1060
                /* If one is zero use the other.  */
1061
                if (reg == 0)
1062
                  (*info->fprintf_func) (info->stream, "%s",
1063
                                         mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1064
                else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1065
                  (*info->fprintf_func) (info->stream, "%s",
1066
                                         mips_gpr_names[reg]);
1067
                else /* Bogus, result depends on processor.  */
1068
                  (*info->fprintf_func) (info->stream, "%s or %s",
1069
                                         mips_gpr_names[reg],
1070
                                         mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1071
              }
1072
          }
1073
          break;
1074
 
1075
        case 'z':
1076
          (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1077
          break;
1078
 
1079
        case '<':
1080
          (*info->fprintf_func) (info->stream, "0x%lx",
1081
                                 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1082
          break;
1083
 
1084
        case 'c':
1085
          (*info->fprintf_func) (info->stream, "0x%lx",
1086
                                 (l >> OP_SH_CODE) & OP_MASK_CODE);
1087
          break;
1088
 
1089
        case 'q':
1090
          (*info->fprintf_func) (info->stream, "0x%lx",
1091
                                 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1092
          break;
1093
 
1094
        case 'C':
1095
          (*info->fprintf_func) (info->stream, "0x%lx",
1096
                                 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1097
          break;
1098
 
1099
        case 'B':
1100
          (*info->fprintf_func) (info->stream, "0x%lx",
1101
 
1102
                                 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1103
          break;
1104
 
1105
        case 'J':
1106
          (*info->fprintf_func) (info->stream, "0x%lx",
1107
                                 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1108
          break;
1109
 
1110
        case 'S':
1111
        case 'V':
1112
          (*info->fprintf_func) (info->stream, "%s",
1113
                                 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1114
          break;
1115
 
1116
        case 'T':
1117
        case 'W':
1118
          (*info->fprintf_func) (info->stream, "%s",
1119
                                 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1120
          break;
1121
 
1122
        case 'D':
1123
          (*info->fprintf_func) (info->stream, "%s",
1124
                                 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1125
          break;
1126
 
1127
        case 'R':
1128
          (*info->fprintf_func) (info->stream, "%s",
1129
                                 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1130
          break;
1131
 
1132
        case 'E':
1133
          /* Coprocessor register for lwcN instructions, et al.
1134
 
1135
             Note that there is no load/store cp0 instructions, and
1136
             that FPU (cp1) instructions disassemble this field using
1137
             'T' format.  Therefore, until we gain understanding of
1138
             cp2 register names, we can simply print the register
1139
             numbers.  */
1140
          (*info->fprintf_func) (info->stream, "$%ld",
1141
                                 (l >> OP_SH_RT) & OP_MASK_RT);
1142
          break;
1143
 
1144
        case 'G':
1145
          /* Coprocessor register for mtcN instructions, et al.  Note
1146
             that FPU (cp1) instructions disassemble this field using
1147
             'S' format.  Therefore, we only need to worry about cp0,
1148
             cp2, and cp3.  */
1149
          op = (l >> OP_SH_OP) & OP_MASK_OP;
1150
          if (op == OP_OP_COP0)
1151
            (*info->fprintf_func) (info->stream, "%s",
1152
                                   mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1153
          else
1154
            (*info->fprintf_func) (info->stream, "$%ld",
1155
                                   (l >> OP_SH_RD) & OP_MASK_RD);
1156
          break;
1157
 
1158
        case 'K':
1159
          (*info->fprintf_func) (info->stream, "%s",
1160
                                 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1161
          break;
1162
 
1163
        case 'N':
1164
          (*info->fprintf_func) (info->stream,
1165
                                 ((opp->pinfo & (FP_D | FP_S)) != 0
1166
                                  ? "$fcc%ld" : "$cc%ld"),
1167
                                 (l >> OP_SH_BCC) & OP_MASK_BCC);
1168
          break;
1169
 
1170
        case 'M':
1171
          (*info->fprintf_func) (info->stream, "$fcc%ld",
1172
                                 (l >> OP_SH_CCC) & OP_MASK_CCC);
1173
          break;
1174
 
1175
        case 'P':
1176
          (*info->fprintf_func) (info->stream, "%ld",
1177
                                 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1178
          break;
1179
 
1180
        case 'e':
1181
          (*info->fprintf_func) (info->stream, "%ld",
1182
                                 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1183
          break;
1184
 
1185
        case '%':
1186
          (*info->fprintf_func) (info->stream, "%ld",
1187
                                 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1188
          break;
1189
 
1190
        case 'H':
1191
          (*info->fprintf_func) (info->stream, "%ld",
1192
                                 (l >> OP_SH_SEL) & OP_MASK_SEL);
1193
          break;
1194
 
1195
        case 'O':
1196
          (*info->fprintf_func) (info->stream, "%ld",
1197
                                 (l >> OP_SH_ALN) & OP_MASK_ALN);
1198
          break;
1199
 
1200
        case 'Q':
1201
          {
1202
            unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1203
 
1204
            if ((vsel & 0x10) == 0)
1205
              {
1206
                int fmt;
1207
 
1208
                vsel &= 0x0f;
1209
                for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1210
                  if ((vsel & 1) == 0)
1211
                    break;
1212
                (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1213
                                       (l >> OP_SH_FT) & OP_MASK_FT,
1214
                                       vsel >> 1);
1215
              }
1216
            else if ((vsel & 0x08) == 0)
1217
              {
1218
                (*info->fprintf_func) (info->stream, "$v%ld",
1219
                                       (l >> OP_SH_FT) & OP_MASK_FT);
1220
              }
1221
            else
1222
              {
1223
                (*info->fprintf_func) (info->stream, "0x%lx",
1224
                                       (l >> OP_SH_FT) & OP_MASK_FT);
1225
              }
1226
          }
1227
          break;
1228
 
1229
        case 'X':
1230
          (*info->fprintf_func) (info->stream, "$v%ld",
1231
                                 (l >> OP_SH_FD) & OP_MASK_FD);
1232
          break;
1233
 
1234
        case 'Y':
1235
          (*info->fprintf_func) (info->stream, "$v%ld",
1236
                                 (l >> OP_SH_FS) & OP_MASK_FS);
1237
          break;
1238
 
1239
        case 'Z':
1240
          (*info->fprintf_func) (info->stream, "$v%ld",
1241
                                 (l >> OP_SH_FT) & OP_MASK_FT);
1242
          break;
1243
 
1244
        default:
1245
          /* xgettext:c-format */
1246
          (*info->fprintf_func) (info->stream,
1247
                                 _("# internal error, undefined modifier (%c)"),
1248
                                 *d);
1249
          return;
1250
        }
1251
    }
1252
}
1253
 
1254
/* Print the mips instruction at address MEMADDR in debugged memory,
1255
   on using INFO.  Returns length of the instruction, in bytes, which is
1256
   always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
1257
   this is little-endian code.  */
1258
 
1259
static int
1260
print_insn_mips (bfd_vma memaddr,
1261
                 unsigned long int word,
1262
                 struct disassemble_info *info)
1263
{
1264
  const struct mips_opcode *op;
1265
  static bfd_boolean init = 0;
1266
  static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1267
 
1268
  /* Build a hash table to shorten the search time.  */
1269
  if (! init)
1270
    {
1271
      unsigned int i;
1272
 
1273
      for (i = 0; i <= OP_MASK_OP; i++)
1274
        {
1275
          for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1276
            {
1277
              if (op->pinfo == INSN_MACRO
1278
                  || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1279
                continue;
1280
              if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1281
                {
1282
                  mips_hash[i] = op;
1283
                  break;
1284
                }
1285
            }
1286
        }
1287
 
1288
      init = 1;
1289
    }
1290
 
1291
  info->bytes_per_chunk = INSNLEN;
1292
  info->display_endian = info->endian;
1293
  info->insn_info_valid = 1;
1294
  info->branch_delay_insns = 0;
1295
  info->data_size = 0;
1296
  info->insn_type = dis_nonbranch;
1297
  info->target = 0;
1298
  info->target2 = 0;
1299
 
1300
  op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1301
  if (op != NULL)
1302
    {
1303
      for (; op < &mips_opcodes[NUMOPCODES]; op++)
1304
        {
1305
          if (op->pinfo != INSN_MACRO
1306
              && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1307
              && (word & op->mask) == op->match)
1308
            {
1309
              const char *d;
1310
 
1311
              /* We always allow to disassemble the jalx instruction.  */
1312
              if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1313
                  && strcmp (op->name, "jalx"))
1314
                continue;
1315
 
1316
              /* Figure out instruction type and branch delay information.  */
1317
              if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1318
                {
1319
                  if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1320
                    info->insn_type = dis_jsr;
1321
                  else
1322
                    info->insn_type = dis_branch;
1323
                  info->branch_delay_insns = 1;
1324
                }
1325
              else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1326
                                     | INSN_COND_BRANCH_LIKELY)) != 0)
1327
                {
1328
                  if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1329
                    info->insn_type = dis_condjsr;
1330
                  else
1331
                    info->insn_type = dis_condbranch;
1332
                  info->branch_delay_insns = 1;
1333
                }
1334
              else if ((op->pinfo & (INSN_STORE_MEMORY
1335
                                     | INSN_LOAD_MEMORY_DELAY)) != 0)
1336
                info->insn_type = dis_dref;
1337
 
1338
              (*info->fprintf_func) (info->stream, "%s", op->name);
1339
 
1340
              d = op->args;
1341
              if (d != NULL && *d != '\0')
1342
                {
1343
                  (*info->fprintf_func) (info->stream, "\t");
1344
                  print_insn_args (d, word, memaddr, info, op);
1345
                }
1346
 
1347
              return INSNLEN;
1348
            }
1349
        }
1350
    }
1351
 
1352
  /* Handle undefined instructions.  */
1353
  info->insn_type = dis_noninsn;
1354
  (*info->fprintf_func) (info->stream, "0x%lx", word);
1355
  return INSNLEN;
1356
}
1357
 
1358
/* Disassemble an operand for a mips16 instruction.  */
1359
 
1360
static void
1361
print_mips16_insn_arg (char type,
1362
                       const struct mips_opcode *op,
1363
                       int l,
1364
                       bfd_boolean use_extend,
1365
                       int extend,
1366
                       bfd_vma memaddr,
1367
                       struct disassemble_info *info)
1368
{
1369
  switch (type)
1370
    {
1371
    case ',':
1372
    case '(':
1373
    case ')':
1374
      (*info->fprintf_func) (info->stream, "%c", type);
1375
      break;
1376
 
1377
    case 'y':
1378
    case 'w':
1379
      (*info->fprintf_func) (info->stream, "%s",
1380
                             mips16_reg_names(((l >> MIPS16OP_SH_RY)
1381
                                               & MIPS16OP_MASK_RY)));
1382
      break;
1383
 
1384
    case 'x':
1385
    case 'v':
1386
      (*info->fprintf_func) (info->stream, "%s",
1387
                             mips16_reg_names(((l >> MIPS16OP_SH_RX)
1388
                                               & MIPS16OP_MASK_RX)));
1389
      break;
1390
 
1391
    case 'z':
1392
      (*info->fprintf_func) (info->stream, "%s",
1393
                             mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1394
                                               & MIPS16OP_MASK_RZ)));
1395
      break;
1396
 
1397
    case 'Z':
1398
      (*info->fprintf_func) (info->stream, "%s",
1399
                             mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1400
                                               & MIPS16OP_MASK_MOVE32Z)));
1401
      break;
1402
 
1403
    case '0':
1404
      (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1405
      break;
1406
 
1407
    case 'S':
1408
      (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1409
      break;
1410
 
1411
    case 'P':
1412
      (*info->fprintf_func) (info->stream, "$pc");
1413
      break;
1414
 
1415
    case 'R':
1416
      (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1417
      break;
1418
 
1419
    case 'X':
1420
      (*info->fprintf_func) (info->stream, "%s",
1421
                             mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1422
                                            & MIPS16OP_MASK_REGR32)]);
1423
      break;
1424
 
1425
    case 'Y':
1426
      (*info->fprintf_func) (info->stream, "%s",
1427
                             mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1428
      break;
1429
 
1430
    case '<':
1431
    case '>':
1432
    case '[':
1433
    case ']':
1434
    case '4':
1435
    case '5':
1436
    case 'H':
1437
    case 'W':
1438
    case 'D':
1439
    case 'j':
1440
    case '6':
1441
    case '8':
1442
    case 'V':
1443
    case 'C':
1444
    case 'U':
1445
    case 'k':
1446
    case 'K':
1447
    case 'p':
1448
    case 'q':
1449
    case 'A':
1450
    case 'B':
1451
    case 'E':
1452
      {
1453
        int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1454
 
1455
        shift = 0;
1456
        signedp = 0;
1457
        extbits = 16;
1458
        pcrel = 0;
1459
        extu = 0;
1460
        branch = 0;
1461
        switch (type)
1462
          {
1463
          case '<':
1464
            nbits = 3;
1465
            immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1466
            extbits = 5;
1467
            extu = 1;
1468
            break;
1469
          case '>':
1470
            nbits = 3;
1471
            immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1472
            extbits = 5;
1473
            extu = 1;
1474
            break;
1475
          case '[':
1476
            nbits = 3;
1477
            immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1478
            extbits = 6;
1479
            extu = 1;
1480
            break;
1481
          case ']':
1482
            nbits = 3;
1483
            immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1484
            extbits = 6;
1485
            extu = 1;
1486
            break;
1487
          case '4':
1488
            nbits = 4;
1489
            immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1490
            signedp = 1;
1491
            extbits = 15;
1492
            break;
1493
          case '5':
1494
            nbits = 5;
1495
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1496
            info->insn_type = dis_dref;
1497
            info->data_size = 1;
1498
            break;
1499
          case 'H':
1500
            nbits = 5;
1501
            shift = 1;
1502
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1503
            info->insn_type = dis_dref;
1504
            info->data_size = 2;
1505
            break;
1506
          case 'W':
1507
            nbits = 5;
1508
            shift = 2;
1509
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1510
            if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1511
                && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1512
              {
1513
                info->insn_type = dis_dref;
1514
                info->data_size = 4;
1515
              }
1516
            break;
1517
          case 'D':
1518
            nbits = 5;
1519
            shift = 3;
1520
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1521
            info->insn_type = dis_dref;
1522
            info->data_size = 8;
1523
            break;
1524
          case 'j':
1525
            nbits = 5;
1526
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1527
            signedp = 1;
1528
            break;
1529
          case '6':
1530
            nbits = 6;
1531
            immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1532
            break;
1533
          case '8':
1534
            nbits = 8;
1535
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1536
            break;
1537
          case 'V':
1538
            nbits = 8;
1539
            shift = 2;
1540
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1541
            /* FIXME: This might be lw, or it might be addiu to $sp or
1542
               $pc.  We assume it's load.  */
1543
            info->insn_type = dis_dref;
1544
            info->data_size = 4;
1545
            break;
1546
          case 'C':
1547
            nbits = 8;
1548
            shift = 3;
1549
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1550
            info->insn_type = dis_dref;
1551
            info->data_size = 8;
1552
            break;
1553
          case 'U':
1554
            nbits = 8;
1555
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1556
            extu = 1;
1557
            break;
1558
          case 'k':
1559
            nbits = 8;
1560
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1561
            signedp = 1;
1562
            break;
1563
          case 'K':
1564
            nbits = 8;
1565
            shift = 3;
1566
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1567
            signedp = 1;
1568
            break;
1569
          case 'p':
1570
            nbits = 8;
1571
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1572
            signedp = 1;
1573
            pcrel = 1;
1574
            branch = 1;
1575
            info->insn_type = dis_condbranch;
1576
            break;
1577
          case 'q':
1578
            nbits = 11;
1579
            immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1580
            signedp = 1;
1581
            pcrel = 1;
1582
            branch = 1;
1583
            info->insn_type = dis_branch;
1584
            break;
1585
          case 'A':
1586
            nbits = 8;
1587
            shift = 2;
1588
            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1589
            pcrel = 1;
1590
            /* FIXME: This can be lw or la.  We assume it is lw.  */
1591
            info->insn_type = dis_dref;
1592
            info->data_size = 4;
1593
            break;
1594
          case 'B':
1595
            nbits = 5;
1596
            shift = 3;
1597
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1598
            pcrel = 1;
1599
            info->insn_type = dis_dref;
1600
            info->data_size = 8;
1601
            break;
1602
          case 'E':
1603
            nbits = 5;
1604
            shift = 2;
1605
            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1606
            pcrel = 1;
1607
            break;
1608
          default:
1609
            abort ();
1610
          }
1611
 
1612
        if (! use_extend)
1613
          {
1614
            if (signedp && immed >= (1 << (nbits - 1)))
1615
              immed -= 1 << nbits;
1616
            immed <<= shift;
1617
            if ((type == '<' || type == '>' || type == '[' || type == ']')
1618
                && immed == 0)
1619
              immed = 8;
1620
          }
1621
        else
1622
          {
1623
            if (extbits == 16)
1624
              immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1625
            else if (extbits == 15)
1626
              immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1627
            else
1628
              immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1629
            immed &= (1 << extbits) - 1;
1630
            if (! extu && immed >= (1 << (extbits - 1)))
1631
              immed -= 1 << extbits;
1632
          }
1633
 
1634
        if (! pcrel)
1635
          (*info->fprintf_func) (info->stream, "%d", immed);
1636
        else
1637
          {
1638
            bfd_vma baseaddr;
1639
 
1640
            if (branch)
1641
              {
1642
                immed *= 2;
1643
                baseaddr = memaddr + 2;
1644
              }
1645
            else if (use_extend)
1646
              baseaddr = memaddr - 2;
1647
            else
1648
              {
1649
                int status;
1650
                bfd_byte buffer[2];
1651
 
1652
                baseaddr = memaddr;
1653
 
1654
                /* If this instruction is in the delay slot of a jr
1655
                   instruction, the base address is the address of the
1656
                   jr instruction.  If it is in the delay slot of jalr
1657
                   instruction, the base address is the address of the
1658
                   jalr instruction.  This test is unreliable: we have
1659
                   no way of knowing whether the previous word is
1660
                   instruction or data.  */
1661
                status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1662
                                                    info);
1663
                if (status == 0
1664
                    && (((info->endian == BFD_ENDIAN_BIG
1665
                          ? bfd_getb16 (buffer)
1666
                          : bfd_getl16 (buffer))
1667
                         & 0xf800) == 0x1800))
1668
                  baseaddr = memaddr - 4;
1669
                else
1670
                  {
1671
                    status = (*info->read_memory_func) (memaddr - 2, buffer,
1672
                                                        2, info);
1673
                    if (status == 0
1674
                        && (((info->endian == BFD_ENDIAN_BIG
1675
                              ? bfd_getb16 (buffer)
1676
                              : bfd_getl16 (buffer))
1677
                             & 0xf81f) == 0xe800))
1678
                      baseaddr = memaddr - 2;
1679
                  }
1680
              }
1681
            info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1682
            if (pcrel && branch
1683
                && info->flavour == bfd_target_unknown_flavour)
1684
              /* For gdb disassembler, maintain odd address.  */
1685
              info->target |= 1;
1686
            (*info->print_address_func) (info->target, info);
1687
          }
1688
      }
1689
      break;
1690
 
1691
    case 'a':
1692
      {
1693
        int jalx = l & 0x400;
1694
 
1695
        if (! use_extend)
1696
          extend = 0;
1697
        l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1698
        if (!jalx && info->flavour == bfd_target_unknown_flavour)
1699
          /* For gdb disassembler, maintain odd address.  */
1700
          l |= 1;
1701
      }
1702
      info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1703
      (*info->print_address_func) (info->target, info);
1704
      info->insn_type = dis_jsr;
1705
      info->branch_delay_insns = 1;
1706
      break;
1707
 
1708
    case 'l':
1709
    case 'L':
1710
      {
1711
        int need_comma, amask, smask;
1712
 
1713
        need_comma = 0;
1714
 
1715
        l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1716
 
1717
        amask = (l >> 3) & 7;
1718
 
1719
        if (amask > 0 && amask < 5)
1720
          {
1721
            (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1722
            if (amask > 1)
1723
              (*info->fprintf_func) (info->stream, "-%s",
1724
                                     mips_gpr_names[amask + 3]);
1725
            need_comma = 1;
1726
          }
1727
 
1728
        smask = (l >> 1) & 3;
1729
        if (smask == 3)
1730
          {
1731
            (*info->fprintf_func) (info->stream, "%s??",
1732
                                   need_comma ? "," : "");
1733
            need_comma = 1;
1734
          }
1735
        else if (smask > 0)
1736
          {
1737
            (*info->fprintf_func) (info->stream, "%s%s",
1738
                                   need_comma ? "," : "",
1739
                                   mips_gpr_names[16]);
1740
            if (smask > 1)
1741
              (*info->fprintf_func) (info->stream, "-%s",
1742
                                     mips_gpr_names[smask + 15]);
1743
            need_comma = 1;
1744
          }
1745
 
1746
        if (l & 1)
1747
          {
1748
            (*info->fprintf_func) (info->stream, "%s%s",
1749
                                   need_comma ? "," : "",
1750
                                   mips_gpr_names[31]);
1751
            need_comma = 1;
1752
          }
1753
 
1754
        if (amask == 5 || amask == 6)
1755
          {
1756
            (*info->fprintf_func) (info->stream, "%s$f0",
1757
                                   need_comma ? "," : "");
1758
            if (amask == 6)
1759
              (*info->fprintf_func) (info->stream, "-$f1");
1760
          }
1761
      }
1762
      break;
1763
 
1764
    case 'm':
1765
    case 'M':
1766
      /* MIPS16e save/restore.  */
1767
      {
1768
      int need_comma = 0;
1769
      int amask, args, statics;
1770
      int nsreg, smask;
1771
      int framesz;
1772
      int i, j;
1773
 
1774
      l = l & 0x7f;
1775
      if (use_extend)
1776
        l |= extend << 16;
1777
 
1778
      amask = (l >> 16) & 0xf;
1779
      if (amask == MIPS16_ALL_ARGS)
1780
        {
1781
          args = 4;
1782
          statics = 0;
1783
        }
1784
      else if (amask == MIPS16_ALL_STATICS)
1785
        {
1786
          args = 0;
1787
          statics = 4;
1788
        }
1789
      else
1790
        {
1791
          args = amask >> 2;
1792
          statics = amask & 3;
1793
        }
1794
 
1795
      if (args > 0) {
1796
          (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1797
          if (args > 1)
1798
            (*info->fprintf_func) (info->stream, "-%s",
1799
                                   mips_gpr_names[4 + args - 1]);
1800
          need_comma = 1;
1801
      }
1802
 
1803
      framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1804
      if (framesz == 0 && !use_extend)
1805
        framesz = 128;
1806
 
1807
      (*info->fprintf_func) (info->stream, "%s%d",
1808
                             need_comma ? "," : "",
1809
                             framesz);
1810
 
1811
      if (l & 0x40)                   /* $ra */
1812
        (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1813
 
1814
      nsreg = (l >> 24) & 0x7;
1815
      smask = 0;
1816
      if (l & 0x20)                   /* $s0 */
1817
        smask |= 1 << 0;
1818
      if (l & 0x10)                   /* $s1 */
1819
        smask |= 1 << 1;
1820
      if (nsreg > 0)                  /* $s2-$s8 */
1821
        smask |= ((1 << nsreg) - 1) << 2;
1822
 
1823
      /* Find first set static reg bit.  */
1824
      for (i = 0; i < 9; i++)
1825
        {
1826
          if (smask & (1 << i))
1827
            {
1828
              (*info->fprintf_func) (info->stream, ",%s",
1829
                                     mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1830
              /* Skip over string of set bits.  */
1831
              for (j = i; smask & (2 << j); j++)
1832
                continue;
1833
              if (j > i)
1834
                (*info->fprintf_func) (info->stream, "-%s",
1835
                                       mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1836
              i = j + 1;
1837
            }
1838
        }
1839
 
1840
      /* Statics $ax - $a3.  */
1841
      if (statics == 1)
1842
        (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1843
      else if (statics > 0)
1844
        (*info->fprintf_func) (info->stream, ",%s-%s",
1845
                               mips_gpr_names[7 - statics + 1],
1846
                               mips_gpr_names[7]);
1847
      }
1848
      break;
1849
 
1850
    default:
1851
      /* xgettext:c-format */
1852
      (*info->fprintf_func)
1853
        (info->stream,
1854
         _("# internal disassembler error, unrecognised modifier (%c)"),
1855
         type);
1856
      abort ();
1857
    }
1858
}
1859
 
1860
/* Disassemble mips16 instructions.  */
1861
 
1862
static int
1863
print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1864
{
1865
  int status;
1866
  bfd_byte buffer[2];
1867
  int length;
1868
  int insn;
1869
  bfd_boolean use_extend;
1870
  int extend = 0;
1871
  const struct mips_opcode *op, *opend;
1872
 
1873
  info->bytes_per_chunk = 2;
1874
  info->display_endian = info->endian;
1875
  info->insn_info_valid = 1;
1876
  info->branch_delay_insns = 0;
1877
  info->data_size = 0;
1878
  info->insn_type = dis_nonbranch;
1879
  info->target = 0;
1880
  info->target2 = 0;
1881
 
1882
  status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1883
  if (status != 0)
1884
    {
1885
      (*info->memory_error_func) (status, memaddr, info);
1886
      return -1;
1887
    }
1888
 
1889
  length = 2;
1890
 
1891
  if (info->endian == BFD_ENDIAN_BIG)
1892
    insn = bfd_getb16 (buffer);
1893
  else
1894
    insn = bfd_getl16 (buffer);
1895
 
1896
  /* Handle the extend opcode specially.  */
1897
  use_extend = FALSE;
1898
  if ((insn & 0xf800) == 0xf000)
1899
    {
1900
      use_extend = TRUE;
1901
      extend = insn & 0x7ff;
1902
 
1903
      memaddr += 2;
1904
 
1905
      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1906
      if (status != 0)
1907
        {
1908
          (*info->fprintf_func) (info->stream, "extend 0x%x",
1909
                                 (unsigned int) extend);
1910
          (*info->memory_error_func) (status, memaddr, info);
1911
          return -1;
1912
        }
1913
 
1914
      if (info->endian == BFD_ENDIAN_BIG)
1915
        insn = bfd_getb16 (buffer);
1916
      else
1917
        insn = bfd_getl16 (buffer);
1918
 
1919
      /* Check for an extend opcode followed by an extend opcode.  */
1920
      if ((insn & 0xf800) == 0xf000)
1921
        {
1922
          (*info->fprintf_func) (info->stream, "extend 0x%x",
1923
                                 (unsigned int) extend);
1924
          info->insn_type = dis_noninsn;
1925
          return length;
1926
        }
1927
 
1928
      length += 2;
1929
    }
1930
 
1931
  /* FIXME: Should probably use a hash table on the major opcode here.  */
1932
 
1933
  opend = mips16_opcodes + bfd_mips16_num_opcodes;
1934
  for (op = mips16_opcodes; op < opend; op++)
1935
    {
1936
      if (op->pinfo != INSN_MACRO
1937
          && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1938
          && (insn & op->mask) == op->match)
1939
        {
1940
          const char *s;
1941
 
1942
          if (strchr (op->args, 'a') != NULL)
1943
            {
1944
              if (use_extend)
1945
                {
1946
                  (*info->fprintf_func) (info->stream, "extend 0x%x",
1947
                                         (unsigned int) extend);
1948
                  info->insn_type = dis_noninsn;
1949
                  return length - 2;
1950
                }
1951
 
1952
              use_extend = FALSE;
1953
 
1954
              memaddr += 2;
1955
 
1956
              status = (*info->read_memory_func) (memaddr, buffer, 2,
1957
                                                  info);
1958
              if (status == 0)
1959
                {
1960
                  use_extend = TRUE;
1961
                  if (info->endian == BFD_ENDIAN_BIG)
1962
                    extend = bfd_getb16 (buffer);
1963
                  else
1964
                    extend = bfd_getl16 (buffer);
1965
                  length += 2;
1966
                }
1967
            }
1968
 
1969
          (*info->fprintf_func) (info->stream, "%s", op->name);
1970
          if (op->args[0] != '\0')
1971
            (*info->fprintf_func) (info->stream, "\t");
1972
 
1973
          for (s = op->args; *s != '\0'; s++)
1974
            {
1975
              if (*s == ','
1976
                  && s[1] == 'w'
1977
                  && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1978
                      == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1979
                {
1980
                  /* Skip the register and the comma.  */
1981
                  ++s;
1982
                  continue;
1983
                }
1984
              if (*s == ','
1985
                  && s[1] == 'v'
1986
                  && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1987
                      == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1988
                {
1989
                  /* Skip the register and the comma.  */
1990
                  ++s;
1991
                  continue;
1992
                }
1993
              print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1994
                                     info);
1995
            }
1996
 
1997
          if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1998
            {
1999
              info->branch_delay_insns = 1;
2000
              if (info->insn_type != dis_jsr)
2001
                info->insn_type = dis_branch;
2002
            }
2003
 
2004
          return length;
2005
        }
2006
    }
2007
 
2008
  if (use_extend)
2009
    (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2010
  (*info->fprintf_func) (info->stream, "0x%x", insn);
2011
  info->insn_type = dis_noninsn;
2012
 
2013
  return length;
2014
}
2015
 
2016
/* In an environment where we do not know the symbol type of the
2017
   instruction we are forced to assume that the low order bit of the
2018
   instructions' address may mark it as a mips16 instruction.  If we
2019
   are single stepping, or the pc is within the disassembled function,
2020
   this works.  Otherwise, we need a clue.  Sometimes.  */
2021
 
2022
static int
2023
_print_insn_mips (bfd_vma memaddr,
2024
                  struct disassemble_info *info,
2025
                  enum bfd_endian endianness)
2026
{
2027
  bfd_byte buffer[INSNLEN];
2028
  int status;
2029
 
2030
  set_default_mips_dis_options (info);
2031
  parse_mips_dis_options (info->disassembler_options);
2032
 
2033
#if 1
2034
  /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
2035
  /* Only a few tools will work this way.  */
2036
  if (memaddr & 0x01)
2037
    return print_insn_mips16 (memaddr, info);
2038
#endif
2039
 
2040
#if SYMTAB_AVAILABLE
2041
  if (info->mach == bfd_mach_mips16
2042
      || (info->flavour == bfd_target_elf_flavour
2043
          && info->symbols != NULL
2044
          && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
2045
              == STO_MIPS16)))
2046
    return print_insn_mips16 (memaddr, info);
2047
#endif
2048
 
2049
  status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2050
  if (status == 0)
2051
    {
2052
      unsigned long insn;
2053
 
2054
      if (endianness == BFD_ENDIAN_BIG)
2055
        insn = (unsigned long) bfd_getb32 (buffer);
2056
      else
2057
        insn = (unsigned long) bfd_getl32 (buffer);
2058
 
2059
      return print_insn_mips (memaddr, insn, info);
2060
    }
2061
  else
2062
    {
2063
      (*info->memory_error_func) (status, memaddr, info);
2064
      return -1;
2065
    }
2066
}
2067
 
2068
int
2069
print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2070
{
2071
  return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2072
}
2073
 
2074
int
2075
print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2076
{
2077
  return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2078
}
2079
 
2080
void
2081
print_mips_disassembler_options (FILE *stream)
2082
{
2083
  unsigned int i;
2084
 
2085
  fprintf (stream, _("\n\
2086
The following MIPS specific disassembler options are supported for use\n\
2087
with the -M switch (multiple options should be separated by commas):\n"));
2088
 
2089
  fprintf (stream, _("\n\
2090
  gpr-names=ABI            Print GPR names according to  specified ABI.\n\
2091
                           Default: based on binary being disassembled.\n"));
2092
 
2093
  fprintf (stream, _("\n\
2094
  fpr-names=ABI            Print FPR names according to specified ABI.\n\
2095
                           Default: numeric.\n"));
2096
 
2097
  fprintf (stream, _("\n\
2098
  cp0-names=ARCH           Print CP0 register names according to\n\
2099
                           specified architecture.\n\
2100
                           Default: based on binary being disassembled.\n"));
2101
 
2102
  fprintf (stream, _("\n\
2103
  hwr-names=ARCH           Print HWR names according to specified \n\
2104
                           architecture.\n\
2105
                           Default: based on binary being disassembled.\n"));
2106
 
2107
  fprintf (stream, _("\n\
2108
  reg-names=ABI            Print GPR and FPR names according to\n\
2109
                           specified ABI.\n"));
2110
 
2111
  fprintf (stream, _("\n\
2112
  reg-names=ARCH           Print CP0 register and HWR names according to\n\
2113
                           specified architecture.\n"));
2114
 
2115
  fprintf (stream, _("\n\
2116
  For the options above, the following values are supported for \"ABI\":\n\
2117
   "));
2118
  for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2119
    fprintf (stream, " %s", mips_abi_choices[i].name);
2120
  fprintf (stream, _("\n"));
2121
 
2122
  fprintf (stream, _("\n\
2123
  For the options above, The following values are supported for \"ARCH\":\n\
2124
   "));
2125
  for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2126
    if (*mips_arch_choices[i].name != '\0')
2127
      fprintf (stream, " %s", mips_arch_choices[i].name);
2128
  fprintf (stream, _("\n"));
2129
 
2130
  fprintf (stream, _("\n"));
2131
}

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