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/* ppc-opc.c -- PowerPC opcode list

   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,

   2005, 2006, 2007, 2008 Free Software Foundation, Inc.

   Written by Ian Lance Taylor, Cygnus Support

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING.  If not, write to the

   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

#include <stdio.h>

#include "sysdep.h"

#include "opcode/ppc.h"

#include "opintl.h"

/* This file holds the PowerPC opcode table.  The opcode table

   includes almost all of the extended instruction mnemonics.  This

   permits the disassembler to use them, and simplifies the assembler

   logic, at the cost of increasing the table size.  The table is

   strictly constant data, so the compiler should be able to put it in

   the .text section.

   This file also holds the operand table.  All knowledge about

   inserting operands into instructions and vice-versa is kept in this

   file.  */

/* Local insertion and extraction functions.  */

static unsigned long insert_bat (unsigned long, long, int, const char **);

static long extract_bat (unsigned long, int, int *);

static unsigned long insert_bba (unsigned long, long, int, const char **);

static long extract_bba (unsigned long, int, int *);

static unsigned long insert_bdm (unsigned long, long, int, const char **);

static long extract_bdm (unsigned long, int, int *);

static unsigned long insert_bdp (unsigned long, long, int, const char **);

static long extract_bdp (unsigned long, int, int *);

static unsigned long insert_bo (unsigned long, long, int, const char **);

static long extract_bo (unsigned long, int, int *);

static unsigned long insert_boe (unsigned long, long, int, const char **);

static long extract_boe (unsigned long, int, int *);

static unsigned long insert_fxm (unsigned long, long, int, const char **);

static long extract_fxm (unsigned long, int, int *);

static unsigned long insert_mbe (unsigned long, long, int, const char **);

static long extract_mbe (unsigned long, int, int *);

static unsigned long insert_mb6 (unsigned long, long, int, const char **);

static long extract_mb6 (unsigned long, int, int *);

static long extract_nb (unsigned long, int, int *);

static unsigned long insert_nsi (unsigned long, long, int, const char **);

static long extract_nsi (unsigned long, int, int *);

static unsigned long insert_ral (unsigned long, long, int, const char **);

static unsigned long insert_ram (unsigned long, long, int, const char **);

static unsigned long insert_raq (unsigned long, long, int, const char **);

static unsigned long insert_ras (unsigned long, long, int, const char **);

static unsigned long insert_rbs (unsigned long, long, int, const char **);

static long extract_rbs (unsigned long, int, int *);

static unsigned long insert_sh6 (unsigned long, long, int, const char **);

static long extract_sh6 (unsigned long, int, int *);

static unsigned long insert_spr (unsigned long, long, int, const char **);

static long extract_spr (unsigned long, int, int *);

static unsigned long insert_sprg (unsigned long, long, int, const char **);

static long extract_sprg (unsigned long, int, int *);

static unsigned long insert_tbr (unsigned long, long, int, const char **);

static long extract_tbr (unsigned long, int, int *);

/* The operands table.

   The fields are bitm, shift, insert, extract, flags.

   We used to put parens around the various additions, like the one

   for BA just below.  However, that caused trouble with feeble

   compilers with a limit on depth of a parenthesized expression, like

   (reportedly) the compiler in Microsoft Developer Studio 5.  So we

   omit the parens, since the macros are never used in a context where

   the addition will be ambiguous.  */

const struct powerpc_operand powerpc_operands[] =

{

  /* The zero index is used to indicate the end of the list of

     operands.  */

#define UNUSED 0

  { 0, 0, NULL, NULL, 0 },

  /* The BA field in an XL form instruction.  */

#define BA UNUSED + 1

  /* The BI field in a B form or XL form instruction.  */

#define BI BA

#define BI_MASK (0x1f << 16)

  { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },

  /* The BA field in an XL form instruction when it must be the same

     as the BT field in the same instruction.  */

#define BAT BA + 1

  { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },

  /* The BB field in an XL form instruction.  */

#define BB BAT + 1

#define BB_MASK (0x1f << 11)

  { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },

  /* The BB field in an XL form instruction when it must be the same

     as the BA field in the same instruction.  */

#define BBA BB + 1

  { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },

  /* The BD field in a B form instruction.  The lower two bits are

     forced to zero.  */

#define BD BBA + 1

  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when absolute addressing is

     used.  */

#define BDA BD + 1

  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used.

     This sets the y bit of the BO field appropriately.  */

#define BDM BDA + 1

  { 0xfffc, 0, insert_bdm, extract_bdm,

      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used

     and absolute address is used.  */

#define BDMA BDM + 1

  { 0xfffc, 0, insert_bdm, extract_bdm,

      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used.

     This sets the y bit of the BO field appropriately.  */

#define BDP BDMA + 1

  { 0xfffc, 0, insert_bdp, extract_bdp,

      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used

     and absolute addressing is used.  */

#define BDPA BDP + 1

  { 0xfffc, 0, insert_bdp, extract_bdp,

      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BF field in an X or XL form instruction.  */

#define BF BDPA + 1

  /* The CRFD field in an X form instruction.  */

#define CRFD BF

  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },

  /* The BF field in an X or XL form instruction.  */

#define BFF BF + 1

  { 0x7, 23, NULL, NULL, 0 },

  /* An optional BF field.  This is used for comparison instructions,

     in which an omitted BF field is taken as zero.  */

#define OBF BFF + 1

  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

  /* The BFA field in an X or XL form instruction.  */

#define BFA OBF + 1

  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },

  /* The BO field in a B form instruction.  Certain values are

     illegal.  */

#define BO BFA + 1

#define BO_MASK (0x1f << 21)

  { 0x1f, 21, insert_bo, extract_bo, 0 },

  /* The BO field in a B form instruction when the + or - modifier is

     used.  This is like the BO field, but it must be even.  */

#define BOE BO + 1

  { 0x1e, 21, insert_boe, extract_boe, 0 },

#define BH BOE + 1

  { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The BT field in an X or XL form instruction.  */

#define BT BH + 1

  { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },

  /* The condition register number portion of the BI field in a B form

     or XL form instruction.  This is used for the extended

     conditional branch mnemonics, which set the lower two bits of the

     BI field.  This field is optional.  */

#define CR BT + 1

  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

  /* The CRB field in an X form instruction.  */

#define CRB CR + 1

  /* The MB field in an M form instruction.  */

#define MB CRB

#define MB_MASK (0x1f << 6)

  { 0x1f, 6, NULL, NULL, 0 },

  /* The CRFS field in an X form instruction.  */

#define CRFS CRB + 1

  { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },

  /* The CT field in an X form instruction.  */

#define CT CRFS + 1

  /* The MO field in an mbar instruction.  */

#define MO CT

  { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The D field in a D form instruction.  This is a displacement off

     a register, and implies that the next operand is a register in

     parentheses.  */

#define D CT + 1

  { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DE field in a DE form instruction.  This is like D, but is 12

     bits only.  */

#define DE D + 1

  { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DES field in a DES form instruction.  This is like DS, but is 14

     bits only (12 stored.)  */

#define DES DE + 1

  { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DQ field in a DQ form instruction.  This is like D, but the

     lower four bits are forced to zero. */

#define DQ DES + 1

  { 0xfff0, 0, NULL, NULL,

    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },

  /* The DS field in a DS form instruction.  This is like D, but the

     lower two bits are forced to zero.  */

#define DS DQ + 1

  { 0xfffc, 0, NULL, NULL,

    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },

  /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */

#define DUIS DS + 1

  { 0x3ff, 11, NULL, NULL, 0 },

  /* The E field in a wrteei instruction.  */

  /* And the W bit in the pair singles instructions.  */

#define E DUIS + 1

#define PSW E

  { 0x1, 15, NULL, NULL, 0 },

  /* The FL1 field in a POWER SC form instruction.  */

#define FL1 E + 1

  /* The U field in an X form instruction.  */

#define U FL1

  { 0xf, 12, NULL, NULL, 0 },

  /* The FL2 field in a POWER SC form instruction.  */

#define FL2 FL1 + 1

  { 0x7, 2, NULL, NULL, 0 },

  /* The FLM field in an XFL form instruction.  */

#define FLM FL2 + 1

  { 0xff, 17, NULL, NULL, 0 },

  /* The FRA field in an X or A form instruction.  */

#define FRA FLM + 1

#define FRA_MASK (0x1f << 16)

  { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRB field in an X or A form instruction.  */

#define FRB FRA + 1

#define FRB_MASK (0x1f << 11)

  { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRC field in an A form instruction.  */

#define FRC FRB + 1

#define FRC_MASK (0x1f << 6)

  { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRS field in an X form instruction or the FRT field in a D, X

     or A form instruction.  */

#define FRS FRC + 1

#define FRT FRS

  { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },

  /* The FXM field in an XFX instruction.  */

#define FXM FRS + 1

  { 0xff, 12, insert_fxm, extract_fxm, 0 },

  /* Power4 version for mfcr.  */

#define FXM4 FXM + 1

  { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },

  /* The L field in a D or X form instruction.  */

#define L FXM4 + 1

  { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The LEV field in a POWER SVC form instruction.  */

#define SVC_LEV L + 1

  { 0x7f, 5, NULL, NULL, 0 },

  /* The LEV field in an SC form instruction.  */

#define LEV SVC_LEV + 1

  { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The LI field in an I form instruction.  The lower two bits are

     forced to zero.  */

#define LI LEV + 1

  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The LI field in an I form instruction when used as an absolute

     address.  */

#define LIA LI + 1

  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The LS field in an X (sync) form instruction.  */

#define LS LIA + 1

  { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The ME field in an M form instruction.  */

#define ME LS + 1

#define ME_MASK (0x1f << 1)

  { 0x1f, 1, NULL, NULL, 0 },

  /* The MB and ME fields in an M form instruction expressed a single

     operand which is a bitmask indicating which bits to select.  This

     is a two operand form using PPC_OPERAND_NEXT.  See the

     description in opcode/ppc.h for what this means.  */

#define MBE ME + 1

  { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },

  { -1, 0, insert_mbe, extract_mbe, 0 },

  /* The MB or ME field in an MD or MDS form instruction.  The high

     bit is wrapped to the low end.  */

#define MB6 MBE + 2

#define ME6 MB6

#define MB6_MASK (0x3f << 5)

  { 0x3f, 5, insert_mb6, extract_mb6, 0 },

  /* The NB field in an X form instruction.  The value 32 is stored as

     0.  */

#define NB MB6 + 1

  { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },

  /* The NSI field in a D form instruction.  This is the same as the

     SI field, only negated.  */

#define NSI NB + 1

  { 0xffff, 0, insert_nsi, extract_nsi,

      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },

  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */

#define RA NSI + 1

#define RA_MASK (0x1f << 16)

  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },

  /* As above, but 0 in the RA field means zero, not r0.  */

#define RA0 RA + 1

  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in the DQ form lq instruction, which has special

     value restrictions.  */

#define RAQ RA0 + 1

  { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in a D or X form instruction which is an updating

     load, which means that the RA field may not be zero and may not

     equal the RT field.  */

#define RAL RAQ + 1

  { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in an lmw instruction, which has special value

     restrictions.  */

#define RAM RAL + 1

  { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in a D or X form instruction which is an updating

     store or an updating floating point load, which means that the RA

     field may not be zero.  */

#define RAS RAM + 1

  { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field of the tlbwe instruction, which is optional.  */

#define RAOPT RAS + 1

  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },

  /* The RB field in an X, XO, M, or MDS form instruction.  */

#define RB RAOPT + 1

#define RB_MASK (0x1f << 11)

  { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },

  /* The RB field in an X form instruction when it must be the same as

     the RS field in the instruction.  This is used for extended

     mnemonics like mr.  */

#define RBS RB + 1

  { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },

  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form

     instruction or the RT field in a D, DS, X, XFX or XO form

     instruction.  */

#define RS RBS + 1

#define RT RS

#define RT_MASK (0x1f << 21)

  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },

  /* The RS and RT fields of the DS form stq instruction, which have

     special value restrictions.  */

#define RSQ RS + 1

#define RTQ RSQ

  { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },

  /* The RS field of the tlbwe instruction, which is optional.  */

#define RSO RSQ + 1

#define RTO RSO

  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },

  /* The SH field in an X or M form instruction.  */

#define SH RSO + 1

#define SH_MASK (0x1f << 11)

  /* The other UIMM field in a EVX form instruction.  */

#define EVUIMM SH

  { 0x1f, 11, NULL, NULL, 0 },

  /* The SH field in an MD form instruction.  This is split.  */

#define SH6 SH + 1

#define SH6_MASK ((0x1f << 11) | (1 << 1))

  { 0x3f, -1, insert_sh6, extract_sh6, 0 },

  /* The SH field of the tlbwe instruction, which is optional.  */

#define SHO SH6 + 1

  { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The SI field in a D form instruction.  */

#define SI SHO + 1

  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },

  /* The SI field in a D form instruction when we accept a wide range

     of positive values.  */

#define SISIGNOPT SI + 1

  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

  /* The SPR field in an XFX form instruction.  This is flipped--the

     lower 5 bits are stored in the upper 5 and vice- versa.  */

#define SPR SISIGNOPT + 1

#define PMR SPR

#define SPR_MASK (0x3ff << 11)

  { 0x3ff, 11, insert_spr, extract_spr, 0 },

  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */

#define SPRBAT SPR + 1

#define SPRBAT_MASK (0x3 << 17)

  { 0x3, 17, NULL, NULL, 0 },

  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */

#define SPRG SPRBAT + 1

  { 0x1f, 16, insert_sprg, extract_sprg, 0 },

  /* The SR field in an X form instruction.  */

#define SR SPRG + 1

  { 0xf, 16, NULL, NULL, 0 },

  /* The STRM field in an X AltiVec form instruction.  */

#define STRM SR + 1

  /* The T field in a tlbilx form instruction.  */

#define T STRM

  { 0x3, 21, NULL, NULL, 0 },

  /* The SV field in a POWER SC form instruction.  */

#define SV STRM + 1

  { 0x3fff, 2, NULL, NULL, 0 },

  /* The TBR field in an XFX form instruction.  This is like the SPR

     field, but it is optional.  */

#define TBR SV + 1

  { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },

  /* The TO field in a D or X form instruction.  */

#define TO TBR + 1

#define DUI TO

#define TO_MASK (0x1f << 21)

  { 0x1f, 21, NULL, NULL, 0 },

  /* The UI field in a D form instruction.  */

#define UI TO + 1

  { 0xffff, 0, NULL, NULL, 0 },

  /* The VA field in a VA, VX or VXR form instruction.  */

#define VA UI + 1

  { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },

  /* The VB field in a VA, VX or VXR form instruction.  */

#define VB VA + 1

  { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },

  /* The VC field in a VA form instruction.  */

#define VC VB + 1

  { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },

  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */

#define VD VC + 1

#define VS VD

  { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },

  /* The SIMM field in a VX form instruction, and TE in Z form.  */

#define SIMM VD + 1

#define TE SIMM

  { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},

  /* The UIMM field in a VX form instruction.  */

#define UIMM SIMM + 1

  { 0x1f, 16, NULL, NULL, 0 },

  /* The SHB field in a VA form instruction.  */

#define SHB UIMM + 1

  { 0xf, 6, NULL, NULL, 0 },

  /* The other UIMM field in a half word EVX form instruction.  */

#define EVUIMM_2 SHB + 1

  { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },

  /* The other UIMM field in a word EVX form instruction.  */

#define EVUIMM_4 EVUIMM_2 + 1

  { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },

  /* The other UIMM field in a double EVX form instruction.  */

#define EVUIMM_8 EVUIMM_4 + 1

  { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },

  /* The WS field.  */

#define WS EVUIMM_8 + 1

  { 0x7, 11, NULL, NULL, 0 },

  /* PowerPC paired singles extensions.  */

  /* W bit in the pair singles instructions for x type instructions.  */

#define PSWM WS + 1

  {  0x1, 10, 0, 0, 0 },

  /* IDX bits for quantization in the pair singles instructions.  */

#define PSQ PSWM + 1

  {  0x7, 12, 0, 0, 0 },

  /* IDX bits for quantization in the pair singles x-type instructions.  */

#define PSQM PSQ + 1

  {  0x7, 7, 0, 0, 0 },

  /* Smaller D field for quantization in the pair singles instructions.  */

#define PSD PSQM + 1

  {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

#define A_L PSD + 1

#define W A_L

#define MTMSRD_L W

  { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },

#define RMC MTMSRD_L + 1

  { 0x3, 9, NULL, NULL, 0 },

#define R RMC + 1

  { 0x1, 16, NULL, NULL, 0 },

#define SP R + 1

  { 0x3, 19, NULL, NULL, 0 },

#define S SP + 1

  { 0x1, 20, NULL, NULL, 0 },

  /* SH field starting at bit position 16.  */

#define SH16 S + 1

  /* The DCM and DGM fields in a Z form instruction.  */

#define DCM SH16

#define DGM DCM

  { 0x3f, 10, NULL, NULL, 0 },

  /* The EH field in larx instruction.  */

#define EH SH16 + 1

  { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The L field in an mtfsf or XFL form instruction.  */

#define XFL_L EH + 1

  { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},

};

const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)

                                           / sizeof (powerpc_operands[0]));

/* The functions used to insert and extract complicated operands.  */

/* The BA field in an XL form instruction when it must be the same as

   the BT field in the same instruction.  This operand is marked FAKE.

   The insertion function just copies the BT field into the BA field,

   and the extraction function just checks that the fields are the

   same.  */

static unsigned long

insert_bat (unsigned long insn,

            long value ATTRIBUTE_UNUSED,

            int dialect ATTRIBUTE_UNUSED,

            const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | (((insn >> 21) & 0x1f) << 16);

}

static long

extract_bat (unsigned long insn,

             int dialect ATTRIBUTE_UNUSED,

             int *invalid)

{

  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))

    *invalid = 1;

  return 0;

}

/* The BB field in an XL form instruction when it must be the same as

   the BA field in the same instruction.  This operand is marked FAKE.

   The insertion function just copies the BA field into the BB field,

   and the extraction function just checks that the fields are the

   same.  */

static unsigned long

insert_bba (unsigned long insn,

            long value ATTRIBUTE_UNUSED,

            int dialect ATTRIBUTE_UNUSED,

            const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | (((insn >> 16) & 0x1f) << 11);

}

static long

extract_bba (unsigned long insn,

             int dialect ATTRIBUTE_UNUSED,

             int *invalid)

{

  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))

    *invalid = 1;

  return 0;

}

/* The BD field in a B form instruction when the - modifier is used.

   This modifier means that the branch is not expected to be taken.

   For chips built to versions of the architecture prior to version 2

   (ie. not Power4 compatible), we set the y bit of the BO field to 1

   if the offset is negative.  When extracting, we require that the y

   bit be 1 and that the offset be positive, since if the y bit is 0

   we just want to print the normal form of the instruction.

   Power4 compatible targets use two bits, "a", and "t", instead of

   the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,

   "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001

   in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000

   for branch on CTR.  We only handle the taken/not-taken hint here.

   Note that we don't relax the conditions tested here when