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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [opcodes/] [sparc-opc.c] - Blame information for rev 816

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1 38 julius
/* Table of opcodes for the sparc.
2
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3
   2000, 2002, 2004, 2005, 2007
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of the GNU opcodes library.
7
 
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
 
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this file; see the file COPYING.  If not, write to the
20
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22
 
23
 
24
/* FIXME-someday: perhaps the ,a's and such should be embedded in the
25
   instruction's name rather than the args.  This would make gas faster, pinsn
26
   slower, but would mess up some macros a bit.  xoxorich. */
27
 
28
#include <stdio.h>
29
#include "sysdep.h"
30
#include "opcode/sparc.h"
31
 
32
/* Some defines to make life easy.  */
33
#define MASK_V6         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
34
#define MASK_V7         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
35
#define MASK_V8         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
36
#define MASK_SPARCLET   SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
37
#define MASK_SPARCLITE  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
38
#define MASK_V9         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
39
#define MASK_V9A        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
40
#define MASK_V9B        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
41
 
42
/* Bit masks of architectures supporting the insn.  */
43
 
44
#define v6              (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
45
                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
46
/* v6 insns not supported on the sparclet.  */
47
#define v6notlet        (MASK_V6 | MASK_V7 | MASK_V8 \
48
                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
49
#define v7              (MASK_V7 | MASK_V8 | MASK_SPARCLET \
50
                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
51
/* Although not all insns are implemented in hardware, sparclite is defined
52
   to be a superset of v8.  Unimplemented insns trap and are then theoretically
53
   implemented in software.
54
   It's not clear that the same is true for sparclet, although the docs
55
   suggest it is.  Rather than complicating things, the sparclet assembler
56
   recognizes all v8 insns.  */
57
#define v8              (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
58
                         | MASK_V9 | MASK_V9A | MASK_V9B)
59
#define sparclet        (MASK_SPARCLET)
60
#define sparclite       (MASK_SPARCLITE)
61
#define v9              (MASK_V9 | MASK_V9A | MASK_V9B)
62
#define v9a             (MASK_V9A | MASK_V9B)
63
#define v9b             (MASK_V9B)
64
/* v6 insns not supported by v9.  */
65
#define v6notv9         (MASK_V6 | MASK_V7 | MASK_V8 \
66
                         | MASK_SPARCLET | MASK_SPARCLITE)
67
/* v9a instructions which would appear to be aliases to v9's impdep's
68
   otherwise.  */
69
#define v9notv9a        (MASK_V9)
70
 
71
/* Table of opcode architectures.
72
   The order is defined in opcode/sparc.h.  */
73
 
74
const struct sparc_opcode_arch sparc_opcode_archs[] =
75
{
76
  { "v6", MASK_V6 },
77
  { "v7", MASK_V6 | MASK_V7 },
78
  { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
79
  { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
80
  { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
81
  /* ??? Don't some v8 priviledged insns conflict with v9?  */
82
  { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
83
  /* v9 with ultrasparc additions */
84
  { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
85
  /* v9 with cheetah additions */
86
  { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
87
  { NULL, 0 }
88
};
89
 
90
/* Given NAME, return it's architecture entry.  */
91
 
92
enum sparc_opcode_arch_val
93
sparc_opcode_lookup_arch (const char *name)
94
{
95
  const struct sparc_opcode_arch *p;
96
 
97
  for (p = &sparc_opcode_archs[0]; p->name; ++p)
98
    if (strcmp (name, p->name) == 0)
99
      return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
100
 
101
  return SPARC_OPCODE_ARCH_BAD;
102
}
103
 
104
/* Branch condition field.  */
105
#define COND(x)         (((x) & 0xf) << 25)
106
 
107
/* v9: Move (MOVcc and FMOVcc) condition field.  */
108
#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
109
 
110
/* v9: Move register (MOVRcc and FMOVRcc) condition field.  */
111
#define RCOND(x)        (((x) & 0x7) << 10)     /* v9 */
112
 
113
#define CONDA   (COND (0x8))
114
#define CONDCC  (COND (0xd))
115
#define CONDCS  (COND (0x5))
116
#define CONDE   (COND (0x1))
117
#define CONDG   (COND (0xa))
118
#define CONDGE  (COND (0xb))
119
#define CONDGU  (COND (0xc))
120
#define CONDL   (COND (0x3))
121
#define CONDLE  (COND (0x2))
122
#define CONDLEU (COND (0x4))
123
#define CONDN   (COND (0x0))
124
#define CONDNE  (COND (0x9))
125
#define CONDNEG (COND (0x6))
126
#define CONDPOS (COND (0xe))
127
#define CONDVC  (COND (0xf))
128
#define CONDVS  (COND (0x7))
129
 
130
#define CONDNZ  CONDNE
131
#define CONDZ   CONDE
132
#define CONDGEU CONDCC
133
#define CONDLU  CONDCS
134
 
135
#define FCONDA          (COND (0x8))
136
#define FCONDE          (COND (0x9))
137
#define FCONDG          (COND (0x6))
138
#define FCONDGE         (COND (0xb))
139
#define FCONDL          (COND (0x4))
140
#define FCONDLE         (COND (0xd))
141
#define FCONDLG         (COND (0x2))
142
#define FCONDN          (COND (0x0))
143
#define FCONDNE         (COND (0x1))
144
#define FCONDO          (COND (0xf))
145
#define FCONDU          (COND (0x7))
146
#define FCONDUE         (COND (0xa))
147
#define FCONDUG         (COND (0x5))
148
#define FCONDUGE        (COND (0xc))
149
#define FCONDUL         (COND (0x3))
150
#define FCONDULE        (COND (0xe))
151
 
152
#define FCONDNZ FCONDNE
153
#define FCONDZ  FCONDE
154
 
155
#define ICC             (0)     /* v9 */
156
#define XCC             (1 << 12) /* v9 */
157
#define FCC(x)          (((x) & 0x3) << 11) /* v9 */
158
#define FBFCC(x)        (((x) & 0x3) << 20)     /* v9 */
159
 
160
/* The order of the opcodes in the table is significant:
161
 
162
        * The assembler requires that all instances of the same mnemonic must
163
        be consecutive. If they aren't, the assembler will bomb at runtime.
164
 
165
        * The disassembler should not care about the order of the opcodes.  */
166
 
167
/* Entries for commutative arithmetic operations.  */
168
/* ??? More entries can make use of this.  */
169
#define COMMUTEOP(opcode, op3, arch_mask) \
170
{ opcode,       F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),   "1,2,d", 0, arch_mask }, \
171
{ opcode,       F3(2, op3, 1), F3(~2, ~op3, ~1),                "1,i,d", 0, arch_mask }, \
172
{ opcode,       F3(2, op3, 1), F3(~2, ~op3, ~1),                "i,1,d", 0, arch_mask }
173
 
174
const struct sparc_opcode sparc_opcodes[] = {
175
 
176
{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0),                "[1+2],d", 0, v6 },
177
{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
178
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", 0, v6 },
179
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", 0, v6 },
180
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", 0, v6 },
181
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),    "[1],d", 0, v6 }, /* ld [rs1+0],d */
182
{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0),                "[1+2],g", 0, v6 },
183
{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
184
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[1+i],g", 0, v6 },
185
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[i+1],g", 0, v6 },
186
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,       "[i],g", 0, v6 },
187
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),    "[1],g", 0, v6 }, /* ld [rs1+0],d */
188
 
189
{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),  "[1+2],F", 0, v6 },
190
{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
191
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),        "[1+i],F", 0, v6 },
192
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),        "[i+1],F", 0, v6 },
193
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
194
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
195
 
196
{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0),                "[1+2],D", 0, v6notv9 },
197
{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */
198
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i],D", 0, v6notv9 },
199
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1],D", 0, v6notv9 },
200
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i],D", 0, v6notv9 },
201
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),    "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */
202
{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0),                "[1+2],C", 0, v6notv9 },
203
{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */
204
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[1+i],C", 0, v6notv9 },
205
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1),              "[i+1],C", 0, v6notv9 },
206
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,       "[i],C", 0, v6notv9 },
207
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),    "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */
208
 
209
/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
210
   'ld' pseudo-op in v9.  */
211
{ "lduw",       F3(3, 0x00, 0), F3(~3, ~0x00, ~0),                "[1+2],d", F_ALIAS, v9 },
212
{ "lduw",       F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */
213
{ "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", F_ALIAS, v9 },
214
{ "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", F_ALIAS, v9 },
215
{ "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", F_ALIAS, v9 },
216
{ "lduw",       F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),    "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */
217
 
218
{ "ldd",        F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 },
219
{ "ldd",        F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),     "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
220
{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[1+i],d", 0, v6 },
221
{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1),              "[i+1],d", 0, v6 },
222
{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,       "[i],d", 0, v6 },
223
{ "ldd",        F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),    "[1],d", 0, v6 }, /* ldd [rs1+0],d */
224
{ "ldd",        F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 },
225
{ "ldd",        F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),     "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
226
{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[1+i],H", 0, v6 },
227
{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1),              "[i+1],H", 0, v6 },
228
{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,       "[i],H", 0, v6 },
229
{ "ldd",        F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),    "[1],H", 0, v6 }, /* ldd [rs1+0],d */
230
 
231
{ "ldd",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 },
232
{ "ldd",        F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),     "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */
233
{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i],D", 0, v6notv9 },
234
{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1],D", 0, v6notv9 },
235
{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i],D", 0, v6notv9 },
236
{ "ldd",        F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),    "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */
237
 
238
{ "ldq",        F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 },
239
{ "ldq",        F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0),     "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */
240
{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[1+i],J", 0, v9 },
241
{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1),              "[i+1],J", 0, v9 },
242
{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0,       "[i],J", 0, v9 },
243
{ "ldq",        F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0),    "[1],J", 0, v9 }, /* ldd [rs1+0],d */
244
 
245
{ "ldsb",       F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 },
246
{ "ldsb",       F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),     "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
247
{ "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[1+i],d", 0, v6 },
248
{ "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1),              "[i+1],d", 0, v6 },
249
{ "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,       "[i],d", 0, v6 },
250
{ "ldsb",       F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),    "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
251
 
252
{ "ldsh",       F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),     "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
253
{ "ldsh",       F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 },
254
{ "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[1+i],d", 0, v6 },
255
{ "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),              "[i+1],d", 0, v6 },
256
{ "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,       "[i],d", 0, v6 },
257
{ "ldsh",       F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),    "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
258
 
259
{ "ldstub",     F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 },
260
{ "ldstub",     F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),     "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
261
{ "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[1+i],d", 0, v6 },
262
{ "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),              "[i+1],d", 0, v6 },
263
{ "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,       "[i],d", 0, v6 },
264
{ "ldstub",     F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0),    "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
265
 
266
{ "ldsw",       F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 },
267
{ "ldsw",       F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0),     "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */
268
{ "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[1+i],d", 0, v9 },
269
{ "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1),              "[i+1],d", 0, v9 },
270
{ "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0,       "[i],d", 0, v9 },
271
{ "ldsw",       F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0),    "[1],d", 0, v9 }, /* ldsw [rs1+0],d */
272
 
273
{ "ldub",       F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 },
274
{ "ldub",       F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),     "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
275
{ "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[1+i],d", 0, v6 },
276
{ "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1),              "[i+1],d", 0, v6 },
277
{ "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,       "[i],d", 0, v6 },
278
{ "ldub",       F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),    "[1],d", 0, v6 }, /* ldub [rs1+0],d */
279
 
280
{ "lduh",       F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 },
281
{ "lduh",       F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),     "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
282
{ "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[1+i],d", 0, v6 },
283
{ "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1),              "[i+1],d", 0, v6 },
284
{ "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,       "[i],d", 0, v6 },
285
{ "lduh",       F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),    "[1],d", 0, v6 }, /* lduh [rs1+0],d */
286
 
287
{ "ldx",        F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 },
288
{ "ldx",        F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),     "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */
289
{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[1+i],d", 0, v9 },
290
{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),              "[i+1],d", 0, v9 },
291
{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0,       "[i],d", 0, v9 },
292
{ "ldx",        F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0),    "[1],d", 0, v9 }, /* ldx [rs1+0],d */
293
 
294
{ "ldx",        F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1),   "[1+2],F", 0, v9 },
295
{ "ldx",        F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),    "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
296
{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 },
297
{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 },
298
{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),  "[i],F", 0, v9 },
299
{ "ldx",        F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
300
 
301
{ "lda",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0),                "[1+2]A,d", 0, v6 },
302
{ "lda",        F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
303
{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", 0, v9 },
304
{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", 0, v9 },
305
{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
306
{ "lda",        F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
307
{ "lda",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0),                "[1+2]A,g", 0, v9 },
308
{ "lda",        F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */
309
{ "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[1+i]o,g", 0, v9 },
310
{ "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1),              "[i+1]o,g", 0, v9 },
311
{ "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,       "[i]o,g", 0, v9 },
312
{ "lda",        F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),    "[1]o,g", 0, v9 }, /* ld [rs1+0],d */
313
 
314
{ "ldda",       F3(3, 0x13, 0), F3(~3, ~0x13, ~0),                "[1+2]A,d", 0, v6 },
315
{ "ldda",       F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
316
{ "ldda",       F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[1+i]o,d", 0, v9 },
317
{ "ldda",       F3(3, 0x13, 1), F3(~3, ~0x13, ~1),              "[i+1]o,d", 0, v9 },
318
{ "ldda",       F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
319
{ "ldda",       F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
320
 
321
{ "ldda",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0),                "[1+2]A,H", 0, v9 },
322
{ "ldda",       F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */
323
{ "ldda",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[1+i]o,H", 0, v9 },
324
{ "ldda",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1),              "[i+1]o,H", 0, v9 },
325
{ "ldda",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,       "[i]o,H", 0, v9 },
326
{ "ldda",       F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),    "[1]o,H", 0, v9 }, /* ld [rs1+0],d */
327
 
328
{ "ldqa",       F3(3, 0x32, 0), F3(~3, ~0x32, ~0),                "[1+2]A,J", 0, v9 },
329
{ "ldqa",       F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */
330
{ "ldqa",       F3(3, 0x32, 1), F3(~3, ~0x32, ~1),              "[1+i]o,J", 0, v9 },
331
{ "ldqa",       F3(3, 0x32, 1), F3(~3, ~0x32, ~1),              "[i+1]o,J", 0, v9 },
332
{ "ldqa",       F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0,       "[i]o,J", 0, v9 },
333
{ "ldqa",       F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0),    "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */
334
 
335
{ "ldsba",      F3(3, 0x19, 0), F3(~3, ~0x19, ~0),                "[1+2]A,d", 0, v6 },
336
{ "ldsba",      F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
337
{ "ldsba",      F3(3, 0x19, 1), F3(~3, ~0x19, ~1),              "[1+i]o,d", 0, v9 },
338
{ "ldsba",      F3(3, 0x19, 1), F3(~3, ~0x19, ~1),              "[i+1]o,d", 0, v9 },
339
{ "ldsba",      F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
340
{ "ldsba",      F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
341
 
342
{ "ldsha",      F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),                "[1+2]A,d", 0, v6 },
343
{ "ldsha",      F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
344
{ "ldsha",      F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),              "[1+i]o,d", 0, v9 },
345
{ "ldsha",      F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),              "[i+1]o,d", 0, v9 },
346
{ "ldsha",      F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
347
{ "ldsha",      F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
348
 
349
{ "ldstuba",    F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),                "[1+2]A,d", 0, v6 },
350
{ "ldstuba",    F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
351
{ "ldstuba",    F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),              "[1+i]o,d", 0, v9 },
352
{ "ldstuba",    F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),              "[i+1]o,d", 0, v9 },
353
{ "ldstuba",    F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
354
{ "ldstuba",    F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
355
 
356
{ "ldswa",      F3(3, 0x18, 0), F3(~3, ~0x18, ~0),                "[1+2]A,d", 0, v9 },
357
{ "ldswa",      F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
358
{ "ldswa",      F3(3, 0x18, 1), F3(~3, ~0x18, ~1),              "[1+i]o,d", 0, v9 },
359
{ "ldswa",      F3(3, 0x18, 1), F3(~3, ~0x18, ~1),              "[i+1]o,d", 0, v9 },
360
{ "ldswa",      F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
361
{ "ldswa",      F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
362
 
363
{ "lduba",      F3(3, 0x11, 0), F3(~3, ~0x11, ~0),                "[1+2]A,d", 0, v6 },
364
{ "lduba",      F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
365
{ "lduba",      F3(3, 0x11, 1), F3(~3, ~0x11, ~1),              "[1+i]o,d", 0, v9 },
366
{ "lduba",      F3(3, 0x11, 1), F3(~3, ~0x11, ~1),              "[i+1]o,d", 0, v9 },
367
{ "lduba",      F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
368
{ "lduba",      F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
369
 
370
{ "lduha",      F3(3, 0x12, 0), F3(~3, ~0x12, ~0),                "[1+2]A,d", 0, v6 },
371
{ "lduha",      F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
372
{ "lduha",      F3(3, 0x12, 1), F3(~3, ~0x12, ~1),              "[1+i]o,d", 0, v9 },
373
{ "lduha",      F3(3, 0x12, 1), F3(~3, ~0x12, ~1),              "[i+1]o,d", 0, v9 },
374
{ "lduha",      F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
375
{ "lduha",      F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
376
 
377
{ "lduwa",      F3(3, 0x10, 0), F3(~3, ~0x10, ~0),                "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */
378
{ "lduwa",      F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */
379
{ "lduwa",      F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[1+i]o,d", F_ALIAS, v9 },
380
{ "lduwa",      F3(3, 0x10, 1), F3(~3, ~0x10, ~1),              "[i+1]o,d", F_ALIAS, v9 },
381
{ "lduwa",      F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,       "[i]o,d", F_ALIAS, v9 },
382
{ "lduwa",      F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),    "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */
383
 
384
{ "ldxa",       F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0),                "[1+2]A,d", 0, v9 },
385
{ "ldxa",       F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
386
{ "ldxa",       F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),              "[1+i]o,d", 0, v9 },
387
{ "ldxa",       F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),              "[i+1]o,d", 0, v9 },
388
{ "ldxa",       F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
389
{ "ldxa",       F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
390
 
391
{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),         "d,[1+2]", 0, v6 },
392
{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),             "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
393
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[1+i]", 0, v6 },
394
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1),                      "d,[i+1]", 0, v6 },
395
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,               "d,[i]", 0, v6 },
396
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),            "d,[1]", 0, v6 }, /* st d,[rs1+0] */
397
{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),         "g,[1+2]", 0, v6 },
398
{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),             "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
399
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[1+i]", 0, v6 },
400
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1),                      "g,[i+1]", 0, v6 },
401
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,               "g,[i]", 0, v6 },
402
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),            "g,[1]", 0, v6 }, /* st d,[rs1+0] */
403
 
404
{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),         "D,[1+2]", 0, v6notv9 },
405
{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),             "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
406
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[1+i]", 0, v6notv9 },
407
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1),                      "D,[i+1]", 0, v6notv9 },
408
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,               "D,[i]", 0, v6notv9 },
409
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),            "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
410
{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),         "C,[1+2]", 0, v6notv9 },
411
{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),             "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
412
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[1+i]", 0, v6notv9 },
413
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1),                      "C,[i+1]", 0, v6notv9 },
414
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,               "C,[i]", 0, v6notv9 },
415
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),            "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
416
 
417
{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),   "F,[1+2]", 0, v6 },
418
{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),       "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
419
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[1+i]", 0, v6 },
420
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,                "F,[i+1]", 0, v6 },
421
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,         "F,[i]", 0, v6 },
422
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0),      "F,[1]", 0, v6 }, /* st d,[rs1+0] */
423
 
424
{ "stw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
425
{ "stw",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
426
{ "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, v9 },
427
{ "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, v9 },
428
{ "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v9 },
429
{ "stw",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
430
{ "stsw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
431
{ "stsw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
432
{ "stsw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, v9 },
433
{ "stsw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, v9 },
434
{ "stsw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v9 },
435
{ "stsw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
436
{ "stuw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
437
{ "stuw",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
438
{ "stuw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, v9 },
439
{ "stuw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, v9 },
440
{ "stuw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v9 },
441
{ "stuw",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
442
 
443
{ "spill",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
444
{ "spill",      F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
445
{ "spill",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[1+i]", F_ALIAS, v6 },
446
{ "spill",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1),              "d,[i+1]", F_ALIAS, v6 },
447
{ "spill",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
448
{ "spill",      F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
449
 
450
{ "sta",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0),                "d,[1+2]A", 0, v6 },
451
{ "sta",        F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
452
{ "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", 0, v9 },
453
{ "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", 0, v9 },
454
{ "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
455
{ "sta",        F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),    "d,[1]o", 0, v9 }, /* st d,[rs1+0] */
456
 
457
{ "sta",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0),                "g,[1+2]A", 0, v9 },
458
{ "sta",        F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */
459
{ "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),              "g,[1+i]o", 0, v9 },
460
{ "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1),              "g,[i+1]o", 0, v9 },
461
{ "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,       "g,[i]o", 0, v9 },
462
{ "sta",        F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),    "g,[1]o", 0, v9 }, /* st d,[rs1+0] */
463
 
464
{ "stwa",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0),                "d,[1+2]A", F_ALIAS, v9 },
465
{ "stwa",       F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
466
{ "stwa",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, v9 },
467
{ "stwa",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, v9 },
468
{ "stwa",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
469
{ "stwa",       F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),    "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
470
{ "stswa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0),                "d,[1+2]A", F_ALIAS, v9 },
471
{ "stswa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
472
{ "stswa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, v9 },
473
{ "stswa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, v9 },
474
{ "stswa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
475
{ "stswa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),    "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
476
{ "stuwa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0),                "d,[1+2]A", F_ALIAS, v9 },
477
{ "stuwa",      F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
478
{ "stuwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[1+i]o", F_ALIAS, v9 },
479
{ "stuwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1),              "d,[i+1]o", F_ALIAS, v9 },
480
{ "stuwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
481
{ "stuwa",      F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),    "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
482
 
483
{ "stb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
484
{ "stb",        F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),     "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
485
{ "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", 0, v6 },
486
{ "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", 0, v6 },
487
{ "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", 0, v6 },
488
{ "stb",        F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),    "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
489
 
490
{ "stsb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
491
{ "stsb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
492
{ "stsb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", F_ALIAS, v6 },
493
{ "stsb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", F_ALIAS, v6 },
494
{ "stsb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
495
{ "stsb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
496
{ "stub",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
497
{ "stub",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
498
{ "stub",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[1+i]", F_ALIAS, v6 },
499
{ "stub",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1),              "d,[i+1]", F_ALIAS, v6 },
500
{ "stub",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
501
{ "stub",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
502
 
503
{ "stba",       F3(3, 0x15, 0), F3(~3, ~0x15, ~0),                "d,[1+2]A", 0, v6 },
504
{ "stba",       F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
505
{ "stba",       F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", 0, v9 },
506
{ "stba",       F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", 0, v9 },
507
{ "stba",       F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
508
{ "stba",       F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),    "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */
509
 
510
{ "stsba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0),                "d,[1+2]A", F_ALIAS, v6 },
511
{ "stsba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
512
{ "stsba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", F_ALIAS, v9 },
513
{ "stsba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", F_ALIAS, v9 },
514
{ "stsba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
515
{ "stsba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),    "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
516
{ "stuba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0),                "d,[1+2]A", F_ALIAS, v6 },
517
{ "stuba",      F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
518
{ "stuba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[1+i]o", F_ALIAS, v9 },
519
{ "stuba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1),              "d,[i+1]o", F_ALIAS, v9 },
520
{ "stuba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
521
{ "stuba",      F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),    "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
522
 
523
{ "std",        F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
524
{ "std",        F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),     "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
525
{ "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", 0, v6 },
526
{ "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", 0, v6 },
527
{ "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", 0, v6 },
528
{ "std",        F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),    "d,[1]", 0, v6 }, /* std d,[rs1+0] */
529
 
530
{ "std",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 },
531
{ "std",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),     "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
532
{ "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[1+i]", 0, v6notv9 },
533
{ "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "q,[i+1]", 0, v6notv9 },
534
{ "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "q,[i]", 0, v6notv9 },
535
{ "std",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),    "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
536
{ "std",        F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 },
537
{ "std",        F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),     "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
538
{ "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[1+i]", 0, v6 },
539
{ "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1),              "H,[i+1]", 0, v6 },
540
{ "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0,       "H,[i]", 0, v6 },
541
{ "std",        F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0),    "H,[1]", 0, v6 }, /* std d,[rs1+0] */
542
 
543
{ "std",        F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 },
544
{ "std",        F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),     "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
545
{ "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[1+i]", 0, v6notv9 },
546
{ "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "Q,[i+1]", 0, v6notv9 },
547
{ "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "Q,[i]", 0, v6notv9 },
548
{ "std",        F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),    "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
549
{ "std",        F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
550
{ "std",        F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),     "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
551
{ "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[1+i]", 0, v6notv9 },
552
{ "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "D,[i+1]", 0, v6notv9 },
553
{ "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "D,[i]", 0, v6notv9 },
554
{ "std",        F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),    "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
555
 
556
{ "spilld",     F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
557
{ "spilld",     F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
558
{ "spilld",     F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[1+i]", F_ALIAS, v6 },
559
{ "spilld",     F3(3, 0x07, 1), F3(~3, ~0x07, ~1),              "d,[i+1]", F_ALIAS, v6 },
560
{ "spilld",     F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
561
{ "spilld",     F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
562
 
563
{ "stda",       F3(3, 0x17, 0), F3(~3, ~0x17, ~0),                "d,[1+2]A", 0, v6 },
564
{ "stda",       F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
565
{ "stda",       F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[1+i]o", 0, v9 },
566
{ "stda",       F3(3, 0x17, 1), F3(~3, ~0x17, ~1),              "d,[i+1]o", 0, v9 },
567
{ "stda",       F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
568
{ "stda",       F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),    "d,[1]o", 0, v9 }, /* std d,[rs1+0] */
569
{ "stda",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0),                "H,[1+2]A", 0, v9 },
570
{ "stda",       F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */
571
{ "stda",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[1+i]o", 0, v9 },
572
{ "stda",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1),              "H,[i+1]o", 0, v9 },
573
{ "stda",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,       "H,[i]o", 0, v9 },
574
{ "stda",       F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),    "H,[1]o", 0, v9 }, /* std d,[rs1+0] */
575
 
576
{ "sth",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
577
{ "sth",        F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),     "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
578
{ "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", 0, v6 },
579
{ "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", 0, v6 },
580
{ "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", 0, v6 },
581
{ "sth",        F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),    "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
582
 
583
{ "stsh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
584
{ "stsh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
585
{ "stsh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", F_ALIAS, v6 },
586
{ "stsh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", F_ALIAS, v6 },
587
{ "stsh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
588
{ "stsh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
589
{ "stuh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
590
{ "stuh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),     "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
591
{ "stuh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", F_ALIAS, v6 },
592
{ "stuh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", F_ALIAS, v6 },
593
{ "stuh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", F_ALIAS, v6 },
594
{ "stuh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),    "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
595
 
596
{ "stha",       F3(3, 0x16, 0), F3(~3, ~0x16, ~0),                "d,[1+2]A", 0, v6 },
597
{ "stha",       F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
598
{ "stha",       F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", 0, v9 },
599
{ "stha",       F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", 0, v9 },
600
{ "stha",       F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
601
{ "stha",       F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),    "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
602
 
603
{ "stsha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0),                "d,[1+2]A", F_ALIAS, v6 },
604
{ "stsha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
605
{ "stsha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", F_ALIAS, v9 },
606
{ "stsha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", F_ALIAS, v9 },
607
{ "stsha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
608
{ "stsha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),    "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
609
{ "stuha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0),                "d,[1+2]A", F_ALIAS, v6 },
610
{ "stuha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
611
{ "stuha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", F_ALIAS, v9 },
612
{ "stuha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", F_ALIAS, v9 },
613
{ "stuha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", F_ALIAS, v9 },
614
{ "stuha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),    "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
615
 
616
{ "stx",        F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 },
617
{ "stx",        F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0),     "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
618
{ "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),              "d,[1+i]", 0, v9 },
619
{ "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),              "d,[i+1]", 0, v9 },
620
{ "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0,       "d,[i]", 0, v9 },
621
{ "stx",        F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0),    "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
622
 
623
{ "stx",        F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1),    "F,[1+2]", 0, v9 },
624
{ "stx",        F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
625
{ "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[1+i]", 0, v9 },
626
{ "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[i+1]", 0, v9 },
627
{ "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),  "F,[i]", 0, v9 },
628
{ "stx",        F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
629
 
630
{ "stxa",       F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0),                "d,[1+2]A", 0, v9 },
631
{ "stxa",       F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
632
{ "stxa",       F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[1+i]o", 0, v9 },
633
{ "stxa",       F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[i+1]o", 0, v9 },
634
{ "stxa",       F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
635
{ "stxa",       F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0),    "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
636
 
637
{ "stq",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 },
638
{ "stq",        F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),     "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
639
{ "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[1+i]", 0, v9 },
640
{ "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[i+1]", 0, v9 },
641
{ "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "J,[i]", 0, v9 },
642
{ "stq",        F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),    "J,[1]", 0, v9 }, /* stq [rs1+0] */
643
 
644
{ "stqa",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 },
645
{ "stqa",       F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),     "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
646
{ "stqa",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[1+i]o", 0, v9 },
647
{ "stqa",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[i+1]o", 0, v9 },
648
{ "stqa",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "J,[i]o", 0, v9 },
649
{ "stqa",       F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),    "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
650
 
651
{ "swap",       F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 },
652
{ "swap",       F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),     "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
653
{ "swap",       F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[1+i],d", 0, v7 },
654
{ "swap",       F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),              "[i+1],d", 0, v7 },
655
{ "swap",       F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0,       "[i],d", 0, v7 },
656
{ "swap",       F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0),    "[1],d", 0, v7 }, /* swap [rs1+0],d */
657
 
658
{ "swapa",      F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),                "[1+2]A,d", 0, v7 },
659
{ "swapa",      F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
660
{ "swapa",      F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),              "[1+i]o,d", 0, v9 },
661
{ "swapa",      F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),              "[i+1]o,d", 0, v9 },
662
{ "swapa",      F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0,       "[i]o,d", 0, v9 },
663
{ "swapa",      F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0),    "[1]o,d", 0, v9 }, /* swap [rs1+0],d */
664
 
665
{ "restore",    F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),                 "1,2,d", 0, v6 },
666
{ "restore",    F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),        "", 0, v6 }, /* restore %g0,%g0,%g0 */
667
{ "restore",    F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),                              "1,i,d", 0, v6 },
668
{ "restore",    F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),       "", 0, v6 }, /* restore %g0,0,%g0 */
669
 
670
{ "rett",       F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),   "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
671
{ "rett",       F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),       "1", F_UNBR|F_DELAYED, v6 },    /* rett rs1,%g0 */
672
{ "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
673
{ "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
674
{ "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
675
{ "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 },    /* rett X */
676
{ "rett",       F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),      "1", F_UNBR|F_DELAYED, v6 },    /* rett rs1+0 */
677
 
678
{ "save",       F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 },
679
{ "save",       F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "1,i,d", 0, v6 },
680
{ "save",       0x81e00000,     ~0x81e00000,                    "", F_ALIAS, v6 },
681
 
682
{ "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),            "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
683
{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
684
 
685
{ "jmpl",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 },
686
{ "jmpl",       F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),     "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
687
{ "jmpl",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0),    "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
688
{ "jmpl",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,       "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
689
{ "jmpl",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "1+i,d", F_JSR|F_DELAYED, v6 },
690
{ "jmpl",       F3(2, 0x38, 1), F3(~2, ~0x38, ~1),              "i+1,d", F_JSR|F_DELAYED, v6 },
691
 
692
{ "done",       F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0),    "", 0, v9 },
693
{ "retry",      F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0),  "", 0, v9 },
694
{ "saved",      F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0),    "", 0, v9 },
695
{ "restored",   F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0),  "", 0, v9 },
696
{ "allclean",   F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0),  "", 0, v9 },
697
{ "otherw",     F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0),  "", 0, v9 },
698
{ "normalw",    F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0),  "", 0, v9 },
699
{ "invalw",     F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0),  "", 0, v9 },
700
{ "sir",        F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,              "i", 0, v9 },
701
 
702
{ "flush",      F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
703
{ "flush",      F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),     "1", 0, v8 }, /* flush rs1+%g0 */
704
{ "flush",      F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),    "1", 0, v8 }, /* flush rs1+0 */
705
{ "flush",      F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", 0, v8 }, /* flush %g0+i */
706
{ "flush",      F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", 0, v8 },
707
{ "flush",      F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", 0, v8 },
708
 
709
/* IFLUSH was renamed to FLUSH in v8.  */
710
{ "iflush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 },
711
{ "iflush",     F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),     "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
712
{ "iflush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),    "1", F_ALIAS, v6 }, /* flush rs1+0 */
713
{ "iflush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,       "i", F_ALIAS, v6 },
714
{ "iflush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "1+i", F_ALIAS, v6 },
715
{ "iflush",     F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),              "i+1", F_ALIAS, v6 },
716
 
717
{ "return",     F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 },
718
{ "return",     F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0),     "1", 0, v9 }, /* return rs1+%g0 */
719
{ "return",     F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0),    "1", 0, v9 }, /* return rs1+0 */
720
{ "return",     F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0,       "i", 0, v9 }, /* return %g0+i */
721
{ "return",     F3(2, 0x39, 1), F3(~2, ~0x39, ~1),              "1+i", 0, v9 },
722
{ "return",     F3(2, 0x39, 1), F3(~2, ~0x39, ~1),              "i+1", 0, v9 },
723
 
724
{ "flushw",     F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),        "", 0, v9 },
725
 
726
{ "membar",     F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
727
{ "stbar",      F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
728
 
729
{ "prefetch",   F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0),                "[1+2],*", 0, v9 },
730
{ "prefetch",   F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
731
{ "prefetch",   F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),              "[1+i],*", 0, v9 },
732
{ "prefetch",   F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),              "[i+1],*", 0, v9 },
733
{ "prefetch",   F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0,       "[i],*", 0, v9 },
734
{ "prefetch",   F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0),    "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
735
{ "prefetcha",  F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0),                "[1+2]A,*", 0, v9 },
736
{ "prefetcha",  F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
737
{ "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),              "[1+i]o,*", 0, v9 },
738
{ "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),              "[i+1]o,*", 0, v9 },
739
{ "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0,       "[i]o,*", 0, v9 },
740
{ "prefetcha",  F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0),    "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
741
 
742
{ "sll",        F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5),      "1,2,d", 0, v6 },
743
{ "sll",        F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, v6 },
744
{ "sra",        F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5),      "1,2,d", 0, v6 },
745
{ "sra",        F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, v6 },
746
{ "srl",        F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5),      "1,2,d", 0, v6 },
747
{ "srl",        F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5),    "1,X,d", 0, v6 },
748
 
749
{ "sllx",       F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5),      "1,2,d", 0, v9 },
750
{ "sllx",       F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6),    "1,Y,d", 0, v9 },
751
{ "srax",       F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5),      "1,2,d", 0, v9 },
752
{ "srax",       F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6),    "1,Y,d", 0, v9 },
753
{ "srlx",       F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5),      "1,2,d", 0, v9 },
754
{ "srlx",       F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6),    "1,Y,d", 0, v9 },
755
 
756
{ "mulscc",     F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 },
757
{ "mulscc",     F3(2, 0x24, 1), F3(~2, ~0x24, ~1),              "1,i,d", 0, v6 },
758
 
759
{ "divscc",     F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite },
760
{ "divscc",     F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1),              "1,i,d", 0, sparclite },
761
 
762
{ "scan",       F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite },
763
{ "scan",       F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),              "1,i,d", 0, sparclet|sparclite },
764
 
765
{ "popc",       F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
766
{ "popc",       F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0,       "i,d", 0, v9 },
767
 
768
{ "clr",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),        "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
769
{ "clr",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),             "d", F_ALIAS, v6 }, /* or %g0,0,d       */
770
{ "clr",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),           "[1+2]", F_ALIAS, v6 },
771
{ "clr",        F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),               "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
772
{ "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[1+i]", F_ALIAS, v6 },
773
{ "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[i+1]", F_ALIAS, v6 },
774
{ "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,                 "[i]", F_ALIAS, v6 },
775
{ "clr",        F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),              "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
776
 
777
{ "clrb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),   "[1+2]", F_ALIAS, v6 },
778
{ "clrb",       F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),       "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
779
{ "clrb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
780
{ "clrb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
781
{ "clrb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v6 },
782
{ "clrb",       F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),      "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
783
 
784
{ "clrh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),   "[1+2]", F_ALIAS, v6 },
785
{ "clrh",       F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),       "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
786
{ "clrh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
787
{ "clrh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
788
{ "clrh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v6 },
789
{ "clrh",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),      "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
790
 
791
{ "clrx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),   "[1+2]", F_ALIAS, v9 },
792
{ "clrx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0),       "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
793
{ "clrx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[1+i]", F_ALIAS, v9 },
794
{ "clrx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[i+1]", F_ALIAS, v9 },
795
{ "clrx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v9 },
796
{ "clrx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0),      "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
797
 
798
{ "orcc",       F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 },
799
{ "orcc",       F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "1,i,d", 0, v6 },
800
{ "orcc",       F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "i,1,d", 0, v6 },
801
 
802
/* This is not a commutative instruction.  */
803
{ "orncc",      F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 },
804
{ "orncc",      F3(2, 0x16, 1), F3(~2, ~0x16, ~1),              "1,i,d", 0, v6 },
805
 
806
/* This is not a commutative instruction.  */
807
{ "orn",        F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 },
808
{ "orn",        F3(2, 0x06, 1), F3(~2, ~0x06, ~1),              "1,i,d", 0, v6 },
809
 
810
{ "tst",        F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),       "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
811
{ "tst",        F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0),    "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
812
{ "tst",        F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),      "1", 0, v6 }, /* orcc rs1, 0, %g0 */
813
 
814
{ "wr", F3(2, 0x30, 0),          F3(~2, ~0x30, ~0)|ASI(~0),                "1,2,m", 0, v8 }, /* wr r,r,%asrX */
815
{ "wr", F3(2, 0x30, 1),         F3(~2, ~0x30, ~1),                      "1,i,m", 0, v8 }, /* wr r,i,%asrX */
816
{ "wr", F3(2, 0x30, 0),          F3(~2, ~0x30, ~0)|ASI_RS2(~0),            "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
817
{ "wr", F3(2, 0x30, 0),          F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),  "1,2,y", 0, v6 }, /* wr r,r,%y */
818
{ "wr", F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", 0, v6 }, /* wr r,i,%y */
819
{ "wr", F3(2, 0x30, 0),          F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),      "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
820
{ "wr", F3(2, 0x31, 0),          F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),  "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
821
{ "wr", F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
822
{ "wr", F3(2, 0x31, 0),          F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),      "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
823
{ "wr", F3(2, 0x32, 0),          F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),  "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
824
{ "wr", F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
825
{ "wr", F3(2, 0x32, 0),          F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),      "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
826
{ "wr", F3(2, 0x33, 0),          F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),  "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
827
{ "wr", F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
828
{ "wr", F3(2, 0x33, 0),          F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),      "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
829
 
830
{ "wr", F3(2, 0x30, 0)|RD(2),    F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */
831
{ "wr", F3(2, 0x30, 1)|RD(2),   F3(~2, ~0x30, ~1)|RD(~2),               "1,i,E", 0, v9 }, /* wr r,i,%ccr */
832
{ "wr", F3(2, 0x30, 0)|RD(3),    F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */
833
{ "wr", F3(2, 0x30, 1)|RD(3),   F3(~2, ~0x30, ~1)|RD(~3),               "1,i,o", 0, v9 }, /* wr r,i,%asi */
834
{ "wr", F3(2, 0x30, 0)|RD(6),    F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */
835
{ "wr", F3(2, 0x30, 1)|RD(6),   F3(~2, ~0x30, ~1)|RD(~6),               "1,i,s", 0, v9 }, /* wr r,i,%fprs */
836
 
837
{ "wr", F3(2, 0x30, 0)|RD(16),   F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%pcr */
838
{ "wr", F3(2, 0x30, 1)|RD(16),  F3(~2, ~0x30, ~1)|RD(~16),              "1,i,_", 0, v9a }, /* wr r,i,%pcr */
839
{ "wr", F3(2, 0x30, 0)|RD(17),   F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%pic */
840
{ "wr", F3(2, 0x30, 1)|RD(17),  F3(~2, ~0x30, ~1)|RD(~17),              "1,i,_", 0, v9a }, /* wr r,i,%pic */
841
{ "wr", F3(2, 0x30, 0)|RD(18),   F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%dcr */
842
{ "wr", F3(2, 0x30, 1)|RD(18),  F3(~2, ~0x30, ~1)|RD(~18),              "1,i,_", 0, v9a }, /* wr r,i,%dcr */
843
{ "wr", F3(2, 0x30, 0)|RD(19),   F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%gsr */
844
{ "wr", F3(2, 0x30, 1)|RD(19),  F3(~2, ~0x30, ~1)|RD(~19),              "1,i,_", 0, v9a }, /* wr r,i,%gsr */
845
{ "wr", F3(2, 0x30, 0)|RD(20),   F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
846
{ "wr", F3(2, 0x30, 1)|RD(20),  F3(~2, ~0x30, ~1)|RD(~20),              "1,i,_", 0, v9a }, /* wr r,i,%set_softint */
847
{ "wr", F3(2, 0x30, 0)|RD(21),   F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
848
{ "wr", F3(2, 0x30, 1)|RD(21),  F3(~2, ~0x30, ~1)|RD(~21),              "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */
849
{ "wr", F3(2, 0x30, 0)|RD(22),   F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%softint */
850
{ "wr", F3(2, 0x30, 1)|RD(22),  F3(~2, ~0x30, ~1)|RD(~22),              "1,i,_", 0, v9a }, /* wr r,i,%softint */
851
{ "wr", F3(2, 0x30, 0)|RD(23),   F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0),        "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
852
{ "wr", F3(2, 0x30, 1)|RD(23),  F3(~2, ~0x30, ~1)|RD(~23),              "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
853
{ "wr", F3(2, 0x30, 0)|RD(24),   F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0),        "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
854
{ "wr", F3(2, 0x30, 1)|RD(24),  F3(~2, ~0x30, ~1)|RD(~24),              "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
855
{ "wr", F3(2, 0x30, 0)|RD(25),   F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0),        "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
856
{ "wr", F3(2, 0x30, 1)|RD(25),  F3(~2, ~0x30, ~1)|RD(~25),              "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
857
 
858
{ "rd", F3(2, 0x28, 0),                  F3(~2, ~0x28, ~0)|SIMM13(~0),             "M,d", 0, v8 }, /* rd %asrX,r */
859
{ "rd", F3(2, 0x28, 0),                  F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),      "y,d", 0, v6 }, /* rd %y,r */
860
{ "rd", F3(2, 0x29, 0),                  F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),      "p,d", 0, v6notv9 }, /* rd %psr,r */
861
{ "rd", F3(2, 0x2a, 0),                  F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),      "w,d", 0, v6notv9 }, /* rd %wim,r */
862
{ "rd", F3(2, 0x2b, 0),                  F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),      "t,d", 0, v6notv9 }, /* rd %tbr,r */
863
 
864
{ "rd", F3(2, 0x28, 0)|RS1(2),           F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0),     "E,d", 0, v9 }, /* rd %ccr,r */
865
{ "rd", F3(2, 0x28, 0)|RS1(3),           F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0),     "o,d", 0, v9 }, /* rd %asi,r */
866
{ "rd", F3(2, 0x28, 0)|RS1(4),           F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0),     "W,d", 0, v9 }, /* rd %tick,r */
867
{ "rd", F3(2, 0x28, 0)|RS1(5),           F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0),     "P,d", 0, v9 }, /* rd %pc,r */
868
{ "rd", F3(2, 0x28, 0)|RS1(6),           F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0),     "s,d", 0, v9 }, /* rd %fprs,r */
869
 
870
{ "rd", F3(2, 0x28, 0)|RS1(16),          F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0),    "/,d", 0, v9a }, /* rd %pcr,r */
871
{ "rd", F3(2, 0x28, 0)|RS1(17),          F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0),    "/,d", 0, v9a }, /* rd %pic,r */
872
{ "rd", F3(2, 0x28, 0)|RS1(18),          F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0),    "/,d", 0, v9a }, /* rd %dcr,r */
873
{ "rd", F3(2, 0x28, 0)|RS1(19),          F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),    "/,d", 0, v9a }, /* rd %gsr,r */
874
{ "rd", F3(2, 0x28, 0)|RS1(22),          F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),    "/,d", 0, v9a }, /* rd %softint,r */
875
{ "rd", F3(2, 0x28, 0)|RS1(23),          F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),    "/,d", 0, v9a }, /* rd %tick_cmpr,r */
876
{ "rd", F3(2, 0x28, 0)|RS1(24),          F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),    "/,d", 0, v9b }, /* rd %sys_tick,r */
877
{ "rd", F3(2, 0x28, 0)|RS1(25),          F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),    "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
878
 
879
{ "rdpr",       F3(2, 0x2a, 0),          F3(~2, ~0x2a, ~0)|SIMM13(~0),     "?,d", 0, v9 },   /* rdpr %priv,r */
880
{ "wrpr",       F3(2, 0x32, 0),          F3(~2, ~0x32, ~0),               "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
881
{ "wrpr",       F3(2, 0x32, 0),          F3(~2, ~0x32, ~0)|SIMM13(~0),     "1,!", 0, v9 },   /* wrpr r1,%priv */
882
{ "wrpr",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1),              "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
883
{ "wrpr",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1),              "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
884
{ "wrpr",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RS1(~0),       "i,!", 0, v9 },   /* wrpr i,%priv */
885
 
886
{ "rdhpr",      F3(2, 0x29, 0),          F3(~2, ~0x29, ~0)|SIMM13(~0),     "$,d", 0, v9 },   /* rdhpr %hpriv,r */
887
{ "wrhpr",      F3(2, 0x33, 0),          F3(~2, ~0x33, ~0),               "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */
888
{ "wrhpr",      F3(2, 0x33, 0),          F3(~2, ~0x33, ~0)|SIMM13(~0),     "1,%", 0, v9 },   /* wrhpr r1,%hpriv */
889
{ "wrhpr",      F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */
890
{ "wrhpr",      F3(2, 0x33, 1),         F3(~2, ~0x33, ~1),              "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */
891
{ "wrhpr",      F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RS1(~0),       "i,%", 0, v9 },   /* wrhpr i,%hpriv */
892
 
893
/* ??? This group seems wrong.  A three operand move?  */
894
{ "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0),         "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
895
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1),                      "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
896
{ "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),   "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
897
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
898
{ "mov",        F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),   "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
899
{ "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
900
{ "mov",        F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),   "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
901
{ "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
902
{ "mov",        F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),   "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
903
{ "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
904
 
905
{ "mov",        F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),              "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
906
{ "mov",        F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),       "y,d", F_ALIAS, v6 }, /* rd %y,r */
907
{ "mov",        F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),       "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
908
{ "mov",        F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),       "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
909
{ "mov",        F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),       "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
910
 
911
{ "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0),             "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
912
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1),                      "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
913
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0),            "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
914
{ "mov",        F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),       "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
915
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,                "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
916
{ "mov",        F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0),      "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
917
{ "mov",        F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),       "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
918
{ "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,                "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
919
{ "mov",        F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0),      "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
920
{ "mov",        F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),       "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
921
{ "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,                "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
922
{ "mov",        F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0),      "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
923
{ "mov",        F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),       "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
924
{ "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,                "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
925
{ "mov",        F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0),      "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
926
 
927
{ "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),  "2,d", 0, v6 }, /* or %g0,rs2,d */
928
{ "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,               "i,d", 0, v6 }, /* or %g0,i,d    */
929
{ "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),             "1,d", 0, v6 }, /* or rs1,%g0,d   */
930
{ "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),            "1,d", 0, v6 }, /* or rs1,0,d */
931
 
932
{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 },
933
{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "1,i,d", 0, v6 },
934
{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,1,d", 0, v6 },
935
 
936
{ "bset",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 },   /* or rd,rs2,rd */
937
{ "bset",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1),              "i,r", F_ALIAS, v6 },   /* or rd,i,rd */
938
 
939
/* This is not a commutative instruction.  */
940
{ "andn",       F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 },
941
{ "andn",       F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "1,i,d", 0, v6 },
942
 
943
/* This is not a commutative instruction.  */
944
{ "andncc",     F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 },
945
{ "andncc",     F3(2, 0x15, 1), F3(~2, ~0x15, ~1),              "1,i,d", 0, v6 },
946
 
947
{ "bclr",       F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 },   /* andn rd,rs2,rd */
948
{ "bclr",       F3(2, 0x05, 1), F3(~2, ~0x05, ~1),              "i,r", F_ALIAS, v6 },   /* andn rd,i,rd */
949
 
950
{ "cmp",        F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0),   "1,2", 0, v6 },  /* subcc rs1,rs2,%g0 */
951
{ "cmp",        F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0,                "1,i", 0, v6 },  /* subcc rs1,i,%g0 */
952
 
953
{ "sub",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 },
954
{ "sub",        F3(2, 0x04, 1), F3(~2, ~0x04, ~1),              "1,i,d", 0, v6 },
955
 
956
{ "subcc",      F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 },
957
{ "subcc",      F3(2, 0x14, 1), F3(~2, ~0x14, ~1),              "1,i,d", 0, v6 },
958
 
959
{ "subx",       F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
960
{ "subx",       F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", 0, v6notv9 },
961
{ "subc",       F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 },
962
{ "subc",       F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),              "1,i,d", 0, v9 },
963
 
964
{ "subxcc",     F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
965
{ "subxcc",     F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", 0, v6notv9 },
966
{ "subccc",     F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 },
967
{ "subccc",     F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),              "1,i,d", 0, v9 },
968
 
969
{ "and",        F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 },
970
{ "and",        F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "1,i,d", 0, v6 },
971
{ "and",        F3(2, 0x01, 1), F3(~2, ~0x01, ~1),              "i,1,d", 0, v6 },
972
 
973
{ "andcc",      F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 },
974
{ "andcc",      F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "1,i,d", 0, v6 },
975
{ "andcc",      F3(2, 0x11, 1), F3(~2, ~0x11, ~1),              "i,1,d", 0, v6 },
976
 
977
{ "dec",        F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* sub rd,1,rd */
978
{ "dec",        F3(2, 0x04, 1),             F3(~2, ~0x04, ~1),                 "i,r", F_ALIAS, v8 },    /* sub rd,imm,rd */
979
{ "deccc",      F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* subcc rd,1,rd */
980
{ "deccc",      F3(2, 0x14, 1),             F3(~2, ~0x14, ~1),                 "i,r", F_ALIAS, v8 },    /* subcc rd,imm,rd */
981
{ "inc",        F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* add rd,1,rd */
982
{ "inc",        F3(2, 0x00, 1),             F3(~2, ~0x00, ~1),                 "i,r", F_ALIAS, v8 },    /* add rd,imm,rd */
983
{ "inccc",      F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 },      /* addcc rd,1,rd */
984
{ "inccc",      F3(2, 0x10, 1),             F3(~2, ~0x10, ~1),                 "i,r", F_ALIAS, v8 },    /* addcc rd,imm,rd */
985
 
986
{ "btst",       F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 },     /* andcc rs1,rs2,%g0 */
987
{ "btst",       F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 },  /* andcc rs1,i,%g0 */
988
 
989
{ "neg",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
990
{ "neg",        F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */
991
 
992
{ "add",        F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 },
993
{ "add",        F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "1,i,d", 0, v6 },
994
{ "add",        F3(2, 0x00, 1), F3(~2, ~0x00, ~1),              "i,1,d", 0, v6 },
995
{ "addcc",      F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 },
996
{ "addcc",      F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "1,i,d", 0, v6 },
997
{ "addcc",      F3(2, 0x10, 1), F3(~2, ~0x10, ~1),              "i,1,d", 0, v6 },
998
 
999
{ "addx",       F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1000
{ "addx",       F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", 0, v6notv9 },
1001
{ "addx",       F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", 0, v6notv9 },
1002
{ "addc",       F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 },
1003
{ "addc",       F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "1,i,d", 0, v9 },
1004
{ "addc",       F3(2, 0x08, 1), F3(~2, ~0x08, ~1),              "i,1,d", 0, v9 },
1005
 
1006
{ "addxcc",     F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1007
{ "addxcc",     F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", 0, v6notv9 },
1008
{ "addxcc",     F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", 0, v6notv9 },
1009
{ "addccc",     F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 },
1010
{ "addccc",     F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "1,i,d", 0, v9 },
1011
{ "addccc",     F3(2, 0x18, 1), F3(~2, ~0x18, ~1),              "i,1,d", 0, v9 },
1012
 
1013
{ "smul",       F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1014
{ "smul",       F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "1,i,d", 0, v8 },
1015
{ "smul",       F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),              "i,1,d", 0, v8 },
1016
{ "smulcc",     F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1017
{ "smulcc",     F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "1,i,d", 0, v8 },
1018
{ "smulcc",     F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),              "i,1,d", 0, v8 },
1019
{ "umul",       F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1020
{ "umul",       F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "1,i,d", 0, v8 },
1021
{ "umul",       F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),              "i,1,d", 0, v8 },
1022
{ "umulcc",     F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1023
{ "umulcc",     F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "1,i,d", 0, v8 },
1024
{ "umulcc",     F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),              "i,1,d", 0, v8 },
1025
{ "sdiv",       F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1026
{ "sdiv",       F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "1,i,d", 0, v8 },
1027
{ "sdiv",       F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),              "i,1,d", 0, v8 },
1028
{ "sdivcc",     F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1029
{ "sdivcc",     F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "1,i,d", 0, v8 },
1030
{ "sdivcc",     F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),              "i,1,d", 0, v8 },
1031
{ "udiv",       F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1032
{ "udiv",       F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "1,i,d", 0, v8 },
1033
{ "udiv",       F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),              "i,1,d", 0, v8 },
1034
{ "udivcc",     F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1035
{ "udivcc",     F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "1,i,d", 0, v8 },
1036
{ "udivcc",     F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),              "i,1,d", 0, v8 },
1037
 
1038
{ "mulx",       F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 },
1039
{ "mulx",       F3(2, 0x09, 1), F3(~2, ~0x09, ~1),              "1,i,d", 0, v9 },
1040
{ "sdivx",      F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1041
{ "sdivx",      F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),              "1,i,d", 0, v9 },
1042
{ "udivx",      F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1043
{ "udivx",      F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1),              "1,i,d", 0, v9 },
1044
 
1045
{ "call",       F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
1046
{ "call",       F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
1047
 
1048
{ "call",       F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),        "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
1049
{ "call",       F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),        "1+2,#", F_JSR|F_DELAYED, v6 },
1050
{ "call",       F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0),    "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
1051
{ "call",       F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0),    "1,#", F_JSR|F_DELAYED, v6 },
1052
{ "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
1053
{ "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "1+i,#", F_JSR|F_DELAYED, v6 },
1054
{ "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
1055
{ "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),             "i+1,#", F_JSR|F_DELAYED, v6 },
1056
{ "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
1057
{ "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,      "i,#", F_JSR|F_DELAYED, v6 },
1058
{ "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),   "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
1059
{ "call",       F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),   "1,#", F_JSR|F_DELAYED, v6 },
1060
 
1061
 
1062
/* Conditional instructions.
1063
 
1064
   Because this part of the table was such a mess earlier, I have
1065
   macrofied it so that all the branches and traps are generated from
1066
   a single-line description of each condition value.  John Gilmore. */
1067
 
1068
/* Define branches -- one annulled, one without, etc. */
1069
#define br(opcode, mask, lose, flags) \
1070
 { opcode, (mask)|ANNUL, (lose),       ",a l",   (flags), v6 }, \
1071
 { opcode, (mask)      , (lose)|ANNUL, "l",     (flags), v6 }
1072
 
1073
#define brx(opcode, mask, lose, flags) /* v9 */ \
1074
 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G",      (flags), v9 }, \
1075
 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G",   (flags), v9 }, \
1076
 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G",   (flags), v9 }, \
1077
 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
1078
 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G",   (flags), v9 }, \
1079
 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
1080
 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G",      (flags), v9 }, \
1081
 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G",   (flags), v9 }, \
1082
 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G",   (flags), v9 }, \
1083
 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
1084
 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G",   (flags), v9 }, \
1085
 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
1086
 
1087
/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1088
#define tr(opcode, mask, lose, flags) \
1089
 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i",   (flags), v9 }, /* %g0 + imm */ \
1090
 { opcode, (mask)|(2<<11)|IMMED, (lose),        "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
1091
 { opcode, (mask)|(2<<11), IMMED|(lose),        "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
1092
 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1",   (flags), v9 }, /* rs1 + %g0 */ \
1093
 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i",   (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
1094
 { opcode, (mask)|IMMED, (lose),        "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
1095
 { opcode, (mask), IMMED|(lose),        "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
1096
 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1",   (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
1097
 { opcode, (mask)|IMMED, (lose)|RS1_G0,         "i",     (flags), v6 }, /* %g0 + imm */ \
1098
 { opcode, (mask)|IMMED, (lose),                "1+i",   (flags), v6 }, /* rs1 + imm */ \
1099
 { opcode, (mask), IMMED|(lose),                "1+2",   (flags), v6 }, /* rs1 + rs2 */ \
1100
 { opcode, (mask), IMMED|(lose)|RS2_G0,         "1",     (flags), v6 } /* rs1 + %g0 */
1101
 
1102
/* v9: We must put `brx' before `br', to ensure that we never match something
1103
   v9: against an expression unless it is an expression.  Otherwise, we end
1104
   v9: up with undefined symbol tables entries, because they get added, but
1105
   v9: are not deleted if the pattern fails to match.  */
1106
 
1107
/* Define both branches and traps based on condition mask */
1108
#define cond(bop, top, mask, flags) \
1109
  brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1110
  br(bop,  F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1111
  tr(top,  F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1112
 
1113
/* Define all the conditions, all the branches, all the traps.  */
1114
 
1115
/* Standard branch, trap mnemonics */
1116
cond ("b",      "ta",   CONDA, F_UNBR),
1117
/* Alternative form (just for assembly, not for disassembly) */
1118
cond ("ba",     "t",    CONDA, F_UNBR|F_ALIAS),
1119
 
1120
cond ("bcc",    "tcc",  CONDCC, F_CONDBR),
1121
cond ("bcs",    "tcs",  CONDCS, F_CONDBR),
1122
cond ("be",     "te",   CONDE, F_CONDBR),
1123
cond ("beq",    "teq",  CONDE, F_CONDBR|F_ALIAS),
1124
cond ("bg",     "tg",   CONDG, F_CONDBR),
1125
cond ("bgt",    "tgt",  CONDG, F_CONDBR|F_ALIAS),
1126
cond ("bge",    "tge",  CONDGE, F_CONDBR),
1127
cond ("bgeu",   "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
1128
cond ("bgu",    "tgu",  CONDGU, F_CONDBR),
1129
cond ("bl",     "tl",   CONDL, F_CONDBR),
1130
cond ("blt",    "tlt",  CONDL, F_CONDBR|F_ALIAS),
1131
cond ("ble",    "tle",  CONDLE, F_CONDBR),
1132
cond ("bleu",   "tleu", CONDLEU, F_CONDBR),
1133
cond ("blu",    "tlu",  CONDLU, F_CONDBR|F_ALIAS), /* for cs */
1134
cond ("bn",     "tn",   CONDN, F_CONDBR),
1135
cond ("bne",    "tne",  CONDNE, F_CONDBR),
1136
cond ("bneg",   "tneg", CONDNEG, F_CONDBR),
1137
cond ("bnz",    "tnz",  CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
1138
cond ("bpos",   "tpos", CONDPOS, F_CONDBR),
1139
cond ("bvc",    "tvc",  CONDVC, F_CONDBR),
1140
cond ("bvs",    "tvs",  CONDVS, F_CONDBR),
1141
cond ("bz",     "tz",   CONDZ, F_CONDBR|F_ALIAS), /* for e */
1142
 
1143
#undef cond
1144
#undef br
1145
#undef brr /* v9 */
1146
#undef tr
1147
 
1148
#define brr(opcode, mask, lose, flags) /* v9 */ \
1149
 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k",      F_DELAYED|(flags), v9 }, \
1150
 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k",   F_DELAYED|(flags), v9 }, \
1151
 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k",   F_DELAYED|(flags), v9 }, \
1152
 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
1153
 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k",   F_DELAYED|(flags), v9 }, \
1154
 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
1155
 
1156
#define condr(bop, mask, flags) /* v9 */ \
1157
  brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1158
 
1159
/* v9 */ condr("brnz", 0x5, F_CONDBR),
1160
/* v9 */ condr("brz", 0x1, F_CONDBR),
1161
/* v9 */ condr("brgez", 0x7, F_CONDBR),
1162
/* v9 */ condr("brlz", 0x3, F_CONDBR),
1163
/* v9 */ condr("brlez", 0x2, F_CONDBR),
1164
/* v9 */ condr("brgz", 0x6, F_CONDBR),
1165
 
1166
#undef condr /* v9 */
1167
#undef brr /* v9 */
1168
 
1169
#define movr(opcode, mask, flags) /* v9 */ \
1170
 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
1171
 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
1172
 
1173
#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1174
 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
1175
#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1176
 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
1177
#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1178
 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
1179
 
1180
#define fmovrs(mop, mask, flags) /* v9 */ \
1181
  fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1182
#define fmovrd(mop, mask, flags) /* v9 */ \
1183
  fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1184
#define fmovrq(mop, mask, flags) /* v9 */ \
1185
  fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1186
 
1187
/* v9 */ movr("movrne", 0x5, 0),
1188
/* v9 */ movr("movre", 0x1, 0),
1189
/* v9 */ movr("movrgez", 0x7, 0),
1190
/* v9 */ movr("movrlz", 0x3, 0),
1191
/* v9 */ movr("movrlez", 0x2, 0),
1192
/* v9 */ movr("movrgz", 0x6, 0),
1193
/* v9 */ movr("movrnz", 0x5, F_ALIAS),
1194
/* v9 */ movr("movrz", 0x1, F_ALIAS),
1195
 
1196
/* v9 */ fmovrs("fmovrsne", 0x5, 0),
1197
/* v9 */ fmovrs("fmovrse", 0x1, 0),
1198
/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1199
/* v9 */ fmovrs("fmovrslz", 0x3, 0),
1200
/* v9 */ fmovrs("fmovrslez", 0x2, 0),
1201
/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1202
/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
1203
/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
1204
 
1205
/* v9 */ fmovrd("fmovrdne", 0x5, 0),
1206
/* v9 */ fmovrd("fmovrde", 0x1, 0),
1207
/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1208
/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1209
/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1210
/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1211
/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
1212
/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
1213
 
1214
/* v9 */ fmovrq("fmovrqne", 0x5, 0),
1215
/* v9 */ fmovrq("fmovrqe", 0x1, 0),
1216
/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1217
/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1218
/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1219
/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1220
/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
1221
/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
1222
 
1223
#undef movr /* v9 */
1224
#undef fmovr /* v9 */
1225
#undef fmrr /* v9 */
1226
 
1227
#define movicc(opcode, cond, flags) /* v9 */ \
1228
  { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
1229
  { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
1230
  { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11),     "Z,2,d", flags, v9 }, \
1231
  { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11),     "Z,I,d", flags, v9 }
1232
 
1233
#define movfcc(opcode, fcond, flags) /* v9 */ \
1234
  { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
1235
  { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
1236
  { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
1237
  { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
1238
  { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
1239
  { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
1240
  { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
1241
  { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
1242
 
1243
#define movcc(opcode, cond, fcond, flags) /* v9 */ \
1244
  movfcc (opcode, fcond, flags), /* v9 */ \
1245
  movicc (opcode, cond, flags) /* v9 */
1246
 
1247
/* v9 */ movcc  ("mova",        CONDA, FCONDA, 0),
1248
/* v9 */ movicc ("movcc",       CONDCC, 0),
1249
/* v9 */ movicc ("movgeu",      CONDGEU, F_ALIAS),
1250
/* v9 */ movicc ("movcs",       CONDCS, 0),
1251
/* v9 */ movicc ("movlu",       CONDLU, F_ALIAS),
1252
/* v9 */ movcc  ("move",        CONDE, FCONDE, 0),
1253
/* v9 */ movcc  ("movg",        CONDG, FCONDG, 0),
1254
/* v9 */ movcc  ("movge",       CONDGE, FCONDGE, 0),
1255
/* v9 */ movicc ("movgu",       CONDGU, 0),
1256
/* v9 */ movcc  ("movl",        CONDL, FCONDL, 0),
1257
/* v9 */ movcc  ("movle",       CONDLE, FCONDLE, 0),
1258
/* v9 */ movicc ("movleu",      CONDLEU, 0),
1259
/* v9 */ movfcc ("movlg",       FCONDLG, 0),
1260
/* v9 */ movcc  ("movn",        CONDN, FCONDN, 0),
1261
/* v9 */ movcc  ("movne",       CONDNE, FCONDNE, 0),
1262
/* v9 */ movicc ("movneg",      CONDNEG, 0),
1263
/* v9 */ movcc  ("movnz",       CONDNZ, FCONDNZ, F_ALIAS),
1264
/* v9 */ movfcc ("movo",        FCONDO, 0),
1265
/* v9 */ movicc ("movpos",      CONDPOS, 0),
1266
/* v9 */ movfcc ("movu",        FCONDU, 0),
1267
/* v9 */ movfcc ("movue",       FCONDUE, 0),
1268
/* v9 */ movfcc ("movug",       FCONDUG, 0),
1269
/* v9 */ movfcc ("movuge",      FCONDUGE, 0),
1270
/* v9 */ movfcc ("movul",       FCONDUL, 0),
1271
/* v9 */ movfcc ("movule",      FCONDULE, 0),
1272
/* v9 */ movicc ("movvc",       CONDVC, 0),
1273
/* v9 */ movicc ("movvs",       CONDVS, 0),
1274
/* v9 */ movcc  ("movz",        CONDZ, FCONDZ, F_ALIAS),
1275
 
1276
#undef movicc /* v9 */
1277
#undef movfcc /* v9 */
1278
#undef movcc /* v9 */
1279
 
1280
#define FM_SF 1         /* v9 - values for fpsize */
1281
#define FM_DF 2         /* v9 */
1282
#define FM_QF 3         /* v9 */
1283
 
1284
#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
1285
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags, v9 }, \
1286
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags, v9 }
1287
 
1288
#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
1289
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \
1290
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \
1291
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \
1292
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 }
1293
 
1294
/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1295
#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
1296
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags | F_FLOAT, v9 }, \
1297
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \
1298
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags | F_FLOAT, v9 }, \
1299
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \
1300
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \
1301
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 }
1302
 
1303
#define fmovicc(suffix, cond, flags) /* v9 */ \
1304
fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags),            \
1305
fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags),            \
1306
fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
1307
 
1308
#define fmovfcc(suffix, fcond, flags) /* v9 */ \
1309
fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags),           \
1310
fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags),           \
1311
fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
1312
 
1313
#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
1314
fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags),      \
1315
fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags),      \
1316
fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
1317
 
1318
/* v9 */ fmovcc  ("a", CONDA, FCONDA, 0),
1319
/* v9 */ fmovicc ("cc", CONDCC, 0),
1320
/* v9 */ fmovicc ("cs", CONDCS, 0),
1321
/* v9 */ fmovcc  ("e", CONDE, FCONDE, 0),
1322
/* v9 */ fmovcc  ("g", CONDG, FCONDG, 0),
1323
/* v9 */ fmovcc  ("ge", CONDGE, FCONDGE, 0),
1324
/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
1325
/* v9 */ fmovicc ("gu", CONDGU, 0),
1326
/* v9 */ fmovcc  ("l", CONDL, FCONDL, 0),
1327
/* v9 */ fmovcc  ("le", CONDLE, FCONDLE, 0),
1328
/* v9 */ fmovicc ("leu", CONDLEU, 0),
1329
/* v9 */ fmovfcc ("lg", FCONDLG, 0),
1330
/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
1331
/* v9 */ fmovcc  ("n", CONDN, FCONDN, 0),
1332
/* v9 */ fmovcc  ("ne", CONDNE, FCONDNE, 0),
1333
/* v9 */ fmovicc ("neg", CONDNEG, 0),
1334
/* v9 */ fmovcc  ("nz", CONDNZ, FCONDNZ, F_ALIAS),
1335
/* v9 */ fmovfcc ("o", FCONDO, 0),
1336
/* v9 */ fmovicc ("pos", CONDPOS, 0),
1337
/* v9 */ fmovfcc ("u", FCONDU, 0),
1338
/* v9 */ fmovfcc ("ue", FCONDUE, 0),
1339
/* v9 */ fmovfcc ("ug", FCONDUG, 0),
1340
/* v9 */ fmovfcc ("uge", FCONDUGE, 0),
1341
/* v9 */ fmovfcc ("ul", FCONDUL, 0),
1342
/* v9 */ fmovfcc ("ule", FCONDULE, 0),
1343
/* v9 */ fmovicc ("vc", CONDVC, 0),
1344
/* v9 */ fmovicc ("vs", CONDVS, 0),
1345
/* v9 */ fmovcc  ("z", CONDZ, FCONDZ, F_ALIAS),
1346
 
1347
#undef fmoviccx /* v9 */
1348
#undef fmovfccx /* v9 */
1349
#undef fmovccx /* v9 */
1350
#undef fmovicc /* v9 */
1351
#undef fmovfcc /* v9 */
1352
#undef fmovcc /* v9 */
1353
#undef FM_DF /* v9 */
1354
#undef FM_QF /* v9 */
1355
#undef FM_SF /* v9 */
1356
 
1357
/* Coprocessor branches.  */
1358
#define CBR(opcode, mask, lose, flags, arch) \
1359
 { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED, arch }, \
1360
 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
1361
 
1362
/* Floating point branches.  */
1363
#define FBR(opcode, mask, lose, flags) \
1364
 { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED | F_FBR, v6 }, \
1365
 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
1366
 
1367
/* V9 extended floating point branches.  */
1368
#define FBRX(opcode, mask, lose, flags) /* v9 */ \
1369
 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G",      flags|F_DELAYED|F_FBR, v9 }, \
1370
 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
1371
 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
1372
 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1373
 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G",   flags|F_DELAYED|F_FBR, v9 }, \
1374
 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1375
 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G",      flags|F_DELAYED|F_FBR, v9 }, \
1376
 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
1377
 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
1378
 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1379
 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G",   flags|F_DELAYED|F_FBR, v9 }, \
1380
 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1381
 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G",      flags|F_DELAYED|F_FBR, v9 }, \
1382
 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
1383
 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
1384
 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1385
 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G",   flags|F_DELAYED|F_FBR, v9 }, \
1386
 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1387
 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G",      flags|F_DELAYED|F_FBR, v9 }, \
1388
 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
1389
 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
1390
 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1391
 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G",   flags|F_DELAYED|F_FBR, v9 }, \
1392
 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
1393
 
1394
/* v9: We must put `FBRX' before `FBR', to ensure that we never match
1395
   v9: something against an expression unless it is an expression.  Otherwise,
1396
   v9: we end up with undefined symbol tables entries, because they get added,
1397
   v9: but are not deleted if the pattern fails to match.  */
1398
 
1399
#define CONDFC(fop, cop, mask, flags) \
1400
  FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1401
  FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1402
  CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1403
 
1404
#define CONDFCL(fop, cop, mask, flags) \
1405
  FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1406
  FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1407
  CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1408
 
1409
#define CONDF(fop, mask, flags) \
1410
  FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1411
  FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1412
 
1413
CONDFC  ("fb",    "cb",    0x8, F_UNBR),
1414
CONDFCL ("fba",   "cba",   0x8, F_UNBR|F_ALIAS),
1415
CONDFC  ("fbe",   "cb0",   0x9, F_CONDBR),
1416
CONDF   ("fbz",            0x9, F_CONDBR|F_ALIAS),
1417
CONDFC  ("fbg",   "cb2",   0x6, F_CONDBR),
1418
CONDFC  ("fbge",  "cb02",  0xb, F_CONDBR),
1419
CONDFC  ("fbl",   "cb1",   0x4, F_CONDBR),
1420
CONDFC  ("fble",  "cb01",  0xd, F_CONDBR),
1421
CONDFC  ("fblg",  "cb12",  0x2, F_CONDBR),
1422
CONDFCL ("fbn",   "cbn",   0x0, F_UNBR),
1423
CONDFC  ("fbne",  "cb123", 0x1, F_CONDBR),
1424
CONDF   ("fbnz",           0x1, F_CONDBR|F_ALIAS),
1425
CONDFC  ("fbo",   "cb012", 0xf, F_CONDBR),
1426
CONDFC  ("fbu",   "cb3",   0x7, F_CONDBR),
1427
CONDFC  ("fbue",  "cb03",  0xa, F_CONDBR),
1428
CONDFC  ("fbug",  "cb23",  0x5, F_CONDBR),
1429
CONDFC  ("fbuge", "cb023", 0xc, F_CONDBR),
1430
CONDFC  ("fbul",  "cb13",  0x3, F_CONDBR),
1431
CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
1432
 
1433
#undef CONDFC
1434
#undef CONDFCL
1435
#undef CONDF
1436
#undef CBR
1437
#undef FBR
1438
#undef FBRX     /* v9 */
1439
 
1440
{ "jmp",        F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0),   "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
1441
{ "jmp",        F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0),       "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
1442
{ "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
1443
{ "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
1444
{ "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
1445
{ "jmp",        F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0),      "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
1446
 
1447
{ "nop",        F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
1448
 
1449
{ "set",        F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 },
1450
{ "setuw",      F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1451
{ "setsw",      F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1452
{ "setx",       F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
1453
 
1454
{ "sethi",      F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
1455
 
1456
{ "taddcc",     F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 },
1457
{ "taddcc",     F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "1,i,d", 0, v6 },
1458
{ "taddcc",     F3(2, 0x20, 1), F3(~2, ~0x20, ~1),              "i,1,d", 0, v6 },
1459
{ "taddcctv",   F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 },
1460
{ "taddcctv",   F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "1,i,d", 0, v6 },
1461
{ "taddcctv",   F3(2, 0x22, 1), F3(~2, ~0x22, ~1),              "i,1,d", 0, v6 },
1462
 
1463
{ "tsubcc",     F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 },
1464
{ "tsubcc",     F3(2, 0x21, 1), F3(~2, ~0x21, ~1),              "1,i,d", 0, v6 },
1465
{ "tsubcctv",   F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 },
1466
{ "tsubcctv",   F3(2, 0x23, 1), F3(~2, ~0x23, ~1),              "1,i,d", 0, v6 },
1467
 
1468
{ "unimp",      F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
1469
{ "illtrap",    F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
1470
 
1471
/* This *is* a commutative instruction.  */
1472
{ "xnor",       F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 },
1473
{ "xnor",       F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "1,i,d", 0, v6 },
1474
{ "xnor",       F3(2, 0x07, 1), F3(~2, ~0x07, ~1),              "i,1,d", 0, v6 },
1475
/* This *is* a commutative instruction.  */
1476
{ "xnorcc",     F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 },
1477
{ "xnorcc",     F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "1,i,d", 0, v6 },
1478
{ "xnorcc",     F3(2, 0x17, 1), F3(~2, ~0x17, ~1),              "i,1,d", 0, v6 },
1479
{ "xor",        F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 },
1480
{ "xor",        F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "1,i,d", 0, v6 },
1481
{ "xor",        F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,1,d", 0, v6 },
1482
{ "xorcc",      F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 },
1483
{ "xorcc",      F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "1,i,d", 0, v6 },
1484
{ "xorcc",      F3(2, 0x13, 1), F3(~2, ~0x13, ~1),              "i,1,d", 0, v6 },
1485
 
1486
{ "not",        F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
1487
{ "not",        F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
1488
 
1489
{ "btog",       F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
1490
{ "btog",       F3(2, 0x03, 1), F3(~2, ~0x03, ~1),              "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
1491
 
1492
/* FPop1 and FPop2 are not instructions.  Don't accept them.  */
1493
 
1494
{ "fdtoi",      F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 },
1495
{ "fstoi",      F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
1496
{ "fqtoi",      F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
1497
 
1498
{ "fdtox",      F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 },
1499
{ "fstox",      F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 },
1500
{ "fqtox",      F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
1501
 
1502
{ "fitod",      F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
1503
{ "fitos",      F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
1504
{ "fitoq",      F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
1505
 
1506
{ "fxtod",      F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 },
1507
{ "fxtos",      F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 },
1508
{ "fxtoq",      F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 },
1509
 
1510
{ "fdtoq",      F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
1511
{ "fdtos",      F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
1512
{ "fqtod",      F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
1513
{ "fqtos",      F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
1514
{ "fstod",      F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 },
1515
{ "fstoq",      F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 },
1516
 
1517
{ "fdivd",      F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 },
1518
{ "fdivq",      F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
1519
{ "fdivx",      F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1520
{ "fdivs",      F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 },
1521
{ "fmuld",      F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 },
1522
{ "fmulq",      F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
1523
{ "fmulx",      F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1524
{ "fmuls",      F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 },
1525
 
1526
{ "fdmulq",     F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 },
1527
{ "fdmulx",     F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 },
1528
{ "fsmuld",     F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 },
1529
 
1530
{ "fsqrtd",     F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
1531
{ "fsqrtq",     F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
1532
{ "fsqrtx",     F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
1533
{ "fsqrts",     F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
1534
 
1535
{ "fabsd",      F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 },
1536
{ "fabsq",      F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
1537
{ "fabsx",      F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1538
{ "fabss",      F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 },
1539
{ "fmovd",      F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 },
1540
{ "fmovq",      F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
1541
{ "fmovx",      F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1542
{ "fmovs",      F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 },
1543
{ "fnegd",      F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 },
1544
{ "fnegq",      F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
1545
{ "fnegx",      F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1546
{ "fnegs",      F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 },
1547
 
1548
{ "faddd",      F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 },
1549
{ "faddq",      F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
1550
{ "faddx",      F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1551
{ "fadds",      F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 },
1552
{ "fsubd",      F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 },
1553
{ "fsubq",      F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
1554
{ "fsubx",      F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1555
{ "fsubs",      F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 },
1556
 
1557
#define CMPFCC(x)       (((x)&0x3)<<25)
1558
 
1559
{ "fcmpd",                F3F(2, 0x35, 0x052),            F3F(~2, ~0x35, ~0x052)|RD_G0,  "v,B",   F_FLOAT, v6 },
1560
{ "fcmpd",      CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052),  "6,v,B", F_FLOAT, v9 },
1561
{ "fcmpd",      CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052),        "7,v,B", F_FLOAT, v9 },
1562
{ "fcmpd",      CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052),        "8,v,B", F_FLOAT, v9 },
1563
{ "fcmpd",      CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052),        "9,v,B", F_FLOAT, v9 },
1564
{ "fcmped",               F3F(2, 0x35, 0x056),            F3F(~2, ~0x35, ~0x056)|RD_G0,  "v,B",   F_FLOAT, v6 },
1565
{ "fcmped",     CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056),  "6,v,B", F_FLOAT, v9 },
1566
{ "fcmped",     CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056),        "7,v,B", F_FLOAT, v9 },
1567
{ "fcmped",     CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056),        "8,v,B", F_FLOAT, v9 },
1568
{ "fcmped",     CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056),        "9,v,B", F_FLOAT, v9 },
1569
{ "fcmpq",                F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,  "V,R", F_FLOAT, v8 },
1570
{ "fcmpq",      CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),  "6,V,R", F_FLOAT, v9 },
1571
{ "fcmpq",      CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),        "7,V,R", F_FLOAT, v9 },
1572
{ "fcmpq",      CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),        "8,V,R", F_FLOAT, v9 },
1573
{ "fcmpq",      CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),        "9,V,R", F_FLOAT, v9 },
1574
{ "fcmpeq",               F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,  "V,R", F_FLOAT, v8 },
1575
{ "fcmpeq",     CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),  "6,V,R", F_FLOAT, v9 },
1576
{ "fcmpeq",     CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),        "7,V,R", F_FLOAT, v9 },
1577
{ "fcmpeq",     CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),        "8,V,R", F_FLOAT, v9 },
1578
{ "fcmpeq",     CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),        "9,V,R", F_FLOAT, v9 },
1579
{ "fcmpx",                F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,  "V,R", F_FLOAT|F_ALIAS, v8 },
1580
{ "fcmpx",      CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),  "6,V,R", F_FLOAT|F_ALIAS, v9 },
1581
{ "fcmpx",      CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),        "7,V,R", F_FLOAT|F_ALIAS, v9 },
1582
{ "fcmpx",      CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),        "8,V,R", F_FLOAT|F_ALIAS, v9 },
1583
{ "fcmpx",      CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),        "9,V,R", F_FLOAT|F_ALIAS, v9 },
1584
{ "fcmpex",               F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,  "V,R", F_FLOAT|F_ALIAS, v8 },
1585
{ "fcmpex",     CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),  "6,V,R", F_FLOAT|F_ALIAS, v9 },
1586
{ "fcmpex",     CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),        "7,V,R", F_FLOAT|F_ALIAS, v9 },
1587
{ "fcmpex",     CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),        "8,V,R", F_FLOAT|F_ALIAS, v9 },
1588
{ "fcmpex",     CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),        "9,V,R", F_FLOAT|F_ALIAS, v9 },
1589
{ "fcmps",                F3F(2, 0x35, 0x051),            F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f",   F_FLOAT, v6 },
1590
{ "fcmps",      CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051),  "6,e,f", F_FLOAT, v9 },
1591
{ "fcmps",      CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051),        "7,e,f", F_FLOAT, v9 },
1592
{ "fcmps",      CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051),        "8,e,f", F_FLOAT, v9 },
1593
{ "fcmps",      CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051),        "9,e,f", F_FLOAT, v9 },
1594
{ "fcmpes",               F3F(2, 0x35, 0x055),            F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f",   F_FLOAT, v6 },
1595
{ "fcmpes",     CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055),  "6,e,f", F_FLOAT, v9 },
1596
{ "fcmpes",     CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055),        "7,e,f", F_FLOAT, v9 },
1597
{ "fcmpes",     CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055),        "8,e,f", F_FLOAT, v9 },
1598
{ "fcmpes",     CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055),        "9,e,f", F_FLOAT, v9 },
1599
 
1600
/* These Extended FPop (FIFO) instructions are new in the Fujitsu
1601
   MB86934, replacing the CPop instructions from v6 and later
1602
   processors.  */
1603
 
1604
#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
1605
#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op),        args, 0, sparclite }
1606
#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0,  args, 0, sparclite }
1607
 
1608
EFPOP1_2 ("efitod",     0x0c8, "f,H"),
1609
EFPOP1_2 ("efitos",     0x0c4, "f,g"),
1610
EFPOP1_2 ("efdtoi",     0x0d2, "B,g"),
1611
EFPOP1_2 ("efstoi",     0x0d1, "f,g"),
1612
EFPOP1_2 ("efstod",     0x0c9, "f,H"),
1613
EFPOP1_2 ("efdtos",     0x0c6, "B,g"),
1614
EFPOP1_2 ("efmovs",     0x001, "f,g"),
1615
EFPOP1_2 ("efnegs",     0x005, "f,g"),
1616
EFPOP1_2 ("efabss",     0x009, "f,g"),
1617
EFPOP1_2 ("efsqrtd",    0x02a, "B,H"),
1618
EFPOP1_2 ("efsqrts",    0x029, "f,g"),
1619
EFPOP1_3 ("efaddd",     0x042, "v,B,H"),
1620
EFPOP1_3 ("efadds",     0x041, "e,f,g"),
1621
EFPOP1_3 ("efsubd",     0x046, "v,B,H"),
1622
EFPOP1_3 ("efsubs",     0x045, "e,f,g"),
1623
EFPOP1_3 ("efdivd",     0x04e, "v,B,H"),
1624
EFPOP1_3 ("efdivs",     0x04d, "e,f,g"),
1625
EFPOP1_3 ("efmuld",     0x04a, "v,B,H"),
1626
EFPOP1_3 ("efmuls",     0x049, "e,f,g"),
1627
EFPOP1_3 ("efsmuld",    0x069, "e,f,H"),
1628
EFPOP2_2 ("efcmpd",     0x052, "v,B"),
1629
EFPOP2_2 ("efcmped",    0x056, "v,B"),
1630
EFPOP2_2 ("efcmps",     0x051, "e,f"),
1631
EFPOP2_2 ("efcmpes",    0x055, "e,f"),
1632
 
1633
#undef EFPOP1_2
1634
#undef EFPOP1_3
1635
#undef EFPOP2_2
1636
 
1637
/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1638
   present.  Otherwise, the F_ALIAS flag is ignored.  */
1639
{ "cpop1",      F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 },
1640
{ "cpop2",      F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
1641
 
1642
/* sparclet specific insns */
1643
 
1644
COMMUTEOP ("umac", 0x3e, sparclet),
1645
COMMUTEOP ("smac", 0x3f, sparclet),
1646
COMMUTEOP ("umacd", 0x2e, sparclet),
1647
COMMUTEOP ("smacd", 0x2f, sparclet),
1648
COMMUTEOP ("umuld", 0x09, sparclet),
1649
COMMUTEOP ("smuld", 0x0d, sparclet),
1650
 
1651
{ "shuffle",    F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet },
1652
{ "shuffle",    F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),              "1,i,d", 0, sparclet },
1653
 
1654
/* The manual isn't completely accurate on these insns.  The `rs2' field is
1655
   treated as being 6 bits to account for 6 bit immediates to cpush.  It is
1656
   assumed that it is intended that bit 5 is 0 when rs2 contains a reg.  */
1657
#define BIT5 (1<<5)
1658
{ "crdcxt",     F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0),       "U,d", 0, sparclet },
1659
{ "cwrcxt",     F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0),       "1,u", 0, sparclet },
1660
{ "cpush",      F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0),  "1,2", 0, sparclet },
1661
{ "cpush",      F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0),             "1,Y", 0, sparclet },
1662
{ "cpusha",     F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0),        "1,2", 0, sparclet },
1663
{ "cpusha",     F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0),           "1,Y", 0, sparclet },
1664
{ "cpull",      F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
1665
#undef BIT5
1666
 
1667
/* sparclet coprocessor branch insns */
1668
#define SLCBCC2(opcode, mask, lose) \
1669
 { opcode, (mask), ANNUL|(lose), "l",    F_DELAYED|F_CONDBR, sparclet }, \
1670
 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
1671
#define SLCBCC(opcode, mask) \
1672
  SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1673
 
1674
/* cbn,cba can't be defined here because they're defined elsewhere and GAS
1675
   requires all mnemonics of the same name to be consecutive.  */
1676
/*SLCBCC("cbn", 0), - already defined */
1677
SLCBCC("cbe", 1),
1678
SLCBCC("cbf", 2),
1679
SLCBCC("cbef", 3),
1680
SLCBCC("cbr", 4),
1681
SLCBCC("cber", 5),
1682
SLCBCC("cbfr", 6),
1683
SLCBCC("cbefr", 7),
1684
/*SLCBCC("cba", 8), - already defined */
1685
SLCBCC("cbne", 9),
1686
SLCBCC("cbnf", 10),
1687
SLCBCC("cbnef", 11),
1688
SLCBCC("cbnr", 12),
1689
SLCBCC("cbner", 13),
1690
SLCBCC("cbnfr", 14),
1691
SLCBCC("cbnefr", 15),
1692
 
1693
#undef SLCBCC2
1694
#undef SLCBCC
1695
 
1696
{ "casa",       F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
1697
{ "casa",       F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
1698
{ "casxa",      F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
1699
{ "casxa",      F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
1700
 
1701
/* v9 synthetic insns */
1702
{ "iprefetch",  F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
1703
{ "signx",      F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
1704
{ "signx",      F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
1705
{ "clruw",      F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
1706
{ "clruw",      F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
1707
{ "cas",        F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
1708
{ "casl",       F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
1709
{ "casx",       F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
1710
{ "casxl",      F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
1711
 
1712
/* Ultrasparc extensions */
1713
{ "shutdown",   F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
1714
 
1715
/* FIXME: Do we want to mark these as F_FLOAT, or something similar?  */
1716
{ "fpadd16",    F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a },
1717
{ "fpadd16s",   F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a },
1718
{ "fpadd32",    F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a },
1719
{ "fpadd32s",   F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a },
1720
{ "fpsub16",    F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a },
1721
{ "fpsub16s",   F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a },
1722
{ "fpsub32",    F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a },
1723
{ "fpsub32s",   F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a },
1724
 
1725
{ "fpack32",    F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a },
1726
{ "fpack16",    F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a },
1727
{ "fpackfix",   F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a },
1728
{ "fexpand",    F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a },
1729
{ "fpmerge",    F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a },
1730
 
1731
/* Note that the mixing of 32/64 bit regs is intentional.  */
1732
{ "fmul8x16",           F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a },
1733
{ "fmul8x16au",         F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a },
1734
{ "fmul8x16al",         F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a },
1735
{ "fmul8sux16",         F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a },
1736
{ "fmul8ulx16",         F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a },
1737
{ "fmuld8sux16",        F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a },
1738
{ "fmuld8ulx16",        F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a },
1739
 
1740
{ "alignaddr",  F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a },
1741
{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a },
1742
{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a },
1743
 
1744
{ "fzero",      F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a },
1745
{ "fzeros",     F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a },
1746
{ "fone",       F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a },
1747
{ "fones",      F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a },
1748
{ "fsrc1",      F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a },
1749
{ "fsrc1s",     F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a },
1750
{ "fsrc2",      F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a },
1751
{ "fsrc2s",     F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a },
1752
{ "fnot1",      F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a },
1753
{ "fnot1s",     F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a },
1754
{ "fnot2",      F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a },
1755
{ "fnot2s",     F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a },
1756
{ "for",        F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a },
1757
{ "fors",       F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a },
1758
{ "fnor",       F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a },
1759
{ "fnors",      F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a },
1760
{ "fand",       F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a },
1761
{ "fands",      F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a },
1762
{ "fnand",      F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a },
1763
{ "fnands",     F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a },
1764
{ "fxor",       F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a },
1765
{ "fxors",      F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a },
1766
{ "fxnor",      F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a },
1767
{ "fxnors",     F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a },
1768
{ "fornot1",    F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a },
1769
{ "fornot1s",   F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a },
1770
{ "fornot2",    F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a },
1771
{ "fornot2s",   F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a },
1772
{ "fandnot1",   F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a },
1773
{ "fandnot1s",  F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a },
1774
{ "fandnot2",   F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a },
1775
{ "fandnot2s",  F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a },
1776
 
1777
{ "fcmpgt16",   F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a },
1778
{ "fcmpgt32",   F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a },
1779
{ "fcmple16",   F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a },
1780
{ "fcmple32",   F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a },
1781
{ "fcmpne16",   F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a },
1782
{ "fcmpne32",   F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a },
1783
{ "fcmpeq16",   F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a },
1784
{ "fcmpeq32",   F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a },
1785
 
1786
{ "edge8",      F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a },
1787
{ "edge8l",     F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a },
1788
{ "edge16",     F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a },
1789
{ "edge16l",    F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a },
1790
{ "edge32",     F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a },
1791
{ "edge32l",    F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a },
1792
 
1793
{ "pdist",      F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a },
1794
 
1795
{ "array8",     F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a },
1796
{ "array16",    F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
1797
{ "array32",    F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
1798
 
1799
/* Cheetah instructions */
1800
{ "edge8n",    F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
1801
{ "edge8ln",   F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
1802
{ "edge16n",   F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
1803
{ "edge16ln",  F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
1804
{ "edge32n",   F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
1805
{ "edge32ln",  F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
1806
 
1807
{ "bmask",     F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
1808
{ "bshuffle",  F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
1809
 
1810
{ "siam",      F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
1811
 
1812
/* More v9 specific insns, these need to come last so they do not clash
1813
   with v9a instructions such as "edge8" which looks like impdep1. */
1814
 
1815
#define IMPDEP(name, code) \
1816
{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
1817
{ name, F3(2, code, 1), F3(~2, ~code, ~1),         "1,i,d", 0, v9notv9a }, \
1818
{ name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,1,2,d", 0, v9notv9a }, \
1819
{ name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,e,f,g", 0, v9notv9a }
1820
 
1821
IMPDEP ("impdep1", 0x36),
1822
IMPDEP ("impdep2", 0x37),
1823
 
1824
#undef IMPDEP
1825
 
1826
};
1827
 
1828
const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
1829
 
1830
/* Utilities for argument parsing.  */
1831
 
1832
typedef struct
1833
{
1834
  int value;
1835
  const char *name;
1836
} arg;
1837
 
1838
/* Look up NAME in TABLE.  */
1839
 
1840
static int
1841
lookup_name (const arg *table, const char *name)
1842
{
1843
  const arg *p;
1844
 
1845
  for (p = table; p->name; ++p)
1846
    if (strcmp (name, p->name) == 0)
1847
      return p->value;
1848
 
1849
  return -1;
1850
}
1851
 
1852
/* Look up VALUE in TABLE.  */
1853
 
1854
static const char *
1855
lookup_value (const arg *table, int value)
1856
{
1857
  const arg *p;
1858
 
1859
  for (p = table; p->name; ++p)
1860
    if (value == p->value)
1861
      return p->name;
1862
 
1863
  return NULL;
1864
}
1865
 
1866
/* Handle ASI's.  */
1867
 
1868
static arg asi_table[] =
1869
{
1870
  /* These are in the v9 architecture manual.  */
1871
  /* The shorter versions appear first, they're here because Sun's as has them.
1872
     Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
1873
     UltraSPARC architecture manual).  */
1874
  { 0x04, "#ASI_N" },
1875
  { 0x0c, "#ASI_N_L" },
1876
  { 0x10, "#ASI_AIUP" },
1877
  { 0x11, "#ASI_AIUS" },
1878
  { 0x18, "#ASI_AIUP_L" },
1879
  { 0x19, "#ASI_AIUS_L" },
1880
  { 0x80, "#ASI_P" },
1881
  { 0x81, "#ASI_S" },
1882
  { 0x82, "#ASI_PNF" },
1883
  { 0x83, "#ASI_SNF" },
1884
  { 0x88, "#ASI_P_L" },
1885
  { 0x89, "#ASI_S_L" },
1886
  { 0x8a, "#ASI_PNF_L" },
1887
  { 0x8b, "#ASI_SNF_L" },
1888
  { 0x04, "#ASI_NUCLEUS" },
1889
  { 0x0c, "#ASI_NUCLEUS_LITTLE" },
1890
  { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
1891
  { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
1892
  { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
1893
  { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
1894
  { 0x80, "#ASI_PRIMARY" },
1895
  { 0x81, "#ASI_SECONDARY" },
1896
  { 0x82, "#ASI_PRIMARY_NOFAULT" },
1897
  { 0x83, "#ASI_SECONDARY_NOFAULT" },
1898
  { 0x88, "#ASI_PRIMARY_LITTLE" },
1899
  { 0x89, "#ASI_SECONDARY_LITTLE" },
1900
  { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
1901
  { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
1902
  /* These are UltraSPARC and Niagara extensions.  */
1903
  { 0x14, "#ASI_PHYS_USE_EC" },
1904
  { 0x15, "#ASI_PHYS_BYPASS_EC_E" },
1905
  { 0x16, "#ASI_BLK_AIUP_4V" },
1906
  { 0x17, "#ASI_BLK_AIUS_4V" },
1907
  { 0x1c, "#ASI_PHYS_USE_EC_L" },
1908
  { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" },
1909
  { 0x1e, "#ASI_BLK_AIUP_L_4V" },
1910
  { 0x1f, "#ASI_BLK_AIUS_L_4V" },
1911
  { 0x20, "#ASI_SCRATCHPAD" },
1912
  { 0x21, "#ASI_MMU" },
1913
  { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" },
1914
  { 0x24, "#ASI_NUCLEUS_QUAD_LDD" },
1915
  { 0x25, "#ASI_QUEUE" },
1916
  { 0x26, "#ASI_QUAD_LDD_PHYS_4V" },
1917
  { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" },
1918
  { 0x30, "#ASI_PCACHE_DATA_STATUS" },
1919
  { 0x31, "#ASI_PCACHE_DATA" },
1920
  { 0x32, "#ASI_PCACHE_TAG" },
1921
  { 0x33, "#ASI_PCACHE_SNOOP_TAG" },
1922
  { 0x34, "#ASI_QUAD_LDD_PHYS" },
1923
  { 0x38, "#ASI_WCACHE_VALID_BITS" },
1924
  { 0x39, "#ASI_WCACHE_DATA" },
1925
  { 0x3a, "#ASI_WCACHE_TAG" },
1926
  { 0x3b, "#ASI_WCACHE_SNOOP_TAG" },
1927
  { 0x3c, "#ASI_QUAD_LDD_PHYS_L" },
1928
  { 0x40, "#ASI_SRAM_FAST_INIT" },
1929
  { 0x41, "#ASI_CORE_AVAILABLE" },
1930
  { 0x41, "#ASI_CORE_ENABLE_STAT" },
1931
  { 0x41, "#ASI_CORE_ENABLE" },
1932
  { 0x41, "#ASI_XIR_STEERING" },
1933
  { 0x41, "#ASI_CORE_RUNNING_RW" },
1934
  { 0x41, "#ASI_CORE_RUNNING_W1S" },
1935
  { 0x41, "#ASI_CORE_RUNNING_W1C" },
1936
  { 0x41, "#ASI_CORE_RUNNING_STAT" },
1937
  { 0x41, "#ASI_CMT_ERROR_STEERING" },
1938
  { 0x41, "#ASI_DCACHE_INVALIDATE" },
1939
  { 0x41, "#ASI_DCACHE_UTAG" },
1940
  { 0x41, "#ASI_DCACHE_SNOOP_TAG" },
1941
  { 0x42, "#ASI_DCACHE_INVALIDATE" },
1942
  { 0x43, "#ASI_DCACHE_UTAG" },
1943
  { 0x44, "#ASI_DCACHE_SNOOP_TAG" },
1944
  { 0x45, "#ASI_LSU_CONTROL_REG" },
1945
  { 0x45, "#ASI_DCU_CONTROL_REG" },
1946
  { 0x46, "#ASI_DCACHE_DATA" },
1947
  { 0x47, "#ASI_DCACHE_TAG" },
1948
  { 0x48, "#ASI_INTR_DISPATCH_STAT" },
1949
  { 0x49, "#ASI_INTR_RECEIVE" },
1950
  { 0x4a, "#ASI_UPA_CONFIG" },
1951
  { 0x4a, "#ASI_JBUS_CONFIG" },
1952
  { 0x4a, "#ASI_SAFARI_CONFIG" },
1953
  { 0x4a, "#ASI_SAFARI_ADDRESS" },
1954
  { 0x4b, "#ASI_ESTATE_ERROR_EN" },
1955
  { 0x4c, "#ASI_AFSR" },
1956
  { 0x4d, "#ASI_AFAR" },
1957
  { 0x4e, "#ASI_EC_TAG_DATA" },
1958
  { 0x50, "#ASI_IMMU" },
1959
  { 0x51, "#ASI_IMMU_TSB_8KB_PTR" },
1960
  { 0x52, "#ASI_IMMU_TSB_16KB_PTR" },
1961
  { 0x54, "#ASI_ITLB_DATA_IN" },
1962
  { 0x55, "#ASI_ITLB_DATA_ACCESS" },
1963
  { 0x56, "#ASI_ITLB_TAG_READ" },
1964
  { 0x57, "#ASI_IMMU_DEMAP" },
1965
  { 0x58, "#ASI_DMMU" },
1966
  { 0x59, "#ASI_DMMU_TSB_8KB_PTR" },
1967
  { 0x5a, "#ASI_DMMU_TSB_64KB_PTR" },
1968
  { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" },
1969
  { 0x5c, "#ASI_DTLB_DATA_IN" },
1970
  { 0x5d, "#ASI_DTLB_DATA_ACCESS" },
1971
  { 0x5e, "#ASI_DTLB_TAG_READ" },
1972
  { 0x5f, "#ASI_DMMU_DEMAP" },
1973
  { 0x60, "#ASI_IIU_INST_TRAP" },
1974
  { 0x63, "#ASI_INTR_ID" },
1975
  { 0x63, "#ASI_CORE_ID" },
1976
  { 0x63, "#ASI_CESR_ID" },
1977
  { 0x66, "#ASI_IC_INSTR" },
1978
  { 0x67, "#ASI_IC_TAG" },
1979
  { 0x68, "#ASI_IC_STAG" },
1980
  { 0x6e, "#ASI_IC_PRE_DECODE" },
1981
  { 0x6f, "#ASI_IC_NEXT_FIELD" },
1982
  { 0x6f, "#ASI_BRPRED_ARRAY" },
1983
  { 0x70, "#ASI_BLK_AIUP" },
1984
  { 0x71, "#ASI_BLK_AIUS" },
1985
  { 0x72, "#ASI_MCU_CTRL_REG" },
1986
  { 0x74, "#ASI_EC_DATA" },
1987
  { 0x75, "#ASI_EC_CTRL" },
1988
  { 0x76, "#ASI_EC_W" },
1989
  { 0x77, "#ASI_UDB_ERROR_W" },
1990
  { 0x77, "#ASI_UDB_CONTROL_W" },
1991
  { 0x77, "#ASI_INTR_W" },
1992
  { 0x77, "#ASI_INTR_DATAN_W" },
1993
  { 0x77, "#ASI_INTR_DISPATCH_W" },
1994
  { 0x78, "#ASI_BLK_AIUPL" },
1995
  { 0x79, "#ASI_BLK_AIUSL" },
1996
  { 0x7e, "#ASI_EC_R" },
1997
  { 0x7f, "#ASI_UDBH_ERROR_R" },
1998
  { 0x7f, "#ASI_UDBL_ERROR_R" },
1999
  { 0x7f, "#ASI_UDBH_CONTROL_R" },
2000
  { 0x7f, "#ASI_UDBL_CONTROL_R" },
2001
  { 0x7f, "#ASI_INTR_R" },
2002
  { 0x7f, "#ASI_INTR_DATAN_R" },
2003
  { 0xc0, "#ASI_PST8_P" },
2004
  { 0xc1, "#ASI_PST8_S" },
2005
  { 0xc2, "#ASI_PST16_P" },
2006
  { 0xc3, "#ASI_PST16_S" },
2007
  { 0xc4, "#ASI_PST32_P" },
2008
  { 0xc5, "#ASI_PST32_S" },
2009
  { 0xc8, "#ASI_PST8_PL" },
2010
  { 0xc9, "#ASI_PST8_SL" },
2011
  { 0xca, "#ASI_PST16_PL" },
2012
  { 0xcb, "#ASI_PST16_SL" },
2013
  { 0xcc, "#ASI_PST32_PL" },
2014
  { 0xcd, "#ASI_PST32_SL" },
2015
  { 0xd0, "#ASI_FL8_P" },
2016
  { 0xd1, "#ASI_FL8_S" },
2017
  { 0xd2, "#ASI_FL16_P" },
2018
  { 0xd3, "#ASI_FL16_S" },
2019
  { 0xd8, "#ASI_FL8_PL" },
2020
  { 0xd9, "#ASI_FL8_SL" },
2021
  { 0xda, "#ASI_FL16_PL" },
2022
  { 0xdb, "#ASI_FL16_SL" },
2023
  { 0xe0, "#ASI_BLK_COMMIT_P", },
2024
  { 0xe1, "#ASI_BLK_COMMIT_S", },
2025
  { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" },
2026
  { 0xf0, "#ASI_BLK_P", },
2027
  { 0xf1, "#ASI_BLK_S", },
2028
  { 0xf8, "#ASI_BLK_PL", },
2029
  { 0xf9, "#ASI_BLK_SL", },
2030
  { 0, 0 }
2031
};
2032
 
2033
/* Return the value for ASI NAME, or -1 if not found.  */
2034
 
2035
int
2036
sparc_encode_asi (const char *name)
2037
{
2038
  return lookup_name (asi_table, name);
2039
}
2040
 
2041
/* Return the name for ASI value VALUE or NULL if not found.  */
2042
 
2043
const char *
2044
sparc_decode_asi (int value)
2045
{
2046
  return lookup_value (asi_table, value);
2047
}
2048
 
2049
/* Handle membar masks.  */
2050
 
2051
static arg membar_table[] =
2052
{
2053
  { 0x40, "#Sync" },
2054
  { 0x20, "#MemIssue" },
2055
  { 0x10, "#Lookaside" },
2056
  { 0x08, "#StoreStore" },
2057
  { 0x04, "#LoadStore" },
2058
  { 0x02, "#StoreLoad" },
2059
  { 0x01, "#LoadLoad" },
2060
  { 0, 0 }
2061
};
2062
 
2063
/* Return the value for membar arg NAME, or -1 if not found.  */
2064
 
2065
int
2066
sparc_encode_membar (const char *name)
2067
{
2068
  return lookup_name (membar_table, name);
2069
}
2070
 
2071
/* Return the name for membar value VALUE or NULL if not found.  */
2072
 
2073
const char *
2074
sparc_decode_membar (int value)
2075
{
2076
  return lookup_value (membar_table, value);
2077
}
2078
 
2079
/* Handle prefetch args.  */
2080
 
2081
static arg prefetch_table[] =
2082
{
2083
  { 0, "#n_reads" },
2084
  { 1, "#one_read" },
2085
  { 2, "#n_writes" },
2086
  { 3, "#one_write" },
2087
  { 4, "#page" },
2088
  { 16, "#invalidate" },
2089
  { 17, "#unified", },
2090
  { 20, "#n_reads_strong", },
2091
  { 21, "#one_read_strong", },
2092
  { 22, "#n_writes_strong", },
2093
  { 23, "#one_write_strong", },
2094
  { 0, 0 }
2095
};
2096
 
2097
/* Return the value for prefetch arg NAME, or -1 if not found.  */
2098
 
2099
int
2100
sparc_encode_prefetch (const char *name)
2101
{
2102
  return lookup_name (prefetch_table, name);
2103
}
2104
 
2105
/* Return the name for prefetch value VALUE or NULL if not found.  */
2106
 
2107
const char *
2108
sparc_decode_prefetch (int value)
2109
{
2110
  return lookup_value (prefetch_table, value);
2111
}
2112
 
2113
/* Handle sparclet coprocessor registers.  */
2114
 
2115
static arg sparclet_cpreg_table[] =
2116
{
2117
  { 0, "%ccsr" },
2118
  { 1, "%ccfr" },
2119
  { 2, "%cccrcr" },
2120
  { 3, "%ccpr" },
2121
  { 4, "%ccsr2" },
2122
  { 5, "%cccrr" },
2123
  { 6, "%ccrstr" },
2124
  { 0, 0 }
2125
};
2126
 
2127
/* Return the value for sparclet cpreg arg NAME, or -1 if not found.  */
2128
 
2129
int
2130
sparc_encode_sparclet_cpreg (const char *name)
2131
{
2132
  return lookup_name (sparclet_cpreg_table, name);
2133
}
2134
 
2135
/* Return the name for sparclet cpreg value VALUE or NULL if not found.  */
2136
 
2137
const char *
2138
sparc_decode_sparclet_cpreg (int value)
2139
{
2140
  return lookup_value (sparclet_cpreg_table, value);
2141
}

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