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/* Definitions of target machine for GNU compiler, for DEC Alpha.

   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,

   2000, 2001, 2002, 2004, 2005, 2007 Free Software Foundation, Inc.

   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3, or (at your option)

any later version.

GCC is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING3.  If not see

<http://www.gnu.org/licenses/>.  */

/* Target CPU builtins.  */

#define TARGET_CPU_CPP_BUILTINS()                       \

  do                                                    \

    {                                                   \

        builtin_define ("__alpha");                     \

        builtin_define ("__alpha__");                   \

        builtin_assert ("cpu=alpha");                   \

        builtin_assert ("machine=alpha");               \

        if (TARGET_CIX)                                 \

          {                                             \

            builtin_define ("__alpha_cix__");           \

            builtin_assert ("cpu=cix");                 \

          }                                             \

        if (TARGET_FIX)                                 \

          {                                             \

            builtin_define ("__alpha_fix__");           \

            builtin_assert ("cpu=fix");                 \

          }                                             \

        if (TARGET_BWX)                                 \

          {                                             \

            builtin_define ("__alpha_bwx__");           \

            builtin_assert ("cpu=bwx");                 \

          }                                             \

        if (TARGET_MAX)                                 \

          {                                             \

            builtin_define ("__alpha_max__");           \

            builtin_assert ("cpu=max");                 \

          }                                             \

        if (alpha_cpu == PROCESSOR_EV6)                 \

          {                                             \

            builtin_define ("__alpha_ev6__");           \

            builtin_assert ("cpu=ev6");                 \

          }                                             \

        else if (alpha_cpu == PROCESSOR_EV5)            \

          {                                             \

            builtin_define ("__alpha_ev5__");           \

            builtin_assert ("cpu=ev5");                 \

          }                                             \

        else    /* Presumably ev4.  */                  \

          {                                             \

            builtin_define ("__alpha_ev4__");           \

            builtin_assert ("cpu=ev4");                 \

          }                                             \

        if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT)    \

          builtin_define ("_IEEE_FP");                  \

        if (TARGET_IEEE_WITH_INEXACT)                   \

          builtin_define ("_IEEE_FP_INEXACT");          \

        if (TARGET_LONG_DOUBLE_128)                     \

          builtin_define ("__LONG_DOUBLE_128__");       \

                                                        \

        /* Macros dependent on the C dialect.  */       \

        SUBTARGET_LANGUAGE_CPP_BUILTINS();              \

} while (0)

#ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS

#define SUBTARGET_LANGUAGE_CPP_BUILTINS()               \

  do                                                    \

    {                                                   \

      if (preprocessing_asm_p ())                       \

        builtin_define_std ("LANGUAGE_ASSEMBLY");       \

      else if (c_dialect_cxx ())                        \

        {                                               \

          builtin_define ("__LANGUAGE_C_PLUS_PLUS");    \

          builtin_define ("__LANGUAGE_C_PLUS_PLUS__");  \

        }                                               \

      else                                              \

        builtin_define_std ("LANGUAGE_C");              \

      if (c_dialect_objc ())                            \

        {                                               \

          builtin_define ("__LANGUAGE_OBJECTIVE_C");    \

          builtin_define ("__LANGUAGE_OBJECTIVE_C__");  \

        }                                               \

    }                                                   \

  while (0)

#endif

#define CPP_SPEC "%(cpp_subtarget)"

#ifndef CPP_SUBTARGET_SPEC

#define CPP_SUBTARGET_SPEC ""

#endif

#define WORD_SWITCH_TAKES_ARG(STR)              \

 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))

/* Print subsidiary information on the compiler version in use.  */

#define TARGET_VERSION

/* Run-time compilation parameters selecting different hardware subsets.  */

/* Which processor to schedule for. The cpu attribute defines a list that

   mirrors this list, so changes to alpha.md must be made at the same time.  */

enum processor_type

{

  PROCESSOR_EV4,                        /* 2106[46]{a,} */

  PROCESSOR_EV5,                        /* 21164{a,pc,} */

  PROCESSOR_EV6,                        /* 21264 */

  PROCESSOR_MAX

};

extern enum processor_type alpha_cpu;

extern enum processor_type alpha_tune;

enum alpha_trap_precision

{

  ALPHA_TP_PROG,        /* No precision (default).  */

  ALPHA_TP_FUNC,        /* Trap contained within originating function.  */

  ALPHA_TP_INSN         /* Instruction accuracy and code is resumption safe.  */

};

enum alpha_fp_rounding_mode

{

  ALPHA_FPRM_NORM,      /* Normal rounding mode.  */

  ALPHA_FPRM_MINF,      /* Round towards minus-infinity.  */

  ALPHA_FPRM_CHOP,      /* Chopped rounding mode (towards 0).  */

  ALPHA_FPRM_DYN        /* Dynamic rounding mode.  */

};

enum alpha_fp_trap_mode

{

  ALPHA_FPTM_N,         /* Normal trap mode.  */

  ALPHA_FPTM_U,         /* Underflow traps enabled.  */

  ALPHA_FPTM_SU,        /* Software completion, w/underflow traps */

  ALPHA_FPTM_SUI        /* Software completion, w/underflow & inexact traps */

};

extern int target_flags;

extern enum alpha_trap_precision alpha_tp;

extern enum alpha_fp_rounding_mode alpha_fprm;

extern enum alpha_fp_trap_mode alpha_fptm;

/* Invert the easy way to make options work.  */

#define TARGET_FP       (!TARGET_SOFT_FP)

/* These are for target os support and cannot be changed at runtime.  */

#define TARGET_ABI_WINDOWS_NT 0

#define TARGET_ABI_OPEN_VMS 0

#define TARGET_ABI_UNICOSMK 0

#define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT  \

                        && !TARGET_ABI_OPEN_VMS \

                        && !TARGET_ABI_UNICOSMK)

#ifndef TARGET_AS_CAN_SUBTRACT_LABELS

#define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS

#endif

#ifndef TARGET_AS_SLASH_BEFORE_SUFFIX

#define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS

#endif

#ifndef TARGET_CAN_FAULT_IN_PROLOGUE

#define TARGET_CAN_FAULT_IN_PROLOGUE 0

#endif

#ifndef TARGET_HAS_XFLOATING_LIBS

#define TARGET_HAS_XFLOATING_LIBS TARGET_LONG_DOUBLE_128

#endif

#ifndef TARGET_PROFILING_NEEDS_GP

#define TARGET_PROFILING_NEEDS_GP 0

#endif

#ifndef TARGET_LD_BUGGY_LDGP

#define TARGET_LD_BUGGY_LDGP 0

#endif

#ifndef TARGET_FIXUP_EV5_PREFETCH

#define TARGET_FIXUP_EV5_PREFETCH 0

#endif

#ifndef HAVE_AS_TLS

#define HAVE_AS_TLS 0

#endif

#define TARGET_DEFAULT MASK_FPREGS

#ifndef TARGET_CPU_DEFAULT

#define TARGET_CPU_DEFAULT 0

#endif

#ifndef TARGET_DEFAULT_EXPLICIT_RELOCS

#ifdef HAVE_AS_EXPLICIT_RELOCS

#define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS

#define TARGET_SUPPORT_ARCH 1

#else

#define TARGET_DEFAULT_EXPLICIT_RELOCS 0

#endif

#endif

#ifndef TARGET_SUPPORT_ARCH

#define TARGET_SUPPORT_ARCH 0

#endif

/* Support for a compile-time default CPU, et cetera.  The rules are:

   --with-cpu is ignored if -mcpu is specified.

   --with-tune is ignored if -mtune is specified.  */

#define OPTION_DEFAULT_SPECS \

  {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \

  {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }

/* This macro defines names of additional specifications to put in the

   specs that can be used in various specifications like CC1_SPEC.  Its

   definition is an initializer with a subgrouping for each command option.

   Each subgrouping contains a string constant, that defines the

   specification name, and a string constant that used by the GCC driver

   program.

   Do not define this macro if it does not need to do anything.  */

#ifndef SUBTARGET_EXTRA_SPECS

#define SUBTARGET_EXTRA_SPECS

#endif

#define EXTRA_SPECS                             \

  { "cpp_subtarget", CPP_SUBTARGET_SPEC },      \

  SUBTARGET_EXTRA_SPECS

/* Sometimes certain combinations of command options do not make sense

   on a particular target machine.  You can define a macro

   `OVERRIDE_OPTIONS' to take account of this.  This macro, if

   defined, is executed once just after all the command options have

   been parsed.

   On the Alpha, it is used to translate target-option strings into

   numeric values.  */

#define OVERRIDE_OPTIONS override_options ()

/* Define this macro to change register usage conditional on target flags.

   On the Alpha, we use this to disable the floating-point registers when

   they don't exist.  */

#define CONDITIONAL_REGISTER_USAGE              \

{                                               \

  int i;                                        \

  if (! TARGET_FPREGS)                          \

    for (i = 32; i < 63; i++)                   \

      fixed_regs[i] = call_used_regs[i] = 1;    \

}

/* Show we can debug even without a frame pointer.  */

#define CAN_DEBUG_WITHOUT_FP

/* target machine storage layout */

/* Define the size of `int'.  The default is the same as the word size.  */

#define INT_TYPE_SIZE 32

/* Define the size of `long long'.  The default is the twice the word size.  */

#define LONG_LONG_TYPE_SIZE 64

/* We're IEEE unless someone says to use VAX.  */

#define TARGET_FLOAT_FORMAT \

  (TARGET_FLOAT_VAX ? VAX_FLOAT_FORMAT : IEEE_FLOAT_FORMAT)

/* The two floating-point formats we support are S-floating, which is

   4 bytes, and T-floating, which is 8 bytes.  `float' is S and `double'

   and `long double' are T.  */

#define FLOAT_TYPE_SIZE 32

#define DOUBLE_TYPE_SIZE 64

#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)

/* Define this to set long double type size to use in libgcc2.c, which can

   not depend on target_flags.  */

#ifdef __LONG_DOUBLE_128__

#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128

#else

#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64

#endif

/* Work around target_flags dependency in ada/targtyps.c.  */

#define WIDEST_HARDWARE_FP_SIZE 64

#define WCHAR_TYPE "unsigned int"

#define WCHAR_TYPE_SIZE 32

/* Define this macro if it is advisable to hold scalars in registers

   in a wider mode than that declared by the program.  In such cases,

   the value is constrained to be within the bounds of the declared

   type, but kept valid in the wider mode.  The signedness of the

   extension may differ from that of the type.

   For Alpha, we always store objects in a full register.  32-bit integers

   are always sign-extended, but smaller objects retain their signedness.

   Note that small vector types can get mapped onto integer modes at the

   whim of not appearing in alpha-modes.def.  We never promoted these

   values before; don't do so now that we've trimmed the set of modes to

   those actually implemented in the backend.  */

#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)                       \

  if (GET_MODE_CLASS (MODE) == MODE_INT                         \

      && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE)      \

      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)                 \

    {                                                           \

      if ((MODE) == SImode)                                     \

        (UNSIGNEDP) = 0;                                 \

      (MODE) = DImode;                                          \

    }

/* Define this if most significant bit is lowest numbered

   in instructions that operate on numbered bit-fields.

   There are no such instructions on the Alpha, but the documentation

   is little endian.  */

#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.

   This is false on the Alpha.  */

#define BYTES_BIG_ENDIAN 0

/* Define this if most significant word of a multiword number is lowest

   numbered.

   For Alpha we can decide arbitrarily since there are no machine instructions

   for them.  Might as well be consistent with bytes.  */

#define WORDS_BIG_ENDIAN 0

/* Width of a word, in units (bytes).  */

#define UNITS_PER_WORD 8

/* Width in bits of a pointer.

   See also the macro `Pmode' defined below.  */

#define POINTER_SIZE 64

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */

#define PARM_BOUNDARY 64

/* Boundary (in *bits*) on which stack pointer should be aligned.  */

#define STACK_BOUNDARY 128

/* Allocation boundary (in *bits*) for the code of a function.  */

#define FUNCTION_BOUNDARY 32

/* Alignment of field after `int : 0' in a structure.  */

#define EMPTY_FIELD_BOUNDARY 64

/* Every structure's size must be a multiple of this.  */

#define STRUCTURE_SIZE_BOUNDARY 8

/* A bit-field declared as `int' forces `int' alignment for the struct.  */

#define PCC_BITFIELD_TYPE_MATTERS 1

/* No data type wants to be aligned rounder than this.  */

#define BIGGEST_ALIGNMENT 128

/* For atomic access to objects, must have at least 32-bit alignment

   unless the machine has byte operations.  */

#define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))

/* Align all constants and variables to at least a word boundary so

   we can pick up pieces of them faster.  */

/* ??? Only if block-move stuff knows about different source/destination

   alignment.  */

#if 0

#define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)

#define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)

#endif

/* Set this nonzero if move instructions will actually fail to work

   when given unaligned data.

   Since we get an error message when we do one, call them invalid.  */

#define STRICT_ALIGNMENT 1

/* Set this nonzero if unaligned move instructions are extremely slow.

   On the Alpha, they trap.  */

#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1

/* Standard register usage.  */

/* Number of actual hardware registers.

   The hardware registers are assigned numbers for the compiler

   from 0 to just below FIRST_PSEUDO_REGISTER.

   All registers that the compiler knows about must be given numbers,

   even those that are not normally considered general registers.

   We define all 32 integer registers, even though $31 is always zero,

   and all 32 floating-point registers, even though $f31 is also

   always zero.  We do not bother defining the FP status register and

   there are no other registers.

   Since $31 is always zero, we will use register number 31 as the

   argument pointer.  It will never appear in the generated code

   because we will always be eliminating it in favor of the stack

   pointer or hardware frame pointer.

   Likewise, we use $f31 for the frame pointer, which will always

   be eliminated in favor of the hardware frame pointer or the

   stack pointer.  */

#define FIRST_PSEUDO_REGISTER 64

/* 1 for registers that have pervasive standard uses

   and are not available for the register allocator.  */

#define FIXED_REGISTERS  \

 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \

  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \

  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }

/* 1 for registers not available across function calls.

   These must include the FIXED_REGISTERS and also any

   registers that can be used without being saved.

   The latter must include the registers where values are returned

   and the register where structure-value addresses are passed.

   Aside from that, you can include as many other registers as you like.  */

#define CALL_USED_REGISTERS  \

 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \

  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \

  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \

  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }

/* List the order in which to allocate registers.  Each register must be

   listed once, even those in FIXED_REGISTERS.  */

#define REG_ALLOC_ORDER { \

   1, 2, 3, 4, 5, 6, 7, 8,      /* nonsaved integer registers */        \

   22, 23, 24, 25, 28,          /* likewise */                          \

   0,                            /* likewise, but return value */        \

   21, 20, 19, 18, 17, 16,      /* likewise, but input args */          \

   27,                          /* likewise, but OSF procedure value */ \

                                                                        \

   42, 43, 44, 45, 46, 47,      /* nonsaved floating-point registers */ \

   54, 55, 56, 57, 58, 59,      /* likewise */                          \

   60, 61, 62,                  /* likewise */                          \

   32, 33,                      /* likewise, but return values */       \

   53, 52, 51, 50, 49, 48,      /* likewise, but input args */          \

                                                                        \

   9, 10, 11, 12, 13, 14,       /* saved integer registers */           \

   26,                          /* return address */                    \

   15,                          /* hard frame pointer */                \

                                                                        \

   34, 35, 36, 37, 38, 39,      /* saved floating-point registers */    \

   40, 41,                      /* likewise */                          \

                                                                        \

   29, 30, 31, 63               /* gp, sp, ap, sfp */                   \

}

/* Return number of consecutive hard regs needed starting at reg REGNO

   to hold something of mode MODE.

   This is ordinarily the length in words of a value of mode MODE

   but can be less for certain modes in special long registers.  */

#define HARD_REGNO_NREGS(REGNO, MODE)   \

  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.

   On Alpha, the integer registers can hold any mode.  The floating-point

   registers can hold 64-bit integers as well, but not smaller values.  */

#define HARD_REGNO_MODE_OK(REGNO, MODE)                                 \

  ((REGNO) >= 32 && (REGNO) <= 62                                       \

   ? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode           \

     || (MODE) == SCmode || (MODE) == DCmode                            \

   : 1)

/* A C expression that is nonzero if a value of mode

   MODE1 is accessible in mode MODE2 without copying.

   This asymmetric test is true when MODE1 could be put

   in an FP register but MODE2 could not.  */

#define MODES_TIEABLE_P(MODE1, MODE2)                           \

  (HARD_REGNO_MODE_OK (32, (MODE1))                             \

   ? HARD_REGNO_MODE_OK (32, (MODE2))                           \

   : 1)

/* Specify the registers used for certain standard purposes.

   The values of these macros are register numbers.  */

/* Alpha pc isn't overloaded on a register that the compiler knows about.  */

/* #define PC_REGNUM  */

/* Register to use for pushing function arguments.  */

#define STACK_POINTER_REGNUM 30

/* Base register for access to local variables of the function.  */

#define HARD_FRAME_POINTER_REGNUM 15

/* Value should be nonzero if functions must have frame pointers.

   Zero means the frame pointer need not be set up (and parms

   may be accessed via the stack pointer) in functions that seem suitable.

   This is computed in `reload', in reload1.c.  */

#define FRAME_POINTER_REQUIRED 0

/* Base register for access to arguments of the function.  */

#define ARG_POINTER_REGNUM 31

/* Base register for access to local variables of function.  */

#define FRAME_POINTER_REGNUM 63

/* Register in which static-chain is passed to a function.

   For the Alpha, this is based on an example; the calling sequence

   doesn't seem to specify this.  */

#define STATIC_CHAIN_REGNUM 1

/* The register number of the register used to address a table of

   static data addresses in memory.  */

#define PIC_OFFSET_TABLE_REGNUM 29

/* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM'

   is clobbered by calls.  */

/* ??? It is and it isn't.  It's required to be valid for a given

   function when the function returns.  It isn't clobbered by

   current_file functions.  Moreover, we do not expose the ldgp

   until after reload, so we're probably safe.  */

/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */

/* Define the classes of registers for register constraints in the

   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.

   If there is more than one class, another class must be named NO_REGS

   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for

   another name such as ALL_REGS).  This is the class of registers

   that is allowed by "g" or "r" in a register constraint.

   Also, registers outside this class are allocated only when

   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,

   a larger-numbered class must never be contained completely

   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another

   class that represents their union.  */

enum reg_class {

  NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG,

  GENERAL_REGS, FLOAT_REGS, ALL_REGS,

  LIM_REG_CLASSES

};

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.  */

#define REG_CLASS_NAMES                                 \

 {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \

  "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }

/* Define which registers fit in which classes.

   This is an initializer for a vector of HARD_REG_SET

   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS                              \

{ {0x00000000, 0x00000000},     /* NO_REGS */           \

  {0x00000001, 0x00000000},     /* R0_REG */            \

  {0x01000000, 0x00000000},     /* R24_REG */           \

  {0x02000000, 0x00000000},     /* R25_REG */           \

  {0x08000000, 0x00000000},     /* R27_REG */           \

  {0xffffffff, 0x80000000},     /* GENERAL_REGS */      \

  {0x00000000, 0x7fffffff},     /* FLOAT_REGS */        \

  {0xffffffff, 0xffffffff} }

/* The same information, inverted:

   Return the class number of the smallest class containing

   reg number REGNO.  This could be a conditional expression

   or could index an array.  */

#define REGNO_REG_CLASS(REGNO)                  \

 ((REGNO) == 0 ? R0_REG                          \

  : (REGNO) == 24 ? R24_REG                     \

  : (REGNO) == 25 ? R25_REG                     \

  : (REGNO) == 27 ? R27_REG                     \

  : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \

  : GENERAL_REGS)

/* The class value for index registers, and the one for base regs.  */

#define INDEX_REG_CLASS NO_REGS

#define BASE_REG_CLASS GENERAL_REGS

/* Get reg_class from a letter such as appears in the machine description.  */

#define REG_CLASS_FROM_LETTER(C)        \

 ((C) == 'a' ? R24_REG                  \

  : (C) == 'b' ? R25_REG                \

  : (C) == 'c' ? R27_REG                \

  : (C) == 'f' ? FLOAT_REGS             \

  : (C) == 'v' ? R0_REG                 \

  : NO_REGS)

/* Define this macro to change register usage conditional on target flags.  */

/* #define CONDITIONAL_REGISTER_USAGE  */

/* The letters I, J, K, L, M, N, O, and P in a register constraint string

   can be used to stand for particular ranges of immediate operands.

   This macro defines what the ranges are.

   C is the letter, and VALUE is a constant value.

   Return 1 if VALUE is in the range specified by C.

   For Alpha:

   `I' is used for the range of constants most insns can contain.

   `J' is the constant zero.

   `K' is used for the constant in an LDA insn.

   `L' is used for the constant in a LDAH insn.

   `M' is used for the constants that can be AND'ed with using a ZAP insn.

   `N' is used for complemented 8-bit constants.

   `O' is used for negated 8-bit constants.

   `P' is used for the constants 1, 2 and 3.  */

#define CONST_OK_FOR_LETTER_P   alpha_const_ok_for_letter_p

/* Similar, but for floating or large integer constants, and defining letters

   G and H.   Here VALUE is the CONST_DOUBLE rtx itself.

   For Alpha, `G' is the floating-point constant zero.  `H' is a CONST_DOUBLE

   that is the operand of a ZAP insn.  */

#define CONST_DOUBLE_OK_FOR_LETTER_P  alpha_const_double_ok_for_letter_p

/* Optional extra constraints for this machine.

   For the Alpha, `Q' means that this is a memory operand but not a

   reference to an unaligned location.

   `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current

   function.

   'S' is a 6-bit constant (valid for a shift insn).

   'T' is a HIGH.

   'U' is a symbolic operand.

   'W' is a vector zero.  */

#define EXTRA_CONSTRAINT  alpha_extra_constraint

/* Given an rtx X being reloaded into a reg required to be

   in class CLASS, return the class of reg to actually use.

   In general this is just CLASS; but on some machines

   in some cases it is preferable to use a more restrictive class.  */

#define PREFERRED_RELOAD_CLASS  alpha_preferred_reload_class

/* Loading and storing HImode or QImode values to and from memory

   usually requires a scratch register.  The exceptions are loading

   QImode and HImode from an aligned address to a general register

   unless byte instructions are permitted.

   We also cannot load an unaligned address or a paradoxical SUBREG into an

   FP register.  */

#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \

  alpha_secondary_reload_class((CLASS), (MODE), (IN), 1)

#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \

  alpha_secondary_reload_class((CLASS), (MODE), (OUT), 0)

/* If we are copying between general and FP registers, we need a memory

   location unless the FIX extension is available.  */

#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \

 (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \

                   || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS)))

/* Specify the mode to be used for memory when a secondary memory

   location is needed.  If MODE is floating-point, use it.  Otherwise,

   widen to a word like the default.  This is needed because we always

   store integers in FP registers in quadword format.  This whole

   area is very tricky! */

#define SECONDARY_MEMORY_NEEDED_MODE(MODE)              \

  (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE)         \

   : GET_MODE_SIZE (MODE) >= 4 ? (MODE)                 \

   : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))

/* Return the maximum number of consecutive registers

   needed to represent mode MODE in a register of class CLASS.  */

#define CLASS_MAX_NREGS(CLASS, MODE)                            \

 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* Return the class of registers that cannot change mode from FROM to TO.  */

#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)               \

  (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)                   \

   ? reg_classes_intersect_p (FLOAT_REGS, CLASS) : 0)

/* Define the cost of moving between registers of various classes.  Moving

   between FLOAT_REGS and anything else except float regs is expensive.

   In fact, we make it quite expensive because we really don't want to

   do these moves unless it is clearly worth it.  Optimizations may

   reduce the impact of not being able to allocate a pseudo to a

   hard register.  */

#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)                \

  (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2     \

   : TARGET_FIX ? ((CLASS1) == FLOAT_REGS ? 6 : 8)              \

   : 4+2*alpha_memory_latency)

/* A C expressions returning the cost of moving data of MODE from a register to

   or from memory.

   On the Alpha, bump this up a bit.  */

extern int alpha_memory_latency;

#define MEMORY_MOVE_COST(MODE,CLASS,IN)  (2*alpha_memory_latency)

/* Provide the cost of a branch.  Exact meaning under development.  */

#define BRANCH_COST 5

/* Stack layout; function entry, exit and calling.  */

/* Define this if pushing a word on the stack

   makes the stack pointer a smaller address.  */

#define STACK_GROWS_DOWNWARD

/* Define this to nonzero if the nominal address of the stack frame

   is at the high-address end of the local variables;

   that is, each additional local variable allocated

   goes at a more negative offset in the frame.  */

/* #define FRAME_GROWS_DOWNWARD 0 */

/* Offset within stack frame to start allocating local variables at.

   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the

   first local allocated.  Otherwise, it is the offset to the BEGINNING

   of the first local allocated.  */

#define STARTING_FRAME_OFFSET 0

/* If we generate an insn to push BYTES bytes,

   this says how many the stack pointer really advances by.

   On Alpha, don't define this because there are no push insns.  */