OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [arm/] [arm1020e.md] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
;; ARM 1020E & ARM 1022E Pipeline Description
2
;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
3
;; Contributed by Richard Earnshaw (richard.earnshaw@arm.com)
4
;;
5
;; This file is part of GCC.
6
;;
7
;; GCC is free software; you can redistribute it and/or modify it
8
;; under the terms of the GNU General Public License as published by
9
;; the Free Software Foundation; either version 3, or (at your option)
10
;; any later version.
11
;;
12
;; GCC is distributed in the hope that it will be useful, but
13
;; WITHOUT ANY WARRANTY; without even the implied warranty of
14
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
;; General Public License for more details.
16
;;
17
;; You should have received a copy of the GNU General Public License
18
;; along with GCC; see the file COPYING3.  If not see
19
;; .  */
20
 
21
;; These descriptions are based on the information contained in the
22
;; ARM1020E Technical Reference Manual, Copyright (c) 2003 ARM
23
;; Limited.
24
;;
25
 
26
;; This automaton provides a pipeline description for the ARM
27
;; 1020E core.
28
;;
29
;; The model given here assumes that the condition for all conditional
30
;; instructions is "true", i.e., that all of the instructions are
31
;; actually executed.
32
 
33
(define_automaton "arm1020e")
34
 
35
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
36
;; Pipelines
37
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
38
 
39
;; There are two pipelines:
40
;;
41
;; - An Arithmetic Logic Unit (ALU) pipeline.
42
;;
43
;;   The ALU pipeline has fetch, issue, decode, execute, memory, and
44
;;   write stages. We only need to model the execute, memory and write
45
;;   stages.
46
;;
47
;; - A Load-Store Unit (LSU) pipeline.
48
;;
49
;;   The LSU pipeline has decode, execute, memory, and write stages.
50
;;   We only model the execute, memory and write stages.
51
 
52
(define_cpu_unit "1020a_e,1020a_m,1020a_w" "arm1020e")
53
(define_cpu_unit "1020l_e,1020l_m,1020l_w" "arm1020e")
54
 
55
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
56
;; ALU Instructions
57
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
58
 
59
;; ALU instructions require three cycles to execute, and use the ALU
60
;; pipeline in each of the three stages.  The results are available
61
;; after the execute stage stage has finished.
62
;;
63
;; If the destination register is the PC, the pipelines are stalled
64
;; for several cycles.  That case is not modeled here.
65
 
66
;; ALU operations with no shifted operand
67
(define_insn_reservation "1020alu_op" 1
68
 (and (eq_attr "tune" "arm1020e,arm1022e")
69
      (eq_attr "type" "alu"))
70
 "1020a_e,1020a_m,1020a_w")
71
 
72
;; ALU operations with a shift-by-constant operand
73
(define_insn_reservation "1020alu_shift_op" 1
74
 (and (eq_attr "tune" "arm1020e,arm1022e")
75
      (eq_attr "type" "alu_shift"))
76
 "1020a_e,1020a_m,1020a_w")
77
 
78
;; ALU operations with a shift-by-register operand
79
;; These really stall in the decoder, in order to read
80
;; the shift value in a second cycle. Pretend we take two cycles in
81
;; the execute stage.
82
(define_insn_reservation "1020alu_shift_reg_op" 2
83
 (and (eq_attr "tune" "arm1020e,arm1022e")
84
      (eq_attr "type" "alu_shift_reg"))
85
 "1020a_e*2,1020a_m,1020a_w")
86
 
87
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
88
;; Multiplication Instructions
89
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
90
 
91
;; Multiplication instructions loop in the execute stage until the
92
;; instruction has been passed through the multiplier array enough
93
;; times.
94
 
95
;; The result of the "smul" and "smulw" instructions is not available
96
;; until after the memory stage.
97
(define_insn_reservation "1020mult1" 2
98
 (and (eq_attr "tune" "arm1020e,arm1022e")
99
      (eq_attr "insn" "smulxy,smulwy"))
100
 "1020a_e,1020a_m,1020a_w")
101
 
102
;; The "smlaxy" and "smlawx" instructions require two iterations through
103
;; the execute stage; the result is available immediately following
104
;; the execute stage.
105
(define_insn_reservation "1020mult2" 2
106
 (and (eq_attr "tune" "arm1020e,arm1022e")
107
      (eq_attr "insn" "smlaxy,smlalxy,smlawx"))
108
 "1020a_e*2,1020a_m,1020a_w")
109
 
110
;; The "smlalxy", "mul", and "mla" instructions require two iterations
111
;; through the execute stage; the result is not available until after
112
;; the memory stage.
113
(define_insn_reservation "1020mult3" 3
114
 (and (eq_attr "tune" "arm1020e,arm1022e")
115
      (eq_attr "insn" "smlalxy,mul,mla"))
116
 "1020a_e*2,1020a_m,1020a_w")
117
 
118
;; The "muls" and "mlas" instructions loop in the execute stage for
119
;; four iterations in order to set the flags.  The value result is
120
;; available after three iterations.
121
(define_insn_reservation "1020mult4" 3
122
 (and (eq_attr "tune" "arm1020e,arm1022e")
123
      (eq_attr "insn" "muls,mlas"))
124
 "1020a_e*4,1020a_m,1020a_w")
125
 
126
;; Long multiply instructions that produce two registers of
127
;; output (such as umull) make their results available in two cycles;
128
;; the least significant word is available before the most significant
129
;; word.  That fact is not modeled; instead, the instructions are
130
;; described.as if the entire result was available at the end of the
131
;; cycle in which both words are available.
132
 
133
;; The "umull", "umlal", "smull", and "smlal" instructions all take
134
;; three iterations through the execute cycle, and make their results
135
;; available after the memory cycle.
136
(define_insn_reservation "1020mult5" 4
137
 (and (eq_attr "tune" "arm1020e,arm1022e")
138
      (eq_attr "insn" "umull,umlal,smull,smlal"))
139
 "1020a_e*3,1020a_m,1020a_w")
140
 
141
;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
142
;; the execute stage for five iterations in order to set the flags.
143
;; The value result is available after four iterations.
144
(define_insn_reservation "1020mult6" 4
145
 (and (eq_attr "tune" "arm1020e,arm1022e")
146
      (eq_attr "insn" "umulls,umlals,smulls,smlals"))
147
 "1020a_e*5,1020a_m,1020a_w")
148
 
149
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
150
;; Load/Store Instructions
151
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
152
 
153
;; The models for load/store instructions do not accurately describe
154
;; the difference between operations with a base register writeback
155
;; (such as "ldm!").  These models assume that all memory references
156
;; hit in dcache.
157
 
158
;; LSU instructions require six cycles to execute.  They use the ALU
159
;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
160
;; three through six.
161
;; Loads and stores which use a scaled register offset or scaled
162
;; register pre-indexed addressing mode take three cycles EXCEPT for
163
;; those that are base + offset with LSL of 0 or 2, or base - offset
164
;; with LSL of zero.  The remainder take 1 cycle to execute.
165
;; For 4byte loads there is a bypass from the load stage
166
 
167
(define_insn_reservation "1020load1_op" 2
168
 (and (eq_attr "tune" "arm1020e,arm1022e")
169
      (eq_attr "type" "load_byte,load1"))
170
 "1020a_e+1020l_e,1020l_m,1020l_w")
171
 
172
(define_insn_reservation "1020store1_op" 0
173
 (and (eq_attr "tune" "arm1020e,arm1022e")
174
      (eq_attr "type" "store1"))
175
 "1020a_e+1020l_e,1020l_m,1020l_w")
176
 
177
;; A load's result can be stored by an immediately following store
178
(define_bypass 1 "1020load1_op" "1020store1_op" "arm_no_early_store_addr_dep")
179
 
180
;; On a LDM/STM operation, the LSU pipeline iterates until all of the
181
;; registers have been processed.
182
;;
183
;; The time it takes to load the data depends on whether or not the
184
;; base address is 64-bit aligned; if it is not, an additional cycle
185
;; is required.  This model assumes that the address is always 64-bit
186
;; aligned.  Because the processor can load two registers per cycle,
187
;; that assumption means that we use the same instruction reservations
188
;; for loading 2k and 2k - 1 registers.
189
;;
190
;; The ALU pipeline is decoupled after the first cycle unless there is
191
;; a register dependency; the dependency is cleared as soon as the LDM/STM
192
;; has dealt with the corresponding register.  So for example,
193
;;  stmia sp, {r0-r3}
194
;;  add r0, r0, #4
195
;; will have one fewer stalls than
196
;;  stmia sp, {r0-r3}
197
;;  add r3, r3, #4
198
;;
199
;; As with ALU operations, if one of the destination registers is the
200
;; PC, there are additional stalls; that is not modeled.
201
 
202
(define_insn_reservation "1020load2_op" 2
203
 (and (eq_attr "tune" "arm1020e,arm1022e")
204
      (eq_attr "type" "load2"))
205
 "1020a_e+1020l_e,1020l_m,1020l_w")
206
 
207
(define_insn_reservation "1020store2_op" 0
208
 (and (eq_attr "tune" "arm1020e,arm1022e")
209
      (eq_attr "type" "store2"))
210
 "1020a_e+1020l_e,1020l_m,1020l_w")
211
 
212
(define_insn_reservation "1020load34_op" 3
213
 (and (eq_attr "tune" "arm1020e,arm1022e")
214
      (eq_attr "type" "load3,load4"))
215
 "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
216
 
217
(define_insn_reservation "1020store34_op" 0
218
 (and (eq_attr "tune" "arm1020e,arm1022e")
219
      (eq_attr "type" "store3,store4"))
220
 "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
221
 
222
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
223
;; Branch and Call Instructions
224
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
225
 
226
;; Branch instructions are difficult to model accurately.  The ARM
227
;; core can predict most branches.  If the branch is predicted
228
;; correctly, and predicted early enough, the branch can be completely
229
;; eliminated from the instruction stream.  Some branches can
230
;; therefore appear to require zero cycles to execute.  We assume that
231
;; all branches are predicted correctly, and that the latency is
232
;; therefore the minimum value.
233
 
234
(define_insn_reservation "1020branch_op" 0
235
 (and (eq_attr "tune" "arm1020e,arm1022e")
236
      (eq_attr "type" "branch"))
237
 "1020a_e")
238
 
239
;; The latency for a call is not predictable.  Therefore, we use 32 as
240
;; roughly equivalent to positive infinity.
241
 
242
(define_insn_reservation "1020call_op" 32
243
 (and (eq_attr "tune" "arm1020e,arm1022e")
244
      (eq_attr "type" "call"))
245
 "1020a_e*32")
246
 
247
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
248
;; VFP
249
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
250
 
251
(define_cpu_unit "v10_fmac" "arm1020e")
252
 
253
(define_cpu_unit "v10_ds" "arm1020e")
254
 
255
(define_cpu_unit "v10_fmstat" "arm1020e")
256
 
257
(define_cpu_unit "v10_ls1,v10_ls2,v10_ls3" "arm1020e")
258
 
259
;; fmstat is a serializing instruction.  It will stall the core until
260
;; the mac and ds units have completed.
261
(exclusion_set "v10_fmac,v10_ds" "v10_fmstat")
262
 
263
(define_attr "vfp10" "yes,no"
264
  (const (if_then_else (and (eq_attr "tune" "arm1020e,arm1022e")
265
                            (eq_attr "fpu" "vfp"))
266
                       (const_string "yes") (const_string "no"))))
267
 
268
;; The VFP "type" attributes differ from those used in the FPA model.
269
;; ffarith      Fast floating point insns, e.g. abs, neg, cpy, cmp.
270
;; farith       Most arithmetic insns.
271
;; fmul         Double precision multiply.
272
;; fdivs        Single precision sqrt or division.
273
;; fdivd        Double precision sqrt or division.
274
;; f_flag       fmstat operation
275
;; f_load       Floating point load from memory.
276
;; f_store      Floating point store to memory.
277
;; f_2_r        Transfer vfp to arm reg.
278
;; r_2_f        Transfer arm to vfp reg.
279
 
280
;; Note, no instruction can issue to the VFP if the core is stalled in the
281
;; first execute state.  We model this by using 1020a_e in the first cycle.
282
(define_insn_reservation "v10_ffarith" 5
283
 (and (eq_attr "vfp10" "yes")
284
      (eq_attr "type" "ffarith"))
285
 "1020a_e+v10_fmac")
286
 
287
(define_insn_reservation "v10_farith" 5
288
 (and (eq_attr "vfp10" "yes")
289
      (eq_attr "type" "farith"))
290
 "1020a_e+v10_fmac")
291
 
292
(define_insn_reservation "v10_cvt" 5
293
 (and (eq_attr "vfp10" "yes")
294
      (eq_attr "type" "f_cvt"))
295
 "1020a_e+v10_fmac")
296
 
297
(define_insn_reservation "v10_fmul" 6
298
 (and (eq_attr "vfp10" "yes")
299
      (eq_attr "type" "fmul"))
300
 "1020a_e+v10_fmac*2")
301
 
302
(define_insn_reservation "v10_fdivs" 18
303
 (and (eq_attr "vfp10" "yes")
304
      (eq_attr "type" "fdivs"))
305
 "1020a_e+v10_ds*14")
306
 
307
(define_insn_reservation "v10_fdivd" 32
308
 (and (eq_attr "vfp10" "yes")
309
      (eq_attr "type" "fdivd"))
310
 "1020a_e+v10_fmac+v10_ds*28")
311
 
312
(define_insn_reservation "v10_floads" 4
313
 (and (eq_attr "vfp10" "yes")
314
      (eq_attr "type" "f_loads"))
315
 "1020a_e+1020l_e+v10_ls1,v10_ls2")
316
 
317
;; We model a load of a double as needing all the vfp ls* stage in cycle 1.
318
;; This gives the correct mix between single-and double loads where a flds
319
;; followed by and fldd will stall for one cycle, but two back-to-back fldd
320
;; insns stall for two cycles.
321
(define_insn_reservation "v10_floadd" 5
322
 (and (eq_attr "vfp10" "yes")
323
      (eq_attr "type" "f_loadd"))
324
 "1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
325
 
326
;; Moves to/from arm regs also use the load/store pipeline.
327
 
328
(define_insn_reservation "v10_c2v" 4
329
 (and (eq_attr "vfp10" "yes")
330
      (eq_attr "type" "r_2_f"))
331
 "1020a_e+1020l_e+v10_ls1,v10_ls2")
332
 
333
(define_insn_reservation "v10_fstores" 1
334
 (and (eq_attr "vfp10" "yes")
335
      (eq_attr "type" "f_stores"))
336
 "1020a_e+1020l_e+v10_ls1,v10_ls2")
337
 
338
(define_insn_reservation "v10_fstored" 1
339
 (and (eq_attr "vfp10" "yes")
340
      (eq_attr "type" "f_stored"))
341
 "1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
342
 
343
(define_insn_reservation "v10_v2c" 1
344
 (and (eq_attr "vfp10" "yes")
345
      (eq_attr "type" "f_2_r"))
346
 "1020a_e+1020l_e,1020l_m,1020l_w")
347
 
348
(define_insn_reservation "v10_to_cpsr" 2
349
 (and (eq_attr "vfp10" "yes")
350
      (eq_attr "type" "f_flag"))
351
 "1020a_e+v10_fmstat,1020a_e+1020l_e,1020l_m,1020l_w")
352
 
353
;; VFP bypasses
354
 
355
;; There are bypasses for most operations other than store
356
 
357
(define_bypass 3
358
 "v10_c2v,v10_floads"
359
 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd,v10_cvt")
360
 
361
(define_bypass 4
362
 "v10_floadd"
363
 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
364
 
365
;; Arithmetic to other arithmetic saves a cycle due to forwarding
366
(define_bypass 4
367
 "v10_ffarith,v10_farith"
368
 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
369
 
370
(define_bypass 5
371
 "v10_fmul"
372
 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
373
 
374
(define_bypass 17
375
 "v10_fdivs"
376
 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
377
 
378
(define_bypass 31
379
 "v10_fdivd"
380
 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
381
 
382
;; VFP anti-dependencies.
383
 
384
;; There is one anti-dependence in the following case (not yet modelled):
385
;; - After a store: one extra cycle for both fsts and fstd
386
;; Note, back-to-back fstd instructions will overload the load/store datapath
387
;; causing a two-cycle stall.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.