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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [arm/] [fpa.md] - Blame information for rev 816

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1 38 julius 
;;- Machine description for FPA co-processor for ARM cpus.
2 
;;  Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000,
3 
;;  2001, 2002, 2003, 2004, 2005, 2007  Free Software Foundation, Inc.
4 
;;  Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 
;;  and Martin Simmons (@harleqn.co.uk).
6 
;;  More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 
 
8 
;; This file is part of GCC.
9 
 
10 
;; GCC is free software; you can redistribute it and/or modify it
11 
;; under the terms of the GNU General Public License as published
12 
;; by the Free Software Foundation; either version 3, or (at your
13 
;; option) any later version.
14 
 
15 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
16 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
18 
;; License for more details.
19 
 
20 
;; You should have received a copy of the GNU General Public License
21 
;; along with GCC; see the file COPYING3.  If not see
22 
;; .
23 
 
24 
;; FPA automaton.
25 
(define_automaton "armfp")
26 
 
27 
;; Floating point unit (FPA)
28 
(define_cpu_unit "fpa" "armfp")
29 
 
30 
; The fpa10 doesn't really have a memory read unit, but it can start
31 
; to speculatively execute the instruction in the pipeline, provided
32 
; the data is already loaded, so pretend reads have a delay of 2 (and
33 
; that the pipeline is infinite).
34 
(define_cpu_unit "fpa_mem" "arm")
35 
 
36 
(define_insn_reservation "fdivx" 71
37 
  (and (eq_attr "fpu" "fpa")
38 
       (eq_attr "type" "fdivx"))
39 
  "core+fpa*69")
40 
 
41 
(define_insn_reservation "fdivd" 59
42 
  (and (eq_attr "fpu" "fpa")
43 
       (eq_attr "type" "fdivd"))
44 
  "core+fpa*57")
45 
 
46 
(define_insn_reservation "fdivs" 31
47 
  (and (eq_attr "fpu" "fpa")
48 
       (eq_attr "type" "fdivs"))
49 
  "core+fpa*29")
50 
 
51 
(define_insn_reservation "fmul" 9
52 
  (and (eq_attr "fpu" "fpa")
53 
       (eq_attr "type" "fmul"))
54 
  "core+fpa*7")
55 
 
56 
(define_insn_reservation "ffmul" 6
57 
  (and (eq_attr "fpu" "fpa")
58 
       (eq_attr "type" "ffmul"))
59 
  "core+fpa*4")
60 
 
61 
(define_insn_reservation "farith" 4
62 
  (and (eq_attr "fpu" "fpa")
63 
       (eq_attr "type" "farith"))
64 
  "core+fpa*2")
65 
 
66 
(define_insn_reservation "ffarith" 2
67 
  (and (eq_attr "fpu" "fpa")
68 
       (eq_attr "type" "ffarith"))
69 
  "core+fpa*2")
70 
 
71 
(define_insn_reservation "r_2_f" 5
72 
  (and (eq_attr "fpu" "fpa")
73 
       (eq_attr "type" "r_2_f"))
74 
  "core+fpa*3")
75 
 
76 
(define_insn_reservation "f_2_r" 1
77 
  (and (eq_attr "fpu" "fpa")
78 
       (eq_attr "type" "f_2_r"))
79 
  "core+fpa*2")
80 
 
81 
(define_insn_reservation "f_load" 3
82 
  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load"))
83 
  "fpa_mem+core*3")
84 
 
85 
(define_insn_reservation "f_store" 4
86 
  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store"))
87 
  "core*4")
88 
 
89 
(define_insn_reservation "r_mem_f" 6
90 
  (and (eq_attr "model_wbuf" "no")
91 
    (and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f")))
92 
  "core*6")
93 
 
94 
(define_insn_reservation "f_mem_r" 7
95 
  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r"))
96 
  "core*7")
97 
 
98 
 
99 
(define_insn "*addsf3_fpa"
100 
  [(set (match_operand:SF          0 "s_register_operand" "=f,f")
101 
        (plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
102 
                 (match_operand:SF 2 "arm_float_add_operand"    "fG,H")))]
103 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
104 
  "@
105 
   adf%?s\\t%0, %1, %2
106 
   suf%?s\\t%0, %1, #%N2"
107 
  [(set_attr "type" "farith")
108 
   (set_attr "predicable" "yes")]
109 
)
110 
 
111 
(define_insn "*adddf3_fpa"
112 
  [(set (match_operand:DF          0 "s_register_operand" "=f,f")
113 
        (plus:DF (match_operand:DF 1 "s_register_operand" "%f,f")
114 
                 (match_operand:DF 2 "arm_float_add_operand"    "fG,H")))]
115 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
116 
  "@
117 
   adf%?d\\t%0, %1, %2
118 
   suf%?d\\t%0, %1, #%N2"
119 
  [(set_attr "type" "farith")
120 
   (set_attr "predicable" "yes")]
121 
)
122 
 
123 
(define_insn "*adddf_esfdf_df_fpa"
124 
  [(set (match_operand:DF           0 "s_register_operand" "=f,f")
125 
        (plus:DF (float_extend:DF
126 
                  (match_operand:SF 1 "s_register_operand"  "f,f"))
127 
                 (match_operand:DF  2 "arm_float_add_operand"    "fG,H")))]
128 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
129 
  "@
130 
   adf%?d\\t%0, %1, %2
131 
   suf%?d\\t%0, %1, #%N2"
132 
  [(set_attr "type" "farith")
133 
   (set_attr "predicable" "yes")]
134 
)
135 
 
136 
(define_insn "*adddf_df_esfdf_fpa"
137 
  [(set (match_operand:DF           0 "s_register_operand" "=f")
138 
        (plus:DF (match_operand:DF  1 "s_register_operand"  "f")
139 
                 (float_extend:DF
140 
                  (match_operand:SF 2 "s_register_operand"  "f"))))]
141 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
142 
  "adf%?d\\t%0, %1, %2"
143 
  [(set_attr "type" "farith")
144 
   (set_attr "predicable" "yes")]
145 
)
146 
 
147 
(define_insn "*adddf_esfdf_esfdf_fpa"
148 
  [(set (match_operand:DF           0 "s_register_operand" "=f")
149 
        (plus:DF (float_extend:DF
150 
                  (match_operand:SF 1 "s_register_operand" "f"))
151 
                 (float_extend:DF
152 
                  (match_operand:SF 2 "s_register_operand" "f"))))]
153 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
154 
  "adf%?d\\t%0, %1, %2"
155 
  [(set_attr "type" "farith")
156 
   (set_attr "predicable" "yes")]
157 
)
158 
 
159 
(define_insn "*subsf3_fpa"
160 
  [(set (match_operand:SF 0 "s_register_operand" "=f,f")
161 
        (minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G")
162 
                  (match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))]
163 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
164 
  "@
165 
   suf%?s\\t%0, %1, %2
166 
   rsf%?s\\t%0, %2, %1"
167 
  [(set_attr "type" "farith")]
168 
)
169 
 
170 
(define_insn "*subdf3_fpa"
171 
  [(set (match_operand:DF           0 "s_register_operand" "=f,f")
172 
        (minus:DF (match_operand:DF 1 "arm_float_rhs_operand"     "f,G")
173 
                  (match_operand:DF 2 "arm_float_rhs_operand"    "fG,f")))]
174 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
175 
  "@
176 
   suf%?d\\t%0, %1, %2
177 
   rsf%?d\\t%0, %2, %1"
178 
  [(set_attr "type" "farith")
179 
   (set_attr "predicable" "yes")]
180 
)
181 
 
182 
(define_insn "*subdf_esfdf_df_fpa"
183 
  [(set (match_operand:DF            0 "s_register_operand" "=f")
184 
        (minus:DF (float_extend:DF
185 
                   (match_operand:SF 1 "s_register_operand"  "f"))
186 
                  (match_operand:DF  2 "arm_float_rhs_operand"    "fG")))]
187 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
188 
  "suf%?d\\t%0, %1, %2"
189 
  [(set_attr "type" "farith")
190 
   (set_attr "predicable" "yes")]
191 
)
192 
 
193 
(define_insn "*subdf_df_esfdf_fpa"
194 
  [(set (match_operand:DF 0 "s_register_operand" "=f,f")
195 
        (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G")
196 
                  (float_extend:DF
197 
                   (match_operand:SF 2 "s_register_operand" "f,f"))))]
198 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
199 
  "@
200 
   suf%?d\\t%0, %1, %2
201 
   rsf%?d\\t%0, %2, %1"
202 
  [(set_attr "type" "farith")
203 
   (set_attr "predicable" "yes")]
204 
)
205 
 
206 
(define_insn "*subdf_esfdf_esfdf_fpa"
207 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
208 
        (minus:DF (float_extend:DF
209 
                   (match_operand:SF 1 "s_register_operand" "f"))
210 
                  (float_extend:DF
211 
                   (match_operand:SF 2 "s_register_operand" "f"))))]
212 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
213 
  "suf%?d\\t%0, %1, %2"
214 
  [(set_attr "type" "farith")
215 
   (set_attr "predicable" "yes")]
216 
)
217 
 
218 
(define_insn "*mulsf3_fpa"
219 
  [(set (match_operand:SF 0 "s_register_operand" "=f")
220 
        (mult:SF (match_operand:SF 1 "s_register_operand" "f")
221 
                 (match_operand:SF 2 "arm_float_rhs_operand" "fG")))]
222 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
223 
  "fml%?s\\t%0, %1, %2"
224 
  [(set_attr "type" "ffmul")
225 
   (set_attr "predicable" "yes")]
226 
)
227 
 
228 
(define_insn "*muldf3_fpa"
229 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
230 
        (mult:DF (match_operand:DF 1 "s_register_operand" "f")
231 
                 (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
232 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
233 
  "muf%?d\\t%0, %1, %2"
234 
  [(set_attr "type" "fmul")
235 
   (set_attr "predicable" "yes")]
236 
)
237 
 
238 
(define_insn "*muldf_esfdf_df_fpa"
239 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
240 
        (mult:DF (float_extend:DF
241 
                  (match_operand:SF 1 "s_register_operand" "f"))
242 
                 (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
243 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
244 
  "muf%?d\\t%0, %1, %2"
245 
  [(set_attr "type" "fmul")
246 
   (set_attr "predicable" "yes")]
247 
)
248 
 
249 
(define_insn "*muldf_df_esfdf_fpa"
250 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
251 
        (mult:DF (match_operand:DF 1 "s_register_operand" "f")
252 
                 (float_extend:DF
253 
                  (match_operand:SF 2 "s_register_operand" "f"))))]
254 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
255 
  "muf%?d\\t%0, %1, %2"
256 
  [(set_attr "type" "fmul")
257 
   (set_attr "predicable" "yes")]
258 
)
259 
 
260 
(define_insn "*muldf_esfdf_esfdf_fpa"
261 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
262 
        (mult:DF
263 
         (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))
264 
         (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))]
265 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
266 
  "muf%?d\\t%0, %1, %2"
267 
  [(set_attr "type" "fmul")
268 
   (set_attr "predicable" "yes")]
269 
)
270 
 
271 
;; Division insns
272 
 
273 
(define_insn "*divsf3_fpa"
274 
  [(set (match_operand:SF 0 "s_register_operand" "=f,f")
275 
        (div:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G")
276 
                (match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))]
277 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
278 
  "@
279 
   fdv%?s\\t%0, %1, %2
280 
   frd%?s\\t%0, %2, %1"
281 
  [(set_attr "type" "fdivs")
282 
   (set_attr "predicable" "yes")]
283 
)
284 
 
285 
(define_insn "*divdf3_fpa"
286 
  [(set (match_operand:DF 0 "s_register_operand" "=f,f")
287 
        (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G")
288 
                (match_operand:DF 2 "arm_float_rhs_operand" "fG,f")))]
289 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
290 
  "@
291 
   dvf%?d\\t%0, %1, %2
292 
   rdf%?d\\t%0, %2, %1"
293 
  [(set_attr "type" "fdivd")
294 
   (set_attr "predicable" "yes")]
295 
)
296 
 
297 
(define_insn "*divdf_esfdf_df_fpa"
298 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
299 
        (div:DF (float_extend:DF
300 
                 (match_operand:SF 1 "s_register_operand" "f"))
301 
                (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
302 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
303 
  "dvf%?d\\t%0, %1, %2"
304 
  [(set_attr "type" "fdivd")
305 
   (set_attr "predicable" "yes")]
306 
)
307 
 
308 
(define_insn "*divdf_df_esfdf_fpa"
309 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
310 
        (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "fG")
311 
                (float_extend:DF
312 
                 (match_operand:SF 2 "s_register_operand" "f"))))]
313 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
314 
  "rdf%?d\\t%0, %2, %1"
315 
  [(set_attr "type" "fdivd")
316 
   (set_attr "predicable" "yes")]
317 
)
318 
 
319 
(define_insn "*divdf_esfdf_esfdf_fpa"
320 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
321 
        (div:DF (float_extend:DF
322 
                 (match_operand:SF 1 "s_register_operand" "f"))
323 
                (float_extend:DF
324 
                 (match_operand:SF 2 "s_register_operand" "f"))))]
325 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
326 
  "dvf%?d\\t%0, %1, %2"
327 
  [(set_attr "type" "fdivd")
328 
   (set_attr "predicable" "yes")]
329 
)
330 
 
331 
(define_insn "*modsf3_fpa"
332 
  [(set (match_operand:SF 0 "s_register_operand" "=f")
333 
        (mod:SF (match_operand:SF 1 "s_register_operand" "f")
334 
                (match_operand:SF 2 "arm_float_rhs_operand" "fG")))]
335 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
336 
  "rmf%?s\\t%0, %1, %2"
337 
  [(set_attr "type" "fdivs")
338 
   (set_attr "predicable" "yes")]
339 
)
340 
 
341 
(define_insn "*moddf3_fpa"
342 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
343 
        (mod:DF (match_operand:DF 1 "s_register_operand" "f")
344 
                (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
345 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
346 
  "rmf%?d\\t%0, %1, %2"
347 
  [(set_attr "type" "fdivd")
348 
   (set_attr "predicable" "yes")]
349 
)
350 
 
351 
(define_insn "*moddf_esfdf_df_fpa"
352 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
353 
        (mod:DF (float_extend:DF
354 
                 (match_operand:SF 1 "s_register_operand" "f"))
355 
                (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
356 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
357 
  "rmf%?d\\t%0, %1, %2"
358 
  [(set_attr "type" "fdivd")
359 
   (set_attr "predicable" "yes")]
360 
)
361 
 
362 
(define_insn "*moddf_df_esfdf_fpa"
363 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
364 
        (mod:DF (match_operand:DF 1 "s_register_operand" "f")
365 
                (float_extend:DF
366 
                 (match_operand:SF 2 "s_register_operand" "f"))))]
367 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
368 
  "rmf%?d\\t%0, %1, %2"
369 
  [(set_attr "type" "fdivd")
370 
   (set_attr "predicable" "yes")]
371 
)
372 
 
373 
(define_insn "*moddf_esfdf_esfdf_fpa"
374 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
375 
        (mod:DF (float_extend:DF
376 
                 (match_operand:SF 1 "s_register_operand" "f"))
377 
                (float_extend:DF
378 
                 (match_operand:SF 2 "s_register_operand" "f"))))]
379 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
380 
  "rmf%?d\\t%0, %1, %2"
381 
  [(set_attr "type" "fdivd")
382 
   (set_attr "predicable" "yes")]
383 
)
384 
 
385 
(define_insn "*negsf2_fpa"
386 
  [(set (match_operand:SF         0 "s_register_operand" "=f")
387 
        (neg:SF (match_operand:SF 1 "s_register_operand" "f")))]
388 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
389 
  "mnf%?s\\t%0, %1"
390 
  [(set_attr "type" "ffarith")
391 
   (set_attr "predicable" "yes")]
392 
)
393 
 
394 
(define_insn "*negdf2_fpa"
395 
  [(set (match_operand:DF         0 "s_register_operand" "=f")
396 
        (neg:DF (match_operand:DF 1 "s_register_operand" "f")))]
397 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
398 
  "mnf%?d\\t%0, %1"
399 
  [(set_attr "type" "ffarith")
400 
   (set_attr "predicable" "yes")]
401 
)
402 
 
403 
(define_insn "*negdf_esfdf_fpa"
404 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
405 
        (neg:DF (float_extend:DF
406 
                 (match_operand:SF 1 "s_register_operand" "f"))))]
407 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
408 
  "mnf%?d\\t%0, %1"
409 
  [(set_attr "type" "ffarith")
410 
   (set_attr "predicable" "yes")]
411 
)
412 
 
413 
(define_insn "*abssf2_fpa"
414 
  [(set (match_operand:SF          0 "s_register_operand" "=f")
415 
         (abs:SF (match_operand:SF 1 "s_register_operand" "f")))]
416 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
417 
  "abs%?s\\t%0, %1"
418 
  [(set_attr "type" "ffarith")
419 
   (set_attr "predicable" "yes")]
420 
)
421 
 
422 
(define_insn "*absdf2_fpa"
423 
  [(set (match_operand:DF         0 "s_register_operand" "=f")
424 
        (abs:DF (match_operand:DF 1 "s_register_operand" "f")))]
425 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
426 
  "abs%?d\\t%0, %1"
427 
  [(set_attr "type" "ffarith")
428 
   (set_attr "predicable" "yes")]
429 
)
430 
 
431 
(define_insn "*absdf_esfdf_fpa"
432 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
433 
        (abs:DF (float_extend:DF
434 
                 (match_operand:SF 1 "s_register_operand" "f"))))]
435 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
436 
  "abs%?d\\t%0, %1"
437 
  [(set_attr "type" "ffarith")
438 
   (set_attr "predicable" "yes")]
439 
)
440 
 
441 
(define_insn "*sqrtsf2_fpa"
442 
  [(set (match_operand:SF 0 "s_register_operand" "=f")
443 
        (sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))]
444 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
445 
  "sqt%?s\\t%0, %1"
446 
  [(set_attr "type" "float_em")
447 
   (set_attr "predicable" "yes")]
448 
)
449 
 
450 
(define_insn "*sqrtdf2_fpa"
451 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
452 
        (sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))]
453 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
454 
  "sqt%?d\\t%0, %1"
455 
  [(set_attr "type" "float_em")
456 
   (set_attr "predicable" "yes")]
457 
)
458 
 
459 
(define_insn "*sqrtdf_esfdf_fpa"
460 
  [(set (match_operand:DF 0 "s_register_operand" "=f")
461 
        (sqrt:DF (float_extend:DF
462 
                  (match_operand:SF 1 "s_register_operand" "f"))))]
463 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
464 
  "sqt%?d\\t%0, %1"
465 
  [(set_attr "type" "float_em")
466 
   (set_attr "predicable" "yes")]
467 
)
468 
 
469 
(define_insn "*floatsisf2_fpa"
470 
  [(set (match_operand:SF           0 "s_register_operand" "=f")
471 
        (float:SF (match_operand:SI 1 "s_register_operand" "r")))]
472 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
473 
  "flt%?s\\t%0, %1"
474 
  [(set_attr "type" "r_2_f")
475 
   (set_attr "predicable" "yes")]
476 
)
477 
 
478 
(define_insn "*floatsidf2_fpa"
479 
  [(set (match_operand:DF           0 "s_register_operand" "=f")
480 
        (float:DF (match_operand:SI 1 "s_register_operand" "r")))]
481 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
482 
  "flt%?d\\t%0, %1"
483 
  [(set_attr "type" "r_2_f")
484 
   (set_attr "predicable" "yes")]
485 
)
486 
 
487 
(define_insn "*fix_truncsfsi2_fpa"
488 
  [(set (match_operand:SI         0 "s_register_operand" "=r")
489 
        (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "f"))))]
490 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
491 
  "fix%?z\\t%0, %1"
492 
  [(set_attr "type" "f_2_r")
493 
   (set_attr "predicable" "yes")]
494 
)
495 
 
496 
(define_insn "*fix_truncdfsi2_fpa"
497 
  [(set (match_operand:SI         0 "s_register_operand" "=r")
498 
        (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "f"))))]
499 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
500 
  "fix%?z\\t%0, %1"
501 
  [(set_attr "type" "f_2_r")
502 
   (set_attr "predicable" "yes")]
503 
)
504 
 
505 
(define_insn "*truncdfsf2_fpa"
506 
  [(set (match_operand:SF 0 "s_register_operand" "=f")
507 
        (float_truncate:SF
508 
         (match_operand:DF 1 "s_register_operand" "f")))]
509 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
510 
  "mvf%?s\\t%0, %1"
511 
  [(set_attr "type" "ffarith")
512 
   (set_attr "predicable" "yes")]
513 
)
514 
 
515 
(define_insn "*extendsfdf2_fpa"
516 
  [(set (match_operand:DF                  0 "s_register_operand" "=f")
517 
        (float_extend:DF (match_operand:SF 1 "s_register_operand"  "f")))]
518 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
519 
  "mvf%?d\\t%0, %1"
520 
  [(set_attr "type" "ffarith")
521 
   (set_attr "predicable" "yes")]
522 
)
523 
 
524 
(define_insn "*movsf_fpa"
525 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m")
526 
        (match_operand:SF 1 "general_operand"      "fG,H,mE,f,r,f,r,mE,r"))]
527 
  "TARGET_ARM
528 
   && TARGET_HARD_FLOAT && TARGET_FPA
529 
   && (GET_CODE (operands[0]) != MEM
530 
       || register_operand (operands[1], SFmode))"
531 
  "@
532 
   mvf%?s\\t%0, %1
533 
   mnf%?s\\t%0, #%N1
534 
   ldf%?s\\t%0, %1
535 
   stf%?s\\t%1, %0
536 
   str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4
537 
   stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4
538 
   mov%?\\t%0, %1
539 
   ldr%?\\t%0, %1\\t%@ float
540 
   str%?\\t%1, %0\\t%@ float"
541 
  [(set_attr "length" "4,4,4,4,8,8,4,4,4")
542 
   (set_attr "predicable" "yes")
543 
   (set_attr "type"
544 
         "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load1,store1")
545 
   (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
546 
   (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")]
547 
)
548 
 
549 
(define_insn "*movdf_fpa"
550 
  [(set (match_operand:DF 0 "nonimmediate_operand"
551 
                                                "=r,Q,r,m,r, f, f,f, m,!f,!r")
552 
        (match_operand:DF 1 "general_operand"
553 
                                                "Q, r,r,r,mF,fG,H,mF,f,r, f"))]
554 
  "TARGET_ARM
555 
   && TARGET_HARD_FLOAT && TARGET_FPA
556 
   && (GET_CODE (operands[0]) != MEM
557 
       || register_operand (operands[1], DFmode))"
558 
  "*
559 
  {
560 
  switch (which_alternative)
561 
    {
562 
    default:
563 
    case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
564 
    case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
565 
    case 2: return \"#\";
566 
    case 3: case 4: return output_move_double (operands);
567 
    case 5: return \"mvf%?d\\t%0, %1\";
568 
    case 6: return \"mnf%?d\\t%0, #%N1\";
569 
    case 7: return \"ldf%?d\\t%0, %1\";
570 
    case 8: return \"stf%?d\\t%1, %0\";
571 
    case 9: return output_mov_double_fpa_from_arm (operands);
572 
    case 10: return output_mov_double_arm_from_fpa (operands);
573 
    }
574 
  }
575 
  "
576 
  [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
577 
   (set_attr "predicable" "yes")
578 
   (set_attr "type"
579 
    "load1,store2,*,store2,load1,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r")
580 
   (set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*")
581 
   (set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")]
582 
)
583 
 
584 
;; We treat XFmode as meaning 'internal format'.  It's the right size and we
585 
;; don't use it for anything else.  We only support moving between FPA
586 
;; registers and moving an FPA register to/from memory.
587 
(define_insn "*movxf_fpa"
588 
  [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,m")
589 
        (match_operand:XF 1 "general_operand" "f,m,f"))]
590 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA
591 
   && (register_operand (operands[0], XFmode)
592 
       || register_operand (operands[1], XFmode))"
593 
  "*
594 
  switch (which_alternative)
595 
    {
596 
    default:
597 
    case 0: return \"mvf%?e\\t%0, %1\";
598 
    case 1: if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
599 
              return \"ldf%?e\\t%0, %1\";
600 
            return \"lfm%?\\t%0, 1, %1\";
601 
    case 2: if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
602 
              return \"stf%?e\\t%1, %0\";
603 
            return \"sfm%?\\t%1, 1, %0\";
604 
    }
605 
  "
606 
  [(set_attr "length" "4,4,4")
607 
   (set_attr "predicable" "yes")
608 
   (set_attr "type" "ffarith,f_load,f_store")]
609 
)
610 
 
611 
(define_insn "*cmpsf_fpa"
612 
  [(set (reg:CCFP CC_REGNUM)
613 
        (compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
614 
                      (match_operand:SF 1 "arm_float_add_operand" "fG,H")))]
615 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
616 
  "@
617 
   cmf%?\\t%0, %1
618 
   cnf%?\\t%0, #%N1"
619 
  [(set_attr "conds" "set")
620 
   (set_attr "type" "f_2_r")]
621 
)
622 
 
623 
(define_insn "*cmpdf_fpa"
624 
  [(set (reg:CCFP CC_REGNUM)
625 
        (compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
626 
                      (match_operand:DF 1 "arm_float_add_operand" "fG,H")))]
627 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
628 
  "@
629 
   cmf%?\\t%0, %1
630 
   cnf%?\\t%0, #%N1"
631 
  [(set_attr "conds" "set")
632 
   (set_attr "type" "f_2_r")]
633 
)
634 
 
635 
(define_insn "*cmpesfdf_df_fpa"
636 
  [(set (reg:CCFP CC_REGNUM)
637 
        (compare:CCFP (float_extend:DF
638 
                       (match_operand:SF 0 "s_register_operand" "f,f"))
639 
                      (match_operand:DF 1 "arm_float_add_operand" "fG,H")))]
640 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
641 
  "@
642 
   cmf%?\\t%0, %1
643 
   cnf%?\\t%0, #%N1"
644 
  [(set_attr "conds" "set")
645 
   (set_attr "type" "f_2_r")]
646 
)
647 
 
648 
(define_insn "*cmpdf_esfdf_fpa"
649 
  [(set (reg:CCFP CC_REGNUM)
650 
        (compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
651 
                      (float_extend:DF
652 
                       (match_operand:SF 1 "s_register_operand" "f"))))]
653 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
654 
  "cmf%?\\t%0, %1"
655 
  [(set_attr "conds" "set")
656 
   (set_attr "type" "f_2_r")]
657 
)
658 
 
659 
(define_insn "*cmpsf_trap_fpa"
660 
  [(set (reg:CCFPE CC_REGNUM)
661 
        (compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
662 
                       (match_operand:SF 1 "arm_float_add_operand" "fG,H")))]
663 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
664 
  "@
665 
   cmf%?e\\t%0, %1
666 
   cnf%?e\\t%0, #%N1"
667 
  [(set_attr "conds" "set")
668 
   (set_attr "type" "f_2_r")]
669 
)
670 
 
671 
(define_insn "*cmpdf_trap_fpa"
672 
  [(set (reg:CCFPE CC_REGNUM)
673 
        (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
674 
                       (match_operand:DF 1 "arm_float_add_operand" "fG,H")))]
675 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
676 
  "@
677 
   cmf%?e\\t%0, %1
678 
   cnf%?e\\t%0, #%N1"
679 
  [(set_attr "conds" "set")
680 
   (set_attr "type" "f_2_r")]
681 
)
682 
 
683 
(define_insn "*cmp_esfdf_df_trap_fpa"
684 
  [(set (reg:CCFPE CC_REGNUM)
685 
        (compare:CCFPE (float_extend:DF
686 
                        (match_operand:SF 0 "s_register_operand" "f,f"))
687 
                       (match_operand:DF 1 "arm_float_add_operand" "fG,H")))]
688 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
689 
  "@
690 
   cmf%?e\\t%0, %1
691 
   cnf%?e\\t%0, #%N1"
692 
  [(set_attr "conds" "set")
693 
   (set_attr "type" "f_2_r")]
694 
)
695 
 
696 
(define_insn "*cmp_df_esfdf_trap_fpa"
697 
  [(set (reg:CCFPE CC_REGNUM)
698 
        (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
699 
                       (float_extend:DF
700 
                        (match_operand:SF 1 "s_register_operand" "f"))))]
701 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
702 
  "cmf%?e\\t%0, %1"
703 
  [(set_attr "conds" "set")
704 
   (set_attr "type" "f_2_r")]
705 
)
706 
 
707 
(define_insn "*movsfcc_fpa"
708 
  [(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
709 
        (if_then_else:SF
710 
         (match_operator 3 "arm_comparison_operator"
711 
          [(match_operand 4 "cc_register" "") (const_int 0)])
712 
         (match_operand:SF 1 "arm_float_add_operand" "0,0,fG,H,fG,fG,H,H")
713 
         (match_operand:SF 2 "arm_float_add_operand" "fG,H,0,0,fG,H,fG,H")))]
714 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
715 
  "@
716 
   mvf%D3s\\t%0, %2
717 
   mnf%D3s\\t%0, #%N2
718 
   mvf%d3s\\t%0, %1
719 
   mnf%d3s\\t%0, #%N1
720 
   mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2
721 
   mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2
722 
   mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2
723 
   mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2"
724 
  [(set_attr "length" "4,4,4,4,8,8,8,8")
725 
   (set_attr "type" "ffarith")
726 
   (set_attr "conds" "use")]
727 
)
728 
 
729 
(define_insn "*movdfcc_fpa"
730 
  [(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
731 
        (if_then_else:DF
732 
         (match_operator 3 "arm_comparison_operator"
733 
          [(match_operand 4 "cc_register" "") (const_int 0)])
734 
         (match_operand:DF 1 "arm_float_add_operand" "0,0,fG,H,fG,fG,H,H")
735 
         (match_operand:DF 2 "arm_float_add_operand" "fG,H,0,0,fG,H,fG,H")))]
736 
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
737 
  "@
738 
   mvf%D3d\\t%0, %2
739 
   mnf%D3d\\t%0, #%N2
740 
   mvf%d3d\\t%0, %1
741 
   mnf%d3d\\t%0, #%N1
742 
   mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2
743 
   mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2
744 
   mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2
745 
   mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2"
746 
  [(set_attr "length" "4,4,4,4,8,8,8,8")
747 
   (set_attr "type" "ffarith")
748 
   (set_attr "conds" "use")]
749 
)

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