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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [arm/] [iwmmxt.md] - Blame information for rev 827

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1 38 julius 
;; Patterns for the Intel Wireless MMX technology architecture.
2 
;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
3 
;; Contributed by Red Hat.
4 
 
5 
;; This file is part of GCC.
6 
 
7 
;; GCC is free software; you can redistribute it and/or modify it under
8 
;; the terms of the GNU General Public License as published by the Free
9 
;; Software Foundation; either version 3, or (at your option) any later
10 
;; version.
11 
 
12 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15 
;; License for more details.
16 
 
17 
;; You should have received a copy of the GNU General Public License
18 
;; along with GCC; see the file COPYING3.  If not see
19 
;; .
20 
 
21 
(define_insn "iwmmxt_iordi3"
22 
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
23 
        (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
24 
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
25 
  "TARGET_REALLY_IWMMXT"
26 
  "@
27 
   wor%?\\t%0, %1, %2
28 
   #
29 
   #"
30 
  [(set_attr "predicable" "yes")
31 
   (set_attr "length" "4,8,8")])
32 
 
33 
(define_insn "iwmmxt_xordi3"
34 
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
35 
        (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
36 
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
37 
  "TARGET_REALLY_IWMMXT"
38 
  "@
39 
   wxor%?\\t%0, %1, %2
40 
   #
41 
   #"
42 
  [(set_attr "predicable" "yes")
43 
   (set_attr "length" "4,8,8")])
44 
 
45 
(define_insn "iwmmxt_anddi3"
46 
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
47 
        (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
48 
                (match_operand:DI 2 "register_operand"  "y,r,r")))]
49 
  "TARGET_REALLY_IWMMXT"
50 
  "@
51 
   wand%?\\t%0, %1, %2
52 
   #
53 
   #"
54 
  [(set_attr "predicable" "yes")
55 
   (set_attr "length" "4,8,8")])
56 
 
57 
(define_insn "iwmmxt_nanddi3"
58 
  [(set (match_operand:DI                 0 "register_operand" "=y")
59 
        (and:DI (match_operand:DI         1 "register_operand"  "y")
60 
                (not:DI (match_operand:DI 2 "register_operand"  "y"))))]
61 
  "TARGET_REALLY_IWMMXT"
62 
  "wandn%?\\t%0, %1, %2"
63 
  [(set_attr "predicable" "yes")])
64 
 
65 
(define_insn "*iwmmxt_arm_movdi"
66 
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
67 
        (match_operand:DI 1 "di_operand"              "rIK,mi,r,y,yr,y,yrUy,y"))]
68 
  "TARGET_REALLY_IWMMXT
69 
   && (   register_operand (operands[0], DImode)
70 
       || register_operand (operands[1], DImode))"
71 
  "*
72 
{
73 
  switch (which_alternative)
74 
    {
75 
    default:
76 
      return output_move_double (operands);
77 
    case 0:
78 
      return \"#\";
79 
    case 3:
80 
      return \"wmov%?\\t%0,%1\";
81 
    case 4:
82 
      return \"tmcrr%?\\t%0,%Q1,%R1\";
83 
    case 5:
84 
      return \"tmrrc%?\\t%Q0,%R0,%1\";
85 
    case 6:
86 
      return \"wldrd%?\\t%0,%1\";
87 
    case 7:
88 
      return \"wstrd%?\\t%1,%0\";
89 
    }
90 
}"
91 
  [(set_attr "length"         "8,8,8,4,4,4,4,4")
92 
   (set_attr "type"           "*,load1,store2,*,*,*,*,*")
93 
   (set_attr "pool_range"     "*,1020,*,*,*,*,*,*")
94 
   (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
95 
)
96 
 
97 
(define_insn "*iwmmxt_movsi_insn"
98 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z")
99 
        (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z,Uy,z,z"))]
100 
  "TARGET_REALLY_IWMMXT
101 
   && (   register_operand (operands[0], SImode)
102 
       || register_operand (operands[1], SImode))"
103 
  "*
104 
   switch (which_alternative)
105 
   {
106 
   case 0: return \"mov\\t%0, %1\";
107 
   case 1: return \"mvn\\t%0, #%B1\";
108 
   case 2: return \"ldr\\t%0, %1\";
109 
   case 3: return \"str\\t%1, %0\";
110 
   case 4: return \"tmcr\\t%0, %1\";
111 
   case 5: return \"tmrc\\t%0, %1\";
112 
   case 6: return arm_output_load_gr (operands);
113 
   case 7: return \"wstrw\\t%1, %0\";
114 
   default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
115 
  }"
116 
  [(set_attr "type"           "*,*,load1,store1,*,*,load1,store1,*")
117 
   (set_attr "length"         "*,*,*,        *,*,*,  16,     *,8")
118 
   (set_attr "pool_range"     "*,*,4096,     *,*,*,1024,     *,*")
119 
   (set_attr "neg_pool_range" "*,*,4084,     *,*,*,   *,  1012,*")
120 
   ;; Note - the "predicable" attribute is not allowed to have alternatives.
121 
   ;; Since the wSTRw wCx instruction is not predicable, we cannot support
122 
   ;; predicating any of the alternatives in this template.  Instead,
123 
   ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
124 
   (set_attr "predicable"     "no")
125 
   ;; Also - we have to pretend that these insns clobber the condition code
126 
   ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
127 
   ;; them.
128 
   (set_attr "conds" "clob")]
129 
)
130 
 
131 
;; Because iwmmxt_movsi_insn is not predicable, we provide the
132 
;; cond_exec version explicitly, with appropriate constraints.
133 
 
134 
(define_insn "*cond_iwmmxt_movsi_insn"
135 
  [(cond_exec
136 
     (match_operator 2 "arm_comparison_operator"
137 
      [(match_operand 3 "cc_register" "")
138 
      (const_int 0)])
139 
     (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
140 
          (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z")))]
141 
  "TARGET_REALLY_IWMMXT
142 
   && (   register_operand (operands[0], SImode)
143 
       || register_operand (operands[1], SImode))"
144 
  "*
145 
   switch (which_alternative)
146 
   {
147 
   case 0: return \"mov%?\\t%0, %1\";
148 
   case 1: return \"mvn%?\\t%0, #%B1\";
149 
   case 2: return \"ldr%?\\t%0, %1\";
150 
   case 3: return \"str%?\\t%1, %0\";
151 
   case 4: return \"tmcr%?\\t%0, %1\";
152 
   default: return \"tmrc%?\\t%0, %1\";
153 
  }"
154 
  [(set_attr "type"           "*,*,load1,store1,*,*")
155 
   (set_attr "pool_range"     "*,*,4096,     *,*,*")
156 
   (set_attr "neg_pool_range" "*,*,4084,     *,*,*")]
157 
)
158 
 
159 
(define_insn "movv8qi_internal"
160 
  [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
161 
        (match_operand:V8QI 1 "general_operand"       "y,y,mi,y,r,mi"))]
162 
  "TARGET_REALLY_IWMMXT"
163 
  "*
164 
   switch (which_alternative)
165 
   {
166 
   case 0: return \"wmov%?\\t%0, %1\";
167 
   case 1: return \"wstrd%?\\t%1, %0\";
168 
   case 2: return \"wldrd%?\\t%0, %1\";
169 
   case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
170 
   case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
171 
   default: return output_move_double (operands);
172 
   }"
173 
  [(set_attr "predicable" "yes")
174 
   (set_attr "length"         "4,     4,   4,4,4,   8")
175 
   (set_attr "type"           "*,store1,load1,*,*,load1")
176 
   (set_attr "pool_range"     "*,     *, 256,*,*, 256")
177 
   (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])
178 
 
179 
(define_insn "movv4hi_internal"
180 
  [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
181 
        (match_operand:V4HI 1 "general_operand"       "y,y,mi,y,r,mi"))]
182 
  "TARGET_REALLY_IWMMXT"
183 
  "*
184 
   switch (which_alternative)
185 
   {
186 
   case 0: return \"wmov%?\\t%0, %1\";
187 
   case 1: return \"wstrd%?\\t%1, %0\";
188 
   case 2: return \"wldrd%?\\t%0, %1\";
189 
   case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
190 
   case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
191 
   default: return output_move_double (operands);
192 
   }"
193 
  [(set_attr "predicable" "yes")
194 
   (set_attr "length"         "4,     4,   4,4,4,   8")
195 
   (set_attr "type"           "*,store1,load1,*,*,load1")
196 
   (set_attr "pool_range"     "*,     *, 256,*,*, 256")
197 
   (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])
198 
 
199 
(define_insn "movv2si_internal"
200 
  [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
201 
        (match_operand:V2SI 1 "general_operand"       "y,y,mi,y,r,mi"))]
202 
  "TARGET_REALLY_IWMMXT"
203 
  "*
204 
   switch (which_alternative)
205 
   {
206 
   case 0: return \"wmov%?\\t%0, %1\";
207 
   case 1: return \"wstrd%?\\t%1, %0\";
208 
   case 2: return \"wldrd%?\\t%0, %1\";
209 
   case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
210 
   case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
211 
   default: return output_move_double (operands);
212 
   }"
213 
  [(set_attr "predicable" "yes")
214 
   (set_attr "length"         "4,     4,   4,4,4,  24")
215 
   (set_attr "type"           "*,store1,load1,*,*,load1")
216 
   (set_attr "pool_range"     "*,     *, 256,*,*, 256")
217 
   (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])
218 
 
219 
;; This pattern should not be needed.  It is to match a
220 
;; wierd case generated by GCC when no optimizations are
221 
;; enabled.  (Try compiling gcc/testsuite/gcc.c-torture/
222 
;; compile/simd-5.c at -O0).  The mode for operands[1] is
223 
;; deliberately omitted.
224 
(define_insn "movv2si_internal_2"
225 
  [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r")
226 
        (match_operand      1 "immediate_operand"      "mi"))]
227 
  "TARGET_REALLY_IWMMXT"
228 
  "* return output_move_double (operands);"
229 
  [(set_attr "predicable"     "yes")
230 
   (set_attr "length"         "8")
231 
   (set_attr "type"           "load1")
232 
   (set_attr "pool_range"     "256")
233 
   (set_attr "neg_pool_range" "244")])
234 
 
235 
;; Vector add/subtract
236 
 
237 
(define_insn "addv8qi3"
238 
  [(set (match_operand:V8QI            0 "register_operand" "=y")
239 
        (plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
240 
                   (match_operand:V8QI 2 "register_operand"  "y")))]
241 
  "TARGET_REALLY_IWMMXT"
242 
  "waddb%?\\t%0, %1, %2"
243 
  [(set_attr "predicable" "yes")])
244 
 
245 
(define_insn "addv4hi3"
246 
  [(set (match_operand:V4HI            0 "register_operand" "=y")
247 
        (plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
248 
                   (match_operand:V4HI 2 "register_operand"  "y")))]
249 
  "TARGET_REALLY_IWMMXT"
250 
  "waddh%?\\t%0, %1, %2"
251 
  [(set_attr "predicable" "yes")])
252 
 
253 
(define_insn "addv2si3"
254 
  [(set (match_operand:V2SI            0 "register_operand" "=y")
255 
        (plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
256 
                   (match_operand:V2SI 2 "register_operand"  "y")))]
257 
  "TARGET_REALLY_IWMMXT"
258 
  "waddw%?\\t%0, %1, %2"
259 
  [(set_attr "predicable" "yes")])
260 
 
261 
(define_insn "ssaddv8qi3"
262 
  [(set (match_operand:V8QI               0 "register_operand" "=y")
263 
        (ss_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
264 
                      (match_operand:V8QI 2 "register_operand"  "y")))]
265 
  "TARGET_REALLY_IWMMXT"
266 
  "waddbss%?\\t%0, %1, %2"
267 
  [(set_attr "predicable" "yes")])
268 
 
269 
(define_insn "ssaddv4hi3"
270 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
271 
        (ss_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
272 
                      (match_operand:V4HI 2 "register_operand"  "y")))]
273 
  "TARGET_REALLY_IWMMXT"
274 
  "waddhss%?\\t%0, %1, %2"
275 
  [(set_attr "predicable" "yes")])
276 
 
277 
(define_insn "ssaddv2si3"
278 
  [(set (match_operand:V2SI               0 "register_operand" "=y")
279 
        (ss_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
280 
                      (match_operand:V2SI 2 "register_operand"  "y")))]
281 
  "TARGET_REALLY_IWMMXT"
282 
  "waddwss%?\\t%0, %1, %2"
283 
  [(set_attr "predicable" "yes")])
284 
 
285 
(define_insn "usaddv8qi3"
286 
  [(set (match_operand:V8QI               0 "register_operand" "=y")
287 
        (us_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
288 
                      (match_operand:V8QI 2 "register_operand"  "y")))]
289 
  "TARGET_REALLY_IWMMXT"
290 
  "waddbus%?\\t%0, %1, %2"
291 
  [(set_attr "predicable" "yes")])
292 
 
293 
(define_insn "usaddv4hi3"
294 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
295 
        (us_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
296 
                      (match_operand:V4HI 2 "register_operand"  "y")))]
297 
  "TARGET_REALLY_IWMMXT"
298 
  "waddhus%?\\t%0, %1, %2"
299 
  [(set_attr "predicable" "yes")])
300 
 
301 
(define_insn "usaddv2si3"
302 
  [(set (match_operand:V2SI               0 "register_operand" "=y")
303 
        (us_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
304 
                      (match_operand:V2SI 2 "register_operand"  "y")))]
305 
  "TARGET_REALLY_IWMMXT"
306 
  "waddwus%?\\t%0, %1, %2"
307 
  [(set_attr "predicable" "yes")])
308 
 
309 
(define_insn "subv8qi3"
310 
  [(set (match_operand:V8QI             0 "register_operand" "=y")
311 
        (minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
312 
                    (match_operand:V8QI 2 "register_operand"  "y")))]
313 
  "TARGET_REALLY_IWMMXT"
314 
  "wsubb%?\\t%0, %1, %2"
315 
  [(set_attr "predicable" "yes")])
316 
 
317 
(define_insn "subv4hi3"
318 
  [(set (match_operand:V4HI             0 "register_operand" "=y")
319 
        (minus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
320 
                    (match_operand:V4HI 2 "register_operand"  "y")))]
321 
  "TARGET_REALLY_IWMMXT"
322 
  "wsubh%?\\t%0, %1, %2"
323 
  [(set_attr "predicable" "yes")])
324 
 
325 
(define_insn "subv2si3"
326 
  [(set (match_operand:V2SI             0 "register_operand" "=y")
327 
        (minus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
328 
                    (match_operand:V2SI 2 "register_operand"  "y")))]
329 
  "TARGET_REALLY_IWMMXT"
330 
  "wsubw%?\\t%0, %1, %2"
331 
  [(set_attr "predicable" "yes")])
332 
 
333 
(define_insn "sssubv8qi3"
334 
  [(set (match_operand:V8QI                0 "register_operand" "=y")
335 
        (ss_minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
336 
                       (match_operand:V8QI 2 "register_operand"  "y")))]
337 
  "TARGET_REALLY_IWMMXT"
338 
  "wsubbss%?\\t%0, %1, %2"
339 
  [(set_attr "predicable" "yes")])
340 
 
341 
(define_insn "sssubv4hi3"
342 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
343 
        (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
344 
                       (match_operand:V4HI 2 "register_operand" "y")))]
345 
  "TARGET_REALLY_IWMMXT"
346 
  "wsubhss%?\\t%0, %1, %2"
347 
  [(set_attr "predicable" "yes")])
348 
 
349 
(define_insn "sssubv2si3"
350 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
351 
        (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
352 
                       (match_operand:V2SI 2 "register_operand" "y")))]
353 
  "TARGET_REALLY_IWMMXT"
354 
  "wsubwss%?\\t%0, %1, %2"
355 
  [(set_attr "predicable" "yes")])
356 
 
357 
(define_insn "ussubv8qi3"
358 
  [(set (match_operand:V8QI                0 "register_operand" "=y")
359 
        (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
360 
                       (match_operand:V8QI 2 "register_operand" "y")))]
361 
  "TARGET_REALLY_IWMMXT"
362 
  "wsubbus%?\\t%0, %1, %2"
363 
  [(set_attr "predicable" "yes")])
364 
 
365 
(define_insn "ussubv4hi3"
366 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
367 
        (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
368 
                       (match_operand:V4HI 2 "register_operand" "y")))]
369 
  "TARGET_REALLY_IWMMXT"
370 
  "wsubhus%?\\t%0, %1, %2"
371 
  [(set_attr "predicable" "yes")])
372 
 
373 
(define_insn "ussubv2si3"
374 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
375 
        (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
376 
                       (match_operand:V2SI 2 "register_operand" "y")))]
377 
  "TARGET_REALLY_IWMMXT"
378 
  "wsubwus%?\\t%0, %1, %2"
379 
  [(set_attr "predicable" "yes")])
380 
 
381 
(define_insn "mulv4hi3"
382 
  [(set (match_operand:V4HI            0 "register_operand" "=y")
383 
        (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
384 
                   (match_operand:V4HI 2 "register_operand" "y")))]
385 
  "TARGET_REALLY_IWMMXT"
386 
  "wmulul%?\\t%0, %1, %2"
387 
  [(set_attr "predicable" "yes")])
388 
 
389 
(define_insn "smulv4hi3_highpart"
390 
  [(set (match_operand:V4HI                                0 "register_operand" "=y")
391 
        (truncate:V4HI
392 
         (lshiftrt:V4SI
393 
          (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
394 
                     (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
395 
          (const_int 16))))]
396 
  "TARGET_REALLY_IWMMXT"
397 
  "wmulsm%?\\t%0, %1, %2"
398 
  [(set_attr "predicable" "yes")])
399 
 
400 
(define_insn "umulv4hi3_highpart"
401 
  [(set (match_operand:V4HI                                0 "register_operand" "=y")
402 
        (truncate:V4HI
403 
         (lshiftrt:V4SI
404 
          (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
405 
                     (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
406 
          (const_int 16))))]
407 
  "TARGET_REALLY_IWMMXT"
408 
  "wmulum%?\\t%0, %1, %2"
409 
  [(set_attr "predicable" "yes")])
410 
 
411 
(define_insn "iwmmxt_wmacs"
412 
  [(set (match_operand:DI               0 "register_operand" "=y")
413 
        (unspec:DI [(match_operand:DI   1 "register_operand" "0")
414 
                    (match_operand:V4HI 2 "register_operand" "y")
415 
                    (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
416 
  "TARGET_REALLY_IWMMXT"
417 
  "wmacs%?\\t%0, %2, %3"
418 
  [(set_attr "predicable" "yes")])
419 
 
420 
(define_insn "iwmmxt_wmacsz"
421 
  [(set (match_operand:DI               0 "register_operand" "=y")
422 
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
423 
                    (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
424 
  "TARGET_REALLY_IWMMXT"
425 
  "wmacsz%?\\t%0, %1, %2"
426 
  [(set_attr "predicable" "yes")])
427 
 
428 
(define_insn "iwmmxt_wmacu"
429 
  [(set (match_operand:DI               0 "register_operand" "=y")
430 
        (unspec:DI [(match_operand:DI   1 "register_operand" "0")
431 
                    (match_operand:V4HI 2 "register_operand" "y")
432 
                    (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
433 
  "TARGET_REALLY_IWMMXT"
434 
  "wmacu%?\\t%0, %2, %3"
435 
  [(set_attr "predicable" "yes")])
436 
 
437 
(define_insn "iwmmxt_wmacuz"
438 
  [(set (match_operand:DI               0 "register_operand" "=y")
439 
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
440 
                    (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
441 
  "TARGET_REALLY_IWMMXT"
442 
  "wmacuz%?\\t%0, %1, %2"
443 
  [(set_attr "predicable" "yes")])
444 
 
445 
;; Same as xordi3, but don't show input operands so that we don't think
446 
;; they are live.
447 
(define_insn "iwmmxt_clrdi"
448 
  [(set (match_operand:DI 0 "register_operand" "=y")
449 
        (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
450 
  "TARGET_REALLY_IWMMXT"
451 
  "wxor%?\\t%0, %0, %0"
452 
  [(set_attr "predicable" "yes")])
453 
 
454 
;; Seems like cse likes to generate these, so we have to support them.
455 
 
456 
(define_insn "*iwmmxt_clrv8qi"
457 
  [(set (match_operand:V8QI 0 "register_operand" "=y")
458 
        (const_vector:V8QI [(const_int 0) (const_int 0)
459 
                            (const_int 0) (const_int 0)
460 
                            (const_int 0) (const_int 0)
461 
                            (const_int 0) (const_int 0)]))]
462 
  "TARGET_REALLY_IWMMXT"
463 
  "wxor%?\\t%0, %0, %0"
464 
  [(set_attr "predicable" "yes")])
465 
 
466 
(define_insn "*iwmmxt_clrv4hi"
467 
  [(set (match_operand:V4HI 0 "register_operand" "=y")
468 
        (const_vector:V4HI [(const_int 0) (const_int 0)
469 
                            (const_int 0) (const_int 0)]))]
470 
  "TARGET_REALLY_IWMMXT"
471 
  "wxor%?\\t%0, %0, %0"
472 
  [(set_attr "predicable" "yes")])
473 
 
474 
(define_insn "*iwmmxt_clrv2si"
475 
  [(set (match_operand:V2SI 0 "register_operand" "=y")
476 
        (const_vector:V2SI [(const_int 0) (const_int 0)]))]
477 
  "TARGET_REALLY_IWMMXT"
478 
  "wxor%?\\t%0, %0, %0"
479 
  [(set_attr "predicable" "yes")])
480 
 
481 
;; Unsigned averages/sum of absolute differences
482 
 
483 
(define_insn "iwmmxt_uavgrndv8qi3"
484 
  [(set (match_operand:V8QI              0 "register_operand" "=y")
485 
        (ashiftrt:V8QI
486 
         (plus:V8QI (plus:V8QI
487 
                     (match_operand:V8QI 1 "register_operand" "y")
488 
                     (match_operand:V8QI 2 "register_operand" "y"))
489 
                    (const_vector:V8QI [(const_int 1)
490 
                                        (const_int 1)
491 
                                        (const_int 1)
492 
                                        (const_int 1)
493 
                                        (const_int 1)
494 
                                        (const_int 1)
495 
                                        (const_int 1)
496 
                                        (const_int 1)]))
497 
         (const_int 1)))]
498 
  "TARGET_REALLY_IWMMXT"
499 
  "wavg2br%?\\t%0, %1, %2"
500 
  [(set_attr "predicable" "yes")])
501 
 
502 
(define_insn "iwmmxt_uavgrndv4hi3"
503 
  [(set (match_operand:V4HI              0 "register_operand" "=y")
504 
        (ashiftrt:V4HI
505 
         (plus:V4HI (plus:V4HI
506 
                     (match_operand:V4HI 1 "register_operand" "y")
507 
                     (match_operand:V4HI 2 "register_operand" "y"))
508 
                    (const_vector:V4HI [(const_int 1)
509 
                                        (const_int 1)
510 
                                        (const_int 1)
511 
                                        (const_int 1)]))
512 
         (const_int 1)))]
513 
  "TARGET_REALLY_IWMMXT"
514 
  "wavg2hr%?\\t%0, %1, %2"
515 
  [(set_attr "predicable" "yes")])
516 
 
517 
 
518 
(define_insn "iwmmxt_uavgv8qi3"
519 
  [(set (match_operand:V8QI                 0 "register_operand" "=y")
520 
        (ashiftrt:V8QI (plus:V8QI
521 
                        (match_operand:V8QI 1 "register_operand" "y")
522 
                        (match_operand:V8QI 2 "register_operand" "y"))
523 
                       (const_int 1)))]
524 
  "TARGET_REALLY_IWMMXT"
525 
  "wavg2b%?\\t%0, %1, %2"
526 
  [(set_attr "predicable" "yes")])
527 
 
528 
(define_insn "iwmmxt_uavgv4hi3"
529 
  [(set (match_operand:V4HI                 0 "register_operand" "=y")
530 
        (ashiftrt:V4HI (plus:V4HI
531 
                        (match_operand:V4HI 1 "register_operand" "y")
532 
                        (match_operand:V4HI 2 "register_operand" "y"))
533 
                       (const_int 1)))]
534 
  "TARGET_REALLY_IWMMXT"
535 
  "wavg2h%?\\t%0, %1, %2"
536 
  [(set_attr "predicable" "yes")])
537 
 
538 
(define_insn "iwmmxt_psadbw"
539 
  [(set (match_operand:V8QI                       0 "register_operand" "=y")
540 
        (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
541 
                              (match_operand:V8QI 2 "register_operand" "y"))))]
542 
  "TARGET_REALLY_IWMMXT"
543 
  "psadbw%?\\t%0, %1, %2"
544 
  [(set_attr "predicable" "yes")])
545 
 
546 
 
547 
;; Insert/extract/shuffle
548 
 
549 
(define_insn "iwmmxt_tinsrb"
550 
  [(set (match_operand:V8QI                             0 "register_operand"    "=y")
551 
        (vec_merge:V8QI (match_operand:V8QI             1 "register_operand"     "0")
552 
                        (vec_duplicate:V8QI
553 
                         (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
554 
                        (match_operand:SI               3 "immediate_operand"    "i")))]
555 
  "TARGET_REALLY_IWMMXT"
556 
  "tinsrb%?\\t%0, %2, %3"
557 
  [(set_attr "predicable" "yes")])
558 
 
559 
(define_insn "iwmmxt_tinsrh"
560 
  [(set (match_operand:V4HI                             0 "register_operand"    "=y")
561 
        (vec_merge:V4HI (match_operand:V4HI             1 "register_operand"     "0")
562 
                        (vec_duplicate:V4HI
563 
                         (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
564 
                        (match_operand:SI               3 "immediate_operand"    "i")))]
565 
  "TARGET_REALLY_IWMMXT"
566 
  "tinsrh%?\\t%0, %2, %3"
567 
  [(set_attr "predicable" "yes")])
568 
 
569 
(define_insn "iwmmxt_tinsrw"
570 
  [(set (match_operand:V2SI                 0 "register_operand"    "=y")
571 
        (vec_merge:V2SI (match_operand:V2SI 1 "register_operand"     "0")
572 
                        (vec_duplicate:V2SI
573 
                         (match_operand:SI  2 "nonimmediate_operand" "r"))
574 
                        (match_operand:SI   3 "immediate_operand"    "i")))]
575 
  "TARGET_REALLY_IWMMXT"
576 
  "tinsrw%?\\t%0, %2, %3"
577 
  [(set_attr "predicable" "yes")])
578 
 
579 
(define_insn "iwmmxt_textrmub"
580 
  [(set (match_operand:SI                                  0 "register_operand" "=r")
581 
        (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
582 
                                       (parallel
583 
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
584 
  "TARGET_REALLY_IWMMXT"
585 
  "textrmub%?\\t%0, %1, %2"
586 
  [(set_attr "predicable" "yes")])
587 
 
588 
(define_insn "iwmmxt_textrmsb"
589 
  [(set (match_operand:SI                                  0 "register_operand" "=r")
590 
        (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
591 
                                       (parallel
592 
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
593 
  "TARGET_REALLY_IWMMXT"
594 
  "textrmsb%?\\t%0, %1, %2"
595 
  [(set_attr "predicable" "yes")])
596 
 
597 
(define_insn "iwmmxt_textrmuh"
598 
  [(set (match_operand:SI                                  0 "register_operand" "=r")
599 
        (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
600 
                                       (parallel
601 
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
602 
  "TARGET_REALLY_IWMMXT"
603 
  "textrmuh%?\\t%0, %1, %2"
604 
  [(set_attr "predicable" "yes")])
605 
 
606 
(define_insn "iwmmxt_textrmsh"
607 
  [(set (match_operand:SI                                  0 "register_operand" "=r")
608 
        (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
609 
                                       (parallel
610 
                                        [(match_operand:SI 2 "immediate_operand" "i")]))))]
611 
  "TARGET_REALLY_IWMMXT"
612 
  "textrmsh%?\\t%0, %1, %2"
613 
  [(set_attr "predicable" "yes")])
614 
 
615 
;; There are signed/unsigned variants of this instruction, but they are
616 
;; pointless.
617 
(define_insn "iwmmxt_textrmw"
618 
  [(set (match_operand:SI                           0 "register_operand" "=r")
619 
        (vec_select:SI (match_operand:V2SI          1 "register_operand" "y")
620 
                       (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
621 
  "TARGET_REALLY_IWMMXT"
622 
  "textrmsw%?\\t%0, %1, %2"
623 
  [(set_attr "predicable" "yes")])
624 
 
625 
(define_insn "iwmmxt_wshufh"
626 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
627 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
628 
                      (match_operand:SI   2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
629 
  "TARGET_REALLY_IWMMXT"
630 
  "wshufh%?\\t%0, %1, %2"
631 
  [(set_attr "predicable" "yes")])
632 
 
633 
;; Mask-generating comparisons
634 
;;
635 
;; Note - you cannot use patterns like these here:
636 
;;
637 
;;   (set: (match:) (: (match:) (match:)))
638 
;;
639 
;; Because GCC will assume that the truth value (1 or 0) is installed
640 
;; into the entire destination vector, (with the '1' going into the least
641 
;; significant element of the vector).  This is not how these instructions
642 
;; behave.
643 
;;
644 
;; Unfortunately the current patterns are illegal.  They are SET insns
645 
;; without a SET in them.  They work in most cases for ordinary code
646 
;; generation, but there are circumstances where they can cause gcc to fail.
647 
;; XXX - FIXME.
648 
 
649 
(define_insn "eqv8qi3"
650 
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
651 
                     (match_operand:V8QI 1 "register_operand"  "y")
652 
                     (match_operand:V8QI 2 "register_operand"  "y")]
653 
                    VUNSPEC_WCMP_EQ)]
654 
  "TARGET_REALLY_IWMMXT"
655 
  "wcmpeqb%?\\t%0, %1, %2"
656 
  [(set_attr "predicable" "yes")])
657 
 
658 
(define_insn "eqv4hi3"
659 
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
660 
                     (match_operand:V4HI 1 "register_operand"  "y")
661 
                     (match_operand:V4HI 2 "register_operand"  "y")]
662 
                    VUNSPEC_WCMP_EQ)]
663 
  "TARGET_REALLY_IWMMXT"
664 
  "wcmpeqh%?\\t%0, %1, %2"
665 
  [(set_attr "predicable" "yes")])
666 
 
667 
(define_insn "eqv2si3"
668 
  [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
669 
                          (match_operand:V2SI 1 "register_operand"  "y")
670 
                          (match_operand:V2SI 2 "register_operand"  "y")]
671 
                         VUNSPEC_WCMP_EQ)]
672 
  "TARGET_REALLY_IWMMXT"
673 
  "wcmpeqw%?\\t%0, %1, %2"
674 
  [(set_attr "predicable" "yes")])
675 
 
676 
(define_insn "gtuv8qi3"
677 
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
678 
                     (match_operand:V8QI 1 "register_operand"  "y")
679 
                     (match_operand:V8QI 2 "register_operand"  "y")]
680 
                    VUNSPEC_WCMP_GTU)]
681 
  "TARGET_REALLY_IWMMXT"
682 
  "wcmpgtub%?\\t%0, %1, %2"
683 
  [(set_attr "predicable" "yes")])
684 
 
685 
(define_insn "gtuv4hi3"
686 
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
687 
                     (match_operand:V4HI 1 "register_operand"  "y")
688 
                     (match_operand:V4HI 2 "register_operand"  "y")]
689 
                    VUNSPEC_WCMP_GTU)]
690 
  "TARGET_REALLY_IWMMXT"
691 
  "wcmpgtuh%?\\t%0, %1, %2"
692 
  [(set_attr "predicable" "yes")])
693 
 
694 
(define_insn "gtuv2si3"
695 
  [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
696 
                     (match_operand:V2SI 1 "register_operand"  "y")
697 
                     (match_operand:V2SI 2 "register_operand"  "y")]
698 
                    VUNSPEC_WCMP_GTU)]
699 
  "TARGET_REALLY_IWMMXT"
700 
  "wcmpgtuw%?\\t%0, %1, %2"
701 
  [(set_attr "predicable" "yes")])
702 
 
703 
(define_insn "gtv8qi3"
704 
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
705 
                     (match_operand:V8QI 1 "register_operand"  "y")
706 
                     (match_operand:V8QI 2 "register_operand"  "y")]
707 
                    VUNSPEC_WCMP_GT)]
708 
  "TARGET_REALLY_IWMMXT"
709 
  "wcmpgtsb%?\\t%0, %1, %2"
710 
  [(set_attr "predicable" "yes")])
711 
 
712 
(define_insn "gtv4hi3"
713 
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
714 
                     (match_operand:V4HI 1 "register_operand"  "y")
715 
                     (match_operand:V4HI 2 "register_operand"  "y")]
716 
                    VUNSPEC_WCMP_GT)]
717 
  "TARGET_REALLY_IWMMXT"
718 
  "wcmpgtsh%?\\t%0, %1, %2"
719 
  [(set_attr "predicable" "yes")])
720 
 
721 
(define_insn "gtv2si3"
722 
  [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
723 
                     (match_operand:V2SI 1 "register_operand"  "y")
724 
                     (match_operand:V2SI 2 "register_operand"  "y")]
725 
                    VUNSPEC_WCMP_GT)]
726 
  "TARGET_REALLY_IWMMXT"
727 
  "wcmpgtsw%?\\t%0, %1, %2"
728 
  [(set_attr "predicable" "yes")])
729 
 
730 
;; Max/min insns
731 
 
732 
(define_insn "smaxv8qi3"
733 
  [(set (match_operand:V8QI            0 "register_operand" "=y")
734 
        (smax:V8QI (match_operand:V8QI 1 "register_operand" "y")
735 
                   (match_operand:V8QI 2 "register_operand" "y")))]
736 
  "TARGET_REALLY_IWMMXT"
737 
  "wmaxsb%?\\t%0, %1, %2"
738 
  [(set_attr "predicable" "yes")])
739 
 
740 
(define_insn "umaxv8qi3"
741 
  [(set (match_operand:V8QI            0 "register_operand" "=y")
742 
        (umax:V8QI (match_operand:V8QI 1 "register_operand" "y")
743 
                   (match_operand:V8QI 2 "register_operand" "y")))]
744 
  "TARGET_REALLY_IWMMXT"
745 
  "wmaxub%?\\t%0, %1, %2"
746 
  [(set_attr "predicable" "yes")])
747 
 
748 
(define_insn "smaxv4hi3"
749 
  [(set (match_operand:V4HI            0 "register_operand" "=y")
750 
        (smax:V4HI (match_operand:V4HI 1 "register_operand" "y")
751 
                   (match_operand:V4HI 2 "register_operand" "y")))]
752 
  "TARGET_REALLY_IWMMXT"
753 
  "wmaxsh%?\\t%0, %1, %2"
754 
  [(set_attr "predicable" "yes")])
755 
 
756 
(define_insn "umaxv4hi3"
757 
  [(set (match_operand:V4HI            0 "register_operand" "=y")
758 
        (umax:V4HI (match_operand:V4HI 1 "register_operand" "y")
759 
                   (match_operand:V4HI 2 "register_operand" "y")))]
760 
  "TARGET_REALLY_IWMMXT"
761 
  "wmaxuh%?\\t%0, %1, %2"
762 
  [(set_attr "predicable" "yes")])
763 
 
764 
(define_insn "smaxv2si3"
765 
  [(set (match_operand:V2SI            0 "register_operand" "=y")
766 
        (smax:V2SI (match_operand:V2SI 1 "register_operand" "y")
767 
                   (match_operand:V2SI 2 "register_operand" "y")))]
768 
  "TARGET_REALLY_IWMMXT"
769 
  "wmaxsw%?\\t%0, %1, %2"
770 
  [(set_attr "predicable" "yes")])
771 
 
772 
(define_insn "umaxv2si3"
773 
  [(set (match_operand:V2SI            0 "register_operand" "=y")
774 
        (umax:V2SI (match_operand:V2SI 1 "register_operand" "y")
775 
                   (match_operand:V2SI 2 "register_operand" "y")))]
776 
  "TARGET_REALLY_IWMMXT"
777 
  "wmaxuw%?\\t%0, %1, %2"
778 
  [(set_attr "predicable" "yes")])
779 
 
780 
(define_insn "sminv8qi3"
781 
  [(set (match_operand:V8QI            0 "register_operand" "=y")
782 
        (smin:V8QI (match_operand:V8QI 1 "register_operand" "y")
783 
                   (match_operand:V8QI 2 "register_operand" "y")))]
784 
  "TARGET_REALLY_IWMMXT"
785 
  "wminsb%?\\t%0, %1, %2"
786 
  [(set_attr "predicable" "yes")])
787 
 
788 
(define_insn "uminv8qi3"
789 
  [(set (match_operand:V8QI            0 "register_operand" "=y")
790 
        (umin:V8QI (match_operand:V8QI 1 "register_operand" "y")
791 
                   (match_operand:V8QI 2 "register_operand" "y")))]
792 
  "TARGET_REALLY_IWMMXT"
793 
  "wminub%?\\t%0, %1, %2"
794 
  [(set_attr "predicable" "yes")])
795 
 
796 
(define_insn "sminv4hi3"
797 
  [(set (match_operand:V4HI            0 "register_operand" "=y")
798 
        (smin:V4HI (match_operand:V4HI 1 "register_operand" "y")
799 
                   (match_operand:V4HI 2 "register_operand" "y")))]
800 
  "TARGET_REALLY_IWMMXT"
801 
  "wminsh%?\\t%0, %1, %2"
802 
  [(set_attr "predicable" "yes")])
803 
 
804 
(define_insn "uminv4hi3"
805 
  [(set (match_operand:V4HI            0 "register_operand" "=y")
806 
        (umin:V4HI (match_operand:V4HI 1 "register_operand" "y")
807 
                   (match_operand:V4HI 2 "register_operand" "y")))]
808 
  "TARGET_REALLY_IWMMXT"
809 
  "wminuh%?\\t%0, %1, %2"
810 
  [(set_attr "predicable" "yes")])
811 
 
812 
(define_insn "sminv2si3"
813 
  [(set (match_operand:V2SI            0 "register_operand" "=y")
814 
        (smin:V2SI (match_operand:V2SI 1 "register_operand" "y")
815 
                   (match_operand:V2SI 2 "register_operand" "y")))]
816 
  "TARGET_REALLY_IWMMXT"
817 
  "wminsw%?\\t%0, %1, %2"
818 
  [(set_attr "predicable" "yes")])
819 
 
820 
(define_insn "uminv2si3"
821 
  [(set (match_operand:V2SI            0 "register_operand" "=y")
822 
        (umin:V2SI (match_operand:V2SI 1 "register_operand" "y")
823 
                   (match_operand:V2SI 2 "register_operand" "y")))]
824 
  "TARGET_REALLY_IWMMXT"
825 
  "wminuw%?\\t%0, %1, %2"
826 
  [(set_attr "predicable" "yes")])
827 
 
828 
;; Pack/unpack insns.
829 
 
830 
(define_insn "iwmmxt_wpackhss"
831 
  [(set (match_operand:V8QI                    0 "register_operand" "=y")
832 
        (vec_concat:V8QI
833 
         (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
834 
         (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
835 
  "TARGET_REALLY_IWMMXT"
836 
  "wpackhss%?\\t%0, %1, %2"
837 
  [(set_attr "predicable" "yes")])
838 
 
839 
(define_insn "iwmmxt_wpackwss"
840 
  [(set (match_operand:V4HI                    0 "register_operand" "=y")
841 
        (vec_concat:V4HI
842 
         (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
843 
         (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
844 
  "TARGET_REALLY_IWMMXT"
845 
  "wpackwss%?\\t%0, %1, %2"
846 
  [(set_attr "predicable" "yes")])
847 
 
848 
(define_insn "iwmmxt_wpackdss"
849 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
850 
        (vec_concat:V2SI
851 
         (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
852 
         (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
853 
  "TARGET_REALLY_IWMMXT"
854 
  "wpackdss%?\\t%0, %1, %2"
855 
  [(set_attr "predicable" "yes")])
856 
 
857 
(define_insn "iwmmxt_wpackhus"
858 
  [(set (match_operand:V8QI                    0 "register_operand" "=y")
859 
        (vec_concat:V8QI
860 
         (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
861 
         (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
862 
  "TARGET_REALLY_IWMMXT"
863 
  "wpackhus%?\\t%0, %1, %2"
864 
  [(set_attr "predicable" "yes")])
865 
 
866 
(define_insn "iwmmxt_wpackwus"
867 
  [(set (match_operand:V4HI                    0 "register_operand" "=y")
868 
        (vec_concat:V4HI
869 
         (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
870 
         (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
871 
  "TARGET_REALLY_IWMMXT"
872 
  "wpackwus%?\\t%0, %1, %2"
873 
  [(set_attr "predicable" "yes")])
874 
 
875 
(define_insn "iwmmxt_wpackdus"
876 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
877 
        (vec_concat:V2SI
878 
         (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
879 
         (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
880 
  "TARGET_REALLY_IWMMXT"
881 
  "wpackdus%?\\t%0, %1, %2"
882 
  [(set_attr "predicable" "yes")])
883 
 
884 
 
885 
(define_insn "iwmmxt_wunpckihb"
886 
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
887 
        (vec_merge:V8QI
888 
         (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
889 
                          (parallel [(const_int 4)
890 
                                     (const_int 0)
891 
                                     (const_int 5)
892 
                                     (const_int 1)
893 
                                     (const_int 6)
894 
                                     (const_int 2)
895 
                                     (const_int 7)
896 
                                     (const_int 3)]))
897 
         (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
898 
                          (parallel [(const_int 0)
899 
                                     (const_int 4)
900 
                                     (const_int 1)
901 
                                     (const_int 5)
902 
                                     (const_int 2)
903 
                                     (const_int 6)
904 
                                     (const_int 3)
905 
                                     (const_int 7)]))
906 
         (const_int 85)))]
907 
  "TARGET_REALLY_IWMMXT"
908 
  "wunpckihb%?\\t%0, %1, %2"
909 
  [(set_attr "predicable" "yes")])
910 
 
911 
(define_insn "iwmmxt_wunpckihh"
912 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
913 
        (vec_merge:V4HI
914 
         (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
915 
                          (parallel [(const_int 0)
916 
                                     (const_int 2)
917 
                                     (const_int 1)
918 
                                     (const_int 3)]))
919 
         (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
920 
                          (parallel [(const_int 2)
921 
                                     (const_int 0)
922 
                                     (const_int 3)
923 
                                     (const_int 1)]))
924 
         (const_int 5)))]
925 
  "TARGET_REALLY_IWMMXT"
926 
  "wunpckihh%?\\t%0, %1, %2"
927 
  [(set_attr "predicable" "yes")])
928 
 
929 
(define_insn "iwmmxt_wunpckihw"
930 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
931 
        (vec_merge:V2SI
932 
         (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
933 
                          (parallel [(const_int 0)
934 
                                     (const_int 1)]))
935 
         (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
936 
                          (parallel [(const_int 1)
937 
                                     (const_int 0)]))
938 
         (const_int 1)))]
939 
  "TARGET_REALLY_IWMMXT"
940 
  "wunpckihw%?\\t%0, %1, %2"
941 
  [(set_attr "predicable" "yes")])
942 
 
943 
(define_insn "iwmmxt_wunpckilb"
944 
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
945 
        (vec_merge:V8QI
946 
         (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
947 
                          (parallel [(const_int 0)
948 
                                     (const_int 4)
949 
                                     (const_int 1)
950 
                                     (const_int 5)
951 
                                     (const_int 2)
952 
                                     (const_int 6)
953 
                                     (const_int 3)
954 
                                     (const_int 7)]))
955 
         (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
956 
                          (parallel [(const_int 4)
957 
                                     (const_int 0)
958 
                                     (const_int 5)
959 
                                     (const_int 1)
960 
                                     (const_int 6)
961 
                                     (const_int 2)
962 
                                     (const_int 7)
963 
                                     (const_int 3)]))
964 
         (const_int 85)))]
965 
  "TARGET_REALLY_IWMMXT"
966 
  "wunpckilb%?\\t%0, %1, %2"
967 
  [(set_attr "predicable" "yes")])
968 
 
969 
(define_insn "iwmmxt_wunpckilh"
970 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
971 
        (vec_merge:V4HI
972 
         (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
973 
                          (parallel [(const_int 2)
974 
                                     (const_int 0)
975 
                                     (const_int 3)
976 
                                     (const_int 1)]))
977 
         (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
978 
                          (parallel [(const_int 0)
979 
                                     (const_int 2)
980 
                                     (const_int 1)
981 
                                     (const_int 3)]))
982 
         (const_int 5)))]
983 
  "TARGET_REALLY_IWMMXT"
984 
  "wunpckilh%?\\t%0, %1, %2"
985 
  [(set_attr "predicable" "yes")])
986 
 
987 
(define_insn "iwmmxt_wunpckilw"
988 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
989 
        (vec_merge:V2SI
990 
         (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
991 
                           (parallel [(const_int 1)
992 
                                      (const_int 0)]))
993 
         (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
994 
                          (parallel [(const_int 0)
995 
                                     (const_int 1)]))
996 
         (const_int 1)))]
997 
  "TARGET_REALLY_IWMMXT"
998 
  "wunpckilw%?\\t%0, %1, %2"
999 
  [(set_attr "predicable" "yes")])
1000 
 
1001 
(define_insn "iwmmxt_wunpckehub"
1002 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
1003 
        (zero_extend:V4HI
1004 
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1005 
                          (parallel [(const_int 4) (const_int 5)
1006 
                                     (const_int 6) (const_int 7)]))))]
1007 
  "TARGET_REALLY_IWMMXT"
1008 
  "wunpckehub%?\\t%0, %1"
1009 
  [(set_attr "predicable" "yes")])
1010 
 
1011 
(define_insn "iwmmxt_wunpckehuh"
1012 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
1013 
        (zero_extend:V2SI
1014 
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1015 
                          (parallel [(const_int 2) (const_int 3)]))))]
1016 
  "TARGET_REALLY_IWMMXT"
1017 
  "wunpckehuh%?\\t%0, %1"
1018 
  [(set_attr "predicable" "yes")])
1019 
 
1020 
(define_insn "iwmmxt_wunpckehuw"
1021 
  [(set (match_operand:DI                   0 "register_operand" "=y")
1022 
        (zero_extend:DI
1023 
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1024 
                        (parallel [(const_int 1)]))))]
1025 
  "TARGET_REALLY_IWMMXT"
1026 
  "wunpckehuw%?\\t%0, %1"
1027 
  [(set_attr "predicable" "yes")])
1028 
 
1029 
(define_insn "iwmmxt_wunpckehsb"
1030 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
1031 
        (sign_extend:V4HI
1032 
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1033 
                          (parallel [(const_int 4) (const_int 5)
1034 
                                     (const_int 6) (const_int 7)]))))]
1035 
  "TARGET_REALLY_IWMMXT"
1036 
  "wunpckehsb%?\\t%0, %1"
1037 
  [(set_attr "predicable" "yes")])
1038 
 
1039 
(define_insn "iwmmxt_wunpckehsh"
1040 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
1041 
        (sign_extend:V2SI
1042 
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1043 
                          (parallel [(const_int 2) (const_int 3)]))))]
1044 
  "TARGET_REALLY_IWMMXT"
1045 
  "wunpckehsh%?\\t%0, %1"
1046 
  [(set_attr "predicable" "yes")])
1047 
 
1048 
(define_insn "iwmmxt_wunpckehsw"
1049 
  [(set (match_operand:DI                   0 "register_operand" "=y")
1050 
        (sign_extend:DI
1051 
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1052 
                        (parallel [(const_int 1)]))))]
1053 
  "TARGET_REALLY_IWMMXT"
1054 
  "wunpckehsw%?\\t%0, %1"
1055 
  [(set_attr "predicable" "yes")])
1056 
 
1057 
(define_insn "iwmmxt_wunpckelub"
1058 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
1059 
        (zero_extend:V4HI
1060 
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1061 
                          (parallel [(const_int 0) (const_int 1)
1062 
                                     (const_int 2) (const_int 3)]))))]
1063 
  "TARGET_REALLY_IWMMXT"
1064 
  "wunpckelub%?\\t%0, %1"
1065 
  [(set_attr "predicable" "yes")])
1066 
 
1067 
(define_insn "iwmmxt_wunpckeluh"
1068 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
1069 
        (zero_extend:V2SI
1070 
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1071 
                          (parallel [(const_int 0) (const_int 1)]))))]
1072 
  "TARGET_REALLY_IWMMXT"
1073 
  "wunpckeluh%?\\t%0, %1"
1074 
  [(set_attr "predicable" "yes")])
1075 
 
1076 
(define_insn "iwmmxt_wunpckeluw"
1077 
  [(set (match_operand:DI                   0 "register_operand" "=y")
1078 
        (zero_extend:DI
1079 
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1080 
                        (parallel [(const_int 0)]))))]
1081 
  "TARGET_REALLY_IWMMXT"
1082 
  "wunpckeluw%?\\t%0, %1"
1083 
  [(set_attr "predicable" "yes")])
1084 
 
1085 
(define_insn "iwmmxt_wunpckelsb"
1086 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
1087 
        (sign_extend:V4HI
1088 
         (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1089 
                          (parallel [(const_int 0) (const_int 1)
1090 
                                     (const_int 2) (const_int 3)]))))]
1091 
  "TARGET_REALLY_IWMMXT"
1092 
  "wunpckelsb%?\\t%0, %1"
1093 
  [(set_attr "predicable" "yes")])
1094 
 
1095 
(define_insn "iwmmxt_wunpckelsh"
1096 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
1097 
        (sign_extend:V2SI
1098 
         (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1099 
                          (parallel [(const_int 0) (const_int 1)]))))]
1100 
  "TARGET_REALLY_IWMMXT"
1101 
  "wunpckelsh%?\\t%0, %1"
1102 
  [(set_attr "predicable" "yes")])
1103 
 
1104 
(define_insn "iwmmxt_wunpckelsw"
1105 
  [(set (match_operand:DI                   0 "register_operand" "=y")
1106 
        (sign_extend:DI
1107 
         (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1108 
                        (parallel [(const_int 0)]))))]
1109 
  "TARGET_REALLY_IWMMXT"
1110 
  "wunpckelsw%?\\t%0, %1"
1111 
  [(set_attr "predicable" "yes")])
1112 
 
1113 
;; Shifts
1114 
 
1115 
(define_insn "rorv4hi3"
1116 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1117 
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1118 
                       (match_operand:SI   2 "register_operand" "z")))]
1119 
  "TARGET_REALLY_IWMMXT"
1120 
  "wrorhg%?\\t%0, %1, %2"
1121 
  [(set_attr "predicable" "yes")])
1122 
 
1123 
(define_insn "rorv2si3"
1124 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1125 
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1126 
                       (match_operand:SI   2 "register_operand" "z")))]
1127 
  "TARGET_REALLY_IWMMXT"
1128 
  "wrorwg%?\\t%0, %1, %2"
1129 
  [(set_attr "predicable" "yes")])
1130 
 
1131 
(define_insn "rordi3"
1132 
  [(set (match_operand:DI              0 "register_operand" "=y")
1133 
        (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1134 
                   (match_operand:SI   2 "register_operand" "z")))]
1135 
  "TARGET_REALLY_IWMMXT"
1136 
  "wrordg%?\\t%0, %1, %2"
1137 
  [(set_attr "predicable" "yes")])
1138 
 
1139 
(define_insn "ashrv4hi3"
1140 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1141 
        (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1142 
                       (match_operand:SI   2 "register_operand" "z")))]
1143 
  "TARGET_REALLY_IWMMXT"
1144 
  "wsrahg%?\\t%0, %1, %2"
1145 
  [(set_attr "predicable" "yes")])
1146 
 
1147 
(define_insn "ashrv2si3"
1148 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1149 
        (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1150 
                       (match_operand:SI   2 "register_operand" "z")))]
1151 
  "TARGET_REALLY_IWMMXT"
1152 
  "wsrawg%?\\t%0, %1, %2"
1153 
  [(set_attr "predicable" "yes")])
1154 
 
1155 
(define_insn "ashrdi3_iwmmxt"
1156 
  [(set (match_operand:DI              0 "register_operand" "=y")
1157 
        (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1158 
                   (match_operand:SI   2 "register_operand" "z")))]
1159 
  "TARGET_REALLY_IWMMXT"
1160 
  "wsradg%?\\t%0, %1, %2"
1161 
  [(set_attr "predicable" "yes")])
1162 
 
1163 
(define_insn "lshrv4hi3"
1164 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1165 
        (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1166 
                       (match_operand:SI   2 "register_operand" "z")))]
1167 
  "TARGET_REALLY_IWMMXT"
1168 
  "wsrlhg%?\\t%0, %1, %2"
1169 
  [(set_attr "predicable" "yes")])
1170 
 
1171 
(define_insn "lshrv2si3"
1172 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1173 
        (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1174 
                       (match_operand:SI   2 "register_operand" "z")))]
1175 
  "TARGET_REALLY_IWMMXT"
1176 
  "wsrlwg%?\\t%0, %1, %2"
1177 
  [(set_attr "predicable" "yes")])
1178 
 
1179 
(define_insn "lshrdi3_iwmmxt"
1180 
  [(set (match_operand:DI              0 "register_operand" "=y")
1181 
        (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1182 
                     (match_operand:SI 2 "register_operand" "z")))]
1183 
  "TARGET_REALLY_IWMMXT"
1184 
  "wsrldg%?\\t%0, %1, %2"
1185 
  [(set_attr "predicable" "yes")])
1186 
 
1187 
(define_insn "ashlv4hi3"
1188 
  [(set (match_operand:V4HI              0 "register_operand" "=y")
1189 
        (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1190 
                     (match_operand:SI   2 "register_operand" "z")))]
1191 
  "TARGET_REALLY_IWMMXT"
1192 
  "wsllhg%?\\t%0, %1, %2"
1193 
  [(set_attr "predicable" "yes")])
1194 
 
1195 
(define_insn "ashlv2si3"
1196 
  [(set (match_operand:V2SI              0 "register_operand" "=y")
1197 
        (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1198 
                       (match_operand:SI 2 "register_operand" "z")))]
1199 
  "TARGET_REALLY_IWMMXT"
1200 
  "wsllwg%?\\t%0, %1, %2"
1201 
  [(set_attr "predicable" "yes")])
1202 
 
1203 
(define_insn "ashldi3_iwmmxt"
1204 
  [(set (match_operand:DI            0 "register_operand" "=y")
1205 
        (ashift:DI (match_operand:DI 1 "register_operand" "y")
1206 
                   (match_operand:SI 2 "register_operand" "z")))]
1207 
  "TARGET_REALLY_IWMMXT"
1208 
  "wslldg%?\\t%0, %1, %2"
1209 
  [(set_attr "predicable" "yes")])
1210 
 
1211 
(define_insn "rorv4hi3_di"
1212 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1213 
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1214 
                       (match_operand:DI   2 "register_operand" "y")))]
1215 
  "TARGET_REALLY_IWMMXT"
1216 
  "wrorh%?\\t%0, %1, %2"
1217 
  [(set_attr "predicable" "yes")])
1218 
 
1219 
(define_insn "rorv2si3_di"
1220 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1221 
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1222 
                       (match_operand:DI   2 "register_operand" "y")))]
1223 
  "TARGET_REALLY_IWMMXT"
1224 
  "wrorw%?\\t%0, %1, %2"
1225 
  [(set_attr "predicable" "yes")])
1226 
 
1227 
(define_insn "rordi3_di"
1228 
  [(set (match_operand:DI              0 "register_operand" "=y")
1229 
        (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1230 
                   (match_operand:DI   2 "register_operand" "y")))]
1231 
  "TARGET_REALLY_IWMMXT"
1232 
  "wrord%?\\t%0, %1, %2"
1233 
  [(set_attr "predicable" "yes")])
1234 
 
1235 
(define_insn "ashrv4hi3_di"
1236 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1237 
        (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1238 
                       (match_operand:DI   2 "register_operand" "y")))]
1239 
  "TARGET_REALLY_IWMMXT"
1240 
  "wsrah%?\\t%0, %1, %2"
1241 
  [(set_attr "predicable" "yes")])
1242 
 
1243 
(define_insn "ashrv2si3_di"
1244 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1245 
        (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1246 
                       (match_operand:DI   2 "register_operand" "y")))]
1247 
  "TARGET_REALLY_IWMMXT"
1248 
  "wsraw%?\\t%0, %1, %2"
1249 
  [(set_attr "predicable" "yes")])
1250 
 
1251 
(define_insn "ashrdi3_di"
1252 
  [(set (match_operand:DI              0 "register_operand" "=y")
1253 
        (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1254 
                   (match_operand:DI   2 "register_operand" "y")))]
1255 
  "TARGET_REALLY_IWMMXT"
1256 
  "wsrad%?\\t%0, %1, %2"
1257 
  [(set_attr "predicable" "yes")])
1258 
 
1259 
(define_insn "lshrv4hi3_di"
1260 
  [(set (match_operand:V4HI                0 "register_operand" "=y")
1261 
        (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1262 
                       (match_operand:DI   2 "register_operand" "y")))]
1263 
  "TARGET_REALLY_IWMMXT"
1264 
  "wsrlh%?\\t%0, %1, %2"
1265 
  [(set_attr "predicable" "yes")])
1266 
 
1267 
(define_insn "lshrv2si3_di"
1268 
  [(set (match_operand:V2SI                0 "register_operand" "=y")
1269 
        (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1270 
                       (match_operand:DI   2 "register_operand" "y")))]
1271 
  "TARGET_REALLY_IWMMXT"
1272 
  "wsrlw%?\\t%0, %1, %2"
1273 
  [(set_attr "predicable" "yes")])
1274 
 
1275 
(define_insn "lshrdi3_di"
1276 
  [(set (match_operand:DI              0 "register_operand" "=y")
1277 
        (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1278 
                     (match_operand:DI 2 "register_operand" "y")))]
1279 
  "TARGET_REALLY_IWMMXT"
1280 
  "wsrld%?\\t%0, %1, %2"
1281 
  [(set_attr "predicable" "yes")])
1282 
 
1283 
(define_insn "ashlv4hi3_di"
1284 
  [(set (match_operand:V4HI              0 "register_operand" "=y")
1285 
        (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1286 
                     (match_operand:DI   2 "register_operand" "y")))]
1287 
  "TARGET_REALLY_IWMMXT"
1288 
  "wsllh%?\\t%0, %1, %2"
1289 
  [(set_attr "predicable" "yes")])
1290 
 
1291 
(define_insn "ashlv2si3_di"
1292 
  [(set (match_operand:V2SI              0 "register_operand" "=y")
1293 
        (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1294 
                       (match_operand:DI 2 "register_operand" "y")))]
1295 
  "TARGET_REALLY_IWMMXT"
1296 
  "wsllw%?\\t%0, %1, %2"
1297 
  [(set_attr "predicable" "yes")])
1298 
 
1299 
(define_insn "ashldi3_di"
1300 
  [(set (match_operand:DI            0 "register_operand" "=y")
1301 
        (ashift:DI (match_operand:DI 1 "register_operand" "y")
1302 
                   (match_operand:DI 2 "register_operand" "y")))]
1303 
  "TARGET_REALLY_IWMMXT"
1304 
  "wslld%?\\t%0, %1, %2"
1305 
  [(set_attr "predicable" "yes")])
1306 
 
1307 
(define_insn "iwmmxt_wmadds"
1308 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1309 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1310 
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1311 
  "TARGET_REALLY_IWMMXT"
1312 
  "wmadds%?\\t%0, %1, %2"
1313 
  [(set_attr "predicable" "yes")])
1314 
 
1315 
(define_insn "iwmmxt_wmaddu"
1316 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1317 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1318 
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1319 
  "TARGET_REALLY_IWMMXT"
1320 
  "wmaddu%?\\t%0, %1, %2"
1321 
  [(set_attr "predicable" "yes")])
1322 
 
1323 
(define_insn "iwmmxt_tmia"
1324 
  [(set (match_operand:DI                    0 "register_operand" "=y")
1325 
        (plus:DI (match_operand:DI           1 "register_operand" "0")
1326 
                 (mult:DI (sign_extend:DI
1327 
                           (match_operand:SI 2 "register_operand" "r"))
1328 
                          (sign_extend:DI
1329 
                           (match_operand:SI 3 "register_operand" "r")))))]
1330 
  "TARGET_REALLY_IWMMXT"
1331 
  "tmia%?\\t%0, %2, %3"
1332 
  [(set_attr "predicable" "yes")])
1333 
 
1334 
(define_insn "iwmmxt_tmiaph"
1335 
  [(set (match_operand:DI          0 "register_operand" "=y")
1336 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1337 
                 (plus:DI
1338 
                  (mult:DI (sign_extend:DI
1339 
                            (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1340 
                           (sign_extend:DI
1341 
                            (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1342 
                  (mult:DI (sign_extend:DI
1343 
                            (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1344 
                           (sign_extend:DI
1345 
                            (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1346 
  "TARGET_REALLY_IWMMXT"
1347 
  "tmiaph%?\\t%0, %2, %3"
1348 
  [(set_attr "predicable" "yes")])
1349 
 
1350 
(define_insn "iwmmxt_tmiabb"
1351 
  [(set (match_operand:DI          0 "register_operand" "=y")
1352 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1353 
                 (mult:DI (sign_extend:DI
1354 
                           (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1355 
                          (sign_extend:DI
1356 
                           (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1357 
  "TARGET_REALLY_IWMMXT"
1358 
  "tmiabb%?\\t%0, %2, %3"
1359 
  [(set_attr "predicable" "yes")])
1360 
 
1361 
(define_insn "iwmmxt_tmiatb"
1362 
  [(set (match_operand:DI          0 "register_operand" "=y")
1363 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1364 
                 (mult:DI (sign_extend:DI
1365 
                           (truncate:HI (ashiftrt:SI
1366 
                                         (match_operand:SI 2 "register_operand" "r")
1367 
                                         (const_int 16))))
1368 
                          (sign_extend:DI
1369 
                           (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1370 
  "TARGET_REALLY_IWMMXT"
1371 
  "tmiatb%?\\t%0, %2, %3"
1372 
  [(set_attr "predicable" "yes")])
1373 
 
1374 
(define_insn "iwmmxt_tmiabt"
1375 
  [(set (match_operand:DI          0 "register_operand" "=y")
1376 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1377 
                 (mult:DI (sign_extend:DI
1378 
                           (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1379 
                          (sign_extend:DI
1380 
                           (truncate:HI (ashiftrt:SI
1381 
                                         (match_operand:SI 3 "register_operand" "r")
1382 
                                         (const_int 16)))))))]
1383 
  "TARGET_REALLY_IWMMXT"
1384 
  "tmiabt%?\\t%0, %2, %3"
1385 
  [(set_attr "predicable" "yes")])
1386 
 
1387 
(define_insn "iwmmxt_tmiatt"
1388 
  [(set (match_operand:DI          0 "register_operand" "=y")
1389 
        (plus:DI (match_operand:DI 1 "register_operand" "0")
1390 
                 (mult:DI (sign_extend:DI
1391 
                           (truncate:HI (ashiftrt:SI
1392 
                                         (match_operand:SI 2 "register_operand" "r")
1393 
                                         (const_int 16))))
1394 
                          (sign_extend:DI
1395 
                           (truncate:HI (ashiftrt:SI
1396 
                                         (match_operand:SI 3 "register_operand" "r")
1397 
                                         (const_int 16)))))))]
1398 
  "TARGET_REALLY_IWMMXT"
1399 
  "tmiatt%?\\t%0, %2, %3"
1400 
  [(set_attr "predicable" "yes")])
1401 
 
1402 
(define_insn "iwmmxt_tbcstqi"
1403 
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
1404 
        (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1405 
  "TARGET_REALLY_IWMMXT"
1406 
  "tbcstb%?\\t%0, %1"
1407 
  [(set_attr "predicable" "yes")])
1408 
 
1409 
(define_insn "iwmmxt_tbcsthi"
1410 
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
1411 
        (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1412 
  "TARGET_REALLY_IWMMXT"
1413 
  "tbcsth%?\\t%0, %1"
1414 
  [(set_attr "predicable" "yes")])
1415 
 
1416 
(define_insn "iwmmxt_tbcstsi"
1417 
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
1418 
        (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1419 
  "TARGET_REALLY_IWMMXT"
1420 
  "tbcstw%?\\t%0, %1"
1421 
  [(set_attr "predicable" "yes")])
1422 
 
1423 
(define_insn "iwmmxt_tmovmskb"
1424 
  [(set (match_operand:SI               0 "register_operand" "=r")
1425 
        (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1426 
  "TARGET_REALLY_IWMMXT"
1427 
  "tmovmskb%?\\t%0, %1"
1428 
  [(set_attr "predicable" "yes")])
1429 
 
1430 
(define_insn "iwmmxt_tmovmskh"
1431 
  [(set (match_operand:SI               0 "register_operand" "=r")
1432 
        (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1433 
  "TARGET_REALLY_IWMMXT"
1434 
  "tmovmskh%?\\t%0, %1"
1435 
  [(set_attr "predicable" "yes")])
1436 
 
1437 
(define_insn "iwmmxt_tmovmskw"
1438 
  [(set (match_operand:SI               0 "register_operand" "=r")
1439 
        (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1440 
  "TARGET_REALLY_IWMMXT"
1441 
  "tmovmskw%?\\t%0, %1"
1442 
  [(set_attr "predicable" "yes")])
1443 
 
1444 
(define_insn "iwmmxt_waccb"
1445 
  [(set (match_operand:DI               0 "register_operand" "=y")
1446 
        (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1447 
  "TARGET_REALLY_IWMMXT"
1448 
  "waccb%?\\t%0, %1"
1449 
  [(set_attr "predicable" "yes")])
1450 
 
1451 
(define_insn "iwmmxt_wacch"
1452 
  [(set (match_operand:DI               0 "register_operand" "=y")
1453 
        (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1454 
  "TARGET_REALLY_IWMMXT"
1455 
  "wacch%?\\t%0, %1"
1456 
  [(set_attr "predicable" "yes")])
1457 
 
1458 
(define_insn "iwmmxt_waccw"
1459 
  [(set (match_operand:DI               0 "register_operand" "=y")
1460 
        (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1461 
  "TARGET_REALLY_IWMMXT"
1462 
  "waccw%?\\t%0, %1"
1463 
  [(set_attr "predicable" "yes")])
1464 
 
1465 
(define_insn "iwmmxt_walign"
1466 
  [(set (match_operand:V8QI                           0 "register_operand" "=y,y")
1467 
        (subreg:V8QI (ashiftrt:TI
1468 
                      (subreg:TI (vec_concat:V16QI
1469 
                                  (match_operand:V8QI 1 "register_operand" "y,y")
1470 
                                  (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1471 
                      (mult:SI
1472 
                       (match_operand:SI              3 "nonmemory_operand" "i,z")
1473 
                       (const_int 8))) 0))]
1474 
  "TARGET_REALLY_IWMMXT"
1475 
  "@
1476 
   waligni%?\\t%0, %1, %2, %3
1477 
   walignr%U3%?\\t%0, %1, %2"
1478 
  [(set_attr "predicable" "yes")])
1479 
 
1480 
(define_insn "iwmmxt_tmrc"
1481 
  [(set (match_operand:SI                      0 "register_operand" "=r")
1482 
        (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1483 
                            VUNSPEC_TMRC))]
1484 
  "TARGET_REALLY_IWMMXT"
1485 
  "tmrc%?\\t%0, %w1"
1486 
  [(set_attr "predicable" "yes")])
1487 
 
1488 
(define_insn "iwmmxt_tmcr"
1489 
  [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1490 
                        (match_operand:SI 1 "register_operand"  "r")]
1491 
                       VUNSPEC_TMCR)]
1492 
  "TARGET_REALLY_IWMMXT"
1493 
  "tmcr%?\\t%w0, %1"
1494 
  [(set_attr "predicable" "yes")])
1495 
 
1496 
(define_insn "iwmmxt_wsadb"
1497 
  [(set (match_operand:V8QI               0 "register_operand" "=y")
1498 
        (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1499 
                      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1500 
  "TARGET_REALLY_IWMMXT"
1501 
  "wsadb%?\\t%0, %1, %2"
1502 
  [(set_attr "predicable" "yes")])
1503 
 
1504 
(define_insn "iwmmxt_wsadh"
1505 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1506 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1507 
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1508 
  "TARGET_REALLY_IWMMXT"
1509 
  "wsadh%?\\t%0, %1, %2"
1510 
  [(set_attr "predicable" "yes")])
1511 
 
1512 
(define_insn "iwmmxt_wsadbz"
1513 
  [(set (match_operand:V8QI               0 "register_operand" "=y")
1514 
        (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1515 
                      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1516 
  "TARGET_REALLY_IWMMXT"
1517 
  "wsadbz%?\\t%0, %1, %2"
1518 
  [(set_attr "predicable" "yes")])
1519 
 
1520 
(define_insn "iwmmxt_wsadhz"
1521 
  [(set (match_operand:V4HI               0 "register_operand" "=y")
1522 
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1523 
                      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1524 
  "TARGET_REALLY_IWMMXT"
1525 
  "wsadhz%?\\t%0, %1, %2"
1526 
  [(set_attr "predicable" "yes")])
1527 
 

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