OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [arm/] [semi.h] - Blame information for rev 853

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/* Definitions of target machine for GNU compiler.  ARM on semi-hosted platform
2
   Copyright (C) 1994, 1995, 1996, 1997, 2001, 2004, 2005, 2007
3
   Free Software Foundation, Inc.
4
   Contributed by Richard Earnshaw (richard.earnshaw@arm.com)
5
 
6
   This file is part of GCC.
7
 
8
   GCC is free software; you can redistribute it and/or modify it
9
   under the terms of the GNU General Public License as published
10
   by the Free Software Foundation; either version 3, or (at your
11
   option) any later version.
12
 
13
   GCC is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with GCC; see the file COPYING3.  If not see
20
   <http://www.gnu.org/licenses/>.  */
21
 
22
#define STARTFILE_SPEC  "crt0.o%s"
23
 
24
#ifndef LIB_SPEC
25
#define LIB_SPEC "-lc"
26
#endif
27
 
28
#ifndef SUBTARGET_CPP_SPEC
29
#define SUBTARGET_CPP_SPEC "-D__semi__"
30
#endif
31
 
32
#ifndef LINK_SPEC
33
#define LINK_SPEC "%{mbig-endian:-EB} -X"
34
#endif
35
 
36
#ifndef TARGET_VERSION
37
#define TARGET_VERSION fputs (" (ARM/semi-hosted)", stderr);
38
#endif
39
 
40
#ifndef TARGET_DEFAULT_FLOAT_ABI
41
#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_HARD
42
#endif
43
 
44
#ifndef TARGET_DEFAULT
45
#define TARGET_DEFAULT (MASK_APCS_FRAME)
46
#endif
47
 
48
#ifndef SUBTARGET_EXTRA_SPECS
49
#define SUBTARGET_EXTRA_SPECS \
50
  { "subtarget_extra_asm_spec", SUBTARGET_EXTRA_ASM_SPEC },
51
#endif
52
 
53
#ifndef SUBTARGET_EXTRA_ASM_SPEC
54
#define SUBTARGET_EXTRA_ASM_SPEC ""
55
#endif
56
 
57
/* The compiler supports PIC code generation, even though the binutils
58
   may not.  If we are asked to compile position independent code, we
59
   always pass -k to the assembler.  If it doesn't recognize it, then
60
   it will barf, which probably means that it doesn't know how to
61
   assemble PIC code.  This is what we want, since otherwise tools
62
   may incorrectly assume we support PIC compilation even if the
63
   binutils can't.  */
64
#ifndef ASM_SPEC
65
#define ASM_SPEC "\
66
%{fpic|fpie: -k} %{fPIC|fPIE: -k} \
67
%{mbig-endian:-EB} \
68
%{mcpu=*:-mcpu=%*} \
69
%{march=*:-march=%*} \
70
%{mapcs-float:-mfloat} \
71
%{msoft-float:-mfloat-abi=soft} %{mhard-float:-mfloat-abi=hard} \
72
%{mfloat-abi=*} %{mfpu=*} \
73
%{mthumb-interwork:-mthumb-interwork} \
74
%(subtarget_extra_asm_spec)"
75
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.