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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [arm/] [vfp.md] - Blame information for rev 827

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1 38 julius
;; ARM VFP coprocessor Machine Description
2
;; Copyright (C) 2003, 2005, 2007 Free Software Foundation, Inc.
3
;; Written by CodeSourcery, LLC.
4
;;
5
;; This file is part of GCC.
6
;;
7
;; GCC is free software; you can redistribute it and/or modify it
8
;; under the terms of the GNU General Public License as published by
9
;; the Free Software Foundation; either version 3, or (at your option)
10
;; any later version.
11
;;
12
;; GCC is distributed in the hope that it will be useful, but
13
;; WITHOUT ANY WARRANTY; without even the implied warranty of
14
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
;; General Public License for more details.
16
;;
17
;; You should have received a copy of the GNU General Public License
18
;; along with GCC; see the file COPYING3.  If not see
19
;; .  */
20
 
21
;; Additional register numbers
22
(define_constants
23
  [(VFPCC_REGNUM 95)]
24
)
25
 
26
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
27
;; Pipeline description
28
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29
 
30
(define_automaton "vfp11")
31
 
32
;; There are 3 pipelines in the VFP11 unit.
33
;;
34
;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
35
;;   fourth stage for simple operations.
36
;;
37
;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
38
;;   These insns also uses first execute stage of FMAC pipeline.
39
;;
40
;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
41
;;   second memory stage for loads.
42
 
43
;; We do not model Write-After-Read hazards.
44
;; We do not do write scheduling with the arm core, so it is only necessary
45
;; to model the first stage of each pipeline
46
;; ??? Need to model LS pipeline properly for load/store multiple?
47
;; We do not model fmstat properly.  This could be done by modeling pipelines
48
;; properly and defining an absence set between a dummy fmstat unit and all
49
;; other vfp units.
50
 
51
(define_cpu_unit "fmac" "vfp11")
52
 
53
(define_cpu_unit "ds" "vfp11")
54
 
55
(define_cpu_unit "vfp_ls" "vfp11")
56
 
57
(define_cpu_unit "fmstat" "vfp11")
58
 
59
(exclusion_set "fmac,ds" "fmstat")
60
 
61
;; The VFP "type" attributes differ from those used in the FPA model.
62
;; ffarith      Fast floating point insns, e.g. abs, neg, cpy, cmp.
63
;; farith       Most arithmetic insns.
64
;; fmul         Double precision multiply.
65
;; fdivs        Single precision sqrt or division.
66
;; fdivd        Double precision sqrt or division.
67
;; f_flag       fmstat operation
68
;; f_load[sd]   Floating point load from memory.
69
;; f_store[sd]  Floating point store to memory.
70
;; f_2_r        Transfer vfp to arm reg.
71
;; r_2_f        Transfer arm to vfp reg.
72
;; f_cvt        Convert floating<->integral
73
 
74
(define_insn_reservation "vfp_ffarith" 4
75
 (and (eq_attr "generic_vfp" "yes")
76
      (eq_attr "type" "ffarith"))
77
 "fmac")
78
 
79
(define_insn_reservation "vfp_farith" 8
80
 (and (eq_attr "generic_vfp" "yes")
81
      (eq_attr "type" "farith,f_cvt"))
82
 "fmac")
83
 
84
(define_insn_reservation "vfp_fmul" 9
85
 (and (eq_attr "generic_vfp" "yes")
86
      (eq_attr "type" "fmul"))
87
 "fmac*2")
88
 
89
(define_insn_reservation "vfp_fdivs" 19
90
 (and (eq_attr "generic_vfp" "yes")
91
      (eq_attr "type" "fdivs"))
92
 "ds*15")
93
 
94
(define_insn_reservation "vfp_fdivd" 33
95
 (and (eq_attr "generic_vfp" "yes")
96
      (eq_attr "type" "fdivd"))
97
 "fmac+ds*29")
98
 
99
;; Moves to/from arm regs also use the load/store pipeline.
100
(define_insn_reservation "vfp_fload" 4
101
 (and (eq_attr "generic_vfp" "yes")
102
      (eq_attr "type" "f_loads,f_loadd,r_2_f"))
103
 "vfp_ls")
104
 
105
(define_insn_reservation "vfp_fstore" 4
106
 (and (eq_attr "generic_vfp" "yes")
107
      (eq_attr "type" "f_stores,f_stored,f_2_r"))
108
 "vfp_ls")
109
 
110
(define_insn_reservation "vfp_to_cpsr" 4
111
 (and (eq_attr "generic_vfp" "yes")
112
      (eq_attr "type" "f_flag"))
113
 "fmstat,vfp_ls*3")
114
 
115
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
116
;; Insn pattern
117
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
118
 
119
;; SImode moves
120
;; ??? For now do not allow loading constants into vfp regs.  This causes
121
;; problems because small constants get converted into adds.
122
(define_insn "*arm_movsi_vfp"
123
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r ,m,*w,r,*w,*w, *Uv")
124
      (match_operand:SI 1 "general_operand"        "rI,K,mi,r,r,*w,*w,*Uvi,*w"))]
125
  "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
126
   && (   s_register_operand (operands[0], SImode)
127
       || s_register_operand (operands[1], SImode))"
128
  "@
129
  mov%?\\t%0, %1
130
  mvn%?\\t%0, #%B1
131
  ldr%?\\t%0, %1
132
  str%?\\t%1, %0
133
  fmsr%?\\t%0, %1\\t%@ int
134
  fmrs%?\\t%0, %1\\t%@ int
135
  fcpys%?\\t%0, %1\\t%@ int
136
  flds%?\\t%0, %1\\t%@ int
137
  fsts%?\\t%1, %0\\t%@ int"
138
  [(set_attr "predicable" "yes")
139
   (set_attr "type" "*,*,load1,store1,r_2_f,f_2_r,ffarith,f_loads,f_stores")
140
   (set_attr "pool_range"     "*,*,4096,*,*,*,*,1020,*")
141
   (set_attr "neg_pool_range" "*,*,4084,*,*,*,*,1008,*")]
142
)
143
 
144
 
145
;; DImode moves
146
 
147
(define_insn "*arm_movdi_vfp"
148
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
149
        (match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
150
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
151
   && (   register_operand (operands[0], DImode)
152
       || register_operand (operands[1], DImode))"
153
  "*
154
  switch (which_alternative)
155
    {
156
    case 0:
157
      return \"#\";
158
    case 1:
159
    case 2:
160
      return output_move_double (operands);
161
    case 3:
162
      return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
163
    case 4:
164
      return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
165
    case 5:
166
      return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
167
    case 6:
168
      return \"fldd%?\\t%P0, %1\\t%@ int\";
169
    case 7:
170
      return \"fstd%?\\t%P1, %0\\t%@ int\";
171
    default:
172
      gcc_unreachable ();
173
    }
174
  "
175
  [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_loadd,f_stored")
176
   (set_attr "length" "8,8,8,4,4,4,4,4")
177
   (set_attr "pool_range"     "*,1020,*,*,*,*,1020,*")
178
   (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
179
)
180
 
181
 
182
;; SFmode moves
183
;; Disparage the w<->r cases because reloading an invalid address is
184
;; preferable to loading the value via integer registers.
185
 
186
(define_insn "*movsf_vfp"
187
  [(set (match_operand:SF 0 "nonimmediate_operand" "=w,?r,w  ,Uv,r ,m,w,r")
188
        (match_operand:SF 1 "general_operand"      " ?r,w,UvE,w, mE,r,w,r"))]
189
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
190
   && (   s_register_operand (operands[0], SFmode)
191
       || s_register_operand (operands[1], SFmode))"
192
  "@
193
  fmsr%?\\t%0, %1
194
  fmrs%?\\t%0, %1
195
  flds%?\\t%0, %1
196
  fsts%?\\t%1, %0
197
  ldr%?\\t%0, %1\\t%@ float
198
  str%?\\t%1, %0\\t%@ float
199
  fcpys%?\\t%0, %1
200
  mov%?\\t%0, %1\\t%@ float"
201
  [(set_attr "predicable" "yes")
202
   (set_attr "type" "r_2_f,f_2_r,ffarith,*,f_loads,f_stores,load1,store1")
203
   (set_attr "pool_range" "*,*,1020,*,4096,*,*,*")
204
   (set_attr "neg_pool_range" "*,*,1008,*,4080,*,*,*")]
205
)
206
 
207
 
208
;; DFmode moves
209
 
210
(define_insn "*movdf_vfp"
211
  [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,r, m,w  ,Uv,w,r")
212
        (match_operand:DF 1 "soft_df_operand"              " ?r,w,mF,r,UvF,w, w,r"))]
213
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
214
   && (   register_operand (operands[0], DFmode)
215
       || register_operand (operands[1], DFmode))"
216
  "*
217
  {
218
    switch (which_alternative)
219
      {
220
      case 0:
221
        return \"fmdrr%?\\t%P0, %Q1, %R1\";
222
      case 1:
223
        return \"fmrrd%?\\t%Q0, %R0, %P1\";
224
      case 2: case 3:
225
        return output_move_double (operands);
226
      case 4:
227
        return \"fldd%?\\t%P0, %1\";
228
      case 5:
229
        return \"fstd%?\\t%P1, %0\";
230
      case 6:
231
        return \"fcpyd%?\\t%P0, %P1\";
232
      case 7:
233
        return \"#\";
234
      default:
235
        gcc_unreachable ();
236
      }
237
    }
238
  "
239
  [(set_attr "type" "r_2_f,f_2_r,ffarith,*,load2,store2,f_loadd,f_stored")
240
   (set_attr "length" "4,4,8,8,4,4,4,8")
241
   (set_attr "pool_range" "*,*,1020,*,1020,*,*,*")
242
   (set_attr "neg_pool_range" "*,*,1008,*,1008,*,*,*")]
243
)
244
 
245
 
246
;; Conditional move patterns
247
 
248
(define_insn "*movsfcc_vfp"
249
  [(set (match_operand:SF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
250
        (if_then_else:SF
251
          (match_operator   3 "arm_comparison_operator"
252
            [(match_operand 4 "cc_register" "") (const_int 0)])
253
          (match_operand:SF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
254
          (match_operand:SF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
255
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
256
  "@
257
   fcpys%D3\\t%0, %2
258
   fcpys%d3\\t%0, %1
259
   fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
260
   fmsr%D3\\t%0, %2
261
   fmsr%d3\\t%0, %1
262
   fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
263
   fmrs%D3\\t%0, %2
264
   fmrs%d3\\t%0, %1
265
   fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
266
   [(set_attr "conds" "use")
267
    (set_attr "length" "4,4,8,4,4,8,4,4,8")
268
    (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
269
)
270
 
271
(define_insn "*movdfcc_vfp"
272
  [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
273
        (if_then_else:DF
274
          (match_operator   3 "arm_comparison_operator"
275
            [(match_operand 4 "cc_register" "") (const_int 0)])
276
          (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
277
          (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
278
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
279
  "@
280
   fcpyd%D3\\t%P0, %P2
281
   fcpyd%d3\\t%P0, %P1
282
   fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
283
   fmdrr%D3\\t%P0, %Q2, %R2
284
   fmdrr%d3\\t%P0, %Q1, %R1
285
   fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
286
   fmrrd%D3\\t%Q0, %R0, %P2
287
   fmrrd%d3\\t%Q0, %R0, %P1
288
   fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
289
   [(set_attr "conds" "use")
290
    (set_attr "length" "4,4,8,4,4,8,4,4,8")
291
    (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
292
)
293
 
294
 
295
;; Sign manipulation functions
296
 
297
(define_insn "*abssf2_vfp"
298
  [(set (match_operand:SF         0 "s_register_operand" "=w")
299
        (abs:SF (match_operand:SF 1 "s_register_operand" "w")))]
300
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
301
  "fabss%?\\t%0, %1"
302
  [(set_attr "predicable" "yes")
303
   (set_attr "type" "ffarith")]
304
)
305
 
306
(define_insn "*absdf2_vfp"
307
  [(set (match_operand:DF         0 "s_register_operand" "=w")
308
        (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
309
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
310
  "fabsd%?\\t%P0, %P1"
311
  [(set_attr "predicable" "yes")
312
   (set_attr "type" "ffarith")]
313
)
314
 
315
(define_insn "*negsf2_vfp"
316
  [(set (match_operand:SF         0 "s_register_operand" "=w,?r")
317
        (neg:SF (match_operand:SF 1 "s_register_operand" "w,r")))]
318
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
319
  "@
320
   fnegs%?\\t%0, %1
321
   eor%?\\t%0, %1, #-2147483648"
322
  [(set_attr "predicable" "yes")
323
   (set_attr "type" "ffarith")]
324
)
325
 
326
(define_insn_and_split "*negdf2_vfp"
327
  [(set (match_operand:DF         0 "s_register_operand" "=w,?r,?r")
328
        (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
329
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
330
  "@
331
   fnegd%?\\t%P0, %P1
332
   #
333
   #"
334
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && reload_completed
335
   && arm_general_register_operand (operands[0], DFmode)"
336
  [(set (match_dup 0) (match_dup 1))]
337
  "
338
  if (REGNO (operands[0]) == REGNO (operands[1]))
339
    {
340
      operands[0] = gen_highpart (SImode, operands[0]);
341
      operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
342
    }
343
  else
344
    {
345
      rtx in_hi, in_lo, out_hi, out_lo;
346
 
347
      in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
348
                           GEN_INT (0x80000000));
349
      in_lo = gen_lowpart (SImode, operands[1]);
350
      out_hi = gen_highpart (SImode, operands[0]);
351
      out_lo = gen_lowpart (SImode, operands[0]);
352
 
353
      if (REGNO (in_lo) == REGNO (out_hi))
354
        {
355
          emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
356
          operands[0] = out_hi;
357
          operands[1] = in_hi;
358
        }
359
      else
360
        {
361
          emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
362
          operands[0] = out_lo;
363
          operands[1] = in_lo;
364
        }
365
    }
366
  "
367
  [(set_attr "predicable" "yes")
368
   (set_attr "length" "4,4,8")
369
   (set_attr "type" "ffarith")]
370
)
371
 
372
 
373
;; Arithmetic insns
374
 
375
(define_insn "*addsf3_vfp"
376
  [(set (match_operand:SF          0 "s_register_operand" "=w")
377
        (plus:SF (match_operand:SF 1 "s_register_operand" "w")
378
                 (match_operand:SF 2 "s_register_operand" "w")))]
379
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
380
  "fadds%?\\t%0, %1, %2"
381
  [(set_attr "predicable" "yes")
382
   (set_attr "type" "farith")]
383
)
384
 
385
(define_insn "*adddf3_vfp"
386
  [(set (match_operand:DF          0 "s_register_operand" "=w")
387
        (plus:DF (match_operand:DF 1 "s_register_operand" "w")
388
                 (match_operand:DF 2 "s_register_operand" "w")))]
389
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
390
  "faddd%?\\t%P0, %P1, %P2"
391
  [(set_attr "predicable" "yes")
392
   (set_attr "type" "farith")]
393
)
394
 
395
 
396
(define_insn "*subsf3_vfp"
397
  [(set (match_operand:SF           0 "s_register_operand" "=w")
398
        (minus:SF (match_operand:SF 1 "s_register_operand" "w")
399
                  (match_operand:SF 2 "s_register_operand" "w")))]
400
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
401
  "fsubs%?\\t%0, %1, %2"
402
  [(set_attr "predicable" "yes")
403
   (set_attr "type" "farith")]
404
)
405
 
406
(define_insn "*subdf3_vfp"
407
  [(set (match_operand:DF           0 "s_register_operand" "=w")
408
        (minus:DF (match_operand:DF 1 "s_register_operand" "w")
409
                  (match_operand:DF 2 "s_register_operand" "w")))]
410
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
411
  "fsubd%?\\t%P0, %P1, %P2"
412
  [(set_attr "predicable" "yes")
413
   (set_attr "type" "farith")]
414
)
415
 
416
 
417
;; Division insns
418
 
419
(define_insn "*divsf3_vfp"
420
  [(set (match_operand:SF         0 "s_register_operand" "+w")
421
        (div:SF (match_operand:SF 1 "s_register_operand" "w")
422
                (match_operand:SF 2 "s_register_operand" "w")))]
423
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
424
  "fdivs%?\\t%0, %1, %2"
425
  [(set_attr "predicable" "yes")
426
   (set_attr "type" "fdivs")]
427
)
428
 
429
(define_insn "*divdf3_vfp"
430
  [(set (match_operand:DF         0 "s_register_operand" "+w")
431
        (div:DF (match_operand:DF 1 "s_register_operand" "w")
432
                (match_operand:DF 2 "s_register_operand" "w")))]
433
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
434
  "fdivd%?\\t%P0, %P1, %P2"
435
  [(set_attr "predicable" "yes")
436
   (set_attr "type" "fdivd")]
437
)
438
 
439
 
440
;; Multiplication insns
441
 
442
(define_insn "*mulsf3_vfp"
443
  [(set (match_operand:SF          0 "s_register_operand" "+w")
444
        (mult:SF (match_operand:SF 1 "s_register_operand" "w")
445
                 (match_operand:SF 2 "s_register_operand" "w")))]
446
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
447
  "fmuls%?\\t%0, %1, %2"
448
  [(set_attr "predicable" "yes")
449
   (set_attr "type" "farith")]
450
)
451
 
452
(define_insn "*muldf3_vfp"
453
  [(set (match_operand:DF          0 "s_register_operand" "+w")
454
        (mult:DF (match_operand:DF 1 "s_register_operand" "w")
455
                 (match_operand:DF 2 "s_register_operand" "w")))]
456
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
457
  "fmuld%?\\t%P0, %P1, %P2"
458
  [(set_attr "predicable" "yes")
459
   (set_attr "type" "fmul")]
460
)
461
 
462
 
463
(define_insn "*mulsf3negsf_vfp"
464
  [(set (match_operand:SF                  0 "s_register_operand" "+w")
465
        (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "w"))
466
                 (match_operand:SF         2 "s_register_operand" "w")))]
467
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
468
  "fnmuls%?\\t%0, %1, %2"
469
  [(set_attr "predicable" "yes")
470
   (set_attr "type" "farith")]
471
)
472
 
473
(define_insn "*muldf3negdf_vfp"
474
  [(set (match_operand:DF                  0 "s_register_operand" "+w")
475
        (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
476
                 (match_operand:DF         2 "s_register_operand" "w")))]
477
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
478
  "fnmuld%?\\t%P0, %P1, %P2"
479
  [(set_attr "predicable" "yes")
480
   (set_attr "type" "fmul")]
481
)
482
 
483
 
484
;; Multiply-accumulate insns
485
 
486
;; 0 = 1 * 2 + 0
487
(define_insn "*mulsf3addsf_vfp"
488
  [(set (match_operand:SF                   0 "s_register_operand" "=w")
489
        (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "w")
490
                          (match_operand:SF 3 "s_register_operand" "w"))
491
                 (match_operand:SF          1 "s_register_operand" "0")))]
492
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
493
  "fmacs%?\\t%0, %2, %3"
494
  [(set_attr "predicable" "yes")
495
   (set_attr "type" "farith")]
496
)
497
 
498
(define_insn "*muldf3adddf_vfp"
499
  [(set (match_operand:DF                   0 "s_register_operand" "=w")
500
        (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
501
                          (match_operand:DF 3 "s_register_operand" "w"))
502
                 (match_operand:DF          1 "s_register_operand" "0")))]
503
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
504
  "fmacd%?\\t%P0, %P2, %P3"
505
  [(set_attr "predicable" "yes")
506
   (set_attr "type" "fmul")]
507
)
508
 
509
;; 0 = 1 * 2 - 0
510
(define_insn "*mulsf3subsf_vfp"
511
  [(set (match_operand:SF                    0 "s_register_operand" "=w")
512
        (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "w")
513
                           (match_operand:SF 3 "s_register_operand" "w"))
514
                  (match_operand:SF          1 "s_register_operand" "0")))]
515
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
516
  "fmscs%?\\t%0, %2, %3"
517
  [(set_attr "predicable" "yes")
518
   (set_attr "type" "farith")]
519
)
520
 
521
(define_insn "*muldf3subdf_vfp"
522
  [(set (match_operand:DF                    0 "s_register_operand" "=w")
523
        (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
524
                           (match_operand:DF 3 "s_register_operand" "w"))
525
                  (match_operand:DF          1 "s_register_operand" "0")))]
526
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
527
  "fmscd%?\\t%P0, %P2, %P3"
528
  [(set_attr "predicable" "yes")
529
   (set_attr "type" "fmul")]
530
)
531
 
532
;; 0 = -(1 * 2) + 0
533
(define_insn "*mulsf3negsfaddsf_vfp"
534
  [(set (match_operand:SF                    0 "s_register_operand" "=w")
535
        (minus:SF (match_operand:SF          1 "s_register_operand" "0")
536
                  (mult:SF (match_operand:SF 2 "s_register_operand" "w")
537
                           (match_operand:SF 3 "s_register_operand" "w"))))]
538
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
539
  "fnmacs%?\\t%0, %2, %3"
540
  [(set_attr "predicable" "yes")
541
   (set_attr "type" "farith")]
542
)
543
 
544
(define_insn "*fmuldf3negdfadddf_vfp"
545
  [(set (match_operand:DF                    0 "s_register_operand" "=w")
546
        (minus:DF (match_operand:DF          1 "s_register_operand" "0")
547
                  (mult:DF (match_operand:DF 2 "s_register_operand" "w")
548
                           (match_operand:DF 3 "s_register_operand" "w"))))]
549
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
550
  "fnmacd%?\\t%P0, %P2, %P3"
551
  [(set_attr "predicable" "yes")
552
   (set_attr "type" "fmul")]
553
)
554
 
555
 
556
;; 0 = -(1 * 2) - 0
557
(define_insn "*mulsf3negsfsubsf_vfp"
558
  [(set (match_operand:SF                     0 "s_register_operand" "=w")
559
        (minus:SF (mult:SF
560
                    (neg:SF (match_operand:SF 2 "s_register_operand" "w"))
561
                    (match_operand:SF         3 "s_register_operand" "w"))
562
                  (match_operand:SF           1 "s_register_operand" "0")))]
563
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
564
  "fnmscs%?\\t%0, %2, %3"
565
  [(set_attr "predicable" "yes")
566
   (set_attr "type" "farith")]
567
)
568
 
569
(define_insn "*muldf3negdfsubdf_vfp"
570
  [(set (match_operand:DF                     0 "s_register_operand" "=w")
571
        (minus:DF (mult:DF
572
                    (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
573
                    (match_operand:DF         3 "s_register_operand" "w"))
574
                  (match_operand:DF           1 "s_register_operand" "0")))]
575
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
576
  "fnmscd%?\\t%P0, %P2, %P3"
577
  [(set_attr "predicable" "yes")
578
   (set_attr "type" "fmul")]
579
)
580
 
581
 
582
;; Conversion routines
583
 
584
(define_insn "*extendsfdf2_vfp"
585
  [(set (match_operand:DF                  0 "s_register_operand" "=w")
586
        (float_extend:DF (match_operand:SF 1 "s_register_operand" "w")))]
587
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
588
  "fcvtds%?\\t%P0, %1"
589
  [(set_attr "predicable" "yes")
590
   (set_attr "type" "f_cvt")]
591
)
592
 
593
(define_insn "*truncdfsf2_vfp"
594
  [(set (match_operand:SF                  0 "s_register_operand" "=w")
595
        (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
596
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
597
  "fcvtsd%?\\t%0, %P1"
598
  [(set_attr "predicable" "yes")
599
   (set_attr "type" "f_cvt")]
600
)
601
 
602
(define_insn "*truncsisf2_vfp"
603
  [(set (match_operand:SI                 0 "s_register_operand" "=w")
604
        (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "w"))))]
605
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
606
  "ftosizs%?\\t%0, %1"
607
  [(set_attr "predicable" "yes")
608
   (set_attr "type" "f_cvt")]
609
)
610
 
611
(define_insn "*truncsidf2_vfp"
612
  [(set (match_operand:SI                 0 "s_register_operand" "=w")
613
        (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
614
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
615
  "ftosizd%?\\t%0, %P1"
616
  [(set_attr "predicable" "yes")
617
   (set_attr "type" "f_cvt")]
618
)
619
 
620
 
621
(define_insn "fixuns_truncsfsi2"
622
  [(set (match_operand:SI                 0 "s_register_operand" "=w")
623
        (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "w"))))]
624
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
625
  "ftouizs%?\\t%0, %1"
626
  [(set_attr "predicable" "yes")
627
   (set_attr "type" "f_cvt")]
628
)
629
 
630
(define_insn "fixuns_truncdfsi2"
631
  [(set (match_operand:SI                 0 "s_register_operand" "=w")
632
        (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
633
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
634
  "ftouizd%?\\t%0, %P1"
635
  [(set_attr "predicable" "yes")
636
   (set_attr "type" "f_cvt")]
637
)
638
 
639
 
640
(define_insn "*floatsisf2_vfp"
641
  [(set (match_operand:SF           0 "s_register_operand" "=w")
642
        (float:SF (match_operand:SI 1 "s_register_operand" "w")))]
643
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
644
  "fsitos%?\\t%0, %1"
645
  [(set_attr "predicable" "yes")
646
   (set_attr "type" "f_cvt")]
647
)
648
 
649
(define_insn "*floatsidf2_vfp"
650
  [(set (match_operand:DF           0 "s_register_operand" "=w")
651
        (float:DF (match_operand:SI 1 "s_register_operand" "w")))]
652
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
653
  "fsitod%?\\t%P0, %1"
654
  [(set_attr "predicable" "yes")
655
   (set_attr "type" "f_cvt")]
656
)
657
 
658
 
659
(define_insn "floatunssisf2"
660
  [(set (match_operand:SF           0 "s_register_operand" "=w")
661
        (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "w")))]
662
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
663
  "fuitos%?\\t%0, %1"
664
  [(set_attr "predicable" "yes")
665
   (set_attr "type" "f_cvt")]
666
)
667
 
668
(define_insn "floatunssidf2"
669
  [(set (match_operand:DF           0 "s_register_operand" "=w")
670
        (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "w")))]
671
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
672
  "fuitod%?\\t%P0, %1"
673
  [(set_attr "predicable" "yes")
674
   (set_attr "type" "f_cvt")]
675
)
676
 
677
 
678
;; Sqrt insns.
679
 
680
(define_insn "*sqrtsf2_vfp"
681
  [(set (match_operand:SF          0 "s_register_operand" "=w")
682
        (sqrt:SF (match_operand:SF 1 "s_register_operand" "w")))]
683
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
684
  "fsqrts%?\\t%0, %1"
685
  [(set_attr "predicable" "yes")
686
   (set_attr "type" "fdivs")]
687
)
688
 
689
(define_insn "*sqrtdf2_vfp"
690
  [(set (match_operand:DF          0 "s_register_operand" "=w")
691
        (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
692
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
693
  "fsqrtd%?\\t%P0, %P1"
694
  [(set_attr "predicable" "yes")
695
   (set_attr "type" "fdivd")]
696
)
697
 
698
 
699
;; Patterns to split/copy vfp condition flags.
700
 
701
(define_insn "*movcc_vfp"
702
  [(set (reg CC_REGNUM)
703
        (reg VFPCC_REGNUM))]
704
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
705
  "fmstat%?"
706
  [(set_attr "conds" "set")
707
   (set_attr "type" "f_flag")]
708
)
709
 
710
(define_insn_and_split "*cmpsf_split_vfp"
711
  [(set (reg:CCFP CC_REGNUM)
712
        (compare:CCFP (match_operand:SF 0 "s_register_operand"  "w")
713
                      (match_operand:SF 1 "vfp_compare_operand" "wG")))]
714
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
715
  "#"
716
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
717
  [(set (reg:CCFP VFPCC_REGNUM)
718
        (compare:CCFP (match_dup 0)
719
                      (match_dup 1)))
720
   (set (reg:CCFP CC_REGNUM)
721
        (reg:CCFP VFPCC_REGNUM))]
722
  ""
723
)
724
 
725
(define_insn_and_split "*cmpsf_trap_split_vfp"
726
  [(set (reg:CCFPE CC_REGNUM)
727
        (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "w")
728
                       (match_operand:SF 1 "vfp_compare_operand" "wG")))]
729
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
730
  "#"
731
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
732
  [(set (reg:CCFPE VFPCC_REGNUM)
733
        (compare:CCFPE (match_dup 0)
734
                       (match_dup 1)))
735
   (set (reg:CCFPE CC_REGNUM)
736
        (reg:CCFPE VFPCC_REGNUM))]
737
  ""
738
)
739
 
740
(define_insn_and_split "*cmpdf_split_vfp"
741
  [(set (reg:CCFP CC_REGNUM)
742
        (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w")
743
                      (match_operand:DF 1 "vfp_compare_operand" "wG")))]
744
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
745
  "#"
746
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
747
  [(set (reg:CCFP VFPCC_REGNUM)
748
        (compare:CCFP (match_dup 0)
749
                       (match_dup 1)))
750
   (set (reg:CCFP CC_REGNUM)
751
        (reg:CCFPE VFPCC_REGNUM))]
752
  ""
753
)
754
 
755
(define_insn_and_split "*cmpdf_trap_split_vfp"
756
  [(set (reg:CCFPE CC_REGNUM)
757
        (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w")
758
                       (match_operand:DF 1 "vfp_compare_operand" "wG")))]
759
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
760
  "#"
761
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
762
  [(set (reg:CCFPE VFPCC_REGNUM)
763
        (compare:CCFPE (match_dup 0)
764
                       (match_dup 1)))
765
   (set (reg:CCFPE CC_REGNUM)
766
        (reg:CCFPE VFPCC_REGNUM))]
767
  ""
768
)
769
 
770
 
771
;; Comparison patterns
772
 
773
(define_insn "*cmpsf_vfp"
774
  [(set (reg:CCFP VFPCC_REGNUM)
775
        (compare:CCFP (match_operand:SF 0 "s_register_operand"  "w,w")
776
                      (match_operand:SF 1 "vfp_compare_operand" "w,G")))]
777
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
778
  "@
779
   fcmps%?\\t%0, %1
780
   fcmpzs%?\\t%0"
781
  [(set_attr "predicable" "yes")
782
   (set_attr "type" "ffarith")]
783
)
784
 
785
(define_insn "*cmpsf_trap_vfp"
786
  [(set (reg:CCFPE VFPCC_REGNUM)
787
        (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "w,w")
788
                       (match_operand:SF 1 "vfp_compare_operand" "w,G")))]
789
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
790
  "@
791
   fcmpes%?\\t%0, %1
792
   fcmpezs%?\\t%0"
793
  [(set_attr "predicable" "yes")
794
   (set_attr "type" "ffarith")]
795
)
796
 
797
(define_insn "*cmpdf_vfp"
798
  [(set (reg:CCFP VFPCC_REGNUM)
799
        (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w,w")
800
                      (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
801
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
802
  "@
803
   fcmpd%?\\t%P0, %P1
804
   fcmpzd%?\\t%P0"
805
  [(set_attr "predicable" "yes")
806
   (set_attr "type" "ffarith")]
807
)
808
 
809
(define_insn "*cmpdf_trap_vfp"
810
  [(set (reg:CCFPE VFPCC_REGNUM)
811
        (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w,w")
812
                       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
813
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
814
  "@
815
   fcmped%?\\t%P0, %P1
816
   fcmpezd%?\\t%P0"
817
  [(set_attr "predicable" "yes")
818
   (set_attr "type" "ffarith")]
819
)
820
 
821
 
822
;; Store multiple insn used in function prologue.
823
 
824
(define_insn "*push_multi_vfp"
825
  [(match_parallel 2 "multi_register_push"
826
    [(set (match_operand:BLK 0 "memory_operand" "=m")
827
          (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")]
828
                      UNSPEC_PUSH_MULT))])]
829
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
830
  "* return vfp_output_fstmx (operands);"
831
  [(set_attr "type" "f_stored")]
832
)
833
 
834
 
835
;; Unimplemented insns:
836
;; fldm*
837
;; fstm*
838
;; fmdhr et al (VFPv1)
839
;; Support for xD (single precision only) variants.
840
;; fmrrs, fmsrr

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