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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [ia64/] [ia64.h] - Blame information for rev 816

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/* Definitions of target machine GNU compiler.  IA-64 version.
2
   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3
   2007 Free Software Foundation, Inc.
4
   Contributed by James E. Wilson <wilson@cygnus.com> and
5
                  David Mosberger <davidm@hpl.hp.com>.
6
 
7
This file is part of GCC.
8
 
9
GCC is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 3, or (at your option)
12
any later version.
13
 
14
GCC is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with GCC; see the file COPYING3.  If not see
21
<http://www.gnu.org/licenses/>.  */
22
 
23
/* ??? Look at ABI group documents for list of preprocessor macros and
24
   other features required for ABI compliance.  */
25
 
26
/* ??? Functions containing a non-local goto target save many registers.  Why?
27
   See for instance execute/920428-2.c.  */
28
 
29
 
30
/* Run-time target specifications */
31
 
32
/* Target CPU builtins.  */
33
#define TARGET_CPU_CPP_BUILTINS()               \
34
do {                                            \
35
        builtin_assert("cpu=ia64");             \
36
        builtin_assert("machine=ia64");         \
37
        builtin_define("__ia64");               \
38
        builtin_define("__ia64__");             \
39
        builtin_define("__itanium__");          \
40
        if (TARGET_BIG_ENDIAN)                  \
41
          builtin_define("__BIG_ENDIAN__");     \
42
} while (0)
43
 
44
#ifndef SUBTARGET_EXTRA_SPECS
45
#define SUBTARGET_EXTRA_SPECS
46
#endif
47
 
48
#define EXTRA_SPECS \
49
  { "asm_extra", ASM_EXTRA_SPEC }, \
50
  SUBTARGET_EXTRA_SPECS
51
 
52
#define CC1_SPEC "%(cc1_cpu) "
53
 
54
#define ASM_EXTRA_SPEC ""
55
 
56
/* Variables which are this size or smaller are put in the sdata/sbss
57
   sections.  */
58
extern unsigned int ia64_section_threshold;
59
 
60
/* If the assembler supports thread-local storage, assume that the
61
   system does as well.  If a particular target system has an
62
   assembler that supports TLS -- but the rest of the system does not
63
   support TLS -- that system should explicit define TARGET_HAVE_TLS
64
   to false in its own configuration file.  */
65
#if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
66
#define TARGET_HAVE_TLS true
67
#endif
68
 
69
#define TARGET_TLS14            (ia64_tls_size == 14)
70
#define TARGET_TLS22            (ia64_tls_size == 22)
71
#define TARGET_TLS64            (ia64_tls_size == 64)
72
 
73
#define TARGET_HPUX             0
74
#define TARGET_HPUX_LD          0
75
 
76
#ifndef TARGET_ILP32
77
#define TARGET_ILP32 0
78
#endif
79
 
80
#ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
81
#define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
82
#endif
83
 
84
/* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and
85
   TARGET_INLINE_SQRT.  */
86
 
87
enum ia64_inline_type
88
{
89
  INL_NO = 0,
90
  INL_MIN_LAT = 1,
91
  INL_MAX_THR = 2
92
};
93
 
94
/* Default target_flags if no switches are specified  */
95
 
96
#ifndef TARGET_DEFAULT
97
#define TARGET_DEFAULT (MASK_DWARF2_ASM)
98
#endif
99
 
100
#ifndef TARGET_CPU_DEFAULT
101
#define TARGET_CPU_DEFAULT 0
102
#endif
103
 
104
/* Which processor to schedule for. The cpu attribute defines a list
105
   that mirrors this list, so changes to ia64.md must be made at the
106
   same time.  */
107
 
108
enum processor_type
109
{
110
  PROCESSOR_ITANIUM,                    /* Original Itanium.  */
111
  PROCESSOR_ITANIUM2,
112
  PROCESSOR_max
113
};
114
 
115
extern enum processor_type ia64_tune;
116
 
117
/* Sometimes certain combinations of command options do not make sense on a
118
   particular target machine.  You can define a macro `OVERRIDE_OPTIONS' to
119
   take account of this.  This macro, if defined, is executed once just after
120
   all the command options have been parsed.  */
121
 
122
#define OVERRIDE_OPTIONS ia64_override_options ()
123
 
124
/* Some machines may desire to change what optimizations are performed for
125
   various optimization levels.  This macro, if defined, is executed once just
126
   after the optimization level is determined and before the remainder of the
127
   command options have been parsed.  Values set in this macro are used as the
128
   default values for the other command line options.  */
129
 
130
/* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
131
 
132
/* Driver configuration */
133
 
134
/* A C string constant that tells the GCC driver program options to pass to
135
   `cc1'.  It can also specify how to translate options you give to GCC into
136
   options for GCC to pass to the `cc1'.  */
137
 
138
#undef CC1_SPEC
139
#define CC1_SPEC "%{G*}"
140
 
141
/* A C string constant that tells the GCC driver program options to pass to
142
   `cc1plus'.  It can also specify how to translate options you give to GCC
143
   into options for GCC to pass to the `cc1plus'.  */
144
 
145
/* #define CC1PLUS_SPEC "" */
146
 
147
/* Storage Layout */
148
 
149
/* Define this macro to have the value 1 if the most significant bit in a byte
150
   has the lowest number; otherwise define it to have the value zero.  */
151
 
152
#define BITS_BIG_ENDIAN 0
153
 
154
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
155
 
156
/* Define this macro to have the value 1 if, in a multiword object, the most
157
   significant word has the lowest number.  */
158
 
159
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
160
 
161
#if defined(__BIG_ENDIAN__)
162
#define LIBGCC2_WORDS_BIG_ENDIAN 1
163
#else
164
#define LIBGCC2_WORDS_BIG_ENDIAN 0
165
#endif
166
 
167
#define UNITS_PER_WORD 8
168
 
169
#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
170
 
171
/* A C expression whose value is zero if pointers that need to be extended
172
   from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
173
   they are zero-extended and negative one if there is a ptr_extend operation.
174
 
175
   You need not define this macro if the `POINTER_SIZE' is equal to the width
176
   of `Pmode'.  */
177
/* Need this for 32 bit pointers, see hpux.h for setting it.  */
178
/* #define POINTERS_EXTEND_UNSIGNED */
179
 
180
/* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
181
   which has the specified mode and signedness is to be stored in a register.
182
   This macro is only called when TYPE is a scalar type.  */
183
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)                               \
184
do                                                                      \
185
  {                                                                     \
186
    if (GET_MODE_CLASS (MODE) == MODE_INT                               \
187
        && GET_MODE_SIZE (MODE) < 4)                                    \
188
      (MODE) = SImode;                                                  \
189
  }                                                                     \
190
while (0)
191
 
192
#define PARM_BOUNDARY 64
193
 
194
/* Define this macro if you wish to preserve a certain alignment for the stack
195
   pointer.  The definition is a C expression for the desired alignment
196
   (measured in bits).  */
197
 
198
#define STACK_BOUNDARY 128
199
 
200
/* Align frames on double word boundaries */
201
#ifndef IA64_STACK_ALIGN
202
#define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
203
#endif
204
 
205
#define FUNCTION_BOUNDARY 128
206
 
207
/* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
208
   128 bit integers all require 128 bit alignment.  */
209
#define BIGGEST_ALIGNMENT 128
210
 
211
/* If defined, a C expression to compute the alignment for a static variable.
212
   TYPE is the data type, and ALIGN is the alignment that the object
213
   would ordinarily have.  The value of this macro is used instead of that
214
   alignment to align the object.  */
215
 
216
#define DATA_ALIGNMENT(TYPE, ALIGN)             \
217
  (TREE_CODE (TYPE) == ARRAY_TYPE               \
218
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode    \
219
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
220
 
221
/* If defined, a C expression to compute the alignment given to a constant that
222
   is being placed in memory.  CONSTANT is the constant and ALIGN is the
223
   alignment that the object would ordinarily have.  The value of this macro is
224
   used instead of that alignment to align the object.  */
225
 
226
#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
227
  (TREE_CODE (EXP) == STRING_CST        \
228
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
229
 
230
#define STRICT_ALIGNMENT 1
231
 
232
/* Define this if you wish to imitate the way many other C compilers handle
233
   alignment of bitfields and the structures that contain them.
234
   The behavior is that the type written for a bit-field (`int', `short', or
235
   other integer type) imposes an alignment for the entire structure, as if the
236
   structure really did contain an ordinary field of that type.  In addition,
237
   the bit-field is placed within the structure so that it would fit within such
238
   a field, not crossing a boundary for it.  */
239
#define PCC_BITFIELD_TYPE_MATTERS 1
240
 
241
/* An integer expression for the size in bits of the largest integer machine
242
   mode that should actually be used.  */
243
 
244
/* Allow pairs of registers to be used, which is the intent of the default.  */
245
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
246
 
247
/* By default, the C++ compiler will use function addresses in the
248
   vtable entries.  Setting this nonzero tells the compiler to use
249
   function descriptors instead.  The value of this macro says how
250
   many words wide the descriptor is (normally 2).  It is assumed
251
   that the address of a function descriptor may be treated as a
252
   pointer to a function.
253
 
254
   For reasons known only to HP, the vtable entries (as opposed to
255
   normal function descriptors) are 16 bytes wide in 32-bit mode as
256
   well, even though the 3rd and 4th words are unused.  */
257
#define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
258
 
259
/* Due to silliness in the HPUX linker, vtable entries must be
260
   8-byte aligned even in 32-bit mode.  Rather than create multiple
261
   ABIs, force this restriction on everyone else too.  */
262
#define TARGET_VTABLE_ENTRY_ALIGN  64
263
 
264
/* Due to the above, we need extra padding for the data entries below 0
265
   to retain the alignment of the descriptors.  */
266
#define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
267
 
268
/* Layout of Source Language Data Types */
269
 
270
#define INT_TYPE_SIZE 32
271
 
272
#define SHORT_TYPE_SIZE 16
273
 
274
#define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
275
 
276
#define LONG_LONG_TYPE_SIZE 64
277
 
278
#define FLOAT_TYPE_SIZE 32
279
 
280
#define DOUBLE_TYPE_SIZE 64
281
 
282
/* long double is XFmode normally, TFmode for HPUX.  */
283
#define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 80)
284
 
285
/* We always want the XFmode operations from libgcc2.c.  */
286
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
287
 
288
#define DEFAULT_SIGNED_CHAR 1
289
 
290
/* A C expression for a string describing the name of the data type to use for
291
   size values.  The typedef name `size_t' is defined using the contents of the
292
   string.  */
293
/* ??? Needs to be defined for P64 code.  */
294
/* #define SIZE_TYPE */
295
 
296
/* A C expression for a string describing the name of the data type to use for
297
   the result of subtracting two pointers.  The typedef name `ptrdiff_t' is
298
   defined using the contents of the string.  See `SIZE_TYPE' above for more
299
   information.  */
300
/* ??? Needs to be defined for P64 code.  */
301
/* #define PTRDIFF_TYPE */
302
 
303
/* A C expression for a string describing the name of the data type to use for
304
   wide characters.  The typedef name `wchar_t' is defined using the contents
305
   of the string.  See `SIZE_TYPE' above for more information.  */
306
/* #define WCHAR_TYPE */
307
 
308
/* A C expression for the size in bits of the data type for wide characters.
309
   This is used in `cpp', which cannot make use of `WCHAR_TYPE'.  */
310
/* #define WCHAR_TYPE_SIZE */
311
 
312
 
313
/* Register Basics */
314
 
315
/* Number of hardware registers known to the compiler.
316
   We have 128 general registers, 128 floating point registers,
317
   64 predicate registers, 8 branch registers, one frame pointer,
318
   and several "application" registers.  */
319
 
320
#define FIRST_PSEUDO_REGISTER 334
321
 
322
/* Ranges for the various kinds of registers.  */
323
#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
324
#define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
325
#define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
326
#define FP_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 254 && (REGNO) != 159)
327
#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
328
#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
329
#define GENERAL_REGNO_P(REGNO) \
330
  (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
331
 
332
#define GR_REG(REGNO) ((REGNO) + 0)
333
#define FR_REG(REGNO) ((REGNO) + 128)
334
#define PR_REG(REGNO) ((REGNO) + 256)
335
#define BR_REG(REGNO) ((REGNO) + 320)
336
#define OUT_REG(REGNO) ((REGNO) + 120)
337
#define IN_REG(REGNO) ((REGNO) + 112)
338
#define LOC_REG(REGNO) ((REGNO) + 32)
339
 
340
#define AR_CCV_REGNUM   329
341
#define AR_UNAT_REGNUM  330
342
#define AR_PFS_REGNUM   331
343
#define AR_LC_REGNUM    332
344
#define AR_EC_REGNUM    333
345
 
346
#define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
347
#define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
348
#define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
349
 
350
#define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
351
                             || (REGNO) == AR_UNAT_REGNUM)
352
#define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
353
                             && (REGNO) < FIRST_PSEUDO_REGISTER)
354
#define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
355
                           && (REGNO) < FIRST_PSEUDO_REGISTER)
356
 
357
 
358
/* ??? Don't really need two sets of macros.  I like this one better because
359
   it is less typing.  */
360
#define R_GR(REGNO) GR_REG (REGNO)
361
#define R_FR(REGNO) FR_REG (REGNO)
362
#define R_PR(REGNO) PR_REG (REGNO)
363
#define R_BR(REGNO) BR_REG (REGNO)
364
 
365
/* An initializer that says which registers are used for fixed purposes all
366
   throughout the compiled code and are therefore not available for general
367
   allocation.
368
 
369
   r0: constant 0
370
   r1: global pointer (gp)
371
   r12: stack pointer (sp)
372
   r13: thread pointer (tp)
373
   f0: constant 0.0
374
   f1: constant 1.0
375
   p0: constant true
376
   fp: eliminable frame pointer */
377
 
378
/* The last 16 stacked regs are reserved for the 8 input and 8 output
379
   registers.  */
380
 
381
#define FIXED_REGISTERS \
382
{ /* General registers.  */                             \
383
  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0,   \
384
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
385
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
386
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
387
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
388
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
389
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
390
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
391
  /* Floating-point registers.  */                      \
392
  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,     \
393
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
394
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
395
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
396
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
397
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
398
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
399
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
400
  /* Predicate registers.  */                           \
401
  1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,      \
402
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
403
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
404
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
405
  /* Branch registers.  */                              \
406
  0, 0, 0, 0, 0, 0, 0, 0,                               \
407
  /*FP CCV UNAT PFS LC EC */                            \
408
     1,  1,   1,  1, 0, 1                                \
409
 }
410
 
411
/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
412
   (in general) by function calls as well as for fixed registers.  This
413
   macro therefore identifies the registers that are not available for
414
   general allocation of values that must live across function calls.  */
415
 
416
#define CALL_USED_REGISTERS \
417
{ /* General registers.  */                             \
418
  1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,   \
419
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
420
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
421
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
422
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
423
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
424
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
425
  0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,       \
426
  /* Floating-point registers.  */                      \
427
  1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   \
428
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
429
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
430
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
431
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
432
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
433
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
434
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
435
  /* Predicate registers.  */                           \
436
  1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,    \
437
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
438
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
439
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
440
  /* Branch registers.  */                              \
441
  1, 0, 0, 0, 0, 0, 1, 1,                            \
442
  /*FP CCV UNAT PFS LC EC */                            \
443
     1,  1,   1,  1, 0, 1                                \
444
}
445
 
446
/* Like `CALL_USED_REGISTERS' but used to overcome a historical
447
   problem which makes CALL_USED_REGISTERS *always* include
448
   all the FIXED_REGISTERS.  Until this problem has been
449
   resolved this macro can be used to overcome this situation.
450
   In particular, block_propagate() requires this list
451
   be accurate, or we can remove registers which should be live.
452
   This macro is used in regs_invalidated_by_call.  */
453
 
454
#define CALL_REALLY_USED_REGISTERS \
455
{ /* General registers.  */                             \
456
  0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1,      \
457
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
458
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
459
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
460
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
461
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
462
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
463
  0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,       \
464
  /* Floating-point registers.  */                      \
465
  0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,     \
466
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
467
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
468
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
469
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
470
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
471
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
472
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,       \
473
  /* Predicate registers.  */                           \
474
  0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,     \
475
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
476
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
477
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,       \
478
  /* Branch registers.  */                              \
479
  1, 0, 0, 0, 0, 0, 1, 1,                            \
480
  /*FP CCV UNAT PFS LC EC */                            \
481
     0,  1,   0,  1, 0, 0                           \
482
}
483
 
484
 
485
/* Define this macro if the target machine has register windows.  This C
486
   expression returns the register number as seen by the called function
487
   corresponding to the register number OUT as seen by the calling function.
488
   Return OUT if register number OUT is not an outbound register.  */
489
 
490
#define INCOMING_REGNO(OUT) \
491
  ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
492
 
493
/* Define this macro if the target machine has register windows.  This C
494
   expression returns the register number as seen by the calling function
495
   corresponding to the register number IN as seen by the called function.
496
   Return IN if register number IN is not an inbound register.  */
497
 
498
#define OUTGOING_REGNO(IN) \
499
  ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
500
 
501
/* Define this macro if the target machine has register windows.  This
502
   C expression returns true if the register is call-saved but is in the
503
   register window.  */
504
 
505
#define LOCAL_REGNO(REGNO) \
506
  (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
507
 
508
/* We define CCImode in ia64-modes.def so we need a selector.  */
509
 
510
#define SELECT_CC_MODE(OP,X,Y)  CCmode
511
 
512
/* Order of allocation of registers */
513
 
514
/* If defined, an initializer for a vector of integers, containing the numbers
515
   of hard registers in the order in which GCC should prefer to use them
516
   (from most preferred to least).
517
 
518
   If this macro is not defined, registers are used lowest numbered first (all
519
   else being equal).
520
 
521
   One use of this macro is on machines where the highest numbered registers
522
   must always be saved and the save-multiple-registers instruction supports
523
   only sequences of consecutive registers.  On such machines, define
524
   `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
525
   allocatable register first.  */
526
 
527
/* ??? Should the GR return value registers come before or after the rest
528
   of the caller-save GRs?  */
529
 
530
#define REG_ALLOC_ORDER                                                    \
531
{                                                                          \
532
  /* Caller-saved general registers.  */                                   \
533
  R_GR (14), R_GR (15), R_GR (16), R_GR (17),                              \
534
  R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23),        \
535
  R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29),        \
536
  R_GR (30), R_GR (31),                                                    \
537
  /* Output registers.  */                                                 \
538
  R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125),  \
539
  R_GR (126), R_GR (127),                                                  \
540
  /* Caller-saved general registers, also used for return values.  */      \
541
  R_GR (8), R_GR (9), R_GR (10), R_GR (11),                                \
542
  /* addl caller-saved general registers.  */                              \
543
  R_GR (2), R_GR (3),                                                      \
544
  /* Caller-saved FP registers.  */                                        \
545
  R_FR (6), R_FR (7),                                                      \
546
  /* Caller-saved FP registers, used for parameters and return values.  */ \
547
  R_FR (8), R_FR (9), R_FR (10), R_FR (11),                                \
548
  R_FR (12), R_FR (13), R_FR (14), R_FR (15),                              \
549
  /* Rotating caller-saved FP registers.  */                               \
550
  R_FR (32), R_FR (33), R_FR (34), R_FR (35),                              \
551
  R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41),        \
552
  R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47),        \
553
  R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53),        \
554
  R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59),        \
555
  R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65),        \
556
  R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71),        \
557
  R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77),        \
558
  R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83),        \
559
  R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89),        \
560
  R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95),        \
561
  R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101),      \
562
  R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107),  \
563
  R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113),  \
564
  R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119),  \
565
  R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125),  \
566
  R_FR (126), R_FR (127),                                                  \
567
  /* Caller-saved predicate registers.  */                                 \
568
  R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11),            \
569
  R_PR (12), R_PR (13), R_PR (14), R_PR (15),                              \
570
  /* Rotating caller-saved predicate registers.  */                        \
571
  R_PR (16), R_PR (17),                                                    \
572
  R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23),        \
573
  R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29),        \
574
  R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35),        \
575
  R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41),        \
576
  R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47),        \
577
  R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53),        \
578
  R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59),        \
579
  R_PR (60), R_PR (61), R_PR (62), R_PR (63),                              \
580
  /* Caller-saved branch registers.  */                                    \
581
  R_BR (6), R_BR (7),                                                      \
582
                                                                           \
583
  /* Stacked callee-saved general registers.  */                           \
584
  R_GR (32), R_GR (33), R_GR (34), R_GR (35),                              \
585
  R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41),        \
586
  R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47),        \
587
  R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53),        \
588
  R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59),        \
589
  R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65),        \
590
  R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71),        \
591
  R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77),        \
592
  R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83),        \
593
  R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89),        \
594
  R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95),        \
595
  R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101),      \
596
  R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107),  \
597
  R_GR (108),                                                              \
598
  /* Input registers.  */                                                  \
599
  R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117),  \
600
  R_GR (118), R_GR (119),                                                  \
601
  /* Callee-saved general registers.  */                                   \
602
  R_GR (4), R_GR (5), R_GR (6), R_GR (7),                                  \
603
  /* Callee-saved FP registers.  */                                        \
604
  R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17),            \
605
  R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23),        \
606
  R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29),        \
607
  R_FR (30), R_FR (31),                                                    \
608
  /* Callee-saved predicate registers.  */                                 \
609
  R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5),                        \
610
  /* Callee-saved branch registers.  */                                    \
611
  R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5),                        \
612
                                                                           \
613
  /* ??? Stacked registers reserved for fp, rp, and ar.pfs.  */            \
614
  R_GR (109), R_GR (110), R_GR (111),                                      \
615
                                                                           \
616
  /* Special general registers.  */                                        \
617
  R_GR (0), R_GR (1), R_GR (12), R_GR (13),                                 \
618
  /* Special FP registers.  */                                             \
619
  R_FR (0), R_FR (1),                                                       \
620
  /* Special predicate registers.  */                                      \
621
  R_PR (0),                                                                 \
622
  /* Special branch registers.  */                                         \
623
  R_BR (0),                                                                 \
624
  /* Other fixed registers.  */                                            \
625
  FRAME_POINTER_REGNUM,                                                    \
626
  AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM,              \
627
  AR_EC_REGNUM                                                             \
628
}
629
 
630
/* How Values Fit in Registers */
631
 
632
/* A C expression for the number of consecutive hard registers, starting at
633
   register number REGNO, required to hold a value of mode MODE.  */
634
 
635
/* ??? We say that BImode PR values require two registers.  This allows us to
636
   easily store the normal and inverted values.  We use CCImode to indicate
637
   a single predicate register.  */
638
 
639
#define HARD_REGNO_NREGS(REGNO, MODE)                                   \
640
  ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64                        \
641
   : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2                         \
642
   : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1                        \
643
   : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1                         \
644
   : FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2                         \
645
   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
646
 
647
/* A C expression that is nonzero if it is permissible to store a value of mode
648
   MODE in hard register number REGNO (or in several registers starting with
649
   that one).  */
650
 
651
#define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
652
  (FR_REGNO_P (REGNO) ?                                         \
653
     GET_MODE_CLASS (MODE) != MODE_CC &&                        \
654
     (MODE) != BImode &&                                        \
655
     (MODE) != TFmode                                           \
656
   : PR_REGNO_P (REGNO) ?                                       \
657
     (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC       \
658
   : GR_REGNO_P (REGNO) ?                                       \
659
     (MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode  \
660
   : AR_REGNO_P (REGNO) ? (MODE) == DImode                      \
661
   : BR_REGNO_P (REGNO) ? (MODE) == DImode                      \
662
   : 0)
663
 
664
/* A C expression that is nonzero if it is desirable to choose register
665
   allocation so as to avoid move instructions between a value of mode MODE1
666
   and a value of mode MODE2.
667
 
668
   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
669
   ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
670
   zero.  */
671
/* Don't tie integer and FP modes, as that causes us to get integer registers
672
   allocated for FP instructions.  XFmode only supported in FP registers so
673
   we can't tie it with any other modes.  */
674
#define MODES_TIEABLE_P(MODE1, MODE2)                   \
675
  (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)     \
676
   && ((((MODE1) == XFmode) || ((MODE1) == XCmode))     \
677
       == (((MODE2) == XFmode) || ((MODE2) == XCmode))) \
678
   && (((MODE1) == BImode) == ((MODE2) == BImode)))
679
 
680
/* Specify the modes required to caller save a given hard regno.
681
   We need to ensure floating pt regs are not saved as DImode.  */
682
 
683
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
684
  ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode        \
685
   : choose_hard_reg_mode ((REGNO), (NREGS), false))
686
 
687
/* Handling Leaf Functions */
688
 
689
/* A C initializer for a vector, indexed by hard register number, which
690
   contains 1 for a register that is allowable in a candidate for leaf function
691
   treatment.  */
692
/* ??? This might be useful.  */
693
/* #define LEAF_REGISTERS */
694
 
695
/* A C expression whose value is the register number to which REGNO should be
696
   renumbered, when a function is treated as a leaf function.  */
697
/* ??? This might be useful.  */
698
/* #define LEAF_REG_REMAP(REGNO) */
699
 
700
 
701
/* Register Classes */
702
 
703
/* An enumeral type that must be defined with all the register class names as
704
   enumeral values.  `NO_REGS' must be first.  `ALL_REGS' must be the last
705
   register class, followed by one more enumeral value, `LIM_REG_CLASSES',
706
   which is not a register class but rather tells how many classes there
707
   are.  */
708
/* ??? When compiling without optimization, it is possible for the only use of
709
   a pseudo to be a parameter load from the stack with a REG_EQUIV note.
710
   Regclass handles this case specially and does not assign any costs to the
711
   pseudo.  The pseudo then ends up using the last class before ALL_REGS.
712
   Thus we must not let either PR_REGS or BR_REGS be the last class.  The
713
   testcase for this is gcc.c-torture/execute/va-arg-7.c.  */
714
enum reg_class
715
{
716
  NO_REGS,
717
  PR_REGS,
718
  BR_REGS,
719
  AR_M_REGS,
720
  AR_I_REGS,
721
  ADDL_REGS,
722
  GR_REGS,
723
  FP_REGS,
724
  FR_REGS,
725
  GR_AND_BR_REGS,
726
  GR_AND_FR_REGS,
727
  ALL_REGS,
728
  LIM_REG_CLASSES
729
};
730
 
731
#define GENERAL_REGS GR_REGS
732
 
733
/* The number of distinct register classes.  */
734
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
735
 
736
/* An initializer containing the names of the register classes as C string
737
   constants.  These names are used in writing some of the debugging dumps.  */
738
#define REG_CLASS_NAMES \
739
{ "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
740
  "ADDL_REGS", "GR_REGS", "FP_REGS", "FR_REGS", \
741
  "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
742
 
743
/* An initializer containing the contents of the register classes, as integers
744
   which are bit masks.  The Nth integer specifies the contents of class N.
745
   The way the integer MASK is interpreted is that register R is in the class
746
   if `MASK & (1 << R)' is 1.  */
747
#define REG_CLASS_CONTENTS \
748
{                                                       \
749
  /* NO_REGS.  */                                       \
750
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
751
    0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
752
    0x00000000, 0x00000000, 0x0000 },                   \
753
  /* PR_REGS.  */                                       \
754
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
755
    0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
756
    0xFFFFFFFF, 0xFFFFFFFF, 0x0000 },                   \
757
  /* BR_REGS.  */                                       \
758
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
759
    0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
760
    0x00000000, 0x00000000, 0x00FF },                   \
761
  /* AR_M_REGS.  */                                     \
762
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
763
    0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
764
    0x00000000, 0x00000000, 0x0600 },                   \
765
  /* AR_I_REGS.  */                                     \
766
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
767
    0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
768
    0x00000000, 0x00000000, 0x3800 },                   \
769
  /* ADDL_REGS.  */                                     \
770
  { 0x0000000F, 0x00000000, 0x00000000, 0x00000000,     \
771
    0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
772
    0x00000000, 0x00000000, 0x0000 },                   \
773
  /* GR_REGS.  */                                       \
774
  { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
775
    0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
776
    0x00000000, 0x00000000, 0x0100 },                   \
777
  /* FP_REGS.  */                                       \
778
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
779
    0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF,     \
780
    0x00000000, 0x00000000, 0x0000 },                   \
781
  /* FR_REGS.  */                                       \
782
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
783
    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
784
    0x00000000, 0x00000000, 0x0000 },                   \
785
  /* GR_AND_BR_REGS.  */                                \
786
  { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
787
    0x00000000, 0x00000000, 0x00000000, 0x00000000,     \
788
    0x00000000, 0x00000000, 0x01FF },                   \
789
  /* GR_AND_FR_REGS.  */                                \
790
  { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
791
    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
792
    0x00000000, 0x00000000, 0x0100 },                   \
793
  /* ALL_REGS.  */                                      \
794
  { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
795
    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     \
796
    0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF },                   \
797
}
798
 
799
/* A C expression whose value is a register class containing hard register
800
   REGNO.  In general there is more than one such class; choose a class which
801
   is "minimal", meaning that no smaller class also contains the register.  */
802
/* The NO_REGS case is primarily for the benefit of rws_access_reg, which
803
   may call here with private (invalid) register numbers, such as
804
   REG_VOLATILE.  */
805
#define REGNO_REG_CLASS(REGNO) \
806
(ADDL_REGNO_P (REGNO) ? ADDL_REGS       \
807
 : GENERAL_REGNO_P (REGNO) ? GR_REGS    \
808
 : FR_REGNO_P (REGNO) ? (REGNO) != R_FR (31) \
809
                        && (REGNO) != R_FR(127) ? FP_REGS : FR_REGS \
810
 : PR_REGNO_P (REGNO) ? PR_REGS         \
811
 : BR_REGNO_P (REGNO) ? BR_REGS         \
812
 : AR_M_REGNO_P (REGNO) ? AR_M_REGS     \
813
 : AR_I_REGNO_P (REGNO) ? AR_I_REGS     \
814
 : NO_REGS)
815
 
816
/* A macro whose definition is the name of the class to which a valid base
817
   register must belong.  A base register is one used in an address which is
818
   the register value plus a displacement.  */
819
#define BASE_REG_CLASS GENERAL_REGS
820
 
821
/* A macro whose definition is the name of the class to which a valid index
822
   register must belong.  An index register is one used in an address where its
823
   value is either multiplied by a scale factor or added to another register
824
   (as well as added to a displacement).  This is needed for POST_MODIFY.  */
825
#define INDEX_REG_CLASS GENERAL_REGS
826
 
827
/* A C expression which defines the machine-dependent operand constraint
828
   letters for register classes.  If CHAR is such a letter, the value should be
829
   the register class corresponding to it.  Otherwise, the value should be
830
   `NO_REGS'.  The register letter `r', corresponding to class `GENERAL_REGS',
831
   will not be passed to this macro; you do not need to handle it.  */
832
 
833
#define REG_CLASS_FROM_LETTER(CHAR) \
834
((CHAR) == 'f' ? FR_REGS                \
835
 : (CHAR) == 'a' ? ADDL_REGS            \
836
 : (CHAR) == 'b' ? BR_REGS              \
837
 : (CHAR) == 'c' ? PR_REGS              \
838
 : (CHAR) == 'd' ? AR_M_REGS            \
839
 : (CHAR) == 'e' ? AR_I_REGS            \
840
 : (CHAR) == 'x' ? FP_REGS              \
841
 : NO_REGS)
842
 
843
/* A C expression which is nonzero if register number NUM is suitable for use
844
   as a base register in operand addresses.  It may be either a suitable hard
845
   register or a pseudo register that has been allocated such a hard reg.  */
846
#define REGNO_OK_FOR_BASE_P(REGNO) \
847
  (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
848
 
849
/* A C expression which is nonzero if register number NUM is suitable for use
850
   as an index register in operand addresses.  It may be either a suitable hard
851
   register or a pseudo register that has been allocated such a hard reg.
852
   This is needed for POST_MODIFY.  */
853
#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
854
 
855
/* A C expression that places additional restrictions on the register class to
856
   use when it is necessary to copy value X into a register in class CLASS.
857
   The value is a register class; perhaps CLASS, or perhaps another, smaller
858
   class.  */
859
 
860
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
861
  ia64_preferred_reload_class (X, CLASS)
862
 
863
/* You should define this macro to indicate to the reload phase that it may
864
   need to allocate at least one register for a reload in addition to the
865
   register to contain the data.  Specifically, if copying X to a register
866
   CLASS in MODE requires an intermediate register, you should define this
867
   to return the largest register class all of whose registers can be used
868
   as intermediate registers or scratch registers.  */
869
 
870
#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
871
 ia64_secondary_reload_class (CLASS, MODE, X)
872
 
873
/* Certain machines have the property that some registers cannot be copied to
874
   some other registers without using memory.  Define this macro on those
875
   machines to be a C expression that is nonzero if objects of mode M in
876
   registers of CLASS1 can only be copied to registers of class CLASS2 by
877
   storing a register of CLASS1 into memory and loading that memory location
878
   into a register of CLASS2.  */
879
 
880
#if 0
881
/* ??? May need this, but since we've disallowed XFmode in GR_REGS,
882
   I'm not quite sure how it could be invoked.  The normal problems
883
   with unions should be solved with the addressof fiddling done by
884
   movxf and friends.  */
885
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)                   \
886
  (((MODE) == XFmode || (MODE) == XCmode)                               \
887
   && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS)                     \
888
       || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
889
#endif
890
 
891
/* A C expression for the maximum number of consecutive registers of
892
   class CLASS needed to hold a value of mode MODE.
893
   This is closely related to the macro `HARD_REGNO_NREGS'.  */
894
 
895
#define CLASS_MAX_NREGS(CLASS, MODE) \
896
  ((MODE) == BImode && (CLASS) == PR_REGS ? 2                   \
897
   : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
898
   : (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
899
   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
900
 
901
/* In FP regs, we can't change FP values to integer values and vice versa,
902
   but we can change e.g. DImode to SImode, and V2SFmode into DImode.  */
903
 
904
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)               \
905
  (SCALAR_FLOAT_MODE_P (FROM) != SCALAR_FLOAT_MODE_P (TO)       \
906
   ? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
907
 
908
/* A C expression that defines the machine-dependent operand constraint
909
   letters (`I', `J', `K', .. 'P') that specify particular ranges of
910
   integer values.  */
911
 
912
/* 14 bit signed immediate for arithmetic instructions.  */
913
#define CONST_OK_FOR_I(VALUE) \
914
  ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
915
/* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source.  */
916
#define CONST_OK_FOR_J(VALUE) \
917
  ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
918
/* 8 bit signed immediate for logical instructions.  */
919
#define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
920
/* 8 bit adjusted signed immediate for compare pseudo-ops.  */
921
#define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
922
/* 6 bit unsigned immediate for shift counts.  */
923
#define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
924
/* 9 bit signed immediate for load/store post-increments.  */
925
#define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
926
/* 0 for r0.  Used by Linux kernel, do not change.  */
927
#define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
928
/* 0 or -1 for dep instruction.  */
929
#define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
930
 
931
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
932
  ia64_const_ok_for_letter_p (VALUE, C)
933
 
934
/* A C expression that defines the machine-dependent operand constraint letters
935
   (`G', `H') that specify particular ranges of `const_double' values.  */
936
 
937
/* 0.0 and 1.0 for fr0 and fr1.  */
938
#define CONST_DOUBLE_OK_FOR_G(VALUE) \
939
  ((VALUE) == CONST0_RTX (GET_MODE (VALUE))     \
940
   || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
941
 
942
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
943
  ia64_const_double_ok_for_letter_p (VALUE, C)
944
 
945
/* A C expression that defines the optional machine-dependent constraint
946
   letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
947
   types of operands, usually memory references, for the target machine.  */
948
 
949
#define EXTRA_CONSTRAINT(VALUE, C) \
950
  ia64_extra_constraint (VALUE, C)
951
 
952
/* Document the constraints that can accept reloaded memory operands.  This is
953
   needed by the extended asm support, and by reload.  'Q' accepts mem, but
954
   only non-volatile mem.  Since we can't reload a volatile mem into a
955
   non-volatile mem, it can not be listed here.  */
956
 
957
#define EXTRA_MEMORY_CONSTRAINT(C, STR)  ((C) == 'S')
958
 
959
/* Basic Stack Layout */
960
 
961
/* Define this macro if pushing a word onto the stack moves the stack pointer
962
   to a smaller address.  */
963
#define STACK_GROWS_DOWNWARD 1
964
 
965
/* Define this macro to nonzero if the addresses of local variable slots
966
   are at negative offsets from the frame pointer.  */
967
#define FRAME_GROWS_DOWNWARD 0
968
 
969
/* Offset from the frame pointer to the first local variable slot to
970
   be allocated.  */
971
#define STARTING_FRAME_OFFSET 0
972
 
973
/* Offset from the stack pointer register to the first location at which
974
   outgoing arguments are placed.  If not specified, the default value of zero
975
   is used.  This is the proper value for most machines.  */
976
/* IA64 has a 16 byte scratch area that is at the bottom of the stack.  */
977
#define STACK_POINTER_OFFSET 16
978
 
979
/* Offset from the argument pointer register to the first argument's address.
980
   On some machines it may depend on the data type of the function.  */
981
#define FIRST_PARM_OFFSET(FUNDECL) 0
982
 
983
/* A C expression whose value is RTL representing the value of the return
984
   address for the frame COUNT steps up from the current frame, after the
985
   prologue.  */
986
 
987
/* ??? Frames other than zero would likely require interpreting the frame
988
   unwind info, so we don't try to support them.  We would also need to define
989
   DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush).  */
990
 
991
#define RETURN_ADDR_RTX(COUNT, FRAME) \
992
  ia64_return_addr_rtx (COUNT, FRAME)
993
 
994
/* A C expression whose value is RTL representing the location of the incoming
995
   return address at the beginning of any function, before the prologue.  This
996
   RTL is either a `REG', indicating that the return value is saved in `REG',
997
   or a `MEM' representing a location in the stack.  This enables DWARF2
998
   unwind info for C++ EH.  */
999
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1000
 
1001
/* ??? This is not defined because of three problems.
1002
   1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1003
   The default value is FIRST_PSEUDO_REGISTER which doesn't.  This can be
1004
   worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1005
   unused register number.
1006
   2) dwarf2out_frame_debug core dumps while processing prologue insns.  We
1007
   need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1008
   3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1009
   to zero, despite what the documentation implies, because it is tested in
1010
   a few places with #ifdef instead of #if.  */
1011
#undef INCOMING_RETURN_ADDR_RTX
1012
 
1013
/* A C expression whose value is an integer giving the offset, in bytes, from
1014
   the value of the stack pointer register to the top of the stack frame at the
1015
   beginning of any function, before the prologue.  The top of the frame is
1016
   defined to be the value of the stack pointer in the previous frame, just
1017
   before the call instruction.  */
1018
/* The CFA is past the red zone, not at the entry-point stack
1019
   pointer.  */
1020
#define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
1021
 
1022
/* We shorten debug info by using CFA-16 as DW_AT_frame_base.  */
1023
#define CFA_FRAME_BASE_OFFSET(FUNDECL) (-INCOMING_FRAME_SP_OFFSET)
1024
 
1025
 
1026
/* Register That Address the Stack Frame.  */
1027
 
1028
/* The register number of the stack pointer register, which must also be a
1029
   fixed register according to `FIXED_REGISTERS'.  On most machines, the
1030
   hardware determines which register this is.  */
1031
 
1032
#define STACK_POINTER_REGNUM 12
1033
 
1034
/* The register number of the frame pointer register, which is used to access
1035
   automatic variables in the stack frame.  On some machines, the hardware
1036
   determines which register this is.  On other machines, you can choose any
1037
   register you wish for this purpose.  */
1038
 
1039
#define FRAME_POINTER_REGNUM 328
1040
 
1041
/* Base register for access to local variables of the function.  */
1042
#define HARD_FRAME_POINTER_REGNUM  LOC_REG (79)
1043
 
1044
/* The register number of the arg pointer register, which is used to access the
1045
   function's argument list.  */
1046
/* r0 won't otherwise be used, so put the always eliminated argument pointer
1047
   in it.  */
1048
#define ARG_POINTER_REGNUM R_GR(0)
1049
 
1050
/* Due to the way varargs and argument spilling happens, the argument
1051
   pointer is not 16-byte aligned like the stack pointer.  */
1052
#define INIT_EXPANDERS                                  \
1053
  do {                                                  \
1054
    if (cfun && cfun->emit->regno_pointer_align)        \
1055
      REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64;    \
1056
  } while (0)
1057
 
1058
/* Register numbers used for passing a function's static chain pointer.  */
1059
/* ??? The ABI sez the static chain should be passed as a normal parameter.  */
1060
#define STATIC_CHAIN_REGNUM 15
1061
 
1062
/* Eliminating the Frame Pointer and the Arg Pointer */
1063
 
1064
/* A C expression which is nonzero if a function must have and use a frame
1065
   pointer.  This expression is evaluated in the reload pass.  If its value is
1066
   nonzero the function will have a frame pointer.  */
1067
#define FRAME_POINTER_REQUIRED 0
1068
 
1069
/* Show we can debug even without a frame pointer.  */
1070
#define CAN_DEBUG_WITHOUT_FP
1071
 
1072
/* If defined, this macro specifies a table of register pairs used to eliminate
1073
   unneeded registers that point into the stack frame.  */
1074
 
1075
#define ELIMINABLE_REGS                                                 \
1076
{                                                                       \
1077
  {ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
1078
  {ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
1079
  {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
1080
  {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},                    \
1081
}
1082
 
1083
/* A C expression that returns nonzero if the compiler is allowed to try to
1084
   replace register number FROM with register number TO.  The frame pointer
1085
   is automatically handled.  */
1086
 
1087
#define CAN_ELIMINATE(FROM, TO) \
1088
  (TO == BR_REG (0) ? current_function_is_leaf : 1)
1089
 
1090
/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
1091
   specifies the initial difference between the specified pair of
1092
   registers.  This macro must be defined if `ELIMINABLE_REGS' is
1093
   defined.  */
1094
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1095
  ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1096
 
1097
/* Passing Function Arguments on the Stack */
1098
 
1099
/* If defined, the maximum amount of space required for outgoing arguments will
1100
   be computed and placed into the variable
1101
   `current_function_outgoing_args_size'.  */
1102
 
1103
#define ACCUMULATE_OUTGOING_ARGS 1
1104
 
1105
/* A C expression that should indicate the number of bytes of its own arguments
1106
   that a function pops on returning, or 0 if the function pops no arguments
1107
   and the caller must therefore pop them all after the function returns.  */
1108
 
1109
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1110
 
1111
 
1112
/* Function Arguments in Registers */
1113
 
1114
#define MAX_ARGUMENT_SLOTS 8
1115
#define MAX_INT_RETURN_SLOTS 4
1116
#define GR_ARG_FIRST IN_REG (0)
1117
#define GR_RET_FIRST GR_REG (8)
1118
#define GR_RET_LAST  GR_REG (11)
1119
#define FR_ARG_FIRST FR_REG (8)
1120
#define FR_RET_FIRST FR_REG (8)
1121
#define FR_RET_LAST  FR_REG (15)
1122
#define AR_ARG_FIRST OUT_REG (0)
1123
 
1124
/* A C expression that controls whether a function argument is passed in a
1125
   register, and which register.  */
1126
 
1127
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1128
  ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1129
 
1130
/* Define this macro if the target machine has "register windows", so that the
1131
   register in which a function sees an arguments is not necessarily the same
1132
   as the one in which the caller passed the argument.  */
1133
 
1134
#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1135
  ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1136
 
1137
/* A C type for declaring a variable that is used as the first argument of
1138
   `FUNCTION_ARG' and other related values.  For some target machines, the type
1139
   `int' suffices and can hold the number of bytes of argument so far.  */
1140
 
1141
typedef struct ia64_args
1142
{
1143
  int words;                    /* # words of arguments so far  */
1144
  int int_regs;                 /* # GR registers used so far  */
1145
  int fp_regs;                  /* # FR registers used so far  */
1146
  int prototype;                /* whether function prototyped  */
1147
} CUMULATIVE_ARGS;
1148
 
1149
/* A C statement (sans semicolon) for initializing the variable CUM for the
1150
   state at the beginning of the argument list.  */
1151
 
1152
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1153
do {                                                                    \
1154
  (CUM).words = 0;                                                       \
1155
  (CUM).int_regs = 0;                                                    \
1156
  (CUM).fp_regs = 0;                                                     \
1157
  (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1158
} while (0)
1159
 
1160
/* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1161
   arguments for the function being compiled.  If this macro is undefined,
1162
   `INIT_CUMULATIVE_ARGS' is used instead.  */
1163
 
1164
/* We set prototype to true so that we never try to return a PARALLEL from
1165
   function_arg.  */
1166
#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1167
do {                                                                    \
1168
  (CUM).words = 0;                                                       \
1169
  (CUM).int_regs = 0;                                                    \
1170
  (CUM).fp_regs = 0;                                                     \
1171
  (CUM).prototype = 1;                                                  \
1172
} while (0)
1173
 
1174
/* A C statement (sans semicolon) to update the summarizer variable CUM to
1175
   advance past an argument in the argument list.  The values MODE, TYPE and
1176
   NAMED describe that argument.  Once this is done, the variable CUM is
1177
   suitable for analyzing the *following* argument with `FUNCTION_ARG'.  */
1178
 
1179
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1180
 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1181
 
1182
/* If defined, a C expression that gives the alignment boundary, in bits, of an
1183
   argument with the specified mode and type.  */
1184
 
1185
/* Return the alignment boundary in bits for an argument with a specified
1186
   mode and type.  */
1187
 
1188
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1189
  ia64_function_arg_boundary (MODE, TYPE)
1190
 
1191
/* A C expression that is nonzero if REGNO is the number of a hard register in
1192
   which function arguments are sometimes passed.  This does *not* include
1193
   implicit arguments such as the static chain and the structure-value address.
1194
   On many machines, no registers can be used for this purpose since all
1195
   function arguments are pushed on the stack.  */
1196
#define FUNCTION_ARG_REGNO_P(REGNO) \
1197
(((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1198
 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1199
 
1200
/* How Scalar Function Values are Returned */
1201
 
1202
/* A C expression to create an RTX representing the place where a function
1203
   returns a value of data type VALTYPE.  */
1204
 
1205
#define FUNCTION_VALUE(VALTYPE, FUNC) \
1206
  ia64_function_value (VALTYPE, FUNC)
1207
 
1208
/* A C expression to create an RTX representing the place where a library
1209
   function returns a value of mode MODE.  */
1210
 
1211
#define LIBCALL_VALUE(MODE) \
1212
  gen_rtx_REG (MODE,                                                    \
1213
               (((GET_MODE_CLASS (MODE) == MODE_FLOAT                   \
1214
                 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) &&     \
1215
                      (MODE) != TFmode) \
1216
                ? FR_RET_FIRST : GR_RET_FIRST))
1217
 
1218
/* A C expression that is nonzero if REGNO is the number of a hard register in
1219
   which the values of called function may come back.  */
1220
 
1221
#define FUNCTION_VALUE_REGNO_P(REGNO)                           \
1222
  (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST)          \
1223
   || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1224
 
1225
 
1226
/* How Large Values are Returned */
1227
 
1228
#define DEFAULT_PCC_STRUCT_RETURN 0
1229
 
1230
 
1231
/* Caller-Saves Register Allocation */
1232
 
1233
/* A C expression to determine whether it is worthwhile to consider placing a
1234
   pseudo-register in a call-clobbered hard register and saving and restoring
1235
   it around each function call.  The expression should be 1 when this is worth
1236
   doing, and 0 otherwise.
1237
 
1238
   If you don't define this macro, a default is used which is good on most
1239
   machines: `4 * CALLS < REFS'.  */
1240
/* ??? Investigate.  */
1241
/* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1242
 
1243
 
1244
/* Function Entry and Exit */
1245
 
1246
/* Define this macro as a C expression that is nonzero if the return
1247
   instruction or the function epilogue ignores the value of the stack pointer;
1248
   in other words, if it is safe to delete an instruction to adjust the stack
1249
   pointer before a return from the function.  */
1250
 
1251
#define EXIT_IGNORE_STACK 1
1252
 
1253
/* Define this macro as a C expression that is nonzero for registers
1254
   used by the epilogue or the `return' pattern.  */
1255
 
1256
#define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1257
 
1258
/* Nonzero for registers used by the exception handling mechanism.  */
1259
 
1260
#define EH_USES(REGNO) ia64_eh_uses (REGNO)
1261
 
1262
/* Output part N of a function descriptor for DECL.  For ia64, both
1263
   words are emitted with a single relocation, so ignore N > 0.  */
1264
#define ASM_OUTPUT_FDESC(FILE, DECL, PART)                              \
1265
do {                                                                    \
1266
  if ((PART) == 0)                                                       \
1267
    {                                                                   \
1268
      if (TARGET_ILP32)                                                 \
1269
        fputs ("\tdata8.ua @iplt(", FILE);                              \
1270
      else                                                              \
1271
        fputs ("\tdata16.ua @iplt(", FILE);                             \
1272
      mark_decl_referenced (DECL);                                      \
1273
      assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0));  \
1274
      fputs (")\n", FILE);                                              \
1275
      if (TARGET_ILP32)                                                 \
1276
        fputs ("\tdata8.ua 0\n", FILE);                                 \
1277
    }                                                                   \
1278
} while (0)
1279
 
1280
/* Generating Code for Profiling.  */
1281
 
1282
/* A C statement or compound statement to output to FILE some assembler code to
1283
   call the profiling subroutine `mcount'.  */
1284
 
1285
#undef FUNCTION_PROFILER
1286
#define FUNCTION_PROFILER(FILE, LABELNO) \
1287
  ia64_output_function_profiler(FILE, LABELNO)
1288
 
1289
/* Neither hpux nor linux use profile counters.  */
1290
#define NO_PROFILE_COUNTERS 1
1291
 
1292
/* Trampolines for Nested Functions.  */
1293
 
1294
/* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1295
   the function containing a non-local goto target.  */
1296
 
1297
#define STACK_SAVEAREA_MODE(LEVEL) \
1298
  ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1299
 
1300
/* Output assembler code for a block containing the constant parts of
1301
   a trampoline, leaving space for the variable parts.
1302
 
1303
   The trampoline should set the static chain pointer to value placed
1304
   into the trampoline and should branch to the specified routine.
1305
   To make the normal indirect-subroutine calling convention work,
1306
   the trampoline must look like a function descriptor; the first
1307
   word being the target address and the second being the target's
1308
   global pointer.
1309
 
1310
   We abuse the concept of a global pointer by arranging for it
1311
   to point to the data we need to load.  The complete trampoline
1312
   has the following form:
1313
 
1314
                +-------------------+ \
1315
        TRAMP:  | __ia64_trampoline | |
1316
                +-------------------+  > fake function descriptor
1317
                | TRAMP+16          | |
1318
                +-------------------+ /
1319
                | target descriptor |
1320
                +-------------------+
1321
                | static link       |
1322
                +-------------------+
1323
*/
1324
 
1325
/* A C expression for the size in bytes of the trampoline, as an integer.  */
1326
 
1327
#define TRAMPOLINE_SIZE         32
1328
 
1329
/* Alignment required for trampolines, in bits.  */
1330
 
1331
#define TRAMPOLINE_ALIGNMENT    64
1332
 
1333
/* A C statement to initialize the variable parts of a trampoline.  */
1334
 
1335
#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1336
  ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1337
 
1338
/* Addressing Modes */
1339
 
1340
/* Define this macro if the machine supports post-increment addressing.  */
1341
 
1342
#define HAVE_POST_INCREMENT 1
1343
#define HAVE_POST_DECREMENT 1
1344
#define HAVE_POST_MODIFY_DISP 1
1345
#define HAVE_POST_MODIFY_REG 1
1346
 
1347
/* A C expression that is 1 if the RTX X is a constant which is a valid
1348
   address.  */
1349
 
1350
#define CONSTANT_ADDRESS_P(X) 0
1351
 
1352
/* The max number of registers that can appear in a valid memory address.  */
1353
 
1354
#define MAX_REGS_PER_ADDRESS 2
1355
 
1356
/* A C compound statement with a conditional `goto LABEL;' executed if X (an
1357
   RTX) is a legitimate memory address on the target machine for a memory
1358
   operand of mode MODE.  */
1359
 
1360
#define LEGITIMATE_ADDRESS_REG(X)                                       \
1361
  ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))                       \
1362
   || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG           \
1363
       && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1364
 
1365
#define LEGITIMATE_ADDRESS_DISP(R, X)                                   \
1366
  (GET_CODE (X) == PLUS                                                 \
1367
   && rtx_equal_p (R, XEXP (X, 0))                                       \
1368
   && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1))                             \
1369
       || (GET_CODE (XEXP (X, 1)) == CONST_INT                          \
1370
           && INTVAL (XEXP (X, 1)) >= -256                              \
1371
           && INTVAL (XEXP (X, 1)) < 256)))
1372
 
1373
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)                        \
1374
do {                                                                    \
1375
  if (LEGITIMATE_ADDRESS_REG (X))                                       \
1376
    goto LABEL;                                                         \
1377
  else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC)       \
1378
           && LEGITIMATE_ADDRESS_REG (XEXP (X, 0))                       \
1379
           && XEXP (X, 0) != arg_pointer_rtx)                            \
1380
    goto LABEL;                                                         \
1381
  else if (GET_CODE (X) == POST_MODIFY                                  \
1382
           && LEGITIMATE_ADDRESS_REG (XEXP (X, 0))                       \
1383
           && XEXP (X, 0) != arg_pointer_rtx                             \
1384
           && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1)))        \
1385
    goto LABEL;                                                         \
1386
} while (0)
1387
 
1388
/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1389
   use as a base register.  */
1390
 
1391
#ifdef REG_OK_STRICT
1392
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1393
#else
1394
#define REG_OK_FOR_BASE_P(X) \
1395
  (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1396
#endif
1397
 
1398
/* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1399
   use as an index register.  This is needed for POST_MODIFY.  */
1400
 
1401
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1402
 
1403
/* A C statement or compound statement with a conditional `goto LABEL;'
1404
   executed if memory address X (an RTX) can have different meanings depending
1405
   on the machine mode of the memory reference it is used for or if the address
1406
   is valid for some modes but not others.  */
1407
 
1408
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)                       \
1409
  if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC)       \
1410
    goto LABEL;
1411
 
1412
/* A C expression that is nonzero if X is a legitimate constant for an
1413
   immediate operand on the target machine.  */
1414
 
1415
#define LEGITIMATE_CONSTANT_P(X) ia64_legitimate_constant_p (X)
1416
 
1417
/* Condition Code Status */
1418
 
1419
/* One some machines not all possible comparisons are defined, but you can
1420
   convert an invalid comparison into a valid one.  */
1421
/* ??? Investigate.  See the alpha definition.  */
1422
/* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1423
 
1424
 
1425
/* Describing Relative Costs of Operations */
1426
 
1427
/* A C expression for the cost of moving data from a register in class FROM to
1428
   one in class TO, using MODE.  */
1429
 
1430
#define REGISTER_MOVE_COST  ia64_register_move_cost
1431
 
1432
/* A C expression for the cost of moving data of mode M between a
1433
   register and memory.  */
1434
#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1435
  ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS || (CLASS) == FP_REGS \
1436
   || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1437
 
1438
/* A C expression for the cost of a branch instruction.  A value of 1 is the
1439
   default; other values are interpreted relative to that.  Used by the
1440
   if-conversion code as max instruction count.  */
1441
/* ??? This requires investigation.  The primary effect might be how
1442
   many additional insn groups we run into, vs how good the dynamic
1443
   branch predictor is.  */
1444
 
1445
#define BRANCH_COST 6
1446
 
1447
/* Define this macro as a C expression which is nonzero if accessing less than
1448
   a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1449
   word of memory.  */
1450
 
1451
#define SLOW_BYTE_ACCESS 1
1452
 
1453
/* Define this macro if it is as good or better to call a constant function
1454
   address than to call an address kept in a register.
1455
 
1456
   Indirect function calls are more expensive that direct function calls, so
1457
   don't cse function addresses.  */
1458
 
1459
#define NO_FUNCTION_CSE
1460
 
1461
 
1462
/* Dividing the output into sections.  */
1463
 
1464
/* A C expression whose value is a string containing the assembler operation
1465
   that should precede instructions and read-only data.  */
1466
 
1467
#define TEXT_SECTION_ASM_OP "\t.text"
1468
 
1469
/* A C expression whose value is a string containing the assembler operation to
1470
   identify the following data as writable initialized data.  */
1471
 
1472
#define DATA_SECTION_ASM_OP "\t.data"
1473
 
1474
/* If defined, a C expression whose value is a string containing the assembler
1475
   operation to identify the following data as uninitialized global data.  */
1476
 
1477
#define BSS_SECTION_ASM_OP "\t.bss"
1478
 
1479
#define IA64_DEFAULT_GVALUE 8
1480
 
1481
/* Position Independent Code.  */
1482
 
1483
/* The register number of the register used to address a table of static data
1484
   addresses in memory.  */
1485
 
1486
/* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1487
   gen_rtx_REG (DImode, 1).  */
1488
 
1489
/* ??? Should we set flag_pic?  Probably need to define
1490
   LEGITIMIZE_PIC_OPERAND_P to make that work.  */
1491
 
1492
#define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1493
 
1494
/* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1495
   clobbered by calls.  */
1496
 
1497
#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1498
 
1499
 
1500
/* The Overall Framework of an Assembler File.  */
1501
 
1502
/* A C string constant describing how to begin a comment in the target
1503
   assembler language.  The compiler assumes that the comment will end at the
1504
   end of the line.  */
1505
 
1506
#define ASM_COMMENT_START "//"
1507
 
1508
/* A C string constant for text to be output before each `asm' statement or
1509
   group of consecutive ones.  */
1510
 
1511
#define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
1512
 
1513
/* A C string constant for text to be output after each `asm' statement or
1514
   group of consecutive ones.  */
1515
 
1516
#define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
1517
 
1518
/* Output of Uninitialized Variables.  */
1519
 
1520
/* This is all handled by svr4.h.  */
1521
 
1522
 
1523
/* Output and Generation of Labels.  */
1524
 
1525
/* A C statement (sans semicolon) to output to the stdio stream STREAM the
1526
   assembler definition of a label named NAME.  */
1527
 
1528
/* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1529
   why ia64_asm_output_label exists.  */
1530
 
1531
extern int ia64_asm_output_label;
1532
#define ASM_OUTPUT_LABEL(STREAM, NAME)                                  \
1533
do {                                                                    \
1534
  ia64_asm_output_label = 1;                                            \
1535
  assemble_name (STREAM, NAME);                                         \
1536
  fputs (":\n", STREAM);                                                \
1537
  ia64_asm_output_label = 0;                                             \
1538
} while (0)
1539
 
1540
/* Globalizing directive for a label.  */
1541
#define GLOBAL_ASM_OP "\t.global "
1542
 
1543
/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1544
   necessary for declaring the name of an external symbol named NAME which is
1545
   referenced in this compilation but not defined.  */
1546
 
1547
#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1548
  ia64_asm_output_external (FILE, DECL, NAME)
1549
 
1550
/* A C statement to store into the string STRING a label whose name is made
1551
   from the string PREFIX and the number NUM.  */
1552
 
1553
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1554
do {                                                                    \
1555
  sprintf (LABEL, "*.%s%d", PREFIX, NUM);                               \
1556
} while (0)
1557
 
1558
/* ??? Not sure if using a ? in the name for Intel as is safe.  */
1559
 
1560
#define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1561
 
1562
/* A C statement to output to the stdio stream STREAM assembler code which
1563
   defines (equates) the symbol NAME to have the value VALUE.  */
1564
 
1565
#define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1566
do {                                                                    \
1567
  assemble_name (STREAM, NAME);                                         \
1568
  fputs (" = ", STREAM);                                                \
1569
  assemble_name (STREAM, VALUE);                                        \
1570
  fputc ('\n', STREAM);                                                 \
1571
} while (0)
1572
 
1573
 
1574
/* Macros Controlling Initialization Routines.  */
1575
 
1576
/* This is handled by svr4.h and sysv4.h.  */
1577
 
1578
 
1579
/* Output of Assembler Instructions.  */
1580
 
1581
/* A C initializer containing the assembler's names for the machine registers,
1582
   each one as a C string constant.  */
1583
 
1584
#define REGISTER_NAMES \
1585
{                                                                       \
1586
  /* General registers.  */                                             \
1587
  "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",           \
1588
  "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1589
  "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1590
  "r30", "r31",                                                         \
1591
  /* Local registers.  */                                               \
1592
  "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",       \
1593
  "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",      \
1594
  "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",      \
1595
  "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",      \
1596
  "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",      \
1597
  "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",      \
1598
  "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",      \
1599
  "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",      \
1600
  "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",      \
1601
  "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79",      \
1602
  /* Input registers.  */                                               \
1603
  "in0",  "in1",  "in2",  "in3",  "in4",  "in5",  "in6",  "in7",        \
1604
  /* Output registers.  */                                              \
1605
  "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7",       \
1606
  /* Floating-point registers.  */                                      \
1607
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",           \
1608
  "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1609
  "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1610
  "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1611
  "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1612
  "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1613
  "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1614
  "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1615
  "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1616
  "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1617
  "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1618
  "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1619
  "f120","f121","f122","f123","f124","f125","f126","f127",              \
1620
  /* Predicate registers.  */                                           \
1621
  "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9",           \
1622
  "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1623
  "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1624
  "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1625
  "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1626
  "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1627
  "p60", "p61", "p62", "p63",                                           \
1628
  /* Branch registers.  */                                              \
1629
  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",                       \
1630
  /* Frame pointer.  Application registers.  */                         \
1631
  "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec",       \
1632
}
1633
 
1634
/* If defined, a C initializer for an array of structures containing a name and
1635
   a register number.  This macro defines additional names for hard registers,
1636
   thus allowing the `asm' option in declarations to refer to registers using
1637
   alternate names.  */
1638
 
1639
#define ADDITIONAL_REGISTER_NAMES \
1640
{                                                                       \
1641
  { "gp", R_GR (1) },                                                   \
1642
  { "sp", R_GR (12) },                                                  \
1643
  { "in0", IN_REG (0) },                                         \
1644
  { "in1", IN_REG (1) },                                                \
1645
  { "in2", IN_REG (2) },                                                \
1646
  { "in3", IN_REG (3) },                                                \
1647
  { "in4", IN_REG (4) },                                                \
1648
  { "in5", IN_REG (5) },                                                \
1649
  { "in6", IN_REG (6) },                                                \
1650
  { "in7", IN_REG (7) },                                                \
1651
  { "out0", OUT_REG (0) },                                               \
1652
  { "out1", OUT_REG (1) },                                              \
1653
  { "out2", OUT_REG (2) },                                              \
1654
  { "out3", OUT_REG (3) },                                              \
1655
  { "out4", OUT_REG (4) },                                              \
1656
  { "out5", OUT_REG (5) },                                              \
1657
  { "out6", OUT_REG (6) },                                              \
1658
  { "out7", OUT_REG (7) },                                              \
1659
  { "loc0", LOC_REG (0) },                                               \
1660
  { "loc1", LOC_REG (1) },                                              \
1661
  { "loc2", LOC_REG (2) },                                              \
1662
  { "loc3", LOC_REG (3) },                                              \
1663
  { "loc4", LOC_REG (4) },                                              \
1664
  { "loc5", LOC_REG (5) },                                              \
1665
  { "loc6", LOC_REG (6) },                                              \
1666
  { "loc7", LOC_REG (7) },                                              \
1667
  { "loc8", LOC_REG (8) },                                              \
1668
  { "loc9", LOC_REG (9) },                                              \
1669
  { "loc10", LOC_REG (10) },                                            \
1670
  { "loc11", LOC_REG (11) },                                            \
1671
  { "loc12", LOC_REG (12) },                                            \
1672
  { "loc13", LOC_REG (13) },                                            \
1673
  { "loc14", LOC_REG (14) },                                            \
1674
  { "loc15", LOC_REG (15) },                                            \
1675
  { "loc16", LOC_REG (16) },                                            \
1676
  { "loc17", LOC_REG (17) },                                            \
1677
  { "loc18", LOC_REG (18) },                                            \
1678
  { "loc19", LOC_REG (19) },                                            \
1679
  { "loc20", LOC_REG (20) },                                            \
1680
  { "loc21", LOC_REG (21) },                                            \
1681
  { "loc22", LOC_REG (22) },                                            \
1682
  { "loc23", LOC_REG (23) },                                            \
1683
  { "loc24", LOC_REG (24) },                                            \
1684
  { "loc25", LOC_REG (25) },                                            \
1685
  { "loc26", LOC_REG (26) },                                            \
1686
  { "loc27", LOC_REG (27) },                                            \
1687
  { "loc28", LOC_REG (28) },                                            \
1688
  { "loc29", LOC_REG (29) },                                            \
1689
  { "loc30", LOC_REG (30) },                                            \
1690
  { "loc31", LOC_REG (31) },                                            \
1691
  { "loc32", LOC_REG (32) },                                            \
1692
  { "loc33", LOC_REG (33) },                                            \
1693
  { "loc34", LOC_REG (34) },                                            \
1694
  { "loc35", LOC_REG (35) },                                            \
1695
  { "loc36", LOC_REG (36) },                                            \
1696
  { "loc37", LOC_REG (37) },                                            \
1697
  { "loc38", LOC_REG (38) },                                            \
1698
  { "loc39", LOC_REG (39) },                                            \
1699
  { "loc40", LOC_REG (40) },                                            \
1700
  { "loc41", LOC_REG (41) },                                            \
1701
  { "loc42", LOC_REG (42) },                                            \
1702
  { "loc43", LOC_REG (43) },                                            \
1703
  { "loc44", LOC_REG (44) },                                            \
1704
  { "loc45", LOC_REG (45) },                                            \
1705
  { "loc46", LOC_REG (46) },                                            \
1706
  { "loc47", LOC_REG (47) },                                            \
1707
  { "loc48", LOC_REG (48) },                                            \
1708
  { "loc49", LOC_REG (49) },                                            \
1709
  { "loc50", LOC_REG (50) },                                            \
1710
  { "loc51", LOC_REG (51) },                                            \
1711
  { "loc52", LOC_REG (52) },                                            \
1712
  { "loc53", LOC_REG (53) },                                            \
1713
  { "loc54", LOC_REG (54) },                                            \
1714
  { "loc55", LOC_REG (55) },                                            \
1715
  { "loc56", LOC_REG (56) },                                            \
1716
  { "loc57", LOC_REG (57) },                                            \
1717
  { "loc58", LOC_REG (58) },                                            \
1718
  { "loc59", LOC_REG (59) },                                            \
1719
  { "loc60", LOC_REG (60) },                                            \
1720
  { "loc61", LOC_REG (61) },                                            \
1721
  { "loc62", LOC_REG (62) },                                            \
1722
  { "loc63", LOC_REG (63) },                                            \
1723
  { "loc64", LOC_REG (64) },                                            \
1724
  { "loc65", LOC_REG (65) },                                            \
1725
  { "loc66", LOC_REG (66) },                                            \
1726
  { "loc67", LOC_REG (67) },                                            \
1727
  { "loc68", LOC_REG (68) },                                            \
1728
  { "loc69", LOC_REG (69) },                                            \
1729
  { "loc70", LOC_REG (70) },                                            \
1730
  { "loc71", LOC_REG (71) },                                            \
1731
  { "loc72", LOC_REG (72) },                                            \
1732
  { "loc73", LOC_REG (73) },                                            \
1733
  { "loc74", LOC_REG (74) },                                            \
1734
  { "loc75", LOC_REG (75) },                                            \
1735
  { "loc76", LOC_REG (76) },                                            \
1736
  { "loc77", LOC_REG (77) },                                            \
1737
  { "loc78", LOC_REG (78) },                                            \
1738
  { "loc79", LOC_REG (79) },                                            \
1739
}
1740
 
1741
/* A C compound statement to output to stdio stream STREAM the assembler syntax
1742
   for an instruction operand X.  X is an RTL expression.  */
1743
 
1744
#define PRINT_OPERAND(STREAM, X, CODE) \
1745
  ia64_print_operand (STREAM, X, CODE)
1746
 
1747
/* A C expression which evaluates to true if CODE is a valid punctuation
1748
   character for use in the `PRINT_OPERAND' macro.  */
1749
 
1750
/* ??? Keep this around for now, as we might need it later.  */
1751
 
1752
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1753
  ((CODE) == '+' || (CODE) == ',')
1754
 
1755
/* A C compound statement to output to stdio stream STREAM the assembler syntax
1756
   for an instruction operand that is a memory reference whose address is X.  X
1757
   is an RTL expression.  */
1758
 
1759
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
1760
  ia64_print_operand_address (STREAM, X)
1761
 
1762
/* If defined, C string expressions to be used for the `%R', `%L', `%U', and
1763
   `%I' options of `asm_fprintf' (see `final.c').  */
1764
 
1765
#define REGISTER_PREFIX ""
1766
#define LOCAL_LABEL_PREFIX "."
1767
#define USER_LABEL_PREFIX ""
1768
#define IMMEDIATE_PREFIX ""
1769
 
1770
 
1771
/* Output of dispatch tables.  */
1772
 
1773
/* This macro should be provided on machines where the addresses in a dispatch
1774
   table are relative to the table's own address.  */
1775
 
1776
/* ??? Depends on the pointer size.  */
1777
 
1778
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)      \
1779
  do {                                                          \
1780
  if (TARGET_ILP32)                                             \
1781
    fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE);          \
1782
  else                                                          \
1783
    fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE);          \
1784
  } while (0)
1785
 
1786
/* Jump tables only need 8 byte alignment.  */
1787
 
1788
#define ADDR_VEC_ALIGN(ADDR_VEC) 3
1789
 
1790
 
1791
/* Assembler Commands for Exception Regions.  */
1792
 
1793
/* Select a format to encode pointers in exception handling data.  CODE
1794
   is 0 for data, 1 for code labels, 2 for function pointers.  GLOBAL is
1795
   true if the symbol may be affected by dynamic relocations.  */
1796
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL)       \
1797
  (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel)  \
1798
   | ((GLOBAL) ? DW_EH_PE_indirect : 0)                  \
1799
   | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
1800
 
1801
/* Handle special EH pointer encodings.  Absolute, pc-relative, and
1802
   indirect are handled automatically.  */
1803
#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
1804
  do {                                                                  \
1805
    const char *reltag = NULL;                                          \
1806
    if (((ENCODING) & 0xF0) == DW_EH_PE_textrel)                        \
1807
      reltag = "@segrel(";                                              \
1808
    else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel)                   \
1809
      reltag = "@gprel(";                                               \
1810
    if (reltag)                                                         \
1811
      {                                                                 \
1812
        fputs (integer_asm_op (SIZE, FALSE), FILE);                     \
1813
        fputs (reltag, FILE);                                           \
1814
        assemble_name (FILE, XSTR (ADDR, 0));                            \
1815
        fputc (')', FILE);                                              \
1816
        goto DONE;                                                      \
1817
      }                                                                 \
1818
  } while (0)
1819
 
1820
 
1821
/* Assembler Commands for Alignment.  */
1822
 
1823
/* ??? Investigate.  */
1824
 
1825
/* The alignment (log base 2) to put in front of LABEL, which follows
1826
   a BARRIER.  */
1827
 
1828
/* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
1829
 
1830
/* The desired alignment for the location counter at the beginning
1831
   of a loop.  */
1832
 
1833
/* #define LOOP_ALIGN(LABEL) */
1834
 
1835
/* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
1836
   section because it fails put zeros in the bytes that are skipped.  */
1837
 
1838
#define ASM_NO_SKIP_IN_TEXT 1
1839
 
1840
/* A C statement to output to the stdio stream STREAM an assembler command to
1841
   advance the location counter to a multiple of 2 to the POWER bytes.  */
1842
 
1843
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1844
  fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
1845
 
1846
 
1847
/* Macros Affecting all Debug Formats.  */
1848
 
1849
/* This is handled in svr4.h and sysv4.h.  */
1850
 
1851
 
1852
/* Specific Options for DBX Output.  */
1853
 
1854
/* This is handled by dbxelf.h which is included by svr4.h.  */
1855
 
1856
 
1857
/* Open ended Hooks for DBX Output.  */
1858
 
1859
/* Likewise.  */
1860
 
1861
 
1862
/* File names in DBX format.  */
1863
 
1864
/* Likewise.  */
1865
 
1866
 
1867
/* Macros for SDB and Dwarf Output.  */
1868
 
1869
/* Define this macro if GCC should produce dwarf version 2 format debugging
1870
   output in response to the `-g' option.  */
1871
 
1872
#define DWARF2_DEBUGGING_INFO 1
1873
 
1874
/* We do not want call-frame info to be output, since debuggers are
1875
   supposed to use the target unwind info.  Leave this undefined it
1876
   TARGET_UNWIND_INFO might ever be false.  */
1877
 
1878
#define DWARF2_FRAME_INFO 0
1879
 
1880
#define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
1881
 
1882
/* Use tags for debug info labels, so that they don't break instruction
1883
   bundles.  This also avoids getting spurious DV warnings from the
1884
   assembler.  This is similar to (*targetm.asm_out.internal_label), except that we
1885
   add brackets around the label.  */
1886
 
1887
#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
1888
  fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
1889
 
1890
/* Use section-relative relocations for debugging offsets.  Unlike other
1891
   targets that fake this by putting the section VMA at 0, IA-64 has
1892
   proper relocations for them.  */
1893
#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL, SECTION)     \
1894
  do {                                                          \
1895
    fputs (integer_asm_op (SIZE, FALSE), FILE);                 \
1896
    fputs ("@secrel(", FILE);                                   \
1897
    assemble_name (FILE, LABEL);                                \
1898
    fputc (')', FILE);                                          \
1899
  } while (0)
1900
 
1901
/* Emit a PC-relative relocation.  */
1902
#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL)       \
1903
  do {                                                  \
1904
    fputs (integer_asm_op (SIZE, FALSE), FILE);         \
1905
    fputs ("@pcrel(", FILE);                            \
1906
    assemble_name (FILE, LABEL);                        \
1907
    fputc (')', FILE);                                  \
1908
  } while (0)
1909
 
1910
/* Register Renaming Parameters.  */
1911
 
1912
/* A C expression that is nonzero if hard register number REGNO2 can be
1913
   considered for use as a rename register for REGNO1 */
1914
 
1915
#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
1916
  ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
1917
 
1918
 
1919
/* Miscellaneous Parameters.  */
1920
 
1921
/* Flag to mark data that is in the small address area (addressable
1922
   via "addl", that is, within a 2MByte offset of 0.  */
1923
#define SYMBOL_FLAG_SMALL_ADDR          (SYMBOL_FLAG_MACH_DEP << 0)
1924
#define SYMBOL_REF_SMALL_ADDR_P(X)      \
1925
        ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
1926
 
1927
/* An alias for a machine mode name.  This is the machine mode that elements of
1928
   a jump-table should have.  */
1929
 
1930
#define CASE_VECTOR_MODE ptr_mode
1931
 
1932
/* Define as C expression which evaluates to nonzero if the tablejump
1933
   instruction expects the table to contain offsets from the address of the
1934
   table.  */
1935
 
1936
#define CASE_VECTOR_PC_RELATIVE 1
1937
 
1938
/* Define this macro if operations between registers with integral mode smaller
1939
   than a word are always performed on the entire register.  */
1940
 
1941
#define WORD_REGISTER_OPERATIONS
1942
 
1943
/* Define this macro to be a C expression indicating when insns that read
1944
   memory in MODE, an integral mode narrower than a word, set the bits outside
1945
   of MODE to be either the sign-extension or the zero-extension of the data
1946
   read.  */
1947
 
1948
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1949
 
1950
/* The maximum number of bytes that a single instruction can move quickly from
1951
   memory to memory.  */
1952
#define MOVE_MAX 8
1953
 
1954
/* A C expression which is nonzero if on this machine it is safe to "convert"
1955
   an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
1956
   than INPREC) by merely operating on it as if it had only OUTPREC bits.  */
1957
 
1958
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1959
 
1960
/* A C expression describing the value returned by a comparison operator with
1961
   an integral mode and stored by a store-flag instruction (`sCOND') when the
1962
   condition is true.  */
1963
 
1964
/* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1.  */
1965
 
1966
/* An alias for the machine mode for pointers.  */
1967
 
1968
/* ??? This would change if we had ILP32 support.  */
1969
 
1970
#define Pmode DImode
1971
 
1972
/* An alias for the machine mode used for memory references to functions being
1973
   called, in `call' RTL expressions.  */
1974
 
1975
#define FUNCTION_MODE Pmode
1976
 
1977
/* Define this macro to handle System V style pragmas: #pragma pack and
1978
   #pragma weak.  Note, #pragma weak will only be supported if SUPPORT_WEAK is
1979
   defined.  */
1980
 
1981
/* If this architecture supports prefetch, define this to be the number of
1982
   prefetch commands that can be executed in parallel.
1983
 
1984
   ??? This number is bogus and needs to be replaced before the value is
1985
   actually used in optimizations.  */
1986
 
1987
#define SIMULTANEOUS_PREFETCHES 6
1988
 
1989
/* If this architecture supports prefetch, define this to be the size of
1990
   the cache line that is prefetched.  */
1991
 
1992
#define PREFETCH_BLOCK 32
1993
 
1994
#define HANDLE_SYSV_PRAGMA 1
1995
 
1996
/* A C expression for the maximum number of instructions to execute via
1997
   conditional execution instructions instead of a branch.  A value of
1998
   BRANCH_COST+1 is the default if the machine does not use
1999
   cc0, and 1 if it does use cc0.  */
2000
/* ??? Investigate.  */
2001
#define MAX_CONDITIONAL_EXECUTE 12
2002
 
2003
extern int ia64_final_schedule;
2004
 
2005
#define TARGET_UNWIND_INFO      1
2006
 
2007
#define TARGET_UNWIND_TABLES_DEFAULT true
2008
 
2009
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2010
 
2011
/* This function contains machine specific function data.  */
2012
struct machine_function GTY(())
2013
{
2014
  /* The new stack pointer when unwinding from EH.  */
2015
  rtx ia64_eh_epilogue_sp;
2016
 
2017
  /* The new bsp value when unwinding from EH.  */
2018
  rtx ia64_eh_epilogue_bsp;
2019
 
2020
  /* The GP value save register.  */
2021
  rtx ia64_gp_save;
2022
 
2023
  /* The number of varargs registers to save.  */
2024
  int n_varargs;
2025
 
2026
  /* The number of the next unwind state to copy.  */
2027
  int state_num;
2028
};
2029
 
2030
#define DONT_USE_BUILTIN_SETJMP
2031
 
2032
/* Output any profiling code before the prologue.  */
2033
 
2034
#undef  PROFILE_BEFORE_PROLOGUE
2035
#define PROFILE_BEFORE_PROLOGUE 1
2036
 
2037
/* Initialize library function table. */
2038
#undef TARGET_INIT_LIBFUNCS
2039
#define TARGET_INIT_LIBFUNCS ia64_init_libfuncs
2040
 
2041
 
2042
/* Switch on code for querying unit reservations.  */
2043
#define CPU_UNITS_QUERY 1
2044
 
2045
/* Define this to change the optimizations performed by default.  */
2046
#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
2047
  ia64_optimization_options ((LEVEL), (SIZE))
2048
 
2049
/* End of ia64.h */

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