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;; Itanium1 (original Itanium) DFA descriptions for insn scheduling
2 
;; and bundling.
3 
;; Copyright (C) 2002, 2004, 2005, 2007 Free Software Foundation, Inc.
4 
;; Contributed by Vladimir Makarov .
5 
;;
6 
;; This file is part of GCC.
7 
;;
8 
;; GCC is free software; you can redistribute it and/or modify
9 
;; it under the terms of the GNU General Public License as published by
10 
;; the Free Software Foundation; either version 3, or (at your option)
11 
;; any later version.
12 
;;
13 
;; GCC is distributed in the hope that it will be useful,
14 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
;; GNU General Public License for more details.
17 
;;
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .  */
21 
;;
22 
 
23 
 
24 
/* This is description of pipeline hazards based on DFA.  The
25 
   following constructions can be used for this:
26 
 
27 
   o define_cpu_unit string [string]) describes a cpu functional unit
28 
     (separated by comma).
29 
 
30 
     1st operand: Names of cpu function units.
31 
     2nd operand: Name of automaton (see comments for
32 
     DEFINE_AUTOMATON).
33 
 
34 
     All define_reservations and define_cpu_units should have unique
35 
     names which cannot be "nothing".
36 
 
37 
   o (exclusion_set string string) means that each CPU function unit
38 
     in the first string cannot be reserved simultaneously with each
39 
     unit whose name is in the second string and vise versa.  CPU
40 
     units in the string are separated by commas. For example, it is
41 
     useful for description CPU with fully pipelined floating point
42 
     functional unit which can execute simultaneously only single
43 
     floating point insns or only double floating point insns.
44 
 
45 
   o (presence_set string string) means that each CPU function unit in
46 
     the first string cannot be reserved unless at least one of
47 
     pattern of units whose names are in the second string is
48 
     reserved.  This is an asymmetric relation.  CPU units or unit
49 
     patterns in the strings are separated by commas.  Pattern is one
50 
     unit name or unit names separated by white-spaces.
51 
 
52 
     For example, it is useful for description that slot1 is reserved
53 
     after slot0 reservation for a VLIW processor.  We could describe
54 
     it by the following construction
55 
 
56 
         (presence_set "slot1" "slot0")
57 
 
58 
     Or slot1 is reserved only after slot0 and unit b0 reservation.
59 
     In this case we could write
60 
 
61 
         (presence_set "slot1" "slot0 b0")
62 
 
63 
     All CPU functional units in a set should belong to the same
64 
     automaton.
65 
 
66 
   o (final_presence_set string string) is analogous to
67 
     `presence_set'.  The difference between them is when checking is
68 
     done.  When an instruction is issued in given automaton state
69 
     reflecting all current and planned unit reservations, the
70 
     automaton state is changed.  The first state is a source state,
71 
     the second one is a result state.  Checking for `presence_set' is
72 
     done on the source state reservation, checking for
73 
     `final_presence_set' is done on the result reservation.  This
74 
     construction is useful to describe a reservation which is
75 
     actually two subsequent reservations.  For example, if we use
76 
 
77 
         (presence_set "slot1" "slot0")
78 
 
79 
     the following insn will be never issued (because slot1 requires
80 
     slot0 which is absent in the source state).
81 
 
82 
         (define_reservation "insn_and_nop" "slot0 + slot1")
83 
 
84 
     but it can be issued if we use analogous `final_presence_set'.
85 
 
86 
   o (absence_set string string) means that each CPU function unit in
87 
     the first string can be reserved only if each pattern of units
88 
     whose names are in the second string is not reserved.  This is an
89 
     asymmetric relation (actually exclusion set is analogous to this
90 
     one but it is symmetric).  CPU units or unit patterns in the
91 
     string are separated by commas.  Pattern is one unit name or unit
92 
     names separated by white-spaces.
93 
 
94 
     For example, it is useful for description that slot0 cannot be
95 
     reserved after slot1 or slot2 reservation for a VLIW processor.
96 
     We could describe it by the following construction
97 
 
98 
        (absence_set "slot2" "slot0, slot1")
99 
 
100 
     Or slot2 cannot be reserved if slot0 and unit b0 are reserved or
101 
     slot1 and unit b1 are reserved .  In this case we could write
102 
 
103 
        (absence_set "slot2" "slot0 b0, slot1 b1")
104 
 
105 
     All CPU functional units in a set should to belong the same
106 
     automaton.
107 
 
108 
   o (final_absence_set string string) is analogous to `absence_set' but
109 
     checking is done on the result (state) reservation.  See comments
110 
     for final_presence_set.
111 
 
112 
   o (define_bypass number out_insn_names in_insn_names) names bypass with
113 
     given latency (the first number) from insns given by the first
114 
     string (see define_insn_reservation) into insns given by the
115 
     second string.  Insn names in the strings are separated by
116 
     commas.
117 
 
118 
   o (define_automaton string) describes names of an automaton
119 
     generated and used for pipeline hazards recognition.  The names
120 
     are separated by comma.  Actually it is possibly to generate the
121 
     single automaton but unfortunately it can be very large.  If we
122 
     use more one automata, the summary size of the automata usually
123 
     is less than the single one.  The automaton name is used in
124 
     define_cpu_unit.  All automata should have unique names.
125 
 
126 
   o (automata_option string) describes option for generation of
127 
     automata.  Currently there are the following options:
128 
 
129 
     o "no-minimization" which makes no minimization of automata.
130 
       This is only worth to do when we are debugging the description
131 
       and need to look more accurately at reservations of states.
132 
 
133 
     o "ndfa" which makes automata with nondetermenistic reservation
134 
        by insns.
135 
 
136 
   o (define_reservation string string) names reservation (the first
137 
     string) of cpu functional units (the 2nd string).  Sometimes unit
138 
     reservations for different insns contain common parts.  In such
139 
     case, you describe common part and use one its name (the 1st
140 
     parameter) in regular expression in define_insn_reservation.  All
141 
     define_reservations, define results and define_cpu_units should
142 
     have unique names which cannot be "nothing".
143 
 
144 
   o (define_insn_reservation name default_latency condition regexpr)
145 
     describes reservation of cpu functional units (the 3nd operand)
146 
     for instruction which is selected by the condition (the 2nd
147 
     parameter).  The first parameter is used for output of debugging
148 
     information.  The reservations are described by a regular
149 
     expression according the following syntax:
150 
 
151 
       regexp = regexp "," oneof
152 
              | oneof
153 
 
154 
       oneof = oneof "|" allof
155 
             | allof
156 
 
157 
       allof = allof "+" repeat
158 
             | repeat
159 
 
160 
       repeat = element "*" number
161 
              | element
162 
 
163 
       element = cpu_function_name
164 
               | reservation_name
165 
               | result_name
166 
               | "nothing"
167 
               | "(" regexp ")"
168 
 
169 
       1. "," is used for describing start of the next cycle in
170 
          reservation.
171 
 
172 
       2. "|" is used for describing the reservation described by the
173 
          first regular expression *or* the reservation described by
174 
          the second regular expression *or* etc.
175 
 
176 
       3. "+" is used for describing the reservation described by the
177 
          first regular expression *and* the reservation described by
178 
          the second regular expression *and* etc.
179 
 
180 
       4. "*" is used for convenience and simply means sequence in
181 
          which the regular expression are repeated NUMBER times with
182 
          cycle advancing (see ",").
183 
 
184 
       5. cpu function unit name which means reservation.
185 
 
186 
       6. reservation name -- see define_reservation.
187 
 
188 
       7. string "nothing" means no units reservation.
189 
 
190 
*/
191 
 
192 
(define_automaton "one")
193 
 
194 
;;   All possible combinations of bundles/syllables
195 
(define_cpu_unit "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\
196 
                  1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx" "one")
197 
(define_cpu_unit "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b,\
198 
                  1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx." "one")
199 
(define_cpu_unit "1_0mii., 1_0mmi., 1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb.,\
200 
                  1_0mib., 1_0mmb., 1_0mfb." "one")
201 
 
202 
(define_cpu_unit "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb,\
203 
                  1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx" "one")
204 
(define_cpu_unit "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1bb.b, 1_1mb.b,\
205 
                  1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx." "one")
206 
(define_cpu_unit "1_1mii., 1_1mmi., 1_1mfi., 1_1bbb., 1_1mbb.,\
207 
                  1_1mib., 1_1mmb., 1_1mfb." "one")
208 
 
209 
;; Slot 1
210 
(exclusion_set "1_0m.ii"
211 
   "1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb,\
212 
    1_0m.lx")
213 
(exclusion_set "1_0m.mi"
214 
   "1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
215 
(exclusion_set "1_0m.fi"
216 
   "1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
217 
(exclusion_set "1_0m.mf"
218 
   "1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
219 
(exclusion_set "1_0b.bb" "1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
220 
(exclusion_set "1_0m.bb" "1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
221 
(exclusion_set "1_0m.ib" "1_0m.mb, 1_0m.fb, 1_0m.lx")
222 
(exclusion_set "1_0m.mb" "1_0m.fb, 1_0m.lx")
223 
(exclusion_set "1_0m.fb" "1_0m.lx")
224 
 
225 
;; Slot 2
226 
(exclusion_set "1_0mi.i"
227 
   "1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b,\
228 
    1_0mlx.")
229 
(exclusion_set "1_0mm.i"
230 
   "1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.")
231 
(exclusion_set "1_0mf.i"
232 
   "1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.")
233 
(exclusion_set "1_0mm.f"
234 
   "1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.")
235 
(exclusion_set "1_0bb.b" "1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.")
236 
(exclusion_set "1_0mb.b" "1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.")
237 
(exclusion_set "1_0mi.b" "1_0mm.b, 1_0mf.b, 1_0mlx.")
238 
(exclusion_set "1_0mm.b" "1_0mf.b, 1_0mlx.")
239 
(exclusion_set "1_0mf.b" "1_0mlx.")
240 
 
241 
;; Slot 3
242 
(exclusion_set "1_0mii."
243 
   "1_0mmi., 1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb.,\
244 
    1_0mlx.")
245 
(exclusion_set "1_0mmi."
246 
   "1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.")
247 
(exclusion_set "1_0mfi."
248 
   "1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.")
249 
(exclusion_set "1_0mmf."
250 
   "1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.")
251 
(exclusion_set "1_0bbb." "1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.")
252 
(exclusion_set "1_0mbb." "1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.")
253 
(exclusion_set "1_0mib." "1_0mmb., 1_0mfb., 1_0mlx.")
254 
(exclusion_set "1_0mmb." "1_0mfb., 1_0mlx.")
255 
(exclusion_set "1_0mfb." "1_0mlx.")
256 
 
257 
;; Slot 4
258 
(exclusion_set "1_1m.ii"
259 
   "1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx")
260 
(exclusion_set "1_1m.mi"
261 
   "1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx")
262 
(exclusion_set "1_1m.fi"
263 
   "1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx")
264 
(exclusion_set "1_1b.bb" "1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx")
265 
(exclusion_set "1_1m.bb" "1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx")
266 
(exclusion_set "1_1m.ib" "1_1m.mb, 1_1m.fb, 1_1m.lx")
267 
(exclusion_set "1_1m.mb" "1_1m.fb, 1_1m.lx")
268 
(exclusion_set "1_1m.fb" "1_1m.lx")
269 
 
270 
;; Slot 5
271 
(exclusion_set "1_1mi.i"
272 
   "1_1mm.i, 1_1mf.i, 1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.")
273 
(exclusion_set "1_1mm.i"
274 
   "1_1mf.i, 1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.")
275 
(exclusion_set "1_1mf.i"
276 
   "1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.")
277 
(exclusion_set "1_1bb.b" "1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.")
278 
(exclusion_set "1_1mb.b" "1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.")
279 
(exclusion_set "1_1mi.b" "1_1mm.b, 1_1mf.b, 1_1mlx.")
280 
(exclusion_set "1_1mm.b" "1_1mf.b, 1_1mlx.")
281 
(exclusion_set "1_1mf.b" "1_1mlx.")
282 
 
283 
;; Slot 6
284 
(exclusion_set "1_1mii."
285 
   "1_1mmi., 1_1mfi., 1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.")
286 
(exclusion_set "1_1mmi."
287 
   "1_1mfi., 1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.")
288 
(exclusion_set "1_1mfi."
289 
   "1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.")
290 
(exclusion_set "1_1bbb." "1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.")
291 
(exclusion_set "1_1mbb." "1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.")
292 
(exclusion_set "1_1mib." "1_1mmb., 1_1mfb., 1_1mlx.")
293 
(exclusion_set "1_1mmb." "1_1mfb., 1_1mlx.")
294 
(exclusion_set "1_1mfb." "1_1mlx.")
295 
 
296 
(final_presence_set "1_0mi.i" "1_0m.ii")
297 
(final_presence_set "1_0mii." "1_0mi.i")
298 
(final_presence_set "1_1mi.i" "1_1m.ii")
299 
(final_presence_set "1_1mii." "1_1mi.i")
300 
 
301 
(final_presence_set "1_0mm.i" "1_0m.mi")
302 
(final_presence_set "1_0mmi." "1_0mm.i")
303 
(final_presence_set "1_1mm.i" "1_1m.mi")
304 
(final_presence_set "1_1mmi." "1_1mm.i")
305 
 
306 
(final_presence_set "1_0mf.i" "1_0m.fi")
307 
(final_presence_set "1_0mfi." "1_0mf.i")
308 
(final_presence_set "1_1mf.i" "1_1m.fi")
309 
(final_presence_set "1_1mfi." "1_1mf.i")
310 
 
311 
(final_presence_set "1_0mm.f" "1_0m.mf")
312 
(final_presence_set "1_0mmf." "1_0mm.f")
313 
 
314 
(final_presence_set "1_0bb.b" "1_0b.bb")
315 
(final_presence_set "1_0bbb." "1_0bb.b")
316 
(final_presence_set "1_1bb.b" "1_1b.bb")
317 
(final_presence_set "1_1bbb." "1_1bb.b")
318 
 
319 
(final_presence_set "1_0mb.b" "1_0m.bb")
320 
(final_presence_set "1_0mbb." "1_0mb.b")
321 
(final_presence_set "1_1mb.b" "1_1m.bb")
322 
(final_presence_set "1_1mbb." "1_1mb.b")
323 
 
324 
(final_presence_set "1_0mi.b" "1_0m.ib")
325 
(final_presence_set "1_0mib." "1_0mi.b")
326 
(final_presence_set "1_1mi.b" "1_1m.ib")
327 
(final_presence_set "1_1mib." "1_1mi.b")
328 
 
329 
(final_presence_set "1_0mm.b" "1_0m.mb")
330 
(final_presence_set "1_0mmb." "1_0mm.b")
331 
(final_presence_set "1_1mm.b" "1_1m.mb")
332 
(final_presence_set "1_1mmb." "1_1mm.b")
333 
 
334 
(final_presence_set "1_0mf.b" "1_0m.fb")
335 
(final_presence_set "1_0mfb." "1_0mf.b")
336 
(final_presence_set "1_1mf.b" "1_1m.fb")
337 
(final_presence_set "1_1mfb." "1_1mf.b")
338 
 
339 
(final_presence_set "1_0mlx." "1_0m.lx")
340 
(final_presence_set "1_1mlx." "1_1m.lx")
341 
 
342 
(final_presence_set
343 
   "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx"
344 
   "1_0mii.,1_0mmi.,1_0mfi.,1_0mmf.,1_0bbb.,1_0mbb.,1_0mib.,1_0mmb.,1_0mfb.,\
345 
    1_0mlx.")
346 
 
347 
;;  Microarchitecture units:
348 
(define_cpu_unit
349 
   "1_um0, 1_um1, 1_ui0, 1_ui1, 1_uf0, 1_uf1, 1_ub0, 1_ub1, 1_ub2,\
350 
    1_unb0, 1_unb1, 1_unb2" "one")
351 
 
352 
(exclusion_set "1_ub0" "1_unb0")
353 
(exclusion_set "1_ub1" "1_unb1")
354 
(exclusion_set "1_ub2" "1_unb2")
355 
 
356 
;; The following rules are used to decrease number of alternatives.
357 
;; They are consequences of Itanium microarchitecture.  They also
358 
;; describe the following rules mentioned in Itanium
359 
;; microarchitecture: rules mentioned in Itanium microarchitecture:
360 
;; o "MMF: Always splits issue before the first M and after F regardless
361 
;;   of surrounding bundles and stops".
362 
;; o "BBB/MBB: Always splits issue after either of these bundles".
363 
;; o "MIB BBB: Split issue after the first bundle in this pair".
364 
 
365 
(exclusion_set "1_0m.mf,1_0mm.f,1_0mmf."
366 
   "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx")
367 
(exclusion_set "1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb."
368 
   "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx")
369 
(exclusion_set "1_0m.ib,1_0mi.b,1_0mib." "1_1b.bb")
370 
 
371 
;;  For exceptions of M, I, B, F insns:
372 
(define_cpu_unit "1_not_um1, 1_not_ui1, 1_not_uf1" "one")
373 
 
374 
(final_absence_set "1_not_um1"  "1_um1")
375 
(final_absence_set "1_not_ui1"  "1_ui1")
376 
(final_absence_set "1_not_uf1"  "1_uf1")
377 
 
378 
;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
379 
;;; B-slot contains a nop.b or a brp instruction".
380 
;;;   "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
381 
;;; nop.b, otherwise it disperses to B2".
382 
(final_absence_set
383 
   "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb,\
384 
    1_1m.lx"
385 
   "1_0mib. 1_ub2, 1_0mfb. 1_ub2, 1_0mmb. 1_ub2")
386 
 
387 
;; This is necessary to start new processor cycle when we meet stop bit.
388 
(define_cpu_unit "1_stop" "one")
389 
(final_absence_set
390 
   "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\
391 
    1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\
392 
    1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\
393 
    1_0m.lx,1_0mlx., \
394 
    1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\
395 
    1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,1_1m.ib,1_1mi.b,1_1mib.,\
396 
    1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,1_1m.lx,1_1mlx."
397 
   "1_stop")
398 
 
399 
;; M and I instruction is dispersed to the lowest numbered M or I unit
400 
;; not already in use.  An I slot in the 3rd position of 2nd bundle is
401 
;; always dispersed to I1
402 
(final_presence_set "1_um1" "1_um0")
403 
(final_presence_set "1_ui1" "1_ui0, 1_1mii., 1_1mmi., 1_1mfi.")
404 
 
405 
;; Insns
406 
 
407 
;; M and I instruction is dispersed to the lowest numbered M or I unit
408 
;; not already in use.  An I slot in the 3rd position of 2nd bundle is
409 
;; always dispersed to I1
410 
(define_reservation "1_M0"
411 
  "1_0m.ii+1_um0|1_0m.mi+1_um0|1_0mm.i+(1_um0|1_um1)\
412 
   |1_0m.fi+1_um0|1_0m.mf+1_um0|1_0mm.f+1_um1\
413 
   |1_0m.bb+1_um0|1_0m.ib+1_um0|1_0m.mb+1_um0\
414 
   |1_0mm.b+1_um1|1_0m.fb+1_um0|1_0m.lx+1_um0\
415 
   |1_1mm.i+1_um1|1_1mm.b+1_um1\
416 
   |(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\
417 
    +(1_um0|1_um1)")
418 
 
419 
(define_reservation "1_M1"
420 
  "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\
421 
    |1_0mib.+1_unb0|1_0mfb.+1_unb0|1_0mmb.+1_unb0)\
422 
     +(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\
423 
     +(1_um0|1_um1)")
424 
 
425 
(define_reservation "1_M" "1_M0|1_M1")
426 
 
427 
;;  Exceptions for dispersal rules.
428 
;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1".
429 
(define_reservation "1_I0"
430 
  "1_0mi.i+1_ui0|1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\
431 
   |1_0mi.b+1_ui0|(1_1mi.i|1_1mi.b)+(1_ui0|1_ui1)\
432 
   |1_1mii.+1_ui1|1_1mmi.+1_ui1|1_1mfi.+1_ui1")
433 
 
434 
(define_reservation "1_I1"
435 
  "1_0m.ii+1_um0+1_0mi.i+1_ui0|1_0mm.i+(1_um0|1_um1)+1_0mmi.+1_ui0\
436 
   |1_0mf.i+1_uf0+1_0mfi.+1_ui0|1_0m.ib+1_um0+1_0mi.b+1_ui0\
437 
   |(1_1m.ii+(1_um0|1_um1)+1_1mi.i\
438 
   |1_1m.ib+(1_um0|1_um1)+1_1mi.b)+(1_ui0|1_ui1)\
439 
   |1_1mm.i+1_um1+1_1mmi.+1_ui1|1_1mf.i+1_uf1+1_1mfi.+1_ui1")
440 
 
441 
(define_reservation "1_I" "1_I0|1_I1")
442 
 
443 
;; "An F slot in the 1st bundle disperses to F0".
444 
;; "An F slot in the 2st bundle disperses to F1".
445 
(define_reservation "1_F0"
446 
   "1_0mf.i+1_uf0|1_0mmf.+1_uf0|1_0mf.b+1_uf0|1_1mf.i+1_uf1|1_1mf.b+1_uf1")
447 
 
448 
(define_reservation "1_F1"
449 
   "1_0m.fi+1_um0+1_0mf.i+1_uf0|1_0mm.f+(1_um0|1_um1)+1_0mmf.+1_uf0\
450 
    |1_0m.fb+1_um0+1_0mf.b+1_uf0|1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\
451 
    |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1")
452 
 
453 
(define_reservation "1_F2"
454 
   "1_0m.mf+1_um0+1_0mm.f+1_um1+1_0mmf.+1_uf0\
455 
    |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\
456 
      |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0)\
457 
     +(1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\
458 
       |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1)")
459 
 
460 
(define_reservation "1_F" "1_F0|1_F1|1_F2")
461 
 
462 
;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
463 
;;; unit. That is, a B slot in 1st position is dispersed to B0.  In the
464 
;;; 2nd position it is dispersed to B2".
465 
(define_reservation "1_NB"
466 
    "1_0b.bb+1_unb0|1_0bb.b+1_unb1|1_0bbb.+1_unb2\
467 
     |1_0mb.b+1_unb1|1_0mbb.+1_unb2\
468 
     |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0\
469 
     |1_1b.bb+1_unb0|1_1bb.b+1_unb1\
470 
     |1_1bbb.+1_unb2|1_1mb.b+1_unb1|1_1mbb.+1_unb2|1_1mib.+1_unb0\
471 
     |1_1mmb.+1_unb0|1_1mfb.+1_unb0")
472 
 
473 
(define_reservation "1_B0"
474 
   "1_0b.bb+1_ub0|1_0bb.b+1_ub1|1_0bbb.+1_ub2\
475 
    |1_0mb.b+1_ub1|1_0mbb.+1_ub2|1_0mib.+1_ub2\
476 
    |1_0mfb.+1_ub2|1_1b.bb+1_ub0|1_1bb.b+1_ub1\
477 
    |1_1bbb.+1_ub2|1_1mb.b+1_ub1\
478 
    |1_1mib.+1_ub2|1_1mmb.+1_ub2|1_1mfb.+1_ub2")
479 
 
480 
(define_reservation "1_B1"
481 
   "1_0m.bb+1_um0+1_0mb.b+1_ub1|1_0mi.b+1_ui0+1_0mib.+1_ub2\
482 
    |1_0mf.b+1_uf0+1_0mfb.+1_ub2\
483 
    |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0)+1_1b.bb+1_ub0\
484 
    |1_1m.bb+(1_um0|1_um1)+1_1mb.b+1_ub1\
485 
    |1_1mi.b+(1_ui0|1_ui1)+1_1mib.+1_ub2\
486 
    |1_1mm.b+1_um1+1_1mmb.+1_ub2\
487 
    |1_1mf.b+1_uf1+1_1mfb.+1_ub2")
488 
 
489 
(define_reservation "1_B" "1_B0|1_B1")
490 
 
491 
;; MLX bunlde uses ports equivalent to MFI bundles.
492 
(define_reservation "1_L0" "1_0mlx.+1_ui0+1_uf0|1_1mlx.+(1_ui0|1_ui1)+1_uf1")
493 
(define_reservation "1_L1"
494 
   "1_0m.lx+1_um0+1_0mlx.+1_ui0+1_uf0\
495 
   |1_1m.lx+(1_um0|1_um1)+1_1mlx.+(1_ui0|1_ui1)+1_uf1")
496 
(define_reservation "1_L2"
497 
   "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\
498 
     |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0)
499 
    +1_1m.lx+(1_um0|1_um1)+1_1mlx.+1_ui1+1_uf1")
500 
(define_reservation "1_L" "1_L0|1_L1|1_L2")
501 
 
502 
(define_reservation "1_A" "1_M|1_I")
503 
 
504 
(define_insn_reservation "1_stop_bit" 0
505 
  (and (and (eq_attr "cpu" "itanium")
506 
            (eq_attr "itanium_class" "stop_bit"))
507 
       (eq (symbol_ref "bundling_p") (const_int 0)))
508 
  "1_stop|1_m0_stop|1_m1_stop|1_mi0_stop|1_mi1_stop")
509 
 
510 
(define_insn_reservation "1_br"      0
511 
  (and (and (eq_attr "cpu" "itanium")
512 
            (eq_attr "itanium_class" "br"))
513 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_B")
514 
(define_insn_reservation "1_scall"   0
515 
  (and (and (eq_attr "cpu" "itanium")
516 
            (eq_attr "itanium_class" "scall"))
517 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_B")
518 
(define_insn_reservation "1_fcmp"    2
519 
  (and (and (eq_attr "cpu" "itanium")
520 
            (eq_attr "itanium_class" "fcmp"))
521 
       (eq (symbol_ref "bundling_p") (const_int 0)))
522 
  "1_F+1_not_uf1")
523 
(define_insn_reservation "1_fcvtfx"  7
524 
  (and (and (eq_attr "cpu" "itanium")
525 
            (eq_attr "itanium_class" "fcvtfx"))
526 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
527 
 
528 
(define_insn_reservation "1_fld"     9
529 
  (and (and (and (eq_attr "cpu" "itanium")
530 
                 (eq_attr "itanium_class" "fld"))
531 
            (eq_attr "check_load" "no"))
532 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
533 
(define_insn_reservation "1_fldc"    0
534 
  (and (and (and (eq_attr "cpu" "itanium")
535 
                 (eq_attr "itanium_class" "fld"))
536 
            (eq_attr "check_load" "yes"))
537 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
538 
 
539 
(define_insn_reservation "1_fldp"    9
540 
  (and (and (and (eq_attr "cpu" "itanium")
541 
                 (eq_attr "itanium_class" "fldp"))
542 
            (eq_attr "check_load" "no"))
543 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
544 
(define_insn_reservation "1_fldpc"   0
545 
  (and (and (and (eq_attr "cpu" "itanium")
546 
                 (eq_attr "itanium_class" "fldp"))
547 
            (eq_attr "check_load" "yes"))
548 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
549 
 
550 
(define_insn_reservation "1_fmac"    5
551 
  (and (and (eq_attr "cpu" "itanium")
552 
            (eq_attr "itanium_class" "fmac"))
553 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
554 
(define_insn_reservation "1_fmisc"   5
555 
  (and (and (eq_attr "cpu" "itanium")
556 
            (eq_attr "itanium_class" "fmisc"))
557 
       (eq (symbol_ref "bundling_p") (const_int 0)))
558 
  "1_F+1_not_uf1")
559 
 
560 
;; There is only one insn `mov = ar.bsp' for frar_i:
561 
(define_insn_reservation "1_frar_i" 13
562 
  (and (and (eq_attr "cpu" "itanium")
563 
            (eq_attr "itanium_class" "frar_i"))
564 
       (eq (symbol_ref "bundling_p") (const_int 0)))
565 
  "1_I+1_not_ui1")
566 
;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m:
567 
(define_insn_reservation "1_frar_m"  6
568 
  (and (and (eq_attr "cpu" "itanium")
569 
            (eq_attr "itanium_class" "frar_m"))
570 
       (eq (symbol_ref "bundling_p") (const_int 0)))
571 
  "1_M+1_not_um1")
572 
(define_insn_reservation "1_frbr"    2
573 
  (and (and (eq_attr "cpu" "itanium")
574 
            (eq_attr "itanium_class" "frbr"))
575 
       (eq (symbol_ref "bundling_p") (const_int 0)))
576 
  "1_I+1_not_ui1")
577 
(define_insn_reservation "1_frfr"    2
578 
  (and (and (eq_attr "cpu" "itanium")
579 
            (eq_attr "itanium_class" "frfr"))
580 
       (eq (symbol_ref "bundling_p") (const_int 0)))
581 
  "1_M+1_not_um1")
582 
(define_insn_reservation "1_frpr"    2
583 
  (and (and (eq_attr "cpu" "itanium")
584 
            (eq_attr "itanium_class" "frpr"))
585 
       (eq (symbol_ref "bundling_p") (const_int 0)))
586 
  "1_I+1_not_ui1")
587 
 
588 
(define_insn_reservation "1_ialu"      1
589 
    (and (and (eq_attr "cpu" "itanium")
590 
              (eq_attr "itanium_class" "ialu"))
591 
         (eq (symbol_ref
592 
              "bundling_p || ia64_produce_address_p (insn)")
593 
              (const_int 0)))
594 
    "1_A")
595 
(define_insn_reservation "1_ialu_addr" 1
596 
    (and (and (eq_attr "cpu" "itanium")
597 
              (eq_attr "itanium_class" "ialu"))
598 
         (eq (symbol_ref
599 
              "!bundling_p && ia64_produce_address_p (insn)")
600 
             (const_int 1)))
601 
    "1_M")
602 
(define_insn_reservation "1_icmp"    1
603 
  (and (and (eq_attr "cpu" "itanium")
604 
            (eq_attr "itanium_class" "icmp"))
605 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
606 
(define_insn_reservation "1_ilog"    1
607 
  (and (and (eq_attr "cpu" "itanium")
608 
            (eq_attr "itanium_class" "ilog"))
609 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
610 
(define_insn_reservation "1_mmalua" 2
611 
    (and (and (eq_attr "cpu" "itanium")
612 
              (eq_attr "itanium_class" "mmalua"))
613 
         (eq (symbol_ref "bundling_p") (const_int 0)))
614 
    "1_A")
615 
(define_insn_reservation "1_ishf"    1
616 
  (and (and (eq_attr "cpu" "itanium")
617 
            (eq_attr "itanium_class" "ishf"))
618 
       (eq (symbol_ref "bundling_p") (const_int 0)))
619 
    "1_I+1_not_ui1")
620 
(define_insn_reservation "1_ld"      2
621 
  (and (and (and (eq_attr "cpu" "itanium")
622 
                 (eq_attr "itanium_class" "ld"))
623 
            (eq_attr "check_load" "no"))
624 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
625 
(define_insn_reservation "1_ldc"     0
626 
  (and (and (and (eq_attr "cpu" "itanium")
627 
                 (eq_attr "itanium_class" "ld"))
628 
            (eq_attr "check_load" "yes"))
629 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
630 
(define_insn_reservation "1_long_i"  1
631 
  (and (and (eq_attr "cpu" "itanium")
632 
            (eq_attr "itanium_class" "long_i"))
633 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_L")
634 
(define_insn_reservation "1_mmmul"   2
635 
  (and (and (eq_attr "cpu" "itanium")
636 
            (eq_attr "itanium_class" "mmmul"))
637 
       (eq (symbol_ref "bundling_p") (const_int 0)))
638 
  "1_I+1_not_ui1")
639 
(define_insn_reservation "1_mmshf"   2
640 
  (and (and (eq_attr "cpu" "itanium")
641 
            (eq_attr "itanium_class" "mmshf"))
642 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
643 
(define_insn_reservation "1_mmshfi"  1
644 
  (and (and (eq_attr "cpu" "itanium")
645 
            (eq_attr "itanium_class" "mmshfi"))
646 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
647 
 
648 
;; Now we have only one insn (flushrs) of such class.  We assume that flushrs
649 
;; is the 1st syllable of the bundle after stop bit.
650 
(define_insn_reservation "1_rse_m"   0
651 
  (and (and (eq_attr "cpu" "itanium")
652 
            (eq_attr "itanium_class" "rse_m"))
653 
       (eq (symbol_ref "bundling_p") (const_int 0)))
654 
  "(1_0m.ii|1_0m.mi|1_0m.fi|1_0m.mf|1_0b.bb|1_0m.bb\
655 
    |1_0m.ib|1_0m.mb|1_0m.fb|1_0m.lx)+1_um0")
656 
(define_insn_reservation "1_sem"     0
657 
  (and (and (eq_attr "cpu" "itanium")
658 
            (eq_attr "itanium_class" "sem"))
659 
       (eq (symbol_ref "bundling_p") (const_int 0)))
660 
  "1_M+1_not_um1")
661 
(define_insn_reservation "1_stf"     1
662 
  (and (and (eq_attr "cpu" "itanium")
663 
            (eq_attr "itanium_class" "stf"))
664 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
665 
(define_insn_reservation "1_st"      1
666 
  (and (and (eq_attr "cpu" "itanium")
667 
            (eq_attr "itanium_class" "st"))
668 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
669 
(define_insn_reservation "1_syst_m0" 0
670 
  (and (and (eq_attr "cpu" "itanium")
671 
            (eq_attr "itanium_class" "syst_m0"))
672 
       (eq (symbol_ref "bundling_p") (const_int 0)))
673 
  "1_M+1_not_um1")
674 
(define_insn_reservation "1_syst_m"  0
675 
  (and (and (eq_attr "cpu" "itanium")
676 
            (eq_attr "itanium_class" "syst_m"))
677 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
678 
(define_insn_reservation "1_tbit"    1
679 
  (and (and (eq_attr "cpu" "itanium")
680 
            (eq_attr "itanium_class" "tbit"))
681 
       (eq (symbol_ref "bundling_p") (const_int 0)))
682 
  "1_I+1_not_ui1")
683 
 
684 
;; There is only ony insn `mov ar.pfs =' for toar_i:
685 
(define_insn_reservation "1_toar_i"  0
686 
  (and (and (eq_attr "cpu" "itanium")
687 
            (eq_attr "itanium_class" "toar_i"))
688 
       (eq (symbol_ref "bundling_p") (const_int 0)))
689 
  "1_I+1_not_ui1")
690 
;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m:
691 
(define_insn_reservation "1_toar_m"  5
692 
  (and (and (eq_attr "cpu" "itanium")
693 
            (eq_attr "itanium_class" "toar_m"))
694 
       (eq (symbol_ref "bundling_p") (const_int 0)))
695 
  "1_M+1_not_um1")
696 
(define_insn_reservation "1_tobr"    1
697 
  (and (and (eq_attr "cpu" "itanium")
698 
            (eq_attr "itanium_class" "tobr"))
699 
       (eq (symbol_ref "bundling_p") (const_int 0)))
700 
  "1_I+1_not_ui1")
701 
(define_insn_reservation "1_tofr"    9
702 
  (and (and (eq_attr "cpu" "itanium")
703 
            (eq_attr "itanium_class" "tofr"))
704 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
705 
(define_insn_reservation "1_topr"    1
706 
  (and (and (eq_attr "cpu" "itanium")
707 
            (eq_attr "itanium_class" "topr"))
708 
       (eq (symbol_ref "bundling_p") (const_int 0)))
709 
  "1_I+1_not_ui1")
710 
(define_insn_reservation "1_xmpy"    7
711 
  (and (and (eq_attr "cpu" "itanium")
712 
            (eq_attr "itanium_class" "xmpy"))
713 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
714 
(define_insn_reservation "1_xtd"     1
715 
  (and (and (eq_attr "cpu" "itanium")
716 
            (eq_attr "itanium_class" "xtd"))
717 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
718 
 
719 
(define_insn_reservation "1_chk_s_i" 0
720 
  (and (and (eq_attr "cpu" "itanium")
721 
            (eq_attr "itanium_class" "chk_s_i"))
722 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
723 
(define_insn_reservation "1_chk_s_f" 0
724 
  (and (and (eq_attr "cpu" "itanium")
725 
            (eq_attr "itanium_class" "chk_s_f"))
726 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
727 
(define_insn_reservation "1_chk_a"   0
728 
  (and (and (eq_attr "cpu" "itanium")
729 
            (eq_attr "itanium_class" "chk_a"))
730 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
731 
 
732 
(define_insn_reservation "1_lfetch"  0
733 
  (and (and (eq_attr "cpu" "itanium")
734 
            (eq_attr "itanium_class" "lfetch"))
735 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
736 
 
737 
(define_insn_reservation "1_nop_m"   0
738 
  (and (and (eq_attr "cpu" "itanium")
739 
            (eq_attr "itanium_class" "nop_m"))
740 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_M0")
741 
(define_insn_reservation "1_nop_b"   0
742 
  (and (and (eq_attr "cpu" "itanium")
743 
            (eq_attr "itanium_class" "nop_b"))
744 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_NB")
745 
(define_insn_reservation "1_nop_i"   0
746 
  (and (and (eq_attr "cpu" "itanium")
747 
            (eq_attr "itanium_class" "nop_i"))
748 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_I0")
749 
(define_insn_reservation "1_nop_f"   0
750 
  (and (and (eq_attr "cpu" "itanium")
751 
            (eq_attr "itanium_class" "nop_f"))
752 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_F0")
753 
(define_insn_reservation "1_nop_x"   0
754 
  (and (and (eq_attr "cpu" "itanium")
755 
            (eq_attr "itanium_class" "nop_x"))
756 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_L0")
757 
 
758 
;; We assume that there is no insn issued on the same cycle as unknown insn.
759 
(define_cpu_unit "1_empty" "one")
760 
(exclusion_set "1_empty"
761 
    "1_0m.ii,1_0m.mi,1_0m.fi,1_0m.mf,1_0b.bb,1_0m.bb,1_0m.ib,1_0m.mb,1_0m.fb,\
762 
     1_0m.lx")
763 
 
764 
(define_insn_reservation "1_unknown" 1
765 
  (and (and (eq_attr "cpu" "itanium")
766 
            (eq_attr "itanium_class" "unknown"))
767 
       (eq (symbol_ref "bundling_p") (const_int 0))) "1_empty")
768 
 
769 
(define_insn_reservation "1_nop" 1
770 
  (and (and (eq_attr "cpu" "itanium")
771 
            (eq_attr "itanium_class" "nop"))
772 
       (eq (symbol_ref "bundling_p") (const_int 0)))
773 
  "1_M0|1_NB|1_I0|1_F0")
774 
 
775 
(define_insn_reservation "1_ignore" 0
776 
  (and (and (eq_attr "cpu" "itanium")
777 
            (eq_attr "itanium_class" "ignore"))
778 
       (eq (symbol_ref "bundling_p") (const_int 0))) "nothing")
779 
 
780 
 
781 
(define_cpu_unit
782 
   "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs"
783 
   "one")
784 
(define_cpu_unit
785 
   "1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs"
786 
   "one")
787 
 
788 
(define_cpu_unit "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont, 1_mb_cont,\
789 
                  1_b_cont, 1_bb_cont" "one")
790 
 
791 
;; For stop in the middle of the bundles.
792 
(define_cpu_unit "1_m_stop, 1_m0_stop, 1_m1_stop, 1_0mmi_cont" "one")
793 
(define_cpu_unit "1_mi_stop, 1_mi0_stop, 1_mi1_stop, 1_0mii_cont" "one")
794 
 
795 
(final_presence_set "1_0m_bs"
796 
   "1_0m.ii, 1_0m.mi, 1_0m.mf, 1_0m.fi, 1_0m.bb,\
797 
    1_0m.ib, 1_0m.fb, 1_0m.mb, 1_0m.lx")
798 
(final_presence_set "1_1m_bs"
799 
   "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1m.bb, 1_1m.ib, 1_1m.fb, 1_1m.mb,\
800 
    1_1m.lx")
801 
(final_presence_set "1_0mi_bs"  "1_0mi.i, 1_0mi.i")
802 
(final_presence_set "1_1mi_bs"  "1_1mi.i, 1_1mi.i")
803 
(final_presence_set "1_0mm_bs"  "1_0mm.i, 1_0mm.f, 1_0mm.b")
804 
(final_presence_set "1_1mm_bs"  "1_1mm.i, 1_1mm.b")
805 
(final_presence_set "1_0mf_bs"  "1_0mf.i, 1_0mf.b")
806 
(final_presence_set "1_1mf_bs"  "1_1mf.i, 1_1mf.b")
807 
(final_presence_set "1_0b_bs"  "1_0b.bb")
808 
(final_presence_set "1_1b_bs"  "1_1b.bb")
809 
(final_presence_set "1_0bb_bs"  "1_0bb.b")
810 
(final_presence_set "1_1bb_bs"  "1_1bb.b")
811 
(final_presence_set "1_0mb_bs"  "1_0mb.b")
812 
(final_presence_set "1_1mb_bs"  "1_1mb.b")
813 
 
814 
(exclusion_set "1_0m_bs"
815 
   "1_0mi.i, 1_0mm.i, 1_0mm.f, 1_0mf.i, 1_0mb.b,\
816 
    1_0mi.b, 1_0mf.b, 1_0mm.b, 1_0mlx., 1_m0_stop")
817 
(exclusion_set "1_1m_bs"
818 
   "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1mb.b, 1_1mi.b, 1_1mf.b, 1_1mm.b,\
819 
    1_1mlx., 1_m1_stop")
820 
(exclusion_set "1_0mi_bs"  "1_0mii., 1_0mib., 1_mi0_stop")
821 
(exclusion_set "1_1mi_bs"  "1_1mii., 1_1mib., 1_mi1_stop")
822 
(exclusion_set "1_0mm_bs"  "1_0mmi., 1_0mmf., 1_0mmb.")
823 
(exclusion_set "1_1mm_bs"  "1_1mmi., 1_1mmb.")
824 
(exclusion_set "1_0mf_bs"  "1_0mfi., 1_0mfb.")
825 
(exclusion_set "1_1mf_bs"  "1_1mfi., 1_1mfb.")
826 
(exclusion_set "1_0b_bs"  "1_0bb.b")
827 
(exclusion_set "1_1b_bs"  "1_1bb.b")
828 
(exclusion_set "1_0bb_bs"  "1_0bbb.")
829 
(exclusion_set "1_1bb_bs"  "1_1bbb.")
830 
(exclusion_set "1_0mb_bs"  "1_0mbb.")
831 
(exclusion_set "1_1mb_bs"  "1_1mbb.")
832 
 
833 
(exclusion_set
834 
   "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs,
835 
    1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs"
836 
   "1_stop")
837 
 
838 
(final_presence_set
839 
   "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\
840 
    1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx."
841 
   "1_m_cont")
842 
(final_presence_set "1_0mii., 1_0mib." "1_mi_cont")
843 
(final_presence_set "1_0mmi., 1_0mmf., 1_0mmb." "1_mm_cont")
844 
(final_presence_set "1_0mfi., 1_0mfb." "1_mf_cont")
845 
(final_presence_set "1_0bb.b" "1_b_cont")
846 
(final_presence_set "1_0bbb." "1_bb_cont")
847 
(final_presence_set "1_0mbb." "1_mb_cont")
848 
 
849 
(exclusion_set
850 
   "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\
851 
    1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx"
852 
   "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont,\
853 
    1_mb_cont, 1_b_cont, 1_bb_cont")
854 
 
855 
(exclusion_set "1_empty"
856 
               "1_m_cont,1_mi_cont,1_mm_cont,1_mf_cont,\
857 
                1_mb_cont,1_b_cont,1_bb_cont")
858 
 
859 
;; For m;mi bundle
860 
(final_presence_set "1_m0_stop" "1_0m.mi")
861 
(final_presence_set "1_0mm.i" "1_0mmi_cont")
862 
(exclusion_set "1_0mmi_cont"
863 
   "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\
864 
    1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
865 
(exclusion_set "1_m0_stop" "1_0mm.i")
866 
(final_presence_set "1_m1_stop" "1_1m.mi")
867 
(exclusion_set "1_m1_stop" "1_1mm.i")
868 
(final_presence_set "1_m_stop" "1_m0_stop, 1_m1_stop")
869 
 
870 
;; For mi;i bundle
871 
(final_presence_set "1_mi0_stop" "1_0mi.i")
872 
(final_presence_set "1_0mii." "1_0mii_cont")
873 
(exclusion_set "1_0mii_cont"
874 
   "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\
875 
    1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx")
876 
(exclusion_set "1_mi0_stop" "1_0mii.")
877 
(final_presence_set "1_mi1_stop" "1_1mi.i")
878 
(exclusion_set "1_mi1_stop" "1_1mii.")
879 
(final_presence_set "1_mi_stop" "1_mi0_stop, 1_mi1_stop")
880 
 
881 
(final_absence_set
882 
   "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\
883 
    1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\
884 
    1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\
885 
    1_0m.lx,1_0mlx., \
886 
    1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\
887 
    1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,\
888 
    1_1m.ib,1_1mi.b,1_1mib.,1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,\
889 
    1_1m.lx,1_1mlx."
890 
   "1_m0_stop,1_m1_stop,1_mi0_stop,1_mi1_stop")
891 
 
892 
(define_cpu_unit "1_m_cont_only, 1_b_cont_only" "one")
893 
(define_cpu_unit "1_mi_cont_only, 1_mm_cont_only, 1_mf_cont_only" "one")
894 
(define_cpu_unit "1_mb_cont_only, 1_bb_cont_only" "one")
895 
 
896 
(final_presence_set "1_m_cont_only" "1_m_cont")
897 
(exclusion_set "1_m_cont_only"
898 
  "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\
899 
   1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.")
900 
 
901 
(final_presence_set "1_b_cont_only" "1_b_cont")
902 
(exclusion_set "1_b_cont_only"  "1_0bb.b")
903 
 
904 
(final_presence_set "1_mi_cont_only" "1_mi_cont")
905 
(exclusion_set "1_mi_cont_only" "1_0mii., 1_0mib.")
906 
 
907 
(final_presence_set "1_mm_cont_only" "1_mm_cont")
908 
(exclusion_set "1_mm_cont_only" "1_0mmi., 1_0mmf., 1_0mmb.")
909 
 
910 
(final_presence_set "1_mf_cont_only" "1_mf_cont")
911 
(exclusion_set "1_mf_cont_only" "1_0mfi., 1_0mfb.")
912 
 
913 
(final_presence_set "1_mb_cont_only" "1_mb_cont")
914 
(exclusion_set "1_mb_cont_only" "1_0mbb.")
915 
 
916 
(final_presence_set "1_bb_cont_only" "1_bb_cont")
917 
(exclusion_set "1_bb_cont_only" "1_0bbb.")
918 
 
919 
(define_insn_reservation "1_pre_cycle" 0
920 
   (and (and (eq_attr "cpu" "itanium")
921 
             (eq_attr "itanium_class" "pre_cycle"))
922 
        (eq (symbol_ref "bundling_p") (const_int 0)))
923 
                         "(1_0m_bs, 1_m_cont)                     \
924 
                          | (1_0mi_bs, (1_mi_cont|nothing))       \
925 
                          | (1_0mm_bs, 1_mm_cont)                 \
926 
                          | (1_0mf_bs, (1_mf_cont|nothing))       \
927 
                          | (1_0b_bs, (1_b_cont|nothing))         \
928 
                          | (1_0bb_bs, (1_bb_cont|nothing))       \
929 
                          | (1_0mb_bs, (1_mb_cont|nothing))       \
930 
                          | (1_1m_bs, 1_m_cont)                   \
931 
                          | (1_1mi_bs, (1_mi_cont|nothing))       \
932 
                          | (1_1mm_bs, 1_mm_cont)                 \
933 
                          | (1_1mf_bs, (1_mf_cont|nothing))       \
934 
                          | (1_1b_bs, (1_b_cont|nothing))         \
935 
                          | (1_1bb_bs, (1_bb_cont|nothing))       \
936 
                          | (1_1mb_bs, (1_mb_cont|nothing))       \
937 
                          | (1_m_cont_only, (1_m_cont|nothing))   \
938 
                          | (1_b_cont_only,  (1_b_cont|nothing))  \
939 
                          | (1_mi_cont_only, (1_mi_cont|nothing)) \
940 
                          | (1_mm_cont_only, (1_mm_cont|nothing)) \
941 
                          | (1_mf_cont_only, (1_mf_cont|nothing)) \
942 
                          | (1_mb_cont_only, (1_mb_cont|nothing)) \
943 
                          | (1_bb_cont_only, (1_bb_cont|nothing)) \
944 
                          | (1_m_stop, (1_0mmi_cont|nothing))     \
945 
                          | (1_mi_stop, (1_0mii_cont|nothing))")
946 
 
947 
;; Bypasses:
948 
(define_bypass  1 "1_fcmp" "1_br,1_scall")
949 
;; ??? I found 7 cycle delay for 1_fmac -> 1_fcmp for Itanium1
950 
(define_bypass  7 "1_fmac" "1_fmisc,1_fcvtfx,1_xmpy,1_fcmp")
951 
 
952 
;; ???
953 
(define_bypass  3 "1_frbr" "1_mmmul,1_mmshf")
954 
(define_bypass 14 "1_frar_i" "1_mmmul,1_mmshf")
955 
(define_bypass  7 "1_frar_m" "1_mmmul,1_mmshf")
956 
 
957 
;; ????
958 
;; There is only one insn `mov ar.pfs =' for toar_i.
959 
(define_bypass  0 "1_tobr,1_topr,1_toar_i" "1_br,1_scall")
960 
 
961 
(define_bypass  3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf,1_mmalua")
962 
;; ??? howto describe ialu for I slot only.  We use ialu_addr for that
963 
;;(define_bypass  2 "1_ialu" "1_ld"  "ia64_ld_address_bypass_p")
964 
;; ??? howto describe ialu st/address for I slot only.  We use ialu_addr
965 
;;   for that.
966 
;;(define_bypass  2 "1_ialu" "1_st"  "ia64_st_address_bypass_p")
967 
 
968 
(define_bypass  0 "1_icmp" "1_br,1_scall")
969 
 
970 
(define_bypass  3 "1_ilog" "1_mmmul,1_mmshf")
971 
 
972 
(define_bypass  2 "1_ilog,1_xtd" "1_ld"  "ia64_ld_address_bypass_p")
973 
(define_bypass  2 "1_ilog,1_xtd" "1_st"  "ia64_st_address_bypass_p")
974 
 
975 
(define_bypass  3 "1_ld,1_ldc" "1_mmmul,1_mmshf")
976 
(define_bypass  3 "1_ld" "1_ld"  "ia64_ld_address_bypass_p")
977 
(define_bypass  3 "1_ld" "1_st"  "ia64_st_address_bypass_p")
978 
 
979 
;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4,
980 
;;      but HP engineers say any non-MM operation.
981 
(define_bypass  4 "1_mmmul,1_mmshf,1_mmalua"
982 
     "1_br,1_fcmp,1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
983 
      1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,1_chk_s_i,1_chk_s_f,1_chk_a,\
984 
      1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\
985 
      1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd")
986 
 
987 
;; ??? how to describe that if scheduled < 4 cycle then latency is 10 cycles.
988 
;; (define_bypass  10 "1_mmmul,1_mmshf" "1_ialu,1_ilog,1_ishf,1_st,1_ld")
989 
 
990 
(define_bypass  0 "1_tbit" "1_br,1_scall")
991 
 
992 
(define_bypass  8 "1_tofr"  "1_frfr,1_stf")
993 
(define_bypass  7 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy"  "1_frfr")
994 
(define_bypass  8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy"  "1_stf")
995 
 
996 
;; We don't use here fcmp because scall may be predicated.
997 
(define_bypass  0 "1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
998 
                   1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\
999 
                   1_ld,1_ldc,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,\
1000 
                   1_toar_m,1_tofr,1_xmpy,1_xtd" "1_scall")
1001 
 
1002 
(define_bypass  0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\
1003 
                   1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\
1004 
                   1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,\
1005 
                   1_chk_s_i,1_chk_s_f,1_chk_a,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_nop,\
1006 
                   1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\
1007 
                   1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\
1008 
                   1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch"
1009 
                  "1_ignore")
1010 
 
1011 
 
1012 
;; Bundling
1013 
 
1014 
(define_automaton "oneb")
1015 
 
1016 
;; Pseudo units for quicker searching for position in two packet window.  */
1017 
(define_query_cpu_unit "1_1,1_2,1_3,1_4,1_5,1_6" "oneb")
1018 
 
1019 
;;   All possible combinations of bundles/syllables
1020 
(define_cpu_unit
1021 
   "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\
1022 
    1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" "oneb")
1023 
(define_cpu_unit
1024 
   "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\
1025 
    1b_0mi.b, 1b_0mm.b, 1b_0mf.b" "oneb")
1026 
(define_query_cpu_unit
1027 
   "1b_0mii., 1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\
1028 
    1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx." "oneb")
1029 
 
1030 
(define_cpu_unit "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\
1031 
                  1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx" "oneb")
1032 
(define_cpu_unit "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\
1033 
                  1b_1mi.b, 1b_1mm.b, 1b_1mf.b" "oneb")
1034 
(define_query_cpu_unit "1b_1mii., 1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\
1035 
                        1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx." "oneb")
1036 
 
1037 
;; Slot 1
1038 
(exclusion_set "1b_0m.ii"
1039 
   "1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\
1040 
    1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1041 
(exclusion_set "1b_0m.mi"
1042 
   "1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib,\
1043 
    1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1044 
(exclusion_set "1b_0m.fi"
1045 
   "1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1046 
(exclusion_set "1b_0m.mf"
1047 
   "1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1048 
(exclusion_set "1b_0b.bb" "1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1049 
(exclusion_set "1b_0m.bb" "1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1050 
(exclusion_set "1b_0m.ib" "1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1051 
(exclusion_set "1b_0m.mb" "1b_0m.fb, 1b_0m.lx")
1052 
(exclusion_set "1b_0m.fb" "1b_0m.lx")
1053 
 
1054 
;; Slot 2
1055 
(exclusion_set "1b_0mi.i"
1056 
   "1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\
1057 
    1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
1058 
(exclusion_set "1b_0mm.i"
1059 
   "1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\
1060 
    1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
1061 
(exclusion_set "1b_0mf.i"
1062 
   "1b_0mm.f, 1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
1063 
(exclusion_set "1b_0mm.f"
1064 
   "1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
1065 
(exclusion_set "1b_0bb.b" "1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
1066 
(exclusion_set "1b_0mb.b" "1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
1067 
(exclusion_set "1b_0mi.b" "1b_0mm.b, 1b_0mf.b, 1b_0mlx.")
1068 
(exclusion_set "1b_0mm.b" "1b_0mf.b, 1b_0mlx.")
1069 
(exclusion_set "1b_0mf.b" "1b_0mlx.")
1070 
 
1071 
;; Slot 3
1072 
(exclusion_set "1b_0mii."
1073 
   "1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\
1074 
    1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
1075 
(exclusion_set "1b_0mmi."
1076 
   "1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\
1077 
    1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
1078 
(exclusion_set "1b_0mfi."
1079 
   "1b_0mmf., 1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
1080 
(exclusion_set "1b_0mmf."
1081 
   "1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
1082 
(exclusion_set "1b_0bbb." "1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
1083 
(exclusion_set "1b_0mbb." "1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.")
1084 
(exclusion_set "1b_0mib." "1b_0mmb., 1b_0mfb., 1b_0mlx.")
1085 
(exclusion_set "1b_0mmb." "1b_0mfb., 1b_0mlx.")
1086 
(exclusion_set "1b_0mfb." "1b_0mlx.")
1087 
 
1088 
;; Slot 4
1089 
(exclusion_set "1b_1m.ii"
1090 
   "1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\
1091 
    1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
1092 
(exclusion_set "1b_1m.mi"
1093 
   "1b_1m.fi, 1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
1094 
(exclusion_set "1b_1m.fi"
1095 
   "1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
1096 
(exclusion_set "1b_1b.bb" "1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
1097 
(exclusion_set "1b_1m.bb" "1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
1098 
(exclusion_set "1b_1m.ib" "1b_1m.mb, 1b_1m.fb, 1b_1m.lx")
1099 
(exclusion_set "1b_1m.mb" "1b_1m.fb, 1b_1m.lx")
1100 
(exclusion_set "1b_1m.fb" "1b_1m.lx")
1101 
 
1102 
;; Slot 5
1103 
(exclusion_set "1b_1mi.i"
1104 
   "1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\
1105 
    1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
1106 
(exclusion_set "1b_1mm.i"
1107 
   "1b_1mf.i, 1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
1108 
(exclusion_set "1b_1mf.i"
1109 
   "1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
1110 
(exclusion_set "1b_1bb.b" "1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
1111 
(exclusion_set "1b_1mb.b" "1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
1112 
(exclusion_set "1b_1mi.b" "1b_1mm.b, 1b_1mf.b, 1b_1mlx.")
1113 
(exclusion_set "1b_1mm.b" "1b_1mf.b, 1b_1mlx.")
1114 
(exclusion_set "1b_1mf.b" "1b_1mlx.")
1115 
 
1116 
;; Slot 6
1117 
(exclusion_set "1b_1mii."
1118 
   "1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\
1119 
    1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
1120 
(exclusion_set "1b_1mmi."
1121 
   "1b_1mfi., 1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
1122 
(exclusion_set "1b_1mfi."
1123 
   "1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
1124 
(exclusion_set "1b_1bbb." "1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
1125 
(exclusion_set "1b_1mbb." "1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.")
1126 
(exclusion_set "1b_1mib." "1b_1mmb., 1b_1mfb., 1b_1mlx.")
1127 
(exclusion_set "1b_1mmb." "1b_1mfb., 1b_1mlx.")
1128 
(exclusion_set "1b_1mfb." "1b_1mlx.")
1129 
 
1130 
(final_presence_set "1b_0mi.i" "1b_0m.ii")
1131 
(final_presence_set "1b_0mii." "1b_0mi.i")
1132 
(final_presence_set "1b_1mi.i" "1b_1m.ii")
1133 
(final_presence_set "1b_1mii." "1b_1mi.i")
1134 
 
1135 
(final_presence_set "1b_0mm.i" "1b_0m.mi")
1136 
(final_presence_set "1b_0mmi." "1b_0mm.i")
1137 
(final_presence_set "1b_1mm.i" "1b_1m.mi")
1138 
(final_presence_set "1b_1mmi." "1b_1mm.i")
1139 
 
1140 
(final_presence_set "1b_0mf.i" "1b_0m.fi")
1141 
(final_presence_set "1b_0mfi." "1b_0mf.i")
1142 
(final_presence_set "1b_1mf.i" "1b_1m.fi")
1143 
(final_presence_set "1b_1mfi." "1b_1mf.i")
1144 
 
1145 
(final_presence_set "1b_0mm.f" "1b_0m.mf")
1146 
(final_presence_set "1b_0mmf." "1b_0mm.f")
1147 
 
1148 
(final_presence_set "1b_0bb.b" "1b_0b.bb")
1149 
(final_presence_set "1b_0bbb." "1b_0bb.b")
1150 
(final_presence_set "1b_1bb.b" "1b_1b.bb")
1151 
(final_presence_set "1b_1bbb." "1b_1bb.b")
1152 
 
1153 
(final_presence_set "1b_0mb.b" "1b_0m.bb")
1154 
(final_presence_set "1b_0mbb." "1b_0mb.b")
1155 
(final_presence_set "1b_1mb.b" "1b_1m.bb")
1156 
(final_presence_set "1b_1mbb." "1b_1mb.b")
1157 
 
1158 
(final_presence_set "1b_0mi.b" "1b_0m.ib")
1159 
(final_presence_set "1b_0mib." "1b_0mi.b")
1160 
(final_presence_set "1b_1mi.b" "1b_1m.ib")
1161 
(final_presence_set "1b_1mib." "1b_1mi.b")
1162 
 
1163 
(final_presence_set "1b_0mm.b" "1b_0m.mb")
1164 
(final_presence_set "1b_0mmb." "1b_0mm.b")
1165 
(final_presence_set "1b_1mm.b" "1b_1m.mb")
1166 
(final_presence_set "1b_1mmb." "1b_1mm.b")
1167 
 
1168 
(final_presence_set "1b_0mf.b" "1b_0m.fb")
1169 
(final_presence_set "1b_0mfb." "1b_0mf.b")
1170 
(final_presence_set "1b_1mf.b" "1b_1m.fb")
1171 
(final_presence_set "1b_1mfb." "1b_1mf.b")
1172 
 
1173 
(final_presence_set "1b_0mlx." "1b_0m.lx")
1174 
(final_presence_set "1b_1mlx." "1b_1m.lx")
1175 
 
1176 
(final_presence_set
1177 
   "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\
1178 
    1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx"
1179 
   "1b_0mii.,1b_0mmi.,1b_0mfi.,1b_0mmf.,1b_0bbb.,1b_0mbb.,\
1180 
    1b_0mib.,1b_0mmb.,1b_0mfb.,1b_0mlx.")
1181 
 
1182 
;;  Microarchitecture units:
1183 
(define_cpu_unit
1184 
   "1b_um0, 1b_um1, 1b_ui0, 1b_ui1, 1b_uf0, 1b_uf1, 1b_ub0, 1b_ub1, 1b_ub2,\
1185 
    1b_unb0, 1b_unb1, 1b_unb2" "oneb")
1186 
 
1187 
(exclusion_set "1b_ub0" "1b_unb0")
1188 
(exclusion_set "1b_ub1" "1b_unb1")
1189 
(exclusion_set "1b_ub2" "1b_unb2")
1190 
 
1191 
;; The following rules are used to decrease number of alternatives.
1192 
;; They are consequences of Itanium microarchitecture.  They also
1193 
;; describe the following rules mentioned in Itanium
1194 
;; microarchitecture: rules mentioned in Itanium microarchitecture:
1195 
;; o "MMF: Always splits issue before the first M and after F regardless
1196 
;;   of surrounding bundles and stops".
1197 
;; o "BBB/MBB: Always splits issue after either of these bundles".
1198 
;; o "MIB BBB: Split issue after the first bundle in this pair".
1199 
 
1200 
(exclusion_set "1b_0m.mf,1b_0mm.f,1b_0mmf."
1201 
   "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\
1202 
    1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx")
1203 
(exclusion_set "1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb."
1204 
   "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\
1205 
    1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx")
1206 
(exclusion_set "1b_0m.ib,1b_0mi.b,1b_0mib." "1b_1b.bb")
1207 
 
1208 
;;  For exceptions of M, I, B, F insns:
1209 
(define_cpu_unit "1b_not_um1, 1b_not_ui1, 1b_not_uf1" "oneb")
1210 
 
1211 
(final_absence_set "1b_not_um1"  "1b_um1")
1212 
(final_absence_set "1b_not_ui1"  "1b_ui1")
1213 
(final_absence_set "1b_not_uf1"  "1b_uf1")
1214 
 
1215 
;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
1216 
;;; B-slot contains a nop.b or a brp instruction".
1217 
;;;   "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
1218 
;;; nop.b, otherwise it disperses to B2".
1219 
(final_absence_set
1220 
   "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\
1221 
    1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx"
1222 
   "1b_0mib. 1b_ub2, 1b_0mfb. 1b_ub2, 1b_0mmb. 1b_ub2")
1223 
 
1224 
;; This is necessary to start new processor cycle when we meet stop bit.
1225 
(define_cpu_unit "1b_stop" "oneb")
1226 
(final_absence_set
1227 
   "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\
1228 
    1b_0m.fi,1b_0mf.i,1b_0mfi.,\
1229 
    1b_0m.mf,1b_0mm.f,1b_0mmf.,1b_0b.bb,1b_0bb.b,1b_0bbb.,\
1230 
    1b_0m.bb,1b_0mb.b,1b_0mbb.,\
1231 
    1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\
1232 
    1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \
1233 
    1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\
1234 
    1b_1m.fi,1b_1mf.i,1b_1mfi.,\
1235 
    1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\
1236 
    1b_1m.ib,1b_1mi.b,1b_1mib.,\
1237 
    1b_1m.mb,1b_1mm.b,1b_1mmb.,1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx."
1238 
   "1b_stop")
1239 
 
1240 
;; M and I instruction is dispersed to the lowest numbered M or I unit
1241 
;; not already in use.  An I slot in the 3rd position of 2nd bundle is
1242 
;; always dispersed to I1
1243 
(final_presence_set "1b_um1" "1b_um0")
1244 
(final_presence_set "1b_ui1" "1b_ui0, 1b_1mii., 1b_1mmi., 1b_1mfi.")
1245 
 
1246 
;; Insns
1247 
 
1248 
;; M and I instruction is dispersed to the lowest numbered M or I unit
1249 
;; not already in use.  An I slot in the 3rd position of 2nd bundle is
1250 
;; always dispersed to I1
1251 
(define_reservation "1b_M"
1252 
  "1b_0m.ii+1_1+1b_um0|1b_0m.mi+1_1+1b_um0|1b_0mm.i+1_2+(1b_um0|1b_um1)\
1253 
   |1b_0m.fi+1_1+1b_um0|1b_0m.mf+1_1+1b_um0|1b_0mm.f+1_2+1b_um1\
1254 
   |1b_0m.bb+1_1+1b_um0|1b_0m.ib+1_1+1b_um0|1b_0m.mb+1_1+1b_um0\
1255 
   |1b_0mm.b+1_2+1b_um1|1b_0m.fb+1_1+1b_um0|1b_0m.lx+1_1+1b_um0\
1256 
   |1b_1mm.i+1_5+1b_um1|1b_1mm.b+1_5+1b_um1\
1257 
   |(1b_1m.ii+1_4|1b_1m.mi+1_4|1b_1m.fi+1_4|1b_1m.bb+1_4|1b_1m.ib+1_4\
1258 
     |1b_1m.mb+1_4|1b_1m.fb+1_4|1b_1m.lx+1_4)\
1259 
    +(1b_um0|1b_um1)")
1260 
 
1261 
;;  Exceptions for dispersal rules.
1262 
;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1".
1263 
(define_reservation "1b_I"
1264 
  "1b_0mi.i+1_2+1b_ui0|1b_0mii.+1_3+(1b_ui0|1b_ui1)|1b_0mmi.+1_3+1b_ui0\
1265 
   |1b_0mfi.+1_3+1b_ui0|1b_0mi.b+1_2+1b_ui0\
1266 
   |(1b_1mi.i+1_5|1b_1mi.b+1_5)+(1b_ui0|1b_ui1)\
1267 
   |1b_1mii.+1_6+1b_ui1|1b_1mmi.+1_6+1b_ui1|1b_1mfi.+1_6+1b_ui1")
1268 
 
1269 
;; "An F slot in the 1st bundle disperses to F0".
1270 
;; "An F slot in the 2st bundle disperses to F1".
1271 
(define_reservation "1b_F"
1272 
   "1b_0mf.i+1_2+1b_uf0|1b_0mmf.+1_3+1b_uf0|1b_0mf.b+1_2+1b_uf0\
1273 
    |1b_1mf.i+1_5+1b_uf1|1b_1mf.b+1_5+1b_uf1")
1274 
 
1275 
;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
1276 
;;; unit. That is, a B slot in 1st position is dispersed to B0.  In the
1277 
;;; 2nd position it is dispersed to B2".
1278 
(define_reservation "1b_NB"
1279 
    "1b_0b.bb+1_1+1b_unb0|1b_0bb.b+1_2+1b_unb1|1b_0bbb.+1_3+1b_unb2\
1280 
     |1b_0mb.b+1_2+1b_unb1|1b_0mbb.+1_3+1b_unb2\
1281 
     |1b_0mib.+1_3+1b_unb0|1b_0mmb.+1_3+1b_unb0|1b_0mfb.+1_3+1b_unb0\
1282 
     |1b_1b.bb+1_4+1b_unb0|1b_1bb.b+1_5+1b_unb1\
1283 
     |1b_1bbb.+1_6+1b_unb2|1b_1mb.b+1_5+1b_unb1|1b_1mbb.+1_6+1b_unb2\
1284 
     |1b_1mib.+1_6+1b_unb0|1b_1mmb.+1_6+1b_unb0|1b_1mfb.+1_6+1b_unb0")
1285 
 
1286 
(define_reservation "1b_B"
1287 
   "1b_0b.bb+1_1+1b_ub0|1b_0bb.b+1_2+1b_ub1|1b_0bbb.+1_3+1b_ub2\
1288 
    |1b_0mb.b+1_2+1b_ub1|1b_0mbb.+1_3+1b_ub2|1b_0mib.+1_3+1b_ub2\
1289 
    |1b_0mfb.+1_3+1b_ub2|1b_1b.bb+1_4+1b_ub0|1b_1bb.b+1_5+1b_ub1\
1290 
    |1b_1bbb.+1_6+1b_ub2|1b_1mb.b+1_5+1b_ub1\
1291 
    |1b_1mib.+1_6+1b_ub2|1b_1mmb.+1_6+1b_ub2|1b_1mfb.+1_6+1b_ub2")
1292 
 
1293 
(define_reservation "1b_L" "1b_0mlx.+1_3+1b_ui0+1b_uf0\
1294 
                           |1b_1mlx.+1_6+(1b_ui0|1b_ui1)+1b_uf1")
1295 
 
1296 
;; We assume that there is no insn issued on the same cycle as unknown insn.
1297 
(define_cpu_unit "1b_empty" "oneb")
1298 
(exclusion_set "1b_empty"
1299 
    "1b_0m.ii,1b_0m.mi,1b_0m.fi,1b_0m.mf,1b_0b.bb,1b_0m.bb,\
1300 
     1b_0m.ib,1b_0m.mb,1b_0m.fb,1b_0m.lx")
1301 
 
1302 
(define_cpu_unit
1303 
   "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs"
1304 
   "oneb")
1305 
(define_cpu_unit
1306 
   "1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs"
1307 
   "oneb")
1308 
 
1309 
(define_cpu_unit "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont, 1b_mb_cont,\
1310 
                  1b_b_cont, 1b_bb_cont" "oneb")
1311 
 
1312 
;; For stop in the middle of the bundles.
1313 
(define_cpu_unit "1b_m_stop, 1b_m0_stop, 1b_m1_stop, 1b_0mmi_cont" "oneb")
1314 
(define_cpu_unit "1b_mi_stop, 1b_mi0_stop, 1b_mi1_stop, 1b_0mii_cont" "oneb")
1315 
 
1316 
(final_presence_set "1b_0m_bs"
1317 
   "1b_0m.ii, 1b_0m.mi, 1b_0m.mf, 1b_0m.fi, 1b_0m.bb,\
1318 
    1b_0m.ib, 1b_0m.fb, 1b_0m.mb, 1b_0m.lx")
1319 
(final_presence_set "1b_1m_bs"
1320 
   "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1m.bb, 1b_1m.ib, 1b_1m.fb, 1b_1m.mb,\
1321 
    1b_1m.lx")
1322 
(final_presence_set "1b_0mi_bs"  "1b_0mi.i, 1b_0mi.i")
1323 
(final_presence_set "1b_1mi_bs"  "1b_1mi.i, 1b_1mi.i")
1324 
(final_presence_set "1b_0mm_bs"  "1b_0mm.i, 1b_0mm.f, 1b_0mm.b")
1325 
(final_presence_set "1b_1mm_bs"  "1b_1mm.i, 1b_1mm.b")
1326 
(final_presence_set "1b_0mf_bs"  "1b_0mf.i, 1b_0mf.b")
1327 
(final_presence_set "1b_1mf_bs"  "1b_1mf.i, 1b_1mf.b")
1328 
(final_presence_set "1b_0b_bs"  "1b_0b.bb")
1329 
(final_presence_set "1b_1b_bs"  "1b_1b.bb")
1330 
(final_presence_set "1b_0bb_bs"  "1b_0bb.b")
1331 
(final_presence_set "1b_1bb_bs"  "1b_1bb.b")
1332 
(final_presence_set "1b_0mb_bs"  "1b_0mb.b")
1333 
(final_presence_set "1b_1mb_bs"  "1b_1mb.b")
1334 
 
1335 
(exclusion_set "1b_0m_bs"
1336 
   "1b_0mi.i, 1b_0mm.i, 1b_0mm.f, 1b_0mf.i, 1b_0mb.b,\
1337 
    1b_0mi.b, 1b_0mf.b, 1b_0mm.b, 1b_0mlx., 1b_m0_stop")
1338 
(exclusion_set "1b_1m_bs"
1339 
   "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1mb.b, 1b_1mi.b, 1b_1mf.b, 1b_1mm.b,\
1340 
    1b_1mlx., 1b_m1_stop")
1341 
(exclusion_set "1b_0mi_bs"  "1b_0mii., 1b_0mib., 1b_mi0_stop")
1342 
(exclusion_set "1b_1mi_bs"  "1b_1mii., 1b_1mib., 1b_mi1_stop")
1343 
(exclusion_set "1b_0mm_bs"  "1b_0mmi., 1b_0mmf., 1b_0mmb.")
1344 
(exclusion_set "1b_1mm_bs"  "1b_1mmi., 1b_1mmb.")
1345 
(exclusion_set "1b_0mf_bs"  "1b_0mfi., 1b_0mfb.")
1346 
(exclusion_set "1b_1mf_bs"  "1b_1mfi., 1b_1mfb.")
1347 
(exclusion_set "1b_0b_bs"  "1b_0bb.b")
1348 
(exclusion_set "1b_1b_bs"  "1b_1bb.b")
1349 
(exclusion_set "1b_0bb_bs"  "1b_0bbb.")
1350 
(exclusion_set "1b_1bb_bs"  "1b_1bbb.")
1351 
(exclusion_set "1b_0mb_bs"  "1b_0mbb.")
1352 
(exclusion_set "1b_1mb_bs"  "1b_1mbb.")
1353 
 
1354 
(exclusion_set
1355 
   "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs,
1356 
    1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs"
1357 
   "1b_stop")
1358 
 
1359 
(final_presence_set
1360 
   "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0mb.b,\
1361 
    1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx."
1362 
   "1b_m_cont")
1363 
(final_presence_set "1b_0mii., 1b_0mib." "1b_mi_cont")
1364 
(final_presence_set "1b_0mmi., 1b_0mmf., 1b_0mmb." "1b_mm_cont")
1365 
(final_presence_set "1b_0mfi., 1b_0mfb." "1b_mf_cont")
1366 
(final_presence_set "1b_0bb.b" "1b_b_cont")
1367 
(final_presence_set "1b_0bbb." "1b_bb_cont")
1368 
(final_presence_set "1b_0mbb." "1b_mb_cont")
1369 
 
1370 
(exclusion_set
1371 
   "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\
1372 
    1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx"
1373 
   "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont,\
1374 
    1b_mb_cont, 1b_b_cont, 1b_bb_cont")
1375 
 
1376 
(exclusion_set "1b_empty"
1377 
               "1b_m_cont,1b_mi_cont,1b_mm_cont,1b_mf_cont,\
1378 
                1b_mb_cont,1b_b_cont,1b_bb_cont")
1379 
 
1380 
;; For m;mi bundle
1381 
(final_presence_set "1b_m0_stop" "1b_0m.mi")
1382 
(final_presence_set "1b_0mm.i" "1b_0mmi_cont")
1383 
(exclusion_set "1b_0mmi_cont"
1384 
   "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\
1385 
    1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1386 
(exclusion_set "1b_m0_stop" "1b_0mm.i")
1387 
(final_presence_set "1b_m1_stop" "1b_1m.mi")
1388 
(exclusion_set "1b_m1_stop" "1b_1mm.i")
1389 
(final_presence_set "1b_m_stop" "1b_m0_stop, 1b_m1_stop")
1390 
 
1391 
;; For mi;i bundle
1392 
(final_presence_set "1b_mi0_stop" "1b_0mi.i")
1393 
(final_presence_set "1b_0mii." "1b_0mii_cont")
1394 
(exclusion_set "1b_0mii_cont"
1395 
   "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\
1396 
    1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx")
1397 
(exclusion_set "1b_mi0_stop" "1b_0mii.")
1398 
(final_presence_set "1b_mi1_stop" "1b_1mi.i")
1399 
(exclusion_set "1b_mi1_stop" "1b_1mii.")
1400 
(final_presence_set "1b_mi_stop" "1b_mi0_stop, 1b_mi1_stop")
1401 
 
1402 
(final_absence_set
1403 
   "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\
1404 
    1b_0m.fi,1b_0mf.i,1b_0mfi.,1b_0m.mf,1b_0mm.f,1b_0mmf.,\
1405 
    1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb.,\
1406 
    1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\
1407 
    1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \
1408 
    1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\
1409 
    1b_1m.fi,1b_1mf.i,1b_1mfi.,\
1410 
    1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\
1411 
    1b_1m.ib,1b_1mi.b,1b_1mib.,1b_1m.mb,1b_1mm.b,1b_1mmb.,\
1412 
    1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx."
1413 
   "1b_m0_stop,1b_m1_stop,1b_mi0_stop,1b_mi1_stop")
1414 
 
1415 
(define_reservation "1b_A" "1b_M|1b_I")
1416 
 
1417 
(define_insn_reservation "1b_stop_bit" 0
1418 
  (and (and (eq_attr "cpu" "itanium")
1419 
            (eq_attr "itanium_class" "stop_bit"))
1420 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1421 
  "1b_stop|1b_m0_stop|1b_m1_stop|1b_mi0_stop|1b_mi1_stop")
1422 
(define_insn_reservation "1b_br"      0
1423 
  (and (and (eq_attr "cpu" "itanium")
1424 
            (eq_attr "itanium_class" "br"))
1425 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B")
1426 
(define_insn_reservation "1b_scall"   0
1427 
  (and (and (eq_attr "cpu" "itanium")
1428 
            (eq_attr "itanium_class" "scall"))
1429 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B")
1430 
(define_insn_reservation "1b_fcmp"    2
1431 
  (and (and (eq_attr "cpu" "itanium")
1432 
            (eq_attr "itanium_class" "fcmp"))
1433 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1434 
  "1b_F+1b_not_uf1")
1435 
(define_insn_reservation "1b_fcvtfx"  7
1436 
  (and (and (eq_attr "cpu" "itanium")
1437 
            (eq_attr "itanium_class" "fcvtfx"))
1438 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1439 
 
1440 
(define_insn_reservation "1b_fld"     9
1441 
  (and (and (and (eq_attr "cpu" "itanium")
1442 
                 (eq_attr "itanium_class" "fld"))
1443 
            (eq_attr "check_load" "no"))
1444 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1445 
(define_insn_reservation "1b_fldc"    0
1446 
  (and (and (and (eq_attr "cpu" "itanium")
1447 
                 (eq_attr "itanium_class" "fld"))
1448 
            (eq_attr "check_load" "yes"))
1449 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1450 
 
1451 
(define_insn_reservation "1b_fldp"    9
1452 
  (and (and (and (eq_attr "cpu" "itanium")
1453 
                 (eq_attr "itanium_class" "fldp"))
1454 
            (eq_attr "check_load" "no"))
1455 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1456 
(define_insn_reservation "1b_fldpc"   0
1457 
  (and (and (and (eq_attr "cpu" "itanium")
1458 
                 (eq_attr "itanium_class" "fldp"))
1459 
            (eq_attr "check_load" "yes"))
1460 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1461 
 
1462 
(define_insn_reservation "1b_fmac"    5
1463 
  (and (and (eq_attr "cpu" "itanium")
1464 
            (eq_attr "itanium_class" "fmac"))
1465 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1466 
(define_insn_reservation "1b_fmisc"   5
1467 
  (and (and (eq_attr "cpu" "itanium")
1468 
            (eq_attr "itanium_class" "fmisc"))
1469 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1470 
  "1b_F+1b_not_uf1")
1471 
(define_insn_reservation "1b_frar_i" 13
1472 
  (and (and (eq_attr "cpu" "itanium")
1473 
            (eq_attr "itanium_class" "frar_i"))
1474 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1475 
  "1b_I+1b_not_ui1")
1476 
(define_insn_reservation "1b_frar_m"  6
1477 
  (and (and (eq_attr "cpu" "itanium")
1478 
            (eq_attr "itanium_class" "frar_m"))
1479 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1480 
  "1b_M+1b_not_um1")
1481 
(define_insn_reservation "1b_frbr"    2
1482 
  (and (and (eq_attr "cpu" "itanium")
1483 
            (eq_attr "itanium_class" "frbr"))
1484 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1485 
  "1b_I+1b_not_ui1")
1486 
(define_insn_reservation "1b_frfr"    2
1487 
  (and (and (eq_attr "cpu" "itanium")
1488 
            (eq_attr "itanium_class" "frfr"))
1489 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1490 
  "1b_M+1b_not_um1")
1491 
(define_insn_reservation "1b_frpr"    2
1492 
  (and (and (eq_attr "cpu" "itanium")
1493 
            (eq_attr "itanium_class" "frpr"))
1494 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1495 
  "1b_I+1b_not_ui1")
1496 
(define_insn_reservation "1b_ialu"      1
1497 
    (and (and (eq_attr "cpu" "itanium")
1498 
              (eq_attr "itanium_class" "ialu"))
1499 
         (ne (symbol_ref
1500 
              "bundling_p && !ia64_produce_address_p (insn)")
1501 
             (const_int 0)))
1502 
    "1b_A")
1503 
(define_insn_reservation "1b_ialu_addr" 1
1504 
    (and (and (eq_attr "cpu" "itanium")
1505 
              (eq_attr "itanium_class" "ialu"))
1506 
         (eq (symbol_ref
1507 
              "bundling_p && ia64_produce_address_p (insn)")
1508 
             (const_int 1)))
1509 
    "1b_M")
1510 
(define_insn_reservation "1b_icmp"    1
1511 
  (and (and (eq_attr "cpu" "itanium")
1512 
            (eq_attr "itanium_class" "icmp"))
1513 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1514 
(define_insn_reservation "1b_ilog"    1
1515 
  (and (and (eq_attr "cpu" "itanium")
1516 
            (eq_attr "itanium_class" "ilog"))
1517 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1518 
(define_insn_reservation "1b_mmalua"  2
1519 
  (and (and (eq_attr "cpu" "itanium")
1520 
            (eq_attr "itanium_class" "mmalua"))
1521 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1522 
(define_insn_reservation "1b_ishf"    1
1523 
  (and (and (eq_attr "cpu" "itanium")
1524 
            (eq_attr "itanium_class" "ishf"))
1525 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1526 
  "1b_I+1b_not_ui1")
1527 
 
1528 
(define_insn_reservation "1b_ld"      2
1529 
  (and (and (and (eq_attr "cpu" "itanium")
1530 
                 (eq_attr "itanium_class" "ld"))
1531 
            (eq_attr "check_load" "no"))
1532 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1533 
(define_insn_reservation "1b_ldc"     0
1534 
  (and (and (and (eq_attr "cpu" "itanium")
1535 
                 (eq_attr "itanium_class" "ld"))
1536 
            (eq_attr "check_load" "yes"))
1537 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1538 
 
1539 
(define_insn_reservation "1b_long_i"  1
1540 
  (and (and (eq_attr "cpu" "itanium")
1541 
            (eq_attr "itanium_class" "long_i"))
1542 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")
1543 
(define_insn_reservation "1b_mmmul"   2
1544 
  (and (and (eq_attr "cpu" "itanium")
1545 
            (eq_attr "itanium_class" "mmmul"))
1546 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1547 
  "1b_I+1b_not_ui1")
1548 
(define_insn_reservation "1b_mmshf"   2
1549 
  (and (and (eq_attr "cpu" "itanium")
1550 
            (eq_attr "itanium_class" "mmshf"))
1551 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
1552 
(define_insn_reservation "1b_mmshfi"  2
1553 
  (and (and (eq_attr "cpu" "itanium")
1554 
            (eq_attr "itanium_class" "mmshfi"))
1555 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
1556 
(define_insn_reservation "1b_rse_m"   0
1557 
  (and (and (eq_attr "cpu" "itanium")
1558 
            (eq_attr "itanium_class" "rse_m"))
1559 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1560 
   "(1b_0m.ii|1b_0m.mi|1b_0m.fi|1b_0m.mf|1b_0b.bb|1b_0m.bb\
1561 
     |1b_0m.ib|1b_0m.mb|1b_0m.fb|1b_0m.lx)+1_1+1b_um0")
1562 
(define_insn_reservation "1b_sem"     0
1563 
  (and (and (eq_attr "cpu" "itanium")
1564 
            (eq_attr "itanium_class" "sem"))
1565 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1566 
  "1b_M+1b_not_um1")
1567 
(define_insn_reservation "1b_stf"     1
1568 
  (and (and (eq_attr "cpu" "itanium")
1569 
            (eq_attr "itanium_class" "stf"))
1570 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1571 
(define_insn_reservation "1b_st"      1
1572 
  (and (and (eq_attr "cpu" "itanium")
1573 
            (eq_attr "itanium_class" "st"))
1574 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1575 
(define_insn_reservation "1b_syst_m0" 0
1576 
  (and (and (eq_attr "cpu" "itanium")
1577 
            (eq_attr "itanium_class" "syst_m0"))
1578 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1579 
  "1b_M+1b_not_um1")
1580 
(define_insn_reservation "1b_syst_m"  0
1581 
  (and (and (eq_attr "cpu" "itanium")
1582 
            (eq_attr "itanium_class" "syst_m"))
1583 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1584 
(define_insn_reservation "1b_tbit"    1
1585 
  (and (and (eq_attr "cpu" "itanium")
1586 
            (eq_attr "itanium_class" "tbit"))
1587 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1588 
  "1b_I+1b_not_ui1")
1589 
(define_insn_reservation "1b_toar_i"  0
1590 
  (and (and (eq_attr "cpu" "itanium")
1591 
            (eq_attr "itanium_class" "toar_i"))
1592 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1593 
  "1b_I+1b_not_ui1")
1594 
(define_insn_reservation "1b_toar_m"  5
1595 
  (and (and (eq_attr "cpu" "itanium")
1596 
            (eq_attr "itanium_class" "toar_m"))
1597 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1598 
  "1b_M+1b_not_um1")
1599 
(define_insn_reservation "1b_tobr"    1
1600 
  (and (and (eq_attr "cpu" "itanium")
1601 
            (eq_attr "itanium_class" "tobr"))
1602 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1603 
  "1b_I+1b_not_ui1")
1604 
(define_insn_reservation "1b_tofr"    9
1605 
  (and (and (eq_attr "cpu" "itanium")
1606 
            (eq_attr "itanium_class" "tofr"))
1607 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1608 
(define_insn_reservation "1b_topr"    1
1609 
  (and (and (eq_attr "cpu" "itanium")
1610 
            (eq_attr "itanium_class" "topr"))
1611 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1612 
  "1b_I+1b_not_ui1")
1613 
(define_insn_reservation "1b_xmpy"    7
1614 
  (and (and (eq_attr "cpu" "itanium")
1615 
            (eq_attr "itanium_class" "xmpy"))
1616 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1617 
(define_insn_reservation "1b_xtd"     1
1618 
  (and (and (eq_attr "cpu" "itanium")
1619 
            (eq_attr "itanium_class" "xtd"))
1620 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
1621 
 
1622 
(define_insn_reservation "1b_chk_s_i" 0
1623 
  (and (and (eq_attr "cpu" "itanium")
1624 
            (eq_attr "itanium_class" "chk_s_i"))
1625 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1626 
(define_insn_reservation "1b_chk_s_f" 0
1627 
  (and (and (eq_attr "cpu" "itanium")
1628 
            (eq_attr "itanium_class" "chk_s_f"))
1629 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1630 
(define_insn_reservation "1b_chk_a"   0
1631 
  (and (and (eq_attr "cpu" "itanium")
1632 
            (eq_attr "itanium_class" "chk_a"))
1633 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1634 
 
1635 
(define_insn_reservation "1b_lfetch"  0
1636 
  (and (and (eq_attr "cpu" "itanium")
1637 
            (eq_attr "itanium_class" "lfetch"))
1638 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1639 
(define_insn_reservation "1b_nop_m"   0
1640 
  (and (and (eq_attr "cpu" "itanium")
1641 
            (eq_attr "itanium_class" "nop_m"))
1642 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1643 
(define_insn_reservation "1b_nop_b"   0
1644 
  (and (and (eq_attr "cpu" "itanium")
1645 
            (eq_attr "itanium_class" "nop_b"))
1646 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_NB")
1647 
(define_insn_reservation "1b_nop_i"   0
1648 
  (and (and (eq_attr "cpu" "itanium")
1649 
            (eq_attr "itanium_class" "nop_i"))
1650 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
1651 
(define_insn_reservation "1b_nop_f"   0
1652 
  (and (and (eq_attr "cpu" "itanium")
1653 
            (eq_attr "itanium_class" "nop_f"))
1654 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1655 
(define_insn_reservation "1b_nop_x"   0
1656 
  (and (and (eq_attr "cpu" "itanium")
1657 
            (eq_attr "itanium_class" "nop_x"))
1658 
       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")
1659 
(define_insn_reservation "1b_unknown" 1
1660 
  (and (and (eq_attr "cpu" "itanium")
1661 
            (eq_attr "itanium_class" "unknown"))
1662 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1663 
  "1b_empty")
1664 
(define_insn_reservation "1b_nop" 1
1665 
  (and (and (eq_attr "cpu" "itanium")
1666 
            (eq_attr "itanium_class" "nop"))
1667 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1668 
  "1b_M|1b_NB|1b_I|1b_F")
1669 
(define_insn_reservation "1b_ignore" 0
1670 
  (and (and (eq_attr "cpu" "itanium")
1671 
            (eq_attr "itanium_class" "ignore"))
1672 
       (ne (symbol_ref "bundling_p") (const_int 0)))
1673 
  "nothing")
1674 
 
1675 
(define_insn_reservation "1b_pre_cycle" 0
1676 
   (and (and (eq_attr "cpu" "itanium")
1677 
             (eq_attr "itanium_class" "pre_cycle"))
1678 
        (ne (symbol_ref "bundling_p") (const_int 0)))
1679 
                         "(1b_0m_bs, 1b_m_cont)     \
1680 
                          | (1b_0mi_bs, 1b_mi_cont) \
1681 
                          | (1b_0mm_bs, 1b_mm_cont) \
1682 
                          | (1b_0mf_bs, 1b_mf_cont) \
1683 
                          | (1b_0b_bs, 1b_b_cont)   \
1684 
                          | (1b_0bb_bs, 1b_bb_cont) \
1685 
                          | (1b_0mb_bs, 1b_mb_cont) \
1686 
                          | (1b_1m_bs, 1b_m_cont)   \
1687 
                          | (1b_1mi_bs, 1b_mi_cont) \
1688 
                          | (1b_1mm_bs, 1b_mm_cont) \
1689 
                          | (1b_1mf_bs, 1b_mf_cont) \
1690 
                          | (1b_1b_bs, 1b_b_cont)   \
1691 
                          | (1b_1bb_bs, 1b_bb_cont) \
1692 
                          | (1b_1mb_bs, 1b_mb_cont) \
1693 
                          | (1b_m_stop, 1b_0mmi_cont)   \
1694 
                          | (1b_mi_stop, 1b_0mii_cont)")
1695 
 

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