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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [iq2000/] [iq2000.h] - Blame information for rev 816

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1 38 julius
/* Definitions of target machine for GNU compiler.
2
   Vitesse IQ2000 processors
3
   Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4
 
5
   This file is part of GCC.
6
 
7
   GCC is free software; you can redistribute it and/or modify it
8
   under the terms of the GNU General Public License as published
9
   by the Free Software Foundation; either version 3, or (at your
10
   option) any later version.
11
 
12
   GCC is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GCC; see the file COPYING3.  If not see
19
   <http://www.gnu.org/licenses/>.  */
20
 
21
/* Driver configuration.  */
22
 
23
#undef  SWITCH_TAKES_ARG
24
#define SWITCH_TAKES_ARG(CHAR)                                          \
25
  (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
26
 
27
/* The svr4.h LIB_SPEC with -leval and --*group tacked on */
28
#undef  LIB_SPEC
29
#define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
30
 
31
#undef STARTFILE_SPEC
32
#undef ENDFILE_SPEC
33
 
34
 
35
/* Run-time target specifications.  */
36
 
37
#define TARGET_CPU_CPP_BUILTINS()               \
38
  do                                            \
39
    {                                           \
40
      builtin_define ("__iq2000__");            \
41
      builtin_assert ("cpu=iq2000");            \
42
      builtin_assert ("machine=iq2000");        \
43
    }                                           \
44
  while (0)
45
 
46
/* Macros used in the machine description to test the flags.  */
47
 
48
#define TARGET_STATS            0
49
 
50
#define TARGET_DEBUG_MODE       0
51
#define TARGET_DEBUG_A_MODE     0
52
#define TARGET_DEBUG_B_MODE     0
53
#define TARGET_DEBUG_C_MODE     0
54
#define TARGET_DEBUG_D_MODE     0
55
 
56
#ifndef IQ2000_ISA_DEFAULT
57
#define IQ2000_ISA_DEFAULT 1
58
#endif
59
 
60
#define IQ2000_VERSION "[1.0]"
61
 
62
#ifndef MACHINE_TYPE
63
#define MACHINE_TYPE "IQ2000"
64
#endif
65
 
66
#ifndef TARGET_VERSION_INTERNAL
67
#define TARGET_VERSION_INTERNAL(STREAM)                                 \
68
  fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
69
#endif
70
 
71
#ifndef TARGET_VERSION
72
#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
73
#endif
74
 
75
#define OVERRIDE_OPTIONS override_options ()
76
 
77
#define CAN_DEBUG_WITHOUT_FP
78
 
79
/* Storage Layout.  */
80
 
81
#define BITS_BIG_ENDIAN                 0
82
#define BYTES_BIG_ENDIAN                1 
83
#define WORDS_BIG_ENDIAN                1
84
#define LIBGCC2_WORDS_BIG_ENDIAN        1
85
#define BITS_PER_WORD                   32
86
#define MAX_BITS_PER_WORD               64
87
#define UNITS_PER_WORD                  4
88
#define MIN_UNITS_PER_WORD              4
89
#define POINTER_SIZE                    32
90
 
91
/* Define this macro if it is advisable to hold scalars in registers
92
   in a wider mode than that declared by the program.  In such cases,
93
   the value is constrained to be within the bounds of the declared
94
   type, but kept valid in the wider mode.  The signedness of the
95
   extension may differ from that of the type.
96
 
97
   We promote any value smaller than SImode up to SImode.  */
98
 
99
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
100
  if (GET_MODE_CLASS (MODE) == MODE_INT         \
101
      && GET_MODE_SIZE (MODE) < 4)              \
102
    (MODE) = SImode;
103
 
104
#define PARM_BOUNDARY 32
105
 
106
#define STACK_BOUNDARY 64
107
 
108
#define FUNCTION_BOUNDARY 32
109
 
110
#define BIGGEST_ALIGNMENT 64
111
 
112
#undef  DATA_ALIGNMENT
113
#define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
114
  ((((ALIGN) < BITS_PER_WORD)                                           \
115
    && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
116
        || TREE_CODE (TYPE) == UNION_TYPE                               \
117
        || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
118
 
119
#define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
120
  ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
121
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
122
 
123
#define EMPTY_FIELD_BOUNDARY 32
124
 
125
#define STRUCTURE_SIZE_BOUNDARY 8
126
 
127
#define STRICT_ALIGNMENT 1
128
 
129
#define PCC_BITFIELD_TYPE_MATTERS 1
130
 
131
#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
132
 
133
 
134
/* Layout of Source Language Data Types.  */
135
 
136
#define INT_TYPE_SIZE           32
137
#define SHORT_TYPE_SIZE         16
138
#define LONG_TYPE_SIZE          32
139
#define LONG_LONG_TYPE_SIZE     64
140
#define CHAR_TYPE_SIZE          BITS_PER_UNIT
141
#define FLOAT_TYPE_SIZE         32
142
#define DOUBLE_TYPE_SIZE        64
143
#define LONG_DOUBLE_TYPE_SIZE   64
144
#define DEFAULT_SIGNED_CHAR     1
145
 
146
 
147
/* Register Basics.  */
148
 
149
/* On the IQ2000, we have 32 integer registers.  */
150
#define FIRST_PSEUDO_REGISTER 33
151
 
152
#define FIXED_REGISTERS                                                 \
153
{                                                                       \
154
  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                     \
155
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                        \
156
}
157
 
158
#define CALL_USED_REGISTERS                                             \
159
{                                                                       \
160
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
161
  0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                      \
162
}
163
 
164
 
165
/* Order of allocation of registers.  */
166
 
167
#define REG_ALLOC_ORDER                                                 \
168
{  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,        \
169
  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
170
}
171
 
172
 
173
/* How Values Fit in Registers.  */
174
 
175
#define HARD_REGNO_NREGS(REGNO, MODE)   \
176
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
177
 
178
#define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
179
 ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
180
  ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4      \
181
  : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
182
 
183
#define MODES_TIEABLE_P(MODE1, MODE2)                           \
184
  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
185
    GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
186
   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
187
       GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
188
 
189
#define AVOID_CCMODE_COPIES
190
 
191
 
192
/* Register Classes.  */
193
 
194
enum reg_class
195
{
196
  NO_REGS,                      /* No registers in set.  */
197
  GR_REGS,                      /* Integer registers.  */
198
  ALL_REGS,                     /* All registers.  */
199
  LIM_REG_CLASSES               /* Max value + 1.  */
200
};
201
 
202
#define GENERAL_REGS GR_REGS
203
 
204
#define N_REG_CLASSES (int) LIM_REG_CLASSES
205
 
206
#define REG_CLASS_NAMES                                         \
207
{                                                               \
208
  "NO_REGS",                                                    \
209
  "GR_REGS",                                                    \
210
  "ALL_REGS"                                                    \
211
}
212
 
213
#define REG_CLASS_CONTENTS                                      \
214
{                                                               \
215
  { 0x00000000, 0x00000000 },   /* No registers,  */            \
216
  { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
217
  { 0xffffffff, 0x00000001 }    /* All registers.  */           \
218
}
219
 
220
#define REGNO_REG_CLASS(REGNO) \
221
((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
222
 
223
#define BASE_REG_CLASS  (GR_REGS)
224
 
225
#define INDEX_REG_CLASS NO_REGS
226
 
227
#define REG_CLASS_FROM_LETTER(C) \
228
  ((C) == 'd' ? GR_REGS :        \
229
   (C) == 'b' ? ALL_REGS :       \
230
   (C) == 'y' ? GR_REGS :        \
231
   NO_REGS)
232
 
233
#define REGNO_OK_FOR_INDEX_P(regno)     0
234
 
235
#define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
236
  ((CLASS) != ALL_REGS                                          \
237
   ? (CLASS)                                                    \
238
   : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
239
       || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
240
      ? (GR_REGS)                                               \
241
      : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
242
          || GET_MODE (X) == VOIDmode)                          \
243
         ? (GR_REGS)                                            \
244
         : (CLASS))))
245
 
246
#define SMALL_REGISTER_CLASSES 0
247
 
248
#define CLASS_MAX_NREGS(CLASS, MODE)    \
249
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
250
 
251
/* For IQ2000:
252
 
253
   `I'  is used for the range of constants an arithmetic insn can
254
        actually contain (16 bits signed integers).
255
 
256
   `J'  is used for the range which is just zero (i.e., $r0).
257
 
258
   `K'  is used for the range of constants a logical insn can actually
259
        contain (16 bit zero-extended integers).
260
 
261
   `L'  is used for the range of constants that be loaded with lui
262
        (i.e., the bottom 16 bits are zero).
263
 
264
   `M'  is used for the range of constants that take two words to load
265
        (i.e., not matched by `I', `K', and `L').
266
 
267
   `N'  is used for constants 0xffffnnnn or 0xnnnnffff
268
 
269
   `O'  is a 5 bit zero-extended integer.  */
270
 
271
#define CONST_OK_FOR_LETTER_P(VALUE, C)                                 \
272
  ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
273
   : (C) == 'J' ? ((VALUE) == 0)                                 \
274
   : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)          \
275
   : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0                           \
276
                   && (((VALUE) & ~2147483647) == 0                      \
277
                       || ((VALUE) & ~2147483647) == ~2147483647))      \
278
   : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)                        \
279
                   && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)          \
280
                   && (((VALUE) & 0x0000ffff) != 0                       \
281
                       || (((VALUE) & ~2147483647) != 0                  \
282
                           && ((VALUE) & ~2147483647) != ~2147483647))) \
283
   : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff)                       \
284
                   || (((VALUE) & 0xffff0000) == 0xffff0000))           \
285
   : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40)    \
286
   : 0)
287
 
288
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)                          \
289
  ((C) == 'G'                                                           \
290
   && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
291
 
292
/* `R' is for memory references which take 1 word for the instruction.  */
293
 
294
#define EXTRA_CONSTRAINT(OP,CODE)                                       \
295
  (((CODE) == 'R')        ? simple_memory_operand (OP, GET_MODE (OP))   \
296
   : FALSE)
297
 
298
 
299
/* Basic Stack Layout.  */
300
 
301
#define STACK_GROWS_DOWNWARD
302
 
303
#define FRAME_GROWS_DOWNWARD 0
304
 
305
#define STARTING_FRAME_OFFSET                                           \
306
  (current_function_outgoing_args_size)
307
 
308
/* Use the default value zero.  */
309
/* #define STACK_POINTER_OFFSET 0 */
310
 
311
#define FIRST_PARM_OFFSET(FNDECL) 0
312
 
313
/* The return address for the current frame is in r31 if this is a leaf
314
   function.  Otherwise, it is on the stack.  It is at a variable offset
315
   from sp/fp/ap, so we define a fake hard register rap which is a
316
   pointer to the return address on the stack.  This always gets eliminated
317
   during reload to be either the frame pointer or the stack pointer plus
318
   an offset.  */
319
 
320
#define RETURN_ADDR_RTX(count, frame)                                   \
321
  (((count) == 0)                                                       \
322
   ? (leaf_function_p ()                                                \
323
      ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
324
      : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
325
                                         RETURN_ADDRESS_POINTER_REGNUM))) \
326
    : (rtx) 0)
327
 
328
/* Before the prologue, RA lives in r31.  */
329
#define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
330
 
331
 
332
/* Register That Address the Stack Frame.  */
333
 
334
#define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
335
#define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
336
#define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
337
#define ARG_POINTER_REGNUM              GP_REG_FIRST
338
#define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
339
#define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
340
 
341
 
342
/* Eliminating the Frame Pointer and the Arg Pointer.  */
343
 
344
#define FRAME_POINTER_REQUIRED 0
345
 
346
#define ELIMINABLE_REGS                                                 \
347
{{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
348
 { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
349
 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
350
 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
351
 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
352
 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
353
 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
354
 
355
 
356
/* We can always eliminate to the frame pointer.  We can eliminate to the
357
   stack pointer unless a frame pointer is needed.  */
358
 
359
#define CAN_ELIMINATE(FROM, TO)                                         \
360
  (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p ()    \
361
   || (TO == GP_REG_FIRST + 31 && leaf_function_p)))                    \
362
  || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM                           \
363
   && ((TO) == HARD_FRAME_POINTER_REGNUM                                \
364
   || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed))))
365
 
366
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
367
        (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
368
 
369
/* Passing Function Arguments on the Stack.  */
370
 
371
/* #define PUSH_ROUNDING(BYTES) 0 */
372
 
373
#define ACCUMULATE_OUTGOING_ARGS 1
374
 
375
#define REG_PARM_STACK_SPACE(FNDECL) 0
376
 
377
#define OUTGOING_REG_PARM_STACK_SPACE
378
 
379
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
380
 
381
 
382
/* Function Arguments in Registers.  */
383
 
384
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
385
  function_arg (& CUM, MODE, TYPE, NAMED)
386
 
387
#define MAX_ARGS_IN_REGISTERS 8
388
 
389
typedef struct iq2000_args
390
{
391
  int gp_reg_found;             /* Whether a gp register was found yet.  */
392
  unsigned int arg_number;      /* Argument number.  */
393
  unsigned int arg_words;       /* # total words the arguments take.  */
394
  unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
395
  int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
396
  int fp_code;                  /* Mode of FP arguments.  */
397
  unsigned int num_adjusts;     /* Number of adjustments made.  */
398
                                /* Adjustments made to args pass in regs.  */
399
  struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
400
} CUMULATIVE_ARGS;
401
 
402
/* Initialize a variable CUM of type CUMULATIVE_ARGS
403
   for a call to a function whose data type is FNTYPE.
404
   For a library call, FNTYPE is 0.  */
405
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
406
  init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
407
 
408
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)                    \
409
  function_arg_advance (& CUM, MODE, TYPE, NAMED)
410
 
411
#define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
412
  (! BYTES_BIG_ENDIAN                                                   \
413
   ? upward                                                             \
414
   : (((MODE) == BLKmode                                                \
415
       ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
416
          && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
417
       : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
418
          && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
419
      ? downward : upward))
420
 
421
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)                               \
422
  (((TYPE) != 0)                                                 \
423
        ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)                          \
424
                ? PARM_BOUNDARY                                         \
425
                : TYPE_ALIGN(TYPE))                                     \
426
        : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)                  \
427
                ? PARM_BOUNDARY                                         \
428
                : GET_MODE_ALIGNMENT(MODE)))
429
 
430
#define FUNCTION_ARG_REGNO_P(N)                                         \
431
  (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
432
 
433
 
434
/* How Scalar Function Values are Returned.  */
435
 
436
#define FUNCTION_VALUE(VALTYPE, FUNC)   iq2000_function_value (VALTYPE, FUNC)
437
 
438
#define LIBCALL_VALUE(MODE)                             \
439
  gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT      \
440
                 || GET_MODE_SIZE (MODE) >= 4)          \
441
                ? (MODE)                                \
442
                : SImode),                              \
443
               GP_RETURN)
444
 
445
/* On the IQ2000, R2 and R3 are the only register thus used.  */
446
 
447
#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
448
 
449
 
450
/* How Large Values are Returned.  */
451
 
452
#define DEFAULT_PCC_STRUCT_RETURN 0
453
 
454
/* Function Entry and Exit.  */
455
 
456
#define EXIT_IGNORE_STACK 1
457
 
458
 
459
/* Generating Code for Profiling.  */
460
 
461
#define FUNCTION_PROFILER(FILE, LABELNO)                                \
462
{                                                                       \
463
  fprintf (FILE, "\t.set\tnoreorder\n");                                \
464
  fprintf (FILE, "\t.set\tnoat\n");                                     \
465
  fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
466
           reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
467
  fprintf (FILE, "\tjal\t_mcount\n");                                   \
468
  fprintf (FILE,                                                        \
469
           "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
470
           "subu",                                                      \
471
           reg_names[STACK_POINTER_REGNUM],                             \
472
           reg_names[STACK_POINTER_REGNUM],                             \
473
           Pmode == DImode ? 16 : 8);                                   \
474
  fprintf (FILE, "\t.set\treorder\n");                                  \
475
  fprintf (FILE, "\t.set\tat\n");                                       \
476
}
477
 
478
 
479
/* Implementing the Varargs Macros.  */
480
 
481
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
482
  iq2000_va_start (valist, nextarg)
483
 
484
 
485
/* Trampolines for Nested Functions.  */
486
 
487
/* A C statement to output, on the stream FILE, assembler code for a
488
   block of data that contains the constant parts of a trampoline.
489
   This code should not include a label--the label is taken care of
490
   automatically.  */
491
 
492
#define TRAMPOLINE_TEMPLATE(STREAM)                                      \
493
{                                                                        \
494
  fprintf (STREAM, "\t.word\t0x03e00821\t\t# move   $1,$31\n");         \
495
  fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");         \
496
  fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n");                   \
497
  if (Pmode == DImode)                                                  \
498
    {                                                                   \
499
      fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld     $3,20($31)\n"); \
500
      fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld     $2,28($31)\n"); \
501
    }                                                                   \
502
  else                                                                  \
503
    {                                                                   \
504
      fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw     $3,20($31)\n"); \
505
      fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw     $2,24($31)\n"); \
506
    }                                                                   \
507
  fprintf (STREAM, "\t.word\t0x0060c821\t\t# move   $25,$3 (abicalls)\n"); \
508
  fprintf (STREAM, "\t.word\t0x00600008\t\t# jr     $3\n");             \
509
  fprintf (STREAM, "\t.word\t0x0020f821\t\t# move   $31,$1\n");         \
510
  fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
511
  fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
512
}
513
 
514
#define TRAMPOLINE_SIZE (40)
515
 
516
#define TRAMPOLINE_ALIGNMENT 32
517
 
518
#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)                            \
519
{                                                                           \
520
  rtx addr = ADDR;                                                          \
521
    emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
522
    emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
523
}
524
 
525
 
526
/* Addressing Modes.  */
527
 
528
#define CONSTANT_ADDRESS_P(X)                                           \
529
  (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
530
    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
531
    || (GET_CODE (X) == CONST)))
532
 
533
#define MAX_REGS_PER_ADDRESS 1
534
 
535
#ifdef REG_OK_STRICT
536
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)         \
537
  {                                                     \
538
    if (iq2000_legitimate_address_p (MODE, X, 1))       \
539
      goto ADDR;                                        \
540
  }
541
#else
542
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)         \
543
  {                                                     \
544
    if (iq2000_legitimate_address_p (MODE, X, 0))        \
545
      goto ADDR;                                        \
546
  }
547
#endif
548
 
549
#define REG_OK_FOR_INDEX_P(X) 0
550
 
551
 
552
/* For the IQ2000, transform:
553
 
554
        memory(X + <large int>)
555
   into:
556
        Y = <large int> & ~0x7fff;
557
        Z = X + Y
558
        memory (Z + (<large int> & 0x7fff));
559
*/
560
 
561
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)                             \
562
{                                                                       \
563
  rtx xinsn = (X);                                                      \
564
                                                                        \
565
  if (TARGET_DEBUG_B_MODE)                                              \
566
    {                                                                   \
567
      GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");                  \
568
      GO_DEBUG_RTX (xinsn);                                             \
569
    }                                                                   \
570
                                                                        \
571
  if (iq2000_check_split (X, MODE))             \
572
    {                                                                   \
573
      X = gen_rtx_LO_SUM (Pmode,                                        \
574
                          copy_to_mode_reg (Pmode,                      \
575
                                            gen_rtx_HIGH (Pmode, X)),   \
576
                          X);                                           \
577
      goto WIN;                                                         \
578
    }                                                                   \
579
                                                                        \
580
  if (GET_CODE (xinsn) == PLUS)                                         \
581
    {                                                                   \
582
      rtx xplus0 = XEXP (xinsn, 0);                                      \
583
      rtx xplus1 = XEXP (xinsn, 1);                                     \
584
      enum rtx_code code0 = GET_CODE (xplus0);                          \
585
      enum rtx_code code1 = GET_CODE (xplus1);                          \
586
                                                                        \
587
      if (code0 != REG && code1 == REG)                                 \
588
        {                                                               \
589
          xplus0 = XEXP (xinsn, 1);                                     \
590
          xplus1 = XEXP (xinsn, 0);                                      \
591
          code0 = GET_CODE (xplus0);                                    \
592
          code1 = GET_CODE (xplus1);                                    \
593
        }                                                               \
594
                                                                        \
595
      if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)         \
596
          && code1 == CONST_INT && !SMALL_INT (xplus1))                 \
597
        {                                                               \
598
          rtx int_reg = gen_reg_rtx (Pmode);                            \
599
          rtx ptr_reg = gen_reg_rtx (Pmode);                            \
600
                                                                        \
601
          emit_move_insn (int_reg,                                      \
602
                          GEN_INT (INTVAL (xplus1) & ~ 0x7fff));        \
603
                                                                        \
604
          emit_insn (gen_rtx_SET (VOIDmode,                             \
605
                                  ptr_reg,                              \
606
                                  gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
607
                                                                        \
608
          X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff);        \
609
          goto WIN;                                                     \
610
        }                                                               \
611
    }                                                                   \
612
                                                                        \
613
  if (TARGET_DEBUG_B_MODE)                                              \
614
    GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");                  \
615
}
616
 
617
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
618
 
619
#define LEGITIMATE_CONSTANT_P(X) (1)
620
 
621
 
622
/* Describing Relative Costs of Operations.  */
623
 
624
#define REGISTER_MOVE_COST(MODE, FROM, TO)      2
625
 
626
#define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
627
  (TO_P ? 2 : 16)
628
 
629
#define BRANCH_COST 2
630
 
631
#define SLOW_BYTE_ACCESS 1
632
 
633
#define NO_FUNCTION_CSE 1
634
 
635
#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
636
  if (REG_NOTE_KIND (LINK) != 0)                                 \
637
    (COST) = 0; /* Anti or output dependence.  */
638
 
639
 
640
/* Dividing the output into sections.  */
641
 
642
#define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
643
 
644
#define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
645
 
646
 
647
/* The Overall Framework of an Assembler File.  */
648
 
649
#define ASM_COMMENT_START " #"
650
 
651
#define ASM_APP_ON "#APP\n"
652
 
653
#define ASM_APP_OFF "#NO_APP\n"
654
 
655
 
656
/* Output and Generation of Labels.  */
657
 
658
#undef ASM_GENERATE_INTERNAL_LABEL
659
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
660
  sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
661
 
662
#define GLOBAL_ASM_OP "\t.globl\t"
663
 
664
 
665
/* Output of Assembler Instructions.  */
666
 
667
#define REGISTER_NAMES                                                  \
668
{                                                                       \
669
 "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
670
 "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
671
 "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
672
 "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
673
};
674
 
675
#define ADDITIONAL_REGISTER_NAMES                                       \
676
{                                                                       \
677
  { "%0",        0 + GP_REG_FIRST },                                     \
678
  { "%1",        1 + GP_REG_FIRST },                                    \
679
  { "%2",        2 + GP_REG_FIRST },                                    \
680
  { "%3",        3 + GP_REG_FIRST },                                    \
681
  { "%4",        4 + GP_REG_FIRST },                                    \
682
  { "%5",        5 + GP_REG_FIRST },                                    \
683
  { "%6",        6 + GP_REG_FIRST },                                    \
684
  { "%7",        7 + GP_REG_FIRST },                                    \
685
  { "%8",        8 + GP_REG_FIRST },                                    \
686
  { "%9",        9 + GP_REG_FIRST },                                    \
687
  { "%10",      10 + GP_REG_FIRST },                                    \
688
  { "%11",      11 + GP_REG_FIRST },                                    \
689
  { "%12",      12 + GP_REG_FIRST },                                    \
690
  { "%13",      13 + GP_REG_FIRST },                                    \
691
  { "%14",      14 + GP_REG_FIRST },                                    \
692
  { "%15",      15 + GP_REG_FIRST },                                    \
693
  { "%16",      16 + GP_REG_FIRST },                                    \
694
  { "%17",      17 + GP_REG_FIRST },                                    \
695
  { "%18",      18 + GP_REG_FIRST },                                    \
696
  { "%19",      19 + GP_REG_FIRST },                                    \
697
  { "%20",      20 + GP_REG_FIRST },                                    \
698
  { "%21",      21 + GP_REG_FIRST },                                    \
699
  { "%22",      22 + GP_REG_FIRST },                                    \
700
  { "%23",      23 + GP_REG_FIRST },                                    \
701
  { "%24",      24 + GP_REG_FIRST },                                    \
702
  { "%25",      25 + GP_REG_FIRST },                                    \
703
  { "%26",      26 + GP_REG_FIRST },                                    \
704
  { "%27",      27 + GP_REG_FIRST },                                    \
705
  { "%28",      28 + GP_REG_FIRST },                                    \
706
  { "%29",      29 + GP_REG_FIRST },                                    \
707
  { "%30",      27 + GP_REG_FIRST },                                    \
708
  { "%31",      31 + GP_REG_FIRST },                                    \
709
  { "%rap",     32 + GP_REG_FIRST },                                    \
710
}
711
 
712
/* Check if the current insn needs a nop in front of it
713
   because of load delays, and also update the delay slot statistics.  */
714
 
715
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
716
  final_prescan_insn (INSN, OPVEC, NOPERANDS)
717
 
718
/* See iq2000.c for the IQ2000 specific codes.  */
719
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
720
 
721
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) iq2000_print_operand_punct[CODE]
722
 
723
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
724
 
725
#define DBR_OUTPUT_SEQEND(STREAM)                                       \
726
do                                                                      \
727
  {                                                                     \
728
    fputs ("\n", STREAM);                                               \
729
  }                                                                     \
730
while (0)
731
 
732
#define LOCAL_LABEL_PREFIX      "$"
733
 
734
#define USER_LABEL_PREFIX       ""
735
 
736
 
737
/* Output of dispatch tables.  */
738
 
739
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
740
  do                                                                    \
741
    {                                                                   \
742
      fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
743
               Pmode == DImode ? ".dword" : ".word",                    \
744
               LOCAL_LABEL_PREFIX, VALUE);                              \
745
    }                                                                   \
746
  while (0)
747
 
748
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
749
  fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
750
           Pmode == DImode ? ".dword" : ".word",                        \
751
           LOCAL_LABEL_PREFIX,                                          \
752
           VALUE)
753
 
754
 
755
/* Assembler Commands for Alignment.  */
756
 
757
#undef ASM_OUTPUT_SKIP
758
#define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
759
  fprintf (STREAM, "\t.space\t%u\n", (SIZE))
760
 
761
#define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
762
  if ((LOG) != 0)                                                \
763
    fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
764
 
765
 
766
/* Macros Affecting all Debug Formats.  */
767
 
768
#define DEBUGGER_AUTO_OFFSET(X)  \
769
  iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
770
 
771
#define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
772
  iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
773
 
774
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
775
 
776
#define DWARF2_DEBUGGING_INFO 1
777
 
778
 
779
/* Miscellaneous Parameters.  */
780
 
781
#define CASE_VECTOR_MODE SImode
782
 
783
#define WORD_REGISTER_OPERATIONS
784
 
785
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
786
 
787
#define MOVE_MAX 4
788
 
789
#define MAX_MOVE_MAX 8
790
 
791
#define SHIFT_COUNT_TRUNCATED 1
792
 
793
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
794
 
795
#define STORE_FLAG_VALUE 1
796
 
797
#define Pmode SImode
798
 
799
#define FUNCTION_MODE SImode
800
 
801
/* Standard GCC variables that we reference.  */
802
 
803
extern char     call_used_regs[];
804
 
805
/* IQ2000 external variables defined in iq2000.c.  */
806
 
807
/* Comparison type.  */
808
enum cmp_type
809
{
810
  CMP_SI,                               /* Compare four byte integers.  */
811
  CMP_DI,                               /* Compare eight byte integers.  */
812
  CMP_SF,                               /* Compare single precision floats.  */
813
  CMP_DF,                               /* Compare double precision floats.  */
814
  CMP_MAX                               /* Max comparison type.  */
815
};
816
 
817
/* Types of delay slot.  */
818
enum delay_type
819
{
820
  DELAY_NONE,                           /* No delay slot.  */
821
  DELAY_LOAD,                           /* Load from memory delay.  */
822
  DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
823
};
824
 
825
/* Which processor to schedule for.  */
826
 
827
enum processor_type
828
{
829
  PROCESSOR_DEFAULT,
830
  PROCESSOR_IQ2000,
831
  PROCESSOR_IQ10
832
};
833
 
834
/* Recast the cpu class to be the cpu attribute.  */
835
#define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
836
 
837
#define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
838
#define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
839
 
840
 
841
#define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
842
 
843
/* Macros to decide whether certain features are available or not,
844
   depending on the instruction set architecture level.  */
845
 
846
#define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
847
 
848
/* ISA has branch likely instructions.  */
849
#define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
850
 
851
 
852
#undef ASM_SPEC
853
 
854
 
855
/* The mapping from gcc register number to DWARF 2 CFA column number.  */
856
#define DWARF_FRAME_REGNUM(REG)        (REG)
857
 
858
/* The DWARF 2 CFA column which tracks the return address.  */
859
#define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
860
 
861
/* Describe how we implement __builtin_eh_return.  */
862
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
863
 
864
/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
865
   location used to store the amount to adjust the stack.  This is
866
   usually a register that is available from end of the function's body
867
   to the end of the epilogue. Thus, this cannot be a register used as a
868
   temporary by the epilogue.
869
 
870
   This must be an integer register.  */
871
#define EH_RETURN_STACKADJ_REGNO        3
872
#define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
873
 
874
/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
875
   location used to store the address the processor should jump to
876
   catch exception.  This is usually a registers that is available from
877
   end of the function's body to the end of the epilogue. Thus, this
878
   cannot be a register used as a temporary by the epilogue.
879
 
880
   This must be an address register.  */
881
#define EH_RETURN_HANDLER_REGNO         26
882
#define EH_RETURN_HANDLER_RTX           \
883
        gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
884
 
885
/* Offsets recorded in opcodes are a multiple of this alignment factor.  */
886
#define DWARF_CIE_DATA_ALIGNMENT 4
887
 
888
/* For IQ2000, width of a floating point register.  */
889
#define UNITS_PER_FPREG 4
890
 
891
/* Force right-alignment for small varargs in 32 bit little_endian mode */
892
 
893
#define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
894
 
895
/* Internal macros to classify a register number as to whether it's a
896
   general purpose register, a floating point register, a
897
   multiply/divide register, or a status register.  */
898
 
899
#define GP_REG_FIRST 0
900
#define GP_REG_LAST  31
901
#define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
902
 
903
#define RAP_REG_NUM   32
904
#define AT_REGNUM       (GP_REG_FIRST + 1)
905
 
906
#define GP_REG_P(REGNO) \
907
  ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
908
 
909
/* IQ2000 registers used in prologue/epilogue code when the stack frame
910
   is larger than 32K bytes.  These registers must come from the
911
   scratch register set, and not used for passing and returning
912
   arguments and any other information used in the calling sequence.  */
913
 
914
#define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
915
#define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
916
 
917
/* This macro is used later on in the file.  */
918
#define GR_REG_CLASS_P(CLASS)                                           \
919
  ((CLASS) == GR_REGS)
920
 
921
#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
922
#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
923
 
924
/* Certain machines have the property that some registers cannot be
925
   copied to some other registers without using memory.  Define this
926
   macro on those machines to be a C expression that is nonzero if
927
   objects of mode MODE in registers of CLASS1 can only be copied to
928
   registers of class CLASS2 by storing a register of CLASS1 into
929
   memory and loading that memory location into a register of CLASS2.
930
 
931
   Do not define this macro if its value would always be zero.  */
932
 
933
/* Return the maximum number of consecutive registers
934
   needed to represent mode MODE in a register of class CLASS.  */
935
 
936
#define CLASS_UNITS(mode, size)                                         \
937
  ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
938
 
939
/* If defined, gives a class of registers that cannot be used as the
940
   operand of a SUBREG that changes the mode of the object illegally.  */
941
 
942
#define CLASS_CANNOT_CHANGE_MODE 0
943
 
944
/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
945
 
946
#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
947
  (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
948
 
949
/* Make sure 4 words are always allocated on the stack.  */
950
 
951
#ifndef STACK_ARGS_ADJUST
952
#define STACK_ARGS_ADJUST(SIZE)                                         \
953
  {                                                                     \
954
    if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
955
      SIZE.constant = 4 * UNITS_PER_WORD;                               \
956
  }
957
#endif
958
 
959
 
960
/* Symbolic macros for the registers used to return integer and floating
961
   point values.  */
962
 
963
#define GP_RETURN (GP_REG_FIRST + 2)
964
 
965
/* Symbolic macros for the first/last argument registers.  */
966
 
967
#define GP_ARG_FIRST (GP_REG_FIRST + 4)
968
#define GP_ARG_LAST  (GP_REG_FIRST + 11)
969
 
970
#define MAX_ARGS_IN_REGISTERS   8
971
 
972
 
973
/* Tell prologue and epilogue if register REGNO should be saved / restored.  */
974
 
975
#define MUST_SAVE_REGISTER(regno) \
976
 ((regs_ever_live[regno] && !call_used_regs[regno])                     \
977
  || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
978
  || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
979
 
980
/* ALIGN FRAMES on double word boundaries */
981
#ifndef IQ2000_STACK_ALIGN
982
#define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
983
#endif
984
 
985
 
986
/* These assume that REGNO is a hard or pseudo reg number.
987
   They give nonzero only if REGNO is a hard reg of the suitable class
988
   or a pseudo reg currently allocated to a suitable hard reg.
989
   These definitions are NOT overridden anywhere.  */
990
 
991
#define BASE_REG_P(regno, mode)                                 \
992
  (GP_REG_P (regno))
993
 
994
#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
995
  BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
996
             (mode))
997
 
998
#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
999
  (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
1000
 
1001
#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
1002
  GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
1003
 
1004
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1005
   and check its validity for a certain class.
1006
   We have two alternate definitions for each of them.
1007
   The usual definition accepts all pseudo regs; the other rejects them all.
1008
   The symbol REG_OK_STRICT causes the latter definition to be used.
1009
 
1010
   Most source files want to accept pseudo regs in the hope that
1011
   they will get allocated to the class that the insn wants them to be in.
1012
   Some source files that are used after register allocation
1013
   need to be strict.  */
1014
 
1015
#ifndef REG_OK_STRICT
1016
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1017
  iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
1018
#else
1019
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1020
  iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
1021
#endif
1022
 
1023
#if 1
1024
#define GO_PRINTF(x)    fprintf (stderr, (x))
1025
#define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
1026
#define GO_DEBUG_RTX(x) debug_rtx (x)
1027
 
1028
#else
1029
#define GO_PRINTF(x)
1030
#define GO_PRINTF2(x,y)
1031
#define GO_DEBUG_RTX(x)
1032
#endif
1033
 
1034
/* If defined, modifies the length assigned to instruction INSN as a
1035
   function of the context in which it is used.  LENGTH is an lvalue
1036
   that contains the initially computed length of the insn and should
1037
   be updated with the correct length of the insn.  */
1038
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1039
  ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
1040
 
1041
 
1042
 
1043
 
1044
/* How to tell the debugger about changes of source files.  */
1045
 
1046
#ifndef SET_FILE_NUMBER
1047
#define SET_FILE_NUMBER() ++ num_source_filenames
1048
#endif
1049
 
1050
/* This is how to output a note the debugger telling it the line number
1051
   to which the following sequence of instructions corresponds.  */
1052
 
1053
#ifndef LABEL_AFTER_LOC
1054
#define LABEL_AFTER_LOC(STREAM)
1055
#endif
1056
 
1057
 
1058
/* Default to -G 8 */
1059
#ifndef IQ2000_DEFAULT_GVALUE
1060
#define IQ2000_DEFAULT_GVALUE 8
1061
#endif
1062
 
1063
#define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
1064
 
1065
 
1066
/* List of all IQ2000 punctuation characters used by print_operand.  */
1067
extern char iq2000_print_operand_punct[256];
1068
 
1069
/* The target cpu for optimization and scheduling.  */
1070
extern enum processor_type iq2000_tune;
1071
 
1072
/* Which instruction set architecture to use.  */
1073
extern int iq2000_isa;
1074
 
1075
/* Cached operands, and operator to compare for use in set/branch/trap
1076
   on condition codes.  */
1077
extern rtx branch_cmp[2];
1078
 
1079
/* What type of branch to use.  */
1080
extern enum cmp_type branch_type;
1081
 
1082
enum iq2000_builtins
1083
{
1084
  IQ2000_BUILTIN_ADO16,
1085
  IQ2000_BUILTIN_CFC0,
1086
  IQ2000_BUILTIN_CFC1,
1087
  IQ2000_BUILTIN_CFC2,
1088
  IQ2000_BUILTIN_CFC3,
1089
  IQ2000_BUILTIN_CHKHDR,
1090
  IQ2000_BUILTIN_CTC0,
1091
  IQ2000_BUILTIN_CTC1,
1092
  IQ2000_BUILTIN_CTC2,
1093
  IQ2000_BUILTIN_CTC3,
1094
  IQ2000_BUILTIN_LU,
1095
  IQ2000_BUILTIN_LUC32L,
1096
  IQ2000_BUILTIN_LUC64,
1097
  IQ2000_BUILTIN_LUC64L,
1098
  IQ2000_BUILTIN_LUK,
1099
  IQ2000_BUILTIN_LULCK,
1100
  IQ2000_BUILTIN_LUM32,
1101
  IQ2000_BUILTIN_LUM32L,
1102
  IQ2000_BUILTIN_LUM64,
1103
  IQ2000_BUILTIN_LUM64L,
1104
  IQ2000_BUILTIN_LUR,
1105
  IQ2000_BUILTIN_LURL,
1106
  IQ2000_BUILTIN_MFC0,
1107
  IQ2000_BUILTIN_MFC1,
1108
  IQ2000_BUILTIN_MFC2,
1109
  IQ2000_BUILTIN_MFC3,
1110
  IQ2000_BUILTIN_MRGB,
1111
  IQ2000_BUILTIN_MTC0,
1112
  IQ2000_BUILTIN_MTC1,
1113
  IQ2000_BUILTIN_MTC2,
1114
  IQ2000_BUILTIN_MTC3,
1115
  IQ2000_BUILTIN_PKRL,
1116
  IQ2000_BUILTIN_RAM,
1117
  IQ2000_BUILTIN_RB,
1118
  IQ2000_BUILTIN_RX,
1119
  IQ2000_BUILTIN_SRRD,
1120
  IQ2000_BUILTIN_SRRDL,
1121
  IQ2000_BUILTIN_SRULC,
1122
  IQ2000_BUILTIN_SRULCK,
1123
  IQ2000_BUILTIN_SRWR,
1124
  IQ2000_BUILTIN_SRWRU,
1125
  IQ2000_BUILTIN_TRAPQF,
1126
  IQ2000_BUILTIN_TRAPQFL,
1127
  IQ2000_BUILTIN_TRAPQN,
1128
  IQ2000_BUILTIN_TRAPQNE,
1129
  IQ2000_BUILTIN_TRAPRE,
1130
  IQ2000_BUILTIN_TRAPREL,
1131
  IQ2000_BUILTIN_WB,
1132
  IQ2000_BUILTIN_WBR,
1133
  IQ2000_BUILTIN_WBU,
1134
  IQ2000_BUILTIN_WX,
1135
  IQ2000_BUILTIN_SYSCALL
1136
};

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