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1 38 julius
/* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2
   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3
   2005, 2006, 2007 Free Software Foundation, Inc.
4
 
5
   This file is part of GCC.
6
 
7
   GCC is free software; you can redistribute it and/or modify it
8
   under the terms of the GNU General Public License as published
9
   by the Free Software Foundation; either version 3, or (at your
10
   option) any later version.
11
 
12
   GCC is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GCC; see the file COPYING3.  If not see
19
   <http://www.gnu.org/licenses/>.  */
20
 
21
/* Things to do:
22
- longlong.h?
23
*/
24
 
25
#undef SWITCH_TAKES_ARG
26
#undef WORD_SWITCH_TAKES_ARG
27
#undef HANDLE_SYSV_PRAGMA
28
#undef SIZE_TYPE
29
#undef PTRDIFF_TYPE
30
#undef WCHAR_TYPE
31
#undef WCHAR_TYPE_SIZE
32
#undef TARGET_VERSION
33
#undef CPP_SPEC
34
#undef ASM_SPEC
35
#undef LINK_SPEC
36
#undef STARTFILE_SPEC
37
#undef ENDFILE_SPEC
38
 
39
#undef ASM_APP_ON
40
#undef ASM_APP_OFF
41
 
42
 
43
/* M32R/X overrides.  */
44
/* Print subsidiary information on the compiler version in use.  */
45
#define TARGET_VERSION fprintf (stderr, " (m32r/x/2)");
46
 
47
/* Additional flags for the preprocessor.  */
48
#define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
49
%{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
50
%{m32r:-U__M32RX__  -U__m32rx__ -U__M32R2__ -U__m32r2__} \
51
 "
52
 
53
/* Assembler switches.  */
54
#define ASM_CPU_SPEC \
55
"%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
56
 
57
/* Use m32rx specific crt0/crtinit/crtfini files.  */
58
#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
59
#define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
60
 
61
/* Define this macro as a C expression for the initializer of an array of
62
   strings to tell the driver program which options are defaults for this
63
   target and thus do not need to be handled specially when using
64
   `MULTILIB_OPTIONS'.  */
65
#define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
66
 
67
/* Number of additional registers the subtarget defines.  */
68
#define SUBTARGET_NUM_REGISTERS 1
69
 
70
/* 1 for registers that cannot be allocated.  */
71
#define SUBTARGET_FIXED_REGISTERS , 1
72
 
73
/* 1 for registers that are not available across function calls.  */
74
#define SUBTARGET_CALL_USED_REGISTERS , 1
75
 
76
/* Order to allocate model specific registers.  */
77
#define SUBTARGET_REG_ALLOC_ORDER , 19
78
 
79
/* Registers which are accumulators.  */
80
#define SUBTARGET_REG_CLASS_ACCUM 0x80000
81
 
82
/* All registers added.  */
83
#define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
84
 
85
/* Additional accumulator registers.  */
86
#define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
87
 
88
/* Define additional register names.  */
89
#define SUBTARGET_REGISTER_NAMES , "a1"
90
/* end M32R/X overrides.  */
91
 
92
/* Print subsidiary information on the compiler version in use.  */
93
#ifndef TARGET_VERSION
94
#define TARGET_VERSION fprintf (stderr, " (m32r)")
95
#endif
96
 
97
/* Switch  Recognition by gcc.c.  Add -G xx support.  */
98
 
99
#undef  SWITCH_TAKES_ARG
100
#define SWITCH_TAKES_ARG(CHAR) \
101
(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
102
 
103
/* Names to predefine in the preprocessor for this target machine.  */
104
/* __M32R__ is defined by the existing compiler so we use that.  */
105
#define TARGET_CPU_CPP_BUILTINS()               \
106
  do                                            \
107
    {                                           \
108
      builtin_define ("__M32R__");              \
109
      builtin_define ("__m32r__");              \
110
      builtin_assert ("cpu=m32r");              \
111
      builtin_assert ("machine=m32r");          \
112
      builtin_define (TARGET_BIG_ENDIAN         \
113
                      ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
114
    }                                           \
115
  while (0)
116
 
117
/* This macro defines names of additional specifications to put in the specs
118
   that can be used in various specifications like CC1_SPEC.  Its definition
119
   is an initializer with a subgrouping for each command option.
120
 
121
   Each subgrouping contains a string constant, that defines the
122
   specification name, and a string constant that used by the GCC driver
123
   program.
124
 
125
   Do not define this macro if it does not need to do anything.  */
126
 
127
#ifndef SUBTARGET_EXTRA_SPECS
128
#define SUBTARGET_EXTRA_SPECS
129
#endif
130
 
131
#ifndef ASM_CPU_SPEC
132
#define ASM_CPU_SPEC ""
133
#endif
134
 
135
#ifndef CPP_CPU_SPEC
136
#define CPP_CPU_SPEC ""
137
#endif
138
 
139
#ifndef CC1_CPU_SPEC
140
#define CC1_CPU_SPEC ""
141
#endif
142
 
143
#ifndef LINK_CPU_SPEC
144
#define LINK_CPU_SPEC ""
145
#endif
146
 
147
#ifndef STARTFILE_CPU_SPEC
148
#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
149
#endif
150
 
151
#ifndef ENDFILE_CPU_SPEC
152
#define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
153
#endif
154
 
155
#ifndef RELAX_SPEC
156
#if 0 /* Not supported yet.  */
157
#define RELAX_SPEC "%{mrelax:-relax}"
158
#else
159
#define RELAX_SPEC ""
160
#endif
161
#endif
162
 
163
#define EXTRA_SPECS                                                     \
164
  { "asm_cpu",                  ASM_CPU_SPEC },                         \
165
  { "cpp_cpu",                  CPP_CPU_SPEC },                         \
166
  { "cc1_cpu",                  CC1_CPU_SPEC },                         \
167
  { "link_cpu",                 LINK_CPU_SPEC },                        \
168
  { "startfile_cpu",            STARTFILE_CPU_SPEC },                   \
169
  { "endfile_cpu",              ENDFILE_CPU_SPEC },                     \
170
  { "relax",                    RELAX_SPEC },                           \
171
  SUBTARGET_EXTRA_SPECS
172
 
173
#define CPP_SPEC "%(cpp_cpu)"
174
 
175
#undef  CC1_SPEC
176
#define CC1_SPEC "%{G*} %(cc1_cpu)"
177
 
178
/* Options to pass on to the assembler.  */
179
#undef  ASM_SPEC
180
#define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}"
181
 
182
#define LINK_SPEC "%{v} %(link_cpu) %(relax)"
183
 
184
#undef  STARTFILE_SPEC
185
#define STARTFILE_SPEC "%(startfile_cpu)"
186
 
187
#undef  ENDFILE_SPEC
188
#define ENDFILE_SPEC "%(endfile_cpu)"
189
 
190
#undef LIB_SPEC
191
 
192
/* Run-time compilation parameters selecting different hardware subsets.  */
193
 
194
#define TARGET_M32R             (! TARGET_M32RX && ! TARGET_M32R2)
195
 
196
#ifndef TARGET_LITTLE_ENDIAN
197
#define TARGET_LITTLE_ENDIAN    0
198
#endif
199
#define TARGET_BIG_ENDIAN       (! TARGET_LITTLE_ENDIAN)
200
 
201
/* This defaults us to m32r.  */
202
#ifndef TARGET_CPU_DEFAULT
203
#define TARGET_CPU_DEFAULT 0
204
#endif
205
 
206
/* Code Models
207
 
208
   Code models are used to select between two choices of two separate
209
   possibilities (address space size, call insn to use):
210
 
211
   small: addresses use 24 bits, use bl to make calls
212
   medium: addresses use 32 bits, use bl to make calls (*1)
213
   large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
214
 
215
   The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
216
   using this one doesn't make much sense.
217
 
218
   (*1) The linker may eventually be able to relax seth/add3 -> ld24.
219
   (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
220
 
221
   Internally these are recorded as TARGET_ADDR{24,32} and
222
   TARGET_CALL{26,32}.
223
 
224
   The __model__ attribute can be used to select the code model to use when
225
   accessing particular objects.  */
226
 
227
enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
228
 
229
extern enum m32r_model m32r_model;
230
#define TARGET_MODEL_SMALL  (m32r_model == M32R_MODEL_SMALL)
231
#define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
232
#define TARGET_MODEL_LARGE  (m32r_model == M32R_MODEL_LARGE)
233
#define TARGET_ADDR24       (m32r_model == M32R_MODEL_SMALL)
234
#define TARGET_ADDR32       (! TARGET_ADDR24)
235
#define TARGET_CALL26       (! TARGET_CALL32)
236
#define TARGET_CALL32       (m32r_model == M32R_MODEL_LARGE)
237
 
238
/* The default is the small model.  */
239
#ifndef M32R_MODEL_DEFAULT
240
#define M32R_MODEL_DEFAULT M32R_MODEL_SMALL
241
#endif
242
 
243
/* Small Data Area
244
 
245
   The SDA consists of sections .sdata, .sbss, and .scommon.
246
   .scommon isn't a real section, symbols in it have their section index
247
   set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
248
 
249
   Two switches control the SDA:
250
 
251
   -G NNN        - specifies the maximum size of variable to go in the SDA
252
 
253
   -msdata=foo   - specifies how such variables are handled
254
 
255
        -msdata=none  - small data area is disabled
256
 
257
        -msdata=sdata - small data goes in the SDA, special code isn't
258
                        generated to use it, and special relocs aren't
259
                        generated
260
 
261
        -msdata=use   - small data goes in the SDA, special code is generated
262
                        to use the SDA and special relocs are generated
263
 
264
   The SDA is not multilib'd, it isn't necessary.
265
   MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
266
   libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
267
   -msdata=use will successfully link with them (references in header files
268
   will cause the compiler to emit code that refers to library objects in
269
   .data).  ??? There can be a problem if the user passes a -G value greater
270
   than the default and a library object in a header file is that size.
271
   The default is 8 so this should be rare - if it occurs the user
272
   is required to rebuild the libraries or use a smaller value for -G.  */
273
 
274
/* Maximum size of variables that go in .sdata/.sbss.
275
   The -msdata=foo switch also controls how small variables are handled.  */
276
#ifndef SDATA_DEFAULT_SIZE
277
#define SDATA_DEFAULT_SIZE 8
278
#endif
279
 
280
enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
281
 
282
extern enum m32r_sdata m32r_sdata;
283
#define TARGET_SDATA_NONE  (m32r_sdata == M32R_SDATA_NONE)
284
#define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
285
#define TARGET_SDATA_USE   (m32r_sdata == M32R_SDATA_USE)
286
 
287
/* Default is to disable the SDA
288
   [for upward compatibility with previous toolchains].  */
289
#ifndef M32R_SDATA_DEFAULT
290
#define M32R_SDATA_DEFAULT M32R_SDATA_NONE
291
#endif
292
 
293
/* Define this macro as a C expression for the initializer of an array of
294
   strings to tell the driver program which options are defaults for this
295
   target and thus do not need to be handled specially when using
296
   `MULTILIB_OPTIONS'.  */
297
#ifndef SUBTARGET_MULTILIB_DEFAULTS
298
#define SUBTARGET_MULTILIB_DEFAULTS
299
#endif
300
 
301
#ifndef MULTILIB_DEFAULTS
302
#define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
303
#endif
304
 
305
/* Sometimes certain combinations of command options do not make
306
   sense on a particular target machine.  You can define a macro
307
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
308
   defined, is executed once just after all the command options have
309
   been parsed.
310
 
311
   Don't use this macro to turn on various extra optimizations for
312
   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
313
 
314
#ifndef SUBTARGET_OVERRIDE_OPTIONS
315
#define SUBTARGET_OVERRIDE_OPTIONS
316
#endif
317
 
318
#define OVERRIDE_OPTIONS                        \
319
  do                                            \
320
    {                                           \
321
      /* These need to be done at start up.     \
322
         It's convenient to do them here.  */   \
323
      m32r_init ();                             \
324
      SUBTARGET_OVERRIDE_OPTIONS                \
325
    }                                           \
326
  while (0)
327
 
328
#ifndef SUBTARGET_OPTIMIZATION_OPTIONS
329
#define SUBTARGET_OPTIMIZATION_OPTIONS
330
#endif
331
 
332
#define OPTIMIZATION_OPTIONS(LEVEL, SIZE)       \
333
  do                                            \
334
    {                                           \
335
      if (LEVEL == 1)                           \
336
        flag_regmove = TRUE;                    \
337
                                                \
338
      if (SIZE)                                 \
339
        {                                       \
340
          flag_omit_frame_pointer = TRUE;       \
341
        }                                       \
342
                                                \
343
      SUBTARGET_OPTIMIZATION_OPTIONS            \
344
    }                                           \
345
  while (0)
346
 
347
/* Define this macro if debugging can be performed even without a
348
   frame pointer.  If this macro is defined, GCC will turn on the
349
   `-fomit-frame-pointer' option whenever `-O' is specified.  */
350
#define CAN_DEBUG_WITHOUT_FP
351
 
352
/* Target machine storage layout.  */
353
 
354
/* Define this if most significant bit is lowest numbered
355
   in instructions that operate on numbered bit-fields.  */
356
#define BITS_BIG_ENDIAN 1
357
 
358
/* Define this if most significant byte of a word is the lowest numbered.  */
359
#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
360
 
361
/* Define this if most significant word of a multiword number is the lowest
362
   numbered.  */
363
#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
364
 
365
/* Define this macro if WORDS_BIG_ENDIAN is not constant.  This must
366
   be a constant value with the same meaning as WORDS_BIG_ENDIAN,
367
   which will be used only when compiling libgcc2.c.  Typically the
368
   value will be set based on preprocessor defines.  */
369
/*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
370
 
371
/* Width of a word, in units (bytes).  */
372
#define UNITS_PER_WORD 4
373
 
374
/* Define this macro if it is advisable to hold scalars in registers
375
   in a wider mode than that declared by the program.  In such cases,
376
   the value is constrained to be within the bounds of the declared
377
   type, but kept valid in the wider mode.  The signedness of the
378
   extension may differ from that of the type.  */
379
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
380
  if (GET_MODE_CLASS (MODE) == MODE_INT         \
381
      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
382
    {                                           \
383
      (MODE) = SImode;                          \
384
    }
385
 
386
/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
387
#define PARM_BOUNDARY 32
388
 
389
/* Boundary (in *bits*) on which stack pointer should be aligned.  */
390
#define STACK_BOUNDARY 32
391
 
392
/* ALIGN FRAMES on word boundaries */
393
#define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
394
 
395
/* Allocation boundary (in *bits*) for the code of a function.  */
396
#define FUNCTION_BOUNDARY 32
397
 
398
/* Alignment of field after `int : 0' in a structure.  */
399
#define EMPTY_FIELD_BOUNDARY 32
400
 
401
/* Every structure's size must be a multiple of this.  */
402
#define STRUCTURE_SIZE_BOUNDARY 8
403
 
404
/* A bit-field declared as `int' forces `int' alignment for the struct.  */
405
#define PCC_BITFIELD_TYPE_MATTERS 1
406
 
407
/* No data type wants to be aligned rounder than this.  */
408
#define BIGGEST_ALIGNMENT 32
409
 
410
/* The best alignment to use in cases where we have a choice.  */
411
#define FASTEST_ALIGNMENT 32
412
 
413
/* Make strings word-aligned so strcpy from constants will be faster.  */
414
#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
415
  ((TREE_CODE (EXP) == STRING_CST       \
416
    && (ALIGN) < FASTEST_ALIGNMENT)     \
417
   ? FASTEST_ALIGNMENT : (ALIGN))
418
 
419
/* Make arrays of chars word-aligned for the same reasons.  */
420
#define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
421
  (TREE_CODE (TYPE) == ARRAY_TYPE                                       \
422
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode                            \
423
   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
424
 
425
/* Set this nonzero if move instructions will actually fail to work
426
   when given unaligned data.  */
427
#define STRICT_ALIGNMENT 1
428
 
429
/* Define LAVEL_ALIGN to calculate code length of PNOP at labels.  */
430
#define LABEL_ALIGN(insn) 2
431
 
432
/* Layout of source language data types.  */
433
 
434
#define SHORT_TYPE_SIZE         16
435
#define INT_TYPE_SIZE           32
436
#define LONG_TYPE_SIZE          32
437
#define LONG_LONG_TYPE_SIZE     64
438
#define FLOAT_TYPE_SIZE         32
439
#define DOUBLE_TYPE_SIZE        64
440
#define LONG_DOUBLE_TYPE_SIZE   64
441
 
442
/* Define this as 1 if `char' should by default be signed; else as 0.  */
443
#define DEFAULT_SIGNED_CHAR 1
444
 
445
#define SIZE_TYPE "long unsigned int"
446
#define PTRDIFF_TYPE "long int"
447
#define WCHAR_TYPE "short unsigned int"
448
#define WCHAR_TYPE_SIZE 16
449
 
450
/* Standard register usage.  */
451
 
452
/* Number of actual hardware registers.
453
   The hardware registers are assigned numbers for the compiler
454
   from 0 to just below FIRST_PSEUDO_REGISTER.
455
   All registers that the compiler knows about must be given numbers,
456
   even those that are not normally considered general registers.  */
457
 
458
#define M32R_NUM_REGISTERS      19
459
 
460
#ifndef SUBTARGET_NUM_REGISTERS
461
#define SUBTARGET_NUM_REGISTERS 0
462
#endif
463
 
464
#define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
465
 
466
/* 1 for registers that have pervasive standard uses
467
   and are not available for the register allocator.
468
 
469
   0-3   - arguments/results
470
   4-5   - call used [4 is used as a tmp during prologue/epilogue generation]
471
   6     - call used, gptmp
472
   7     - call used, static chain pointer
473
   8-11  - call saved
474
   12    - call saved [reserved for global pointer]
475
   13    - frame pointer
476
   14    - subroutine link register
477
   15    - stack pointer
478
   16    - arg pointer
479
   17    - carry flag
480
   18    - accumulator
481
   19    - accumulator 1 in the m32r/x
482
   By default, the extension registers are not available.  */
483
 
484
#ifndef SUBTARGET_FIXED_REGISTERS
485
#define SUBTARGET_FIXED_REGISTERS
486
#endif
487
 
488
#define FIXED_REGISTERS         \
489
{                               \
490
  0, 0, 0, 0, 0, 0, 0, 0,       \
491
  0, 0, 0, 0, 0, 0, 0, 1,       \
492
  1, 1, 1                       \
493
  SUBTARGET_FIXED_REGISTERS     \
494
}
495
 
496
/* 1 for registers not available across function calls.
497
   These must include the FIXED_REGISTERS and also any
498
   registers that can be used without being saved.
499
   The latter must include the registers where values are returned
500
   and the register where structure-value addresses are passed.
501
   Aside from that, you can include as many other registers as you like.  */
502
 
503
#ifndef SUBTARGET_CALL_USED_REGISTERS
504
#define SUBTARGET_CALL_USED_REGISTERS
505
#endif
506
 
507
#define CALL_USED_REGISTERS     \
508
{                               \
509
  1, 1, 1, 1, 1, 1, 1, 1,       \
510
  0, 0, 0, 0, 0, 0, 1, 1,       \
511
  1, 1, 1                       \
512
  SUBTARGET_CALL_USED_REGISTERS \
513
}
514
 
515
#define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
516
 
517
/* Zero or more C statements that may conditionally modify two variables
518
   `fixed_regs' and `call_used_regs' (both of type `char []') after they
519
   have been initialized from the two preceding macros.
520
 
521
   This is necessary in case the fixed or call-clobbered registers depend
522
   on target flags.
523
 
524
   You need not define this macro if it has no work to do.  */
525
 
526
#ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
527
#define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
528
#else
529
#define CONDITIONAL_REGISTER_USAGE                       \
530
  do                                                     \
531
    {                                                    \
532
      if (flag_pic)                                      \
533
       {                                                 \
534
         fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;        \
535
         call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;    \
536
       }                                                 \
537
    }                                                    \
538
  while (0)
539
#endif
540
 
541
/* If defined, an initializer for a vector of integers, containing the
542
   numbers of hard registers in the order in which GCC should
543
   prefer to use them (from most preferred to least).  */
544
 
545
#ifndef SUBTARGET_REG_ALLOC_ORDER
546
#define SUBTARGET_REG_ALLOC_ORDER
547
#endif
548
 
549
#if 1 /* Better for int code.  */
550
#define REG_ALLOC_ORDER                         \
551
{                                               \
552
  4,  5,  6,  7,  2,  3,  8,  9, 10,            \
553
  11, 12, 13, 14,  0,  1, 15, 16, 17, 18        \
554
  SUBTARGET_REG_ALLOC_ORDER                     \
555
}
556
 
557
#else /* Better for fp code at expense of int code.  */
558
#define REG_ALLOC_ORDER                         \
559
{                                               \
560
   0,  1,  2,  3,  4,  5,  6,  7,  8,           \
561
   9, 10, 11, 12, 13, 14, 15, 16, 17, 18        \
562
  SUBTARGET_REG_ALLOC_ORDER                     \
563
}
564
#endif
565
 
566
/* Return number of consecutive hard regs needed starting at reg REGNO
567
   to hold something of mode MODE.
568
   This is ordinarily the length in words of a value of mode MODE
569
   but can be less for certain modes in special long registers.  */
570
#define HARD_REGNO_NREGS(REGNO, MODE) \
571
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
572
 
573
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.  */
574
extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
575
extern unsigned int m32r_mode_class[];
576
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
577
  ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
578
 
579
/* A C expression that is nonzero if it is desirable to choose
580
   register allocation so as to avoid move instructions between a
581
   value of mode MODE1 and a value of mode MODE2.
582
 
583
   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
584
   MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
585
   MODE2)' must be zero.  */
586
 
587
/* Tie QI/HI/SI modes together.  */
588
#define MODES_TIEABLE_P(MODE1, MODE2)           \
589
  (   GET_MODE_CLASS (MODE1) == MODE_INT        \
590
   && GET_MODE_CLASS (MODE2) == MODE_INT        \
591
   && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD   \
592
   && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
593
 
594
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
595
  m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
596
 
597
/* Register classes and constants.  */
598
 
599
/* Define the classes of registers for register constraints in the
600
   machine description.  Also define ranges of constants.
601
 
602
   One of the classes must always be named ALL_REGS and include all hard regs.
603
   If there is more than one class, another class must be named NO_REGS
604
   and contain no registers.
605
 
606
   The name GENERAL_REGS must be the name of a class (or an alias for
607
   another name such as ALL_REGS).  This is the class of registers
608
   that is allowed by "g" or "r" in a register constraint.
609
   Also, registers outside this class are allocated only when
610
   instructions express preferences for them.
611
 
612
   The classes must be numbered in nondecreasing order; that is,
613
   a larger-numbered class must never be contained completely
614
   in a smaller-numbered class.
615
 
616
   For any two classes, it is very desirable that there be another
617
   class that represents their union.
618
 
619
   It is important that any condition codes have class NO_REGS.
620
   See `register_operand'.  */
621
 
622
enum reg_class
623
{
624
  NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
625
};
626
 
627
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
628
 
629
/* Give names of register classes as strings for dump file.  */
630
#define REG_CLASS_NAMES \
631
  { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
632
 
633
/* Define which registers fit in which classes.
634
   This is an initializer for a vector of HARD_REG_SET
635
   of length N_REG_CLASSES.  */
636
 
637
#ifndef SUBTARGET_REG_CLASS_CARRY
638
#define SUBTARGET_REG_CLASS_CARRY 0
639
#endif
640
 
641
#ifndef SUBTARGET_REG_CLASS_ACCUM
642
#define SUBTARGET_REG_CLASS_ACCUM 0
643
#endif
644
 
645
#ifndef SUBTARGET_REG_CLASS_GENERAL
646
#define SUBTARGET_REG_CLASS_GENERAL 0
647
#endif
648
 
649
#ifndef SUBTARGET_REG_CLASS_ALL
650
#define SUBTARGET_REG_CLASS_ALL 0
651
#endif
652
 
653
#define REG_CLASS_CONTENTS                                              \
654
{                                                                       \
655
  { 0x00000 },                                                          \
656
  { 0x20000 | SUBTARGET_REG_CLASS_CARRY },                              \
657
  { 0x40000 | SUBTARGET_REG_CLASS_ACCUM },                              \
658
  { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL },                            \
659
  { 0x7ffff | SUBTARGET_REG_CLASS_ALL },                                \
660
}
661
 
662
/* The same information, inverted:
663
   Return the class number of the smallest class containing
664
   reg number REGNO.  This could be a conditional expression
665
   or could index an array.  */
666
extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
667
#define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
668
 
669
/* The class value for index registers, and the one for base regs.  */
670
#define INDEX_REG_CLASS GENERAL_REGS
671
#define BASE_REG_CLASS GENERAL_REGS
672
 
673
#define REG_CLASS_FROM_LETTER(C)                        \
674
  (  (C) == 'c' ? CARRY_REG                             \
675
   : (C) == 'a' ? ACCUM_REGS                            \
676
   :              NO_REGS)
677
 
678
/* These assume that REGNO is a hard or pseudo reg number.
679
   They give nonzero only if REGNO is a hard reg of the suitable class
680
   or a pseudo reg currently allocated to a suitable hard reg.
681
   Since they use reg_renumber, they are safe only once reg_renumber
682
   has been allocated, which happens in local-alloc.c.  */
683
#define REGNO_OK_FOR_BASE_P(REGNO) \
684
  ((REGNO) < FIRST_PSEUDO_REGISTER                      \
685
   ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM     \
686
   : GPR_P (reg_renumber[REGNO]))
687
 
688
#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
689
 
690
/* Given an rtx X being reloaded into a reg required to be
691
   in class CLASS, return the class of reg to actually use.
692
   In general this is just CLASS; but on some machines
693
   in some cases it is preferable to use a more restrictive class.  */
694
#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
695
 
696
/* Return the maximum number of consecutive registers
697
   needed to represent mode MODE in a register of class CLASS.  */
698
#define CLASS_MAX_NREGS(CLASS, MODE) \
699
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
700
 
701
/* The letters I, J, K, L, M, N, O, P in a register constraint string
702
   can be used to stand for particular ranges of immediate operands.
703
   This macro defines what the ranges are.
704
   C is the letter, and VALUE is a constant value.
705
   Return 1 if VALUE is in the range specified by C.  */
706
/* 'I' is used for 8 bit signed immediates.
707
   'J' is used for 16 bit signed immediates.
708
   'K' is used for 16 bit unsigned immediates.
709
   'L' is used for 16 bit immediates left shifted by 16 (sign ???).
710
   'M' is used for 24 bit unsigned immediates.
711
   'N' is used for any 32 bit non-symbolic value.
712
   'O' is used for 5 bit unsigned immediates (shift count).
713
   'P' is used for 16 bit signed immediates for compares
714
       (values in the range -32767 to +32768).  */
715
 
716
/* Return true if a value is inside a range.  */
717
#define IN_RANGE_P(VALUE, LOW, HIGH)                                    \
718
  (((unsigned HOST_WIDE_INT)((VALUE) - (LOW)))                          \
719
   <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
720
 
721
/* Local to this file.  */
722
#define INT8_P(X)      ((X) >= -   0x80 && (X) <= 0x7f)
723
#define INT16_P(X)     ((X) >= - 0x8000 && (X) <= 0x7fff)
724
#define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
725
#define UPPER16_P(X)  (((X) & 0xffff) == 0                              \
726
                        && ((X) >> 16) >= - 0x8000                      \
727
                        && ((X) >> 16) <= 0x7fff)
728
#define UINT16_P(X)   (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
729
#define UINT24_P(X)   (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
730
#define UINT32_P(X)   (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
731
#define UINT5_P(X)    ((X) >= 0 && (X) < 32)
732
#define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
733
 
734
#define CONST_OK_FOR_LETTER_P(VALUE, C)                                 \
735
  (  (C) == 'I' ? INT8_P (VALUE)                                        \
736
   : (C) == 'J' ? INT16_P (VALUE)                                       \
737
   : (C) == 'K' ? UINT16_P (VALUE)                                      \
738
   : (C) == 'L' ? UPPER16_P (VALUE)                                     \
739
   : (C) == 'M' ? UINT24_P (VALUE)                                      \
740
   : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE)                          \
741
   : (C) == 'O' ? UINT5_P (VALUE)                                       \
742
   : (C) == 'P' ? CMP_INT16_P (VALUE)                                   \
743
   : 0)
744
 
745
/* Similar, but for floating constants, and defining letters G and H.
746
   Here VALUE is the CONST_DOUBLE rtx itself.
747
   For the m32r, handle a few constants inline.
748
   ??? We needn't treat DI and DF modes differently, but for now we do.  */
749
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)                          \
750
  (  (C) == 'G' ? easy_di_const (VALUE)                                 \
751
   : (C) == 'H' ? easy_df_const (VALUE)                                 \
752
   : 0)
753
 
754
/* A C expression that defines the optional machine-dependent constraint
755
   letters that can be used to segregate specific types of operands,
756
   usually memory references, for the target machine.  It should return 1 if
757
   VALUE corresponds to the operand type represented by the constraint letter
758
   C.  If C is not defined as an extra constraint, the value returned should
759
   be 0 regardless of VALUE.  */
760
/* Q is for symbolic addresses loadable with ld24.
761
   R is for symbolic addresses when ld24 can't be used.
762
   S is for stores with pre {inc,dec}rement
763
   T is for indirect of a pointer.
764
   U is for loads with post increment.  */
765
 
766
#define EXTRA_CONSTRAINT(VALUE, C)                                      \
767
  (  (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF)     \
768
                 || addr24_operand (VALUE, VOIDmode))                   \
769
   : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF)     \
770
                 || addr32_operand (VALUE, VOIDmode))                   \
771
   : (C) == 'S' ? (GET_CODE (VALUE) == MEM                              \
772
                 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE),            \
773
                                           XEXP (VALUE, 0)))            \
774
   : (C) == 'T' ? (GET_CODE (VALUE) == MEM                              \
775
                 && memreg_operand (VALUE, GET_MODE (VALUE)))           \
776
   : (C) == 'U' ? (GET_CODE (VALUE) == MEM                              \
777
                 && LOAD_POSTINC_P (GET_MODE (VALUE),                   \
778
                                    XEXP (VALUE, 0)))                   \
779
   : 0)
780
 
781
/* Stack layout and stack pointer usage.  */
782
 
783
/* Define this macro if pushing a word onto the stack moves the stack
784
   pointer to a smaller address.  */
785
#define STACK_GROWS_DOWNWARD
786
 
787
/* Offset from frame pointer to start allocating local variables at.
788
   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
789
   first local allocated.  Otherwise, it is the offset to the BEGINNING
790
   of the first local allocated.  */
791
/* The frame pointer points at the same place as the stack pointer, except if
792
   alloca has been called.  */
793
#define STARTING_FRAME_OFFSET \
794
  M32R_STACK_ALIGN (current_function_outgoing_args_size)
795
 
796
/* Offset from the stack pointer register to the first location at which
797
   outgoing arguments are placed.  */
798
#define STACK_POINTER_OFFSET 0
799
 
800
/* Offset of first parameter from the argument pointer register value.  */
801
#define FIRST_PARM_OFFSET(FNDECL) 0
802
 
803
/* Register to use for pushing function arguments.  */
804
#define STACK_POINTER_REGNUM 15
805
 
806
/* Base register for access to local variables of the function.  */
807
#define FRAME_POINTER_REGNUM 13
808
 
809
/* Base register for access to arguments of the function.  */
810
#define ARG_POINTER_REGNUM 16
811
 
812
/* Register in which static-chain is passed to a function.
813
   This must not be a register used by the prologue.  */
814
#define STATIC_CHAIN_REGNUM  7
815
 
816
/* These aren't official macros.  */
817
#define PROLOGUE_TMP_REGNUM  4
818
#define RETURN_ADDR_REGNUM  14
819
/* #define GP_REGNUM        12 */
820
#define CARRY_REGNUM        17
821
#define ACCUM_REGNUM        18
822
#define M32R_MAX_INT_REGS   16
823
 
824
#ifndef SUBTARGET_GPR_P
825
#define SUBTARGET_GPR_P(REGNO) 0
826
#endif
827
 
828
#ifndef SUBTARGET_ACCUM_P
829
#define SUBTARGET_ACCUM_P(REGNO) 0
830
#endif
831
 
832
#ifndef SUBTARGET_CARRY_P
833
#define SUBTARGET_CARRY_P(REGNO) 0
834
#endif
835
 
836
#define GPR_P(REGNO)   (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
837
#define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
838
#define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
839
 
840
/* Eliminating the frame and arg pointers.  */
841
 
842
/* A C expression which is nonzero if a function must have and use a
843
   frame pointer.  This expression is evaluated in the reload pass.
844
   If its value is nonzero the function will have a frame pointer.  */
845
#define FRAME_POINTER_REQUIRED current_function_calls_alloca
846
 
847
#if 0
848
/* C statement to store the difference between the frame pointer
849
   and the stack pointer values immediately after the function prologue.
850
   If `ELIMINABLE_REGS' is defined, this macro will be not be used and
851
   need not be defined.  */
852
#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
853
((VAR) = m32r_compute_frame_size (get_frame_size ()))
854
#endif
855
 
856
/* If defined, this macro specifies a table of register pairs used to
857
   eliminate unneeded registers that point into the stack frame.  If
858
   it is not defined, the only elimination attempted by the compiler
859
   is to replace references to the frame pointer with references to
860
   the stack pointer.
861
 
862
   Note that the elimination of the argument pointer with the stack
863
   pointer is specified first since that is the preferred elimination.  */
864
 
865
#define ELIMINABLE_REGS                                 \
866
{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },        \
867
 { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },        \
868
 { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM }}
869
 
870
/* A C expression that returns nonzero if the compiler is allowed to
871
   try to replace register number FROM-REG with register number
872
   TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
873
   defined, and will usually be the constant 1, since most of the
874
   cases preventing register elimination are things that the compiler
875
   already knows about.  */
876
 
877
#define CAN_ELIMINATE(FROM, TO)                                         \
878
  ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM         \
879
   ? ! frame_pointer_needed                                             \
880
   : 1)
881
 
882
/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
883
   specifies the initial difference between the specified pair of
884
   registers.  This macro must be defined if `ELIMINABLE_REGS' is
885
   defined.  */
886
 
887
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                            \
888
  do                                                                            \
889
    {                                                                           \
890
      int size = m32r_compute_frame_size (get_frame_size ());                   \
891
                                                                                \
892
      if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)       \
893
        (OFFSET) = 0;                                                           \
894
      else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)    \
895
        (OFFSET) = size - current_function_pretend_args_size;                   \
896
      else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)    \
897
        (OFFSET) = size - current_function_pretend_args_size;                   \
898
      else                                                                      \
899
        gcc_unreachable ();                                                             \
900
    }                                                                           \
901
  while (0)
902
 
903
/* Function argument passing.  */
904
 
905
/* If defined, the maximum amount of space required for outgoing
906
   arguments will be computed and placed into the variable
907
   `current_function_outgoing_args_size'.  No space will be pushed
908
   onto the stack for each call; instead, the function prologue should
909
   increase the stack frame size by this amount.  */
910
#define ACCUMULATE_OUTGOING_ARGS 1
911
 
912
/* Value is the number of bytes of arguments automatically
913
   popped when returning from a subroutine call.
914
   FUNDECL is the declaration node of the function (as a tree),
915
   FUNTYPE is the data type of the function (as a tree),
916
   or for a library call it is an identifier node for the subroutine name.
917
   SIZE is the number of bytes of arguments passed on the stack.  */
918
#define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
919
 
920
/* Define a data type for recording info about an argument list
921
   during the scan of that argument list.  This data type should
922
   hold all necessary information about the function itself
923
   and about the args processed so far, enough to enable macros
924
   such as FUNCTION_ARG to determine where the next arg should go.  */
925
#define CUMULATIVE_ARGS int
926
 
927
/* Initialize a variable CUM of type CUMULATIVE_ARGS
928
   for a call to a function whose data type is FNTYPE.
929
   For a library call, FNTYPE is 0.  */
930
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
931
  ((CUM) = 0)
932
 
933
/* The number of registers used for parameter passing.  Local to this file.  */
934
#define M32R_MAX_PARM_REGS 4
935
 
936
/* 1 if N is a possible register number for function argument passing.  */
937
#define FUNCTION_ARG_REGNO_P(N) \
938
  ((unsigned) (N) < M32R_MAX_PARM_REGS)
939
 
940
/* The ROUND_ADVANCE* macros are local to this file.  */
941
/* Round SIZE up to a word boundary.  */
942
#define ROUND_ADVANCE(SIZE) \
943
  (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
944
 
945
/* Round arg MODE/TYPE up to the next word boundary.  */
946
#define ROUND_ADVANCE_ARG(MODE, TYPE) \
947
  ((MODE) == BLKmode                            \
948
   ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE))    \
949
   : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
950
 
951
/* Round CUM up to the necessary point for argument MODE/TYPE.  */
952
#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
953
 
954
/* Return boolean indicating arg of type TYPE and mode MODE will be passed in
955
   a reg.  This includes arguments that have to be passed by reference as the
956
   pointer to them is passed in a reg if one is available (and that is what
957
   we're given).
958
   This macro is only used in this file.  */
959
#define PASS_IN_REG_P(CUM, MODE, TYPE) \
960
  (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
961
 
962
/* Determine where to put an argument to a function.
963
   Value is zero to push the argument on the stack,
964
   or a hard register in which to store the argument.
965
 
966
   MODE is the argument's machine mode.
967
   TYPE is the data type of the argument (as a tree).
968
    This is null for libcalls where that information may
969
    not be available.
970
   CUM is a variable of type CUMULATIVE_ARGS which gives info about
971
    the preceding args and about the function being called.
972
   NAMED is nonzero if this argument is a named parameter
973
    (otherwise it is an extra parameter matching an ellipsis).  */
974
/* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
975
   and the rest are pushed.  */
976
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
977
  (PASS_IN_REG_P ((CUM), (MODE), (TYPE))                        \
978
   ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))    \
979
   : 0)
980
 
981
/* Update the data in CUM to advance over an argument
982
   of mode MODE and data type TYPE.
983
   (TYPE is null for libcalls where that information may not be available.)  */
984
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
985
  ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
986
          + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
987
 
988
/* If defined, a C expression that gives the alignment boundary, in bits,
989
   of an argument with the specified mode and type.  If it is not defined,
990
   PARM_BOUNDARY is used for all arguments.  */
991
#if 0
992
/* We assume PARM_BOUNDARY == UNITS_PER_WORD here.  */
993
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
994
  (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
995
   ? PARM_BOUNDARY : 2 * PARM_BOUNDARY)
996
#endif
997
 
998
/* Function results.  */
999
 
1000
/* Define how to find the value returned by a function.
1001
   VALTYPE is the data type of the value (as a tree).
1002
   If the precise function being called is known, FUNC is its FUNCTION_DECL;
1003
   otherwise, FUNC is 0.  */
1004
#define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1005
 
1006
/* Define how to find the value returned by a library function
1007
   assuming the value has mode MODE.  */
1008
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1009
 
1010
/* 1 if N is a possible register number for a function value
1011
   as seen by the caller.  */
1012
/* ??? What about r1 in DI/DF values.  */
1013
#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1014
 
1015
/* Tell GCC to use TARGET_RETURN_IN_MEMORY.  */
1016
#define DEFAULT_PCC_STRUCT_RETURN 0
1017
 
1018
/* Function entry and exit.  */
1019
 
1020
/* Initialize data used by insn expanders.  This is called from
1021
   init_emit, once for each function, before code is generated.  */
1022
#define INIT_EXPANDERS m32r_init_expanders ()
1023
 
1024
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1025
   the stack pointer does not matter.  The value is tested only in
1026
   functions that have frame pointers.
1027
   No definition is equivalent to always zero.  */
1028
#define EXIT_IGNORE_STACK 1
1029
 
1030
/* Output assembler code to FILE to increment profiler label # LABELNO
1031
   for profiling a function entry.  */
1032
#undef  FUNCTION_PROFILER
1033
#define FUNCTION_PROFILER(FILE, LABELNO)                        \
1034
  do                                                            \
1035
    {                                                           \
1036
      if (flag_pic)                                             \
1037
        {                                                       \
1038
          fprintf (FILE, "\tld24 r14,#mcount\n");               \
1039
          fprintf (FILE, "\tadd r14,r12\n");                    \
1040
          fprintf (FILE, "\tld r14,@r14\n");                    \
1041
          fprintf (FILE, "\tjl r14\n");                         \
1042
        }                                                       \
1043
      else                                                      \
1044
        {                                                       \
1045
          if (TARGET_ADDR24)                                    \
1046
            fprintf (FILE, "\tbl mcount\n");                    \
1047
          else                                                  \
1048
            {                                                   \
1049
              fprintf (FILE, "\tseth r14,#high(mcount)\n");     \
1050
              fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n");   \
1051
              fprintf (FILE, "\tjl r14\n");                     \
1052
            }                                                   \
1053
        }                                                       \
1054
      fprintf (FILE, "\taddi sp,#4\n");                         \
1055
    }                                                           \
1056
  while (0)
1057
 
1058
/* Trampolines.  */
1059
 
1060
/* On the M32R, the trampoline is:
1061
 
1062
        mv      r7, lr   -> bl L1        ; 178e 7e01
1063
L1:     add3    r6, lr, #L2-L1           ; 86ae 000c (L2 - L1 = 12)
1064
        mv      lr, r7   -> ld r7,@r6+   ; 1e87 27e6
1065
        ld      r6, @r6  -> jmp r6       ; 26c6 1fc6
1066
L2:     .word STATIC
1067
        .word FUNCTION  */
1068
 
1069
#ifndef CACHE_FLUSH_FUNC
1070
#define CACHE_FLUSH_FUNC "_flush_cache"
1071
#endif
1072
#ifndef CACHE_FLUSH_TRAP
1073
#define CACHE_FLUSH_TRAP 12
1074
#endif
1075
 
1076
/* Length in bytes of the trampoline for entering a nested function.  */
1077
#define TRAMPOLINE_SIZE 24
1078
 
1079
/* Emit RTL insns to initialize the variable parts of a trampoline.
1080
   FNADDR is an RTX for the address of the function's pure code.
1081
   CXT is an RTX for the static chain value for the function.  */
1082
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                               \
1083
  do                                                                            \
1084
    {                                                                           \
1085
      emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)),            \
1086
                      GEN_INT                                                   \
1087
                      (TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01));        \
1088
      emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)),           \
1089
                      GEN_INT                                                   \
1090
                      (TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c));        \
1091
      emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)),           \
1092
                      GEN_INT                                                   \
1093
                      (TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6));        \
1094
      emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)),          \
1095
                      GEN_INT                                                   \
1096
                      (TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6));        \
1097
      emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)),          \
1098
                      (CXT));                                                   \
1099
      emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)),          \
1100
                      (FNADDR));                                                \
1101
      if (m32r_cache_flush_trap >= 0)                                            \
1102
        emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\
1103
                                     GEN_INT (m32r_cache_flush_trap) ));        \
1104
      else if (m32r_cache_flush_func && m32r_cache_flush_func[0])                \
1105
        emit_library_call (m32r_function_symbol (m32r_cache_flush_func),        \
1106
                           0, VOIDmode, 3, TRAMP, Pmode,                 \
1107
                           GEN_INT (TRAMPOLINE_SIZE), SImode,                   \
1108
                           GEN_INT (3), SImode);                                \
1109
    }                                                                           \
1110
  while (0)
1111
 
1112
#define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
1113
 
1114
#define INCOMING_RETURN_ADDR_RTX   gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1115
 
1116
/* Addressing modes, and classification of registers for them.  */
1117
 
1118
/* Maximum number of registers that can appear in a valid memory address.  */
1119
#define MAX_REGS_PER_ADDRESS 1
1120
 
1121
/* We have post-inc load and pre-dec,pre-inc store,
1122
   but only for 4 byte vals.  */
1123
#define HAVE_PRE_DECREMENT  1
1124
#define HAVE_PRE_INCREMENT  1
1125
#define HAVE_POST_INCREMENT 1
1126
 
1127
/* Recognize any constant value that is a valid address.  */
1128
#define CONSTANT_ADDRESS_P(X)   \
1129
  (    GET_CODE (X) == LABEL_REF  \
1130
   ||  GET_CODE (X) == SYMBOL_REF \
1131
   ||  GET_CODE (X) == CONST_INT  \
1132
   || (GET_CODE (X) == CONST      \
1133
       && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
1134
 
1135
/* Nonzero if the constant value X is a legitimate general operand.
1136
   We don't allow (plus symbol large-constant) as the relocations can't
1137
   describe it.  INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1138
   We allow all CONST_DOUBLE's as the md file patterns will force the
1139
   constant to memory if they can't handle them.  */
1140
 
1141
#define LEGITIMATE_CONSTANT_P(X)                                        \
1142
  (! (GET_CODE (X) == CONST                                             \
1143
      && GET_CODE (XEXP (X, 0)) == PLUS                                  \
1144
      && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF                   \
1145
      && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT                   \
1146
      && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1147
 
1148
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1149
   and check its validity for a certain class.
1150
   We have two alternate definitions for each of them.
1151
   The usual definition accepts all pseudo regs; the other rejects
1152
   them unless they have been allocated suitable hard regs.
1153
   The symbol REG_OK_STRICT causes the latter definition to be used.
1154
 
1155
   Most source files want to accept pseudo regs in the hope that
1156
   they will get allocated to the class that the insn wants them to be in.
1157
   Source files for reload pass need to be strict.
1158
   After reload, it makes no difference, since pseudo regs have
1159
   been eliminated by then.  */
1160
 
1161
#ifdef REG_OK_STRICT
1162
 
1163
/* Nonzero if X is a hard reg that can be used as a base reg.  */
1164
#define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1165
/* Nonzero if X is a hard reg that can be used as an index.  */
1166
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1167
 
1168
#else
1169
 
1170
/* Nonzero if X is a hard reg that can be used as a base reg
1171
   or if it is a pseudo reg.  */
1172
#define REG_OK_FOR_BASE_P(X)            \
1173
  (GPR_P (REGNO (X))                    \
1174
   || (REGNO (X)) == ARG_POINTER_REGNUM \
1175
   || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1176
/* Nonzero if X is a hard reg that can be used as an index
1177
   or if it is a pseudo reg.  */
1178
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1179
 
1180
#endif
1181
 
1182
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1183
   that is a valid memory address for an instruction.
1184
   The MODE argument is the machine mode for the MEM expression
1185
   that wants to use this address.  */
1186
 
1187
/* Local to this file.  */
1188
#define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1189
 
1190
/* Local to this file.  */
1191
#define RTX_OK_FOR_OFFSET_P(X) \
1192
  (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1193
 
1194
/* Local to this file.  */
1195
#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X)                    \
1196
  (GET_CODE (X) == PLUS                                         \
1197
   && RTX_OK_FOR_BASE_P (XEXP (X, 0))                            \
1198
   && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1199
 
1200
/* Local to this file.  */
1201
/* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1202
   since more than one instruction will be required.  */
1203
#define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X)                    \
1204
  (GET_CODE (X) == LO_SUM                                       \
1205
   && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
1206
   && RTX_OK_FOR_BASE_P (XEXP (X, 0))                            \
1207
   && CONSTANT_P (XEXP (X, 1)))
1208
 
1209
/* Local to this file.  */
1210
/* Is this a load and increment operation.  */
1211
#define LOAD_POSTINC_P(MODE, X)                                 \
1212
  (((MODE) == SImode || (MODE) == SFmode)                       \
1213
   && GET_CODE (X) == POST_INC                                  \
1214
   && GET_CODE (XEXP (X, 0)) == REG                              \
1215
   && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1216
 
1217
/* Local to this file.  */
1218
/* Is this an increment/decrement and store operation.  */
1219
#define STORE_PREINC_PREDEC_P(MODE, X)                          \
1220
  (((MODE) == SImode || (MODE) == SFmode)                       \
1221
   && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC)      \
1222
   && GET_CODE (XEXP (X, 0)) == REG                              \
1223
   && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1224
 
1225
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)                 \
1226
  do                                                            \
1227
    {                                                           \
1228
      if (RTX_OK_FOR_BASE_P (X))                                \
1229
        goto ADDR;                                              \
1230
      if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X)))            \
1231
        goto ADDR;                                              \
1232
      if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X)))            \
1233
        goto ADDR;                                              \
1234
      if (LOAD_POSTINC_P ((MODE), (X)))                         \
1235
        goto ADDR;                                              \
1236
      if (STORE_PREINC_PREDEC_P ((MODE), (X)))                  \
1237
        goto ADDR;                                              \
1238
    }                                                           \
1239
  while (0)
1240
 
1241
/* Try machine-dependent ways of modifying an illegitimate address
1242
   to be legitimate.  If we find one, return the new, valid address.
1243
   This macro is used in only one place: `memory_address' in explow.c.
1244
 
1245
   OLDX is the address as it was before break_out_memory_refs was called.
1246
   In some cases it is useful to look at this to decide what needs to be done.
1247
 
1248
   MODE and WIN are passed so that this macro can use
1249
   GO_IF_LEGITIMATE_ADDRESS.
1250
 
1251
   It is always safe for this macro to do nothing.  It exists to recognize
1252
   opportunities to optimize the output.  */
1253
 
1254
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)                   \
1255
  do                                                             \
1256
    {                                                            \
1257
      if (flag_pic)                                              \
1258
        (X) = m32r_legitimize_pic_address (X, NULL_RTX);         \
1259
      if (memory_address_p (MODE, X))                            \
1260
        goto WIN;                                                \
1261
    }                                                            \
1262
  while (0)
1263
 
1264
/* Go to LABEL if ADDR (a legitimate address expression)
1265
   has an effect that depends on the machine mode it is used for.  */
1266
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)               \
1267
  do                                                            \
1268
    {                                                           \
1269
      if (   GET_CODE (ADDR) == PRE_DEC                         \
1270
          || GET_CODE (ADDR) == PRE_INC                         \
1271
          || GET_CODE (ADDR) == POST_INC                        \
1272
          || GET_CODE (ADDR) == LO_SUM)                         \
1273
        goto LABEL;                                             \
1274
    }                                                           \
1275
  while (0)
1276
 
1277
/* Condition code usage.  */
1278
 
1279
/* Return nonzero if SELECT_CC_MODE will never return MODE for a
1280
   floating point inequality comparison.  */
1281
#define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1282
 
1283
/* Costs.  */
1284
 
1285
/* Compute extra cost of moving data between one register class
1286
   and another.  */
1287
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1288
 
1289
/* Compute the cost of moving data between registers and memory.  */
1290
/* Memory is 3 times as expensive as registers.
1291
   ??? Is that the right way to look at it?  */
1292
#define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1293
(GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1294
 
1295
/* The cost of a branch insn.  */
1296
/* A value of 2 here causes GCC to avoid using branches in comparisons like
1297
   while (a < N && a).  Branches aren't that expensive on the M32R so
1298
   we define this as 1.  Defining it as 2 had a heavy hit in fp-bit.c.  */
1299
#define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1300
 
1301
/* Nonzero if access to memory by bytes is slow and undesirable.
1302
   For RISC chips, it means that access to memory by bytes is no
1303
   better than access by words when possible, so grab a whole word
1304
   and maybe make use of that.  */
1305
#define SLOW_BYTE_ACCESS 1
1306
 
1307
/* Define this macro if it is as good or better to call a constant
1308
   function address than to call an address kept in a register.  */
1309
#define NO_FUNCTION_CSE
1310
 
1311
/* Section selection.  */
1312
 
1313
#define TEXT_SECTION_ASM_OP     "\t.section .text"
1314
#define DATA_SECTION_ASM_OP     "\t.section .data"
1315
#define BSS_SECTION_ASM_OP      "\t.section .bss"
1316
 
1317
/* Define this macro if jump tables (for tablejump insns) should be
1318
   output in the text section, along with the assembler instructions.
1319
   Otherwise, the readonly data section is used.
1320
   This macro is irrelevant if there is no separate readonly data section.  */
1321
#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1322
 
1323
/* Position Independent Code.  */
1324
 
1325
/* The register number of the register used to address a table of static
1326
   data addresses in memory.  In some cases this register is defined by a
1327
   processor's ``application binary interface'' (ABI).  When this macro
1328
   is defined, RTL is generated for this register once, as with the stack
1329
   pointer and frame pointer registers.  If this macro is not defined, it
1330
   is up to the machine-dependent files to allocate such a register (if
1331
   necessary).  */
1332
#define PIC_OFFSET_TABLE_REGNUM 12
1333
 
1334
/* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1335
   clobbered by calls.  Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1336
   is not defined.  */
1337
/* This register is call-saved on the M32R.  */
1338
/*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1339
 
1340
/* A C expression that is nonzero if X is a legitimate immediate
1341
   operand on the target machine when generating position independent code.
1342
   You can assume that X satisfies CONSTANT_P, so you need not
1343
   check this.  You can also assume `flag_pic' is true, so you need not
1344
   check it either.  You need not define this macro if all constants
1345
   (including SYMBOL_REF) can be immediate operands when generating
1346
   position independent code.  */
1347
#define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
1348
 
1349
/* Control the assembler format that we output.  */
1350
 
1351
/* A C string constant describing how to begin a comment in the target
1352
   assembler language.  The compiler assumes that the comment will
1353
   end at the end of the line.  */
1354
#define ASM_COMMENT_START ";"
1355
 
1356
/* Output to assembler file text saying following lines
1357
   may contain character constants, extra white space, comments, etc.  */
1358
#define ASM_APP_ON ""
1359
 
1360
/* Output to assembler file text saying following lines
1361
   no longer contain unusual constructs.  */
1362
#define ASM_APP_OFF ""
1363
 
1364
/* Globalizing directive for a label.  */
1365
#define GLOBAL_ASM_OP "\t.global\t"
1366
 
1367
/* We do not use DBX_LINES_FUNCTION_RELATIVE or
1368
   dbxout_stab_value_internal_label_diff here because
1369
   we need to use .debugsym for the line label.  */
1370
 
1371
#define DBX_OUTPUT_SOURCE_LINE(file, line, counter)                     \
1372
  do                                                                    \
1373
    {                                                                   \
1374
      const char * begin_label =                                        \
1375
        XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);             \
1376
      char label[64];                                                   \
1377
      ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter);               \
1378
                                                                        \
1379
      dbxout_begin_stabn_sline (line);                                  \
1380
      assemble_name (file, label);                                      \
1381
      putc ('-', file);                                                 \
1382
      assemble_name (file, begin_label);                                \
1383
      fputs ("\n\t.debugsym ", file);                                   \
1384
      assemble_name (file, label);                                      \
1385
      putc ('\n', file);                                                \
1386
      counter += 1;                                                     \
1387
     }                                                                  \
1388
  while (0)
1389
 
1390
/* How to refer to registers in assembler output.
1391
   This sequence is indexed by compiler's hard-register-number (see above).  */
1392
#ifndef SUBTARGET_REGISTER_NAMES
1393
#define SUBTARGET_REGISTER_NAMES
1394
#endif
1395
 
1396
#define REGISTER_NAMES                                  \
1397
{                                                       \
1398
  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",       \
1399
  "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",    \
1400
  "ap", "cbit", "a0"                                    \
1401
  SUBTARGET_REGISTER_NAMES                              \
1402
}
1403
 
1404
/* If defined, a C initializer for an array of structures containing
1405
   a name and a register number.  This macro defines additional names
1406
   for hard registers, thus allowing the `asm' option in declarations
1407
   to refer to registers using alternate names.  */
1408
#ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1409
#define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1410
#endif
1411
 
1412
#define ADDITIONAL_REGISTER_NAMES       \
1413
{                                       \
1414
  /*{ "gp", GP_REGNUM },*/              \
1415
  { "r13", FRAME_POINTER_REGNUM },      \
1416
  { "r14", RETURN_ADDR_REGNUM },        \
1417
  { "r15", STACK_POINTER_REGNUM },      \
1418
  SUBTARGET_ADDITIONAL_REGISTER_NAMES   \
1419
}
1420
 
1421
/* A C expression which evaluates to true if CODE is a valid
1422
   punctuation character for use in the `PRINT_OPERAND' macro.  */
1423
extern char m32r_punct_chars[256];
1424
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1425
  m32r_punct_chars[(unsigned char) (CHAR)]
1426
 
1427
/* Print operand X (an rtx) in assembler syntax to file FILE.
1428
   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1429
   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
1430
#define PRINT_OPERAND(FILE, X, CODE) \
1431
  m32r_print_operand (FILE, X, CODE)
1432
 
1433
/* A C compound statement to output to stdio stream STREAM the
1434
   assembler syntax for an instruction operand that is a memory
1435
   reference whose address is ADDR.  ADDR is an RTL expression.  */
1436
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1437
  m32r_print_operand_address (FILE, ADDR)
1438
 
1439
/* If defined, C string expressions to be used for the `%R', `%L',
1440
   `%U', and `%I' options of `asm_fprintf' (see `final.c').  These
1441
   are useful when a single `md' file must support multiple assembler
1442
   formats.  In that case, the various `tm.h' files can define these
1443
   macros differently.  */
1444
#define REGISTER_PREFIX         ""
1445
#define LOCAL_LABEL_PREFIX      ".L"
1446
#define USER_LABEL_PREFIX       ""
1447
#define IMMEDIATE_PREFIX        "#"
1448
 
1449
/* This is how to output an element of a case-vector that is absolute.  */
1450
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)            \
1451
   do                                                   \
1452
     {                                                  \
1453
       char label[30];                                  \
1454
       ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1455
       fprintf (FILE, "\t.word\t");                     \
1456
       assemble_name (FILE, label);                     \
1457
       fprintf (FILE, "\n");                            \
1458
     }                                                  \
1459
  while (0)
1460
 
1461
/* This is how to output an element of a case-vector that is relative.  */
1462
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1463
  do                                                    \
1464
    {                                                   \
1465
      char label[30];                                   \
1466
      ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);  \
1467
      fprintf (FILE, "\t.word\t");                      \
1468
      assemble_name (FILE, label);                      \
1469
      fprintf (FILE, "-");                              \
1470
      ASM_GENERATE_INTERNAL_LABEL (label, "L", REL);    \
1471
      assemble_name (FILE, label);                      \
1472
      fprintf (FILE, "\n");                             \
1473
    }                                                   \
1474
  while (0)
1475
 
1476
/* The desired alignment for the location counter at the beginning
1477
   of a loop.  */
1478
/* On the M32R, align loops to 32 byte boundaries (cache line size)
1479
   if -malign-loops.  */
1480
#define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1481
 
1482
/* Define this to be the maximum number of insns to move around when moving
1483
   a loop test from the top of a loop to the bottom
1484
   and seeing whether to duplicate it.  The default is thirty.
1485
 
1486
   Loop unrolling currently doesn't like this optimization, so
1487
   disable doing if we are unrolling loops and saving space.  */
1488
#define LOOP_TEST_THRESHOLD (optimize_size                              \
1489
                             && !flag_unroll_loops                      \
1490
                             && !flag_unroll_all_loops ? 2 : 30)
1491
 
1492
/* This is how to output an assembler line
1493
   that says to advance the location counter
1494
   to a multiple of 2**LOG bytes.  */
1495
/* .balign is used to avoid confusion.  */
1496
#define ASM_OUTPUT_ALIGN(FILE,LOG)                      \
1497
  do                                                    \
1498
    {                                                   \
1499
      if ((LOG) != 0)                                    \
1500
        fprintf (FILE, "\t.balign %d\n", 1 << (LOG));   \
1501
    }                                                   \
1502
  while (0)
1503
 
1504
/* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1505
   separate, explicit argument.  If you define this macro, it is used in
1506
   place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1507
   handling the required alignment of the variable.  The alignment is
1508
   specified as the number of bits.  */
1509
 
1510
#define SCOMMON_ASM_OP "\t.scomm\t"
1511
 
1512
#undef  ASM_OUTPUT_ALIGNED_COMMON
1513
#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)              \
1514
  do                                                                    \
1515
    {                                                                   \
1516
      if (! TARGET_SDATA_NONE                                           \
1517
          && (SIZE) > 0 && (SIZE) <= g_switch_value)                     \
1518
        fprintf ((FILE), "%s", SCOMMON_ASM_OP);                         \
1519
      else                                                              \
1520
        fprintf ((FILE), "%s", COMMON_ASM_OP);                          \
1521
      assemble_name ((FILE), (NAME));                                   \
1522
      fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
1523
    }                                                                   \
1524
  while (0)
1525
 
1526
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)           \
1527
  do                                                                    \
1528
    {                                                                   \
1529
      if (! TARGET_SDATA_NONE                                           \
1530
          && (SIZE) > 0 && (SIZE) <= g_switch_value)                     \
1531
        switch_to_section (get_named_section (NULL, ".sbss", 0));        \
1532
      else                                                              \
1533
        switch_to_section (bss_section);                                \
1534
      ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT));      \
1535
      last_assemble_variable_decl = DECL;                               \
1536
      ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL);                       \
1537
      ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1);                          \
1538
    }                                                                   \
1539
  while (0)
1540
 
1541
/* Debugging information.  */
1542
 
1543
/* Generate DBX and DWARF debugging information.  */
1544
#define DBX_DEBUGGING_INFO    1
1545
#define DWARF2_DEBUGGING_INFO 1
1546
 
1547
/* Use DWARF2 debugging info by default.  */
1548
#undef  PREFERRED_DEBUGGING_TYPE
1549
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1550
 
1551
/* Turn off splitting of long stabs.  */
1552
#define DBX_CONTIN_LENGTH 0
1553
 
1554
/* Miscellaneous.  */
1555
 
1556
/* Specify the machine mode that this machine uses
1557
   for the index in the tablejump instruction.  */
1558
#define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1559
 
1560
/* Define if operations between registers always perform the operation
1561
   on the full register even if a narrower mode is specified.  */
1562
#define WORD_REGISTER_OPERATIONS
1563
 
1564
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1565
   will either zero-extend or sign-extend.  The value of this macro should
1566
   be the code that says which one of the two operations is implicitly
1567
   done, UNKNOWN if none.  */
1568
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1569
 
1570
/* Max number of bytes we can move from memory
1571
   to memory in one reasonably fast instruction.  */
1572
#define MOVE_MAX 4
1573
 
1574
/* Define this to be nonzero if shift instructions ignore all but the low-order
1575
   few bits.  */
1576
#define SHIFT_COUNT_TRUNCATED 1
1577
 
1578
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1579
   is done just by pretending it is already truncated.  */
1580
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1581
 
1582
/* Specify the machine mode that pointers have.
1583
   After generation of rtl, the compiler makes no further distinction
1584
   between pointers and any other objects of this machine mode.  */
1585
/* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
1586
   its own problems (you have to add extendpsisi2 and truncsipsi2).
1587
   Try to avoid it.  */
1588
#define Pmode SImode
1589
 
1590
/* A function address in a call instruction.  */
1591
#define FUNCTION_MODE SImode
1592
 
1593
/* Define the information needed to generate branch and scc insns.  This is
1594
   stored from the compare operation.  Note that we can't use "rtx" here
1595
   since it hasn't been defined!  */
1596
extern struct rtx_def * m32r_compare_op0;
1597
extern struct rtx_def * m32r_compare_op1;
1598
 
1599
/* M32R function types.  */
1600
enum m32r_function_type
1601
{
1602
  M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
1603
};
1604
 
1605
#define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1606
 
1607
/* The maximum number of bytes to copy using pairs of load/store instructions.
1608
   If a block is larger than this then a loop will be generated to copy
1609
   MAX_MOVE_BYTES chunks at a time.  The value of 32 is a semi-arbitrary choice.
1610
   A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
1611
   string copy in it.  */
1612
#define MAX_MOVE_BYTES 32

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