Subversion Repositories openrisc

;; Machine description of the Renesas M32R cpu for GNU C compiler

;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004, 2005, 2007

;; Free Software Foundation, Inc.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it

;; under the terms of the GNU General Public License as published

;; by the Free Software Foundation; either version 3, or (at your

;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT

;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

;; License for more details.

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING3.  If not see

;; .

;; See file "rtl.def" for documentation on define_insn, match_*, et. al.

;; UNSPEC_VOLATILE usage

(define_constants

  [(UNSPECV_BLOCKAGE            0)

   (UNSPECV_FLUSH_ICACHE        1)])

;; UNSPEC usage

(define_constants

  [(UNSPEC_LOAD_SDA_BASE        2)

   (UNSPEC_SET_CBIT             3)

   (UNSPEC_PIC_LOAD_ADDR        4)

   (UNSPEC_GET_PC               5)

   (UNSPEC_GOTOFF               6)

   ])

;; Insn type.  Used to default other attribute values.

(define_attr "type"

  "int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"

  (const_string "misc"))

;; Length in bytes.

(define_attr "length" ""

  (cond [(eq_attr "type" "int2,load2,store2,shift2,mul2")

         (const_int 2)

         (eq_attr "type" "int4,load4,store4,shift4,div4")

         (const_int 4)

         (eq_attr "type" "multi")

         (const_int 8)

         (eq_attr "type" "uncond_branch,branch,call")

         (const_int 4)]

         (const_int 4)))

;; The length here is the length of a single asm.  Unfortunately it might be

;; 2 or 4 so we must allow for 4.  That's ok though.

(define_asm_attributes

  [(set_attr "length" "4")

   (set_attr "type" "multi")])

;; Whether an instruction is short (16-bit) or long (32-bit).

(define_attr "insn_size" "short,long"

  (if_then_else (eq_attr "type" "int2,load2,store2,shift2,mul2")

                (const_string "short")

                (const_string "long")))

;; The target CPU we're compiling for.

(define_attr "cpu" "m32r,m32r2,m32rx"

  (cond [(ne (symbol_ref "TARGET_M32RX") (const_int 0))

             (const_string "m32rx")

         (ne (symbol_ref "TARGET_M32R2") (const_int 0))

             (const_string "m32r2")]

    (const_string "m32r")))

;; Defines the pipeline where an instruction can be executed on.

;; For the M32R, a short instruction can execute one of the two pipes.

;; For the M32Rx, the restrictions are modelled in the second

;;  condition of this attribute definition.

(define_attr "m32r_pipeline" "either,s,o,long"

  (cond [(and (eq_attr "cpu" "m32r")

              (eq_attr "insn_size" "short"))

             (const_string "either")

         (eq_attr "insn_size" "!short")

             (const_string "long")]

         (cond [(eq_attr "type" "int2")

                   (const_string "either")

                (eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")

                   (const_string "o")

                (eq_attr "type" "mul2")

                   (const_string "s")]

         (const_string "long"))))

;; ::::::::::::::::::::

;; ::

;; :: Pipeline description

;; ::

;; ::::::::::::::::::::

;; This model is based on Chapter 2, Appendix 3 and Appendix 4 of the

;; "M32R-FPU Software Manual", Revision 1.01, plus additional information

;; obtained by our best friend and mine, Google.

;;

;; The pipeline is modelled as a fetch unit, and a core with a memory unit,

;; two execution units, where "fetch" models IF and D, "memory" for MEM1

;; and MEM2, and "EXEC" for E, E1, E2, EM, and EA.  Writeback and

;; bypasses are not modelled.

(define_automaton "m32r")

;; We pretend there are two short (16 bits) instruction fetchers.  The

;; "s" short fetcher cannot be reserved until the "o" short fetcher is

;; reserved.  Some instructions reserve both the left and right fetchers.

;; These fetch units are a hack to get GCC to better pack the instructions

;; for the M32Rx processor, which has two execution pipes.

;;

;; In reality there is only one decoder, which can decode either two 16 bits

;; instructions, or a single 32 bits instruction.

;;

;; Note, "fetch" models both the IF and the D pipeline stages.

;;

;; The m32rx core has two execution pipes.  We name them o_E and s_E.

;; In addition, there's a memory unit.

(define_cpu_unit "o_IF,s_IF,o_E,s_E,memory" "m32r")

;; Prevent the s pipe from being reserved before the o pipe.

(absence_set "s_IF" "o_IF")

(absence_set "s_E"  "o_E")

;; On the M32Rx, long instructions execute on both pipes, so reserve

;; both fetch slots and both pipes.

(define_reservation "long_IF" "o_IF+s_IF")

(define_reservation "long_E" "o_E+s_E")

;; ::::::::::::::::::::

;; Simple instructions do 4 stages: IF D E WB.  WB is not modelled.

;; Hence, ready latency is 1.

(define_insn_reservation "short_left" 1

  (and (eq_attr "m32r_pipeline" "o")

       (and (eq_attr "insn_size" "short")

            (eq_attr "type" "!load2")))

  "o_IF,o_E")

(define_insn_reservation "short_right" 1

  (and (eq_attr "m32r_pipeline" "s")

       (and (eq_attr "insn_size" "short")

            (eq_attr "type" "!load2")))

  "s_IF,s_E")

(define_insn_reservation "short_either" 1

  (and (eq_attr "m32r_pipeline" "either")

       (and (eq_attr "insn_size" "short")

            (eq_attr "type" "!load2")))

  "o_IF|s_IF,o_E|s_E")

(define_insn_reservation "long_m32r" 1

  (and (eq_attr "cpu" "m32r")

       (and (eq_attr "insn_size" "long")

            (eq_attr "type" "!load4,load8")))

  "long_IF,long_E")

(define_insn_reservation "long_m32rx" 2

  (and (eq_attr "m32r_pipeline" "long")

       (and (eq_attr "insn_size" "long")

            (eq_attr "type" "!load4,load8")))

  "long_IF,long_E")

;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB.

;; MEM1 may require more than one cycle depending on locality.  We

;; optimistically assume all memory is nearby, i.e. MEM1 takes only

;; one cycle.  Hence, ready latency is 3.

;; The M32Rx can do short load/store only on the left pipe.

(define_insn_reservation "short_load_left" 3

  (and (eq_attr "m32r_pipeline" "o")

       (and (eq_attr "insn_size" "short")

            (eq_attr "type" "load2")))

  "o_IF,o_E,memory*2")

(define_insn_reservation "short_load" 3

  (and (eq_attr "m32r_pipeline" "either")

       (and (eq_attr "insn_size" "short")

            (eq_attr "type" "load2")))

  "s_IF|o_IF,s_E|o_E,memory*2")

(define_insn_reservation "long_load" 3

  (and (eq_attr "cpu" "m32r")

       (and (eq_attr "insn_size" "long")

            (eq_attr "type" "load4,load8")))

  "long_IF,long_E,memory*2")

(define_insn_reservation "long_load_m32rx" 3

  (and (eq_attr "m32r_pipeline" "long")

       (eq_attr "type" "load4,load8"))

  "long_IF,long_E,memory*2")

(include "predicates.md")

;; Expand prologue as RTL

(define_expand "prologue"

  [(const_int 1)]

  ""

  "

{

  m32r_expand_prologue ();

  DONE;

}")

;; Move instructions.

;;

;; For QI and HI moves, the register must contain the full properly

;; sign-extended value.  nonzero_bits assumes this [otherwise

;; SHORT_IMMEDIATES_SIGN_EXTEND must be used, but the comment for it

;; says it's a kludge and the .md files should be fixed instead].

(define_expand "movqi"

  [(set (match_operand:QI 0 "general_operand" "")

        (match_operand:QI 1 "general_operand" ""))]

  ""

  "

{

  /* Fixup PIC cases.  */

  if (flag_pic)

    {

      if (symbolic_operand (operands[1], QImode))

        {

          if (reload_in_progress || reload_completed)

            operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);

          else

            operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);

        }

    }

  /* Everything except mem = const or mem = mem can be done easily.

     Objects in the small data area are handled too.  */

  if (GET_CODE (operands[0]) == MEM)

    operands[1] = force_reg (QImode, operands[1]);

}")

(define_insn "*movqi_insn"

  [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m")

        (match_operand:QI 1 "move_src_operand" "r,I,JQR,T,m,r,r"))]

  "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)"

  "@

   mv %0,%1

   ldi %0,%#%1

   ldi %0,%#%1

   ldub %0,%1

   ldub %0,%1

   stb %1,%0

   stb %1,%0"

  [(set_attr "type" "int2,int2,int4,load2,load4,store2,store4")

   (set_attr "length" "2,2,4,2,4,2,4")])

(define_expand "movhi"

  [(set (match_operand:HI 0 "general_operand" "")

        (match_operand:HI 1 "general_operand" ""))]

  ""

  "

{

  /* Fixup PIC cases.  */

  if (flag_pic)

    {

      if (symbolic_operand (operands[1], HImode))

        {

          if (reload_in_progress || reload_completed)

            operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);

          else

            operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);

        }

    }

  /* Everything except mem = const or mem = mem can be done easily.  */

  if (GET_CODE (operands[0]) == MEM)

    operands[1] = force_reg (HImode, operands[1]);

}")

(define_insn "*movhi_insn"

  [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m")

        (match_operand:HI 1 "move_src_operand" "r,I,JQR,K,T,m,r,r"))]

  "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)"

  "@

   mv %0,%1

   ldi %0,%#%1

   ldi %0,%#%1

   ld24 %0,%#%1

   lduh %0,%1

   lduh %0,%1

   sth %1,%0

   sth %1,%0"

  [(set_attr "type" "int2,int2,int4,int4,load2,load4,store2,store4")

   (set_attr "length" "2,2,4,4,2,4,2,4")])

(define_expand "movsi_push"

  [(set (mem:SI (pre_dec:SI (match_operand:SI 0 "register_operand" "")))

        (match_operand:SI 1 "register_operand" ""))]

  ""

  "")

(define_expand "movsi_pop"

  [(set (match_operand:SI 0 "register_operand" "")

        (mem:SI (post_inc:SI (match_operand:SI 1 "register_operand" ""))))]

  ""

  "")

(define_expand "movsi"

  [(set (match_operand:SI 0 "general_operand" "")

        (match_operand:SI 1 "general_operand" ""))]

  ""

  "

{

  /* Fixup PIC cases.  */

  if (flag_pic)

    {

      if (symbolic_operand (operands[1], SImode))

        {

          if (reload_in_progress || reload_completed)

            operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);

          else

            operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);

        }

    }

  /* Everything except mem = const or mem = mem can be done easily.  */

  if (GET_CODE (operands[0]) == MEM)

    operands[1] = force_reg (SImode, operands[1]);

  /* Small Data Area reference?  */

  if (small_data_operand (operands[1], SImode))

    {

      emit_insn (gen_movsi_sda (operands[0], operands[1]));

      DONE;

    }

  /* If medium or large code model, symbols have to be loaded with

     seth/add3.  */

  if (addr32_operand (operands[1], SImode))

    {

      emit_insn (gen_movsi_addr32 (operands[0], operands[1]));

      DONE;

    }

}")

;; ??? Do we need a const_double constraint here for large unsigned values?

(define_insn "*movsi_insn"

  [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")

        (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]

  "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"

  "*

{

  if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG)

    {

      switch (GET_CODE (operands[1]))

        {

          HOST_WIDE_INT value;

          default:

            break;

          case REG:

          case SUBREG:

            return \"mv %0,%1\";

          case MEM:

            if (GET_CODE (XEXP (operands[1], 0)) == POST_INC

                && XEXP (XEXP (operands[1], 0), 0) == stack_pointer_rtx)

              return \"pop %0\";

            return \"ld %0,%1\";

          case CONST_INT:

            value = INTVAL (operands[1]);

            if (INT16_P (value))

              return \"ldi %0,%#%1\\t; %X1\";

            if (UINT24_P (value))

              return \"ld24 %0,%#%1\\t; %X1\";

            if (UPPER16_P (value))

              return \"seth %0,%#%T1\\t; %X1\";

            return \"#\";

          case CONST:

          case SYMBOL_REF:

          case LABEL_REF:

            if (TARGET_ADDR24)

              return \"ld24 %0,%#%1\";

            return \"#\";

        }

    }

  else if (GET_CODE (operands[0]) == MEM

           && (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG))

    {

      if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC

          && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)

        return \"push %1\";

      return \"st %1,%0\";

    }

  gcc_unreachable ();

}"

  [(set_attr "type" "int2,int2,int4,int4,int4,multi,load2,load2,load4,store2,store2,store4")

   (set_attr "length" "2,2,4,4,4,8,2,2,4,2,2,4")])

; Try to use a four byte / two byte pair for constants not loadable with

; ldi, ld24, seth.

(define_split

 [(set (match_operand:SI 0 "register_operand" "")

       (match_operand:SI 1 "two_insn_const_operand" ""))]

  ""

  [(set (match_dup 0) (match_dup 2))

   (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]

  "

{

  unsigned HOST_WIDE_INT val = INTVAL (operands[1]);

  unsigned HOST_WIDE_INT tmp;

  int shift;

  /* In all cases we will emit two instructions.  However we try to

     use 2 byte instructions wherever possible.  We can assume the

     constant isn't loadable with any of ldi, ld24, or seth.  */

  /* See if we can load a 24 bit unsigned value and invert it.  */

  if (UINT24_P (~ val))

    {

      emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));

      emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));

      DONE;

    }

  /* See if we can load a 24 bit unsigned value and shift it into place.

     0x01fffffe is just beyond ld24's range.  */

  for (shift = 1, tmp = 0x01fffffe;

       shift < 8;

       ++shift, tmp <<= 1)

    {

      if ((val & ~tmp) == 0)

        {

          emit_insn (gen_movsi (operands[0], GEN_INT (val >> shift)));

          emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (shift)));

          DONE;

        }

    }

  /* Can't use any two byte insn, fall back to seth/or3.  Use ~0xffff instead

     of 0xffff0000, since the later fails on a 64-bit host.  */

  operands[2] = GEN_INT ((val) & ~0xffff);

  operands[3] = GEN_INT ((val) & 0xffff);

}")

(define_split

  [(set (match_operand:SI 0 "register_operand" "")

        (match_operand:SI 1 "seth_add3_operand" ""))]

  "TARGET_ADDR32"

  [(set (match_dup 0)

        (high:SI (match_dup 1)))

   (set (match_dup 0)

        (lo_sum:SI (match_dup 0)

                   (match_dup 1)))]

  "")

;; Small data area support.

;; The address of _SDA_BASE_ is loaded into a register and all objects in

;; the small data area are indexed off that.  This is done for each reference

;; but cse will clean things up for us.  We let the compiler choose the

;; register to use so we needn't allocate (and maybe even fix) a special

;; register to use.  Since the load and store insns have a 16 bit offset the

;; total size of the data area can be 64K.  However, if the data area lives

;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which

;; would then yield 3 instructions to reference an object [though there would

;; be no net loss if two or more objects were referenced].  The 3 insns can be

;; reduced back to 2 if the size of the small data area were reduced to 32K

;; [then seth + ld/st would work for any object in the area].  Doing this

;; would require special handling of _SDA_BASE_ (its value would be

;; (.sdata + 32K) & 0xffff0000) and reloc computations would be different

;; [I think].  What to do about this is deferred until later and for now we

;; require .sdata to be in the first 16M.

(define_expand "movsi_sda"

  [(set (match_dup 2)

        (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))

   (set (match_operand:SI 0 "register_operand" "")

        (lo_sum:SI (match_dup 2)

                   (match_operand:SI 1 "small_data_operand" "")))]

  ""

  "

{

  if (reload_in_progress || reload_completed)

    operands[2] = operands[0];

  else

    operands[2] = gen_reg_rtx (SImode);

}")

(define_insn "*load_sda_base_32"

  [(set (match_operand:SI 0 "register_operand" "=r")

        (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]

  "TARGET_ADDR32"

  "seth %0,%#shigh(_SDA_BASE_)\;add3 %0,%0,%#low(_SDA_BASE_)"

  [(set_attr "type" "multi")

   (set_attr "length" "8")])

(define_insn "*load_sda_base"

  [(set (match_operand:SI 0 "register_operand" "=r")

        (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]

  ""

  "ld24 %0,#_SDA_BASE_"

  [(set_attr "type" "int4")

   (set_attr "length" "4")])

;; 32 bit address support.

(define_expand "movsi_addr32"

  [(set (match_dup 2)

        ; addr32_operand isn't used because it's too restrictive,

        ; seth_add3_operand is more general and thus safer.

        (high:SI (match_operand:SI 1 "seth_add3_operand" "")))

   (set (match_operand:SI 0 "register_operand" "")

        (lo_sum:SI (match_dup 2) (match_dup 1)))]

  ""

  "

{

  if (reload_in_progress || reload_completed)

    operands[2] = operands[0];

  else

    operands[2] = gen_reg_rtx (SImode);

}")

(define_insn "set_hi_si"

  [(set (match_operand:SI 0 "register_operand" "=r")

        (high:SI (match_operand 1 "symbolic_operand" "")))]

  ""

  "seth %0,%#shigh(%1)"

  [(set_attr "type" "int4")

   (set_attr "length" "4")])

(define_insn "lo_sum_si"

  [(set (match_operand:SI 0 "register_operand" "=r")

        (lo_sum:SI (match_operand:SI 1 "register_operand" "r")

                   (match_operand:SI 2 "immediate_operand" "in")))]

  ""

  "add3 %0,%1,%#%B2"

  [(set_attr "type" "int4")

   (set_attr "length" "4")])

(define_expand "movdi"

  [(set (match_operand:DI 0 "general_operand" "")

        (match_operand:DI 1 "general_operand" ""))]

  ""

  "

{

  /* Fixup PIC cases.  */

  if (flag_pic)

    {

      if (symbolic_operand (operands[1], DImode))

        {

          if (reload_in_progress || reload_completed)

            operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);

          else

            operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);

        }

    }

  /* Everything except mem = const or mem = mem can be done easily.  */

  if (GET_CODE (operands[0]) == MEM)

    operands[1] = force_reg (DImode, operands[1]);

}")

(define_insn "*movdi_insn"

  [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m")

        (match_operand:DI 1 "move_double_src_operand" "r,nG,F,m,r"))]

  "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"

  "#"

  [(set_attr "type" "multi,multi,multi,load8,store8")

   (set_attr "length" "4,4,16,6,6")])

(define_split

  [(set (match_operand:DI 0 "move_dest_operand" "")

        (match_operand:DI 1 "move_double_src_operand" ""))]

  "reload_completed"

  [(match_dup 2)]

  "operands[2] = gen_split_move_double (operands);")

;; Floating point move insns.

(define_expand "movsf"

  [(set (match_operand:SF 0 "general_operand" "")

        (match_operand:SF 1 "general_operand" ""))]

  ""

  "

{

  /* Fixup PIC cases.  */

  if (flag_pic)

    {

      if (symbolic_operand (operands[1], SFmode))

        {

          if (reload_in_progress || reload_completed)

            operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);

          else

            operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);

        }

    }

  /* Everything except mem = const or mem = mem can be done easily.  */

  if (GET_CODE (operands[0]) == MEM)

    operands[1] = force_reg (SFmode, operands[1]);

}")

(define_insn "*movsf_insn"

  [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")

        (match_operand:SF 1 "move_src_operand" "r,F,U,S,m,r,r,r"))]

  "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"

  "@

   mv %0,%1

   #

   ld %0,%1

   ld %0,%1

   ld %0,%1

   st %1,%0

   st %1,%0

   st %1,%0"

  ;; ??? Length of alternative 1 is either 2, 4 or 8.

  [(set_attr "type" "int2,multi,load2,load2,load4,store2,store2,store4")

   (set_attr "length" "2,8,2,2,4,2,2,4")])

(define_split

  [(set (match_operand:SF 0 "register_operand" "")

        (match_operand:SF 1 "const_double_operand" ""))]

  "reload_completed"

  [(set (match_dup 2) (match_dup 3))]

  "

{

  operands[2] = operand_subword (operands[0], 0, 0, SFmode);

  operands[3] = operand_subword (operands[1], 0, 0, SFmode);

}")

(define_expand "movdf"

  [(set (match_operand:DF 0 "general_operand" "")

        (match_operand:DF 1 "general_operand" ""))]

  ""

  "

{

  /* Fixup PIC cases.  */

  if (flag_pic)

    {

      if (symbolic_operand (operands[1], DFmode))

        {

          if (reload_in_progress || reload_completed)

            operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);

          else

            operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);

        }

    }

  /* Everything except mem = const or mem = mem can be done easily.  */

  if (GET_CODE (operands[0]) == MEM)

    operands[1] = force_reg (DFmode, operands[1]);

}")

(define_insn "*movdf_insn"

  [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")

        (match_operand:DF 1 "move_double_src_operand" "r,F,m,r"))]

  "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"

  "#"

  [(set_attr "type" "multi,multi,load8,store8")

   (set_attr "length" "4,16,6,6")])

(define_split

  [(set (match_operand:DF 0 "move_dest_operand" "")

        (match_operand:DF 1 "move_double_src_operand" ""))]

  "reload_completed"

  [(match_dup 2)]

  "operands[2] = gen_split_move_double (operands);")

;; Zero extension instructions.

(define_insn "zero_extendqihi2"

  [(set (match_operand:HI 0 "register_operand" "=r,r,r")

        (zero_extend:HI (match_operand:QI 1 "extend_operand" "r,T,m")))]

  ""

  "@

   and3 %0,%1,%#255

   ldub %0,%1

   ldub %0,%1"

  [(set_attr "type" "int4,load2,load4")

   (set_attr "length" "4,2,4")])

(define_insn "zero_extendqisi2"

  [(set (match_operand:SI 0 "register_operand" "=r,r,r")

        (zero_extend:SI (match_operand:QI 1 "extend_operand" "r,T,m")))]

  ""

  "@

   and3 %0,%1,%#255

   ldub %0,%1

   ldub %0,%1"

  [(set_attr "type" "int4,load2,load4")

   (set_attr "length" "4,2,4")])

(define_insn "zero_extendhisi2"

  [(set (match_operand:SI 0 "register_operand" "=r,r,r")

        (zero_extend:SI (match_operand:HI 1 "extend_operand" "r,T,m")))]

  ""

  "@

   and3 %0,%1,%#65535

   lduh %0,%1

   lduh %0,%1"

  [(set_attr "type" "int4,load2,load4")

   (set_attr "length" "4,2,4")])

;; Signed conversions from a smaller integer to a larger integer

(define_insn "extendqihi2"

  [(set (match_operand:HI 0 "register_operand" "=r,r,r")

        (sign_extend:HI (match_operand:QI 1 "extend_operand" "0,T,m")))]

  ""

  "@

    #

    ldb %0,%1

    ldb %0,%1"

  [(set_attr "type" "multi,load2,load4")

   (set_attr "length" "2,2,4")])

(define_split

  [(set (match_operand:HI 0 "register_operand" "")

        (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]

  "reload_completed"

  [(match_dup 2)

   (match_dup 3)]

  "

{

  rtx op0   = gen_lowpart (SImode, operands[0]);

  rtx shift = GEN_INT (24);

  operands[2] = gen_ashlsi3 (op0, op0, shift);

  operands[3] = gen_ashrsi3 (op0, op0, shift);

}")

(define_insn "extendqisi2"

  [(set (match_operand:SI 0 "register_operand" "=r,r,r")

        (sign_extend:SI (match_operand:QI 1 "extend_operand" "0,T,m")))]

  ""

  "@

    #

    ldb %0,%1

    ldb %0,%1"

  [(set_attr "type" "multi,load2,load4")

   (set_attr "length" "4,2,4")])

(define_split

  [(set (match_operand:SI 0 "register_operand" "")

        (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]

  "reload_completed"

  [(match_dup 2)

   (match_dup 3)]

  "

{

  rtx shift = GEN_INT (24);

  operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);

  operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);

}")

(define_insn "extendhisi2"

  [(set (match_operand:SI 0 "register_operand" "=r,r,r")

        (sign_extend:SI (match_operand:HI 1 "extend_operand" "0,T,m")))]

  ""

  "@

    #

    ldh %0,%1

    ldh %0,%1"

  [(set_attr "type" "multi,load2,load4")

   (set_attr "length" "4,2,4")])

(define_split

  [(set (match_operand:SI 0 "register_operand" "")

        (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]

  "reload_completed"

  [(match_dup 2)

   (match_dup 3)]

  "

{

  rtx shift = GEN_INT (16);

  operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);

  operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);

}")

;; Arithmetic instructions.

; ??? Adding an alternative to split add3 of small constants into two

; insns yields better instruction packing but slower code.  Adds of small

; values is done a lot.

(define_insn "addsi3"

  [(set (match_operand:SI 0 "register_operand" "=r,r,r")

        (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")

                 (match_operand:SI 2 "nonmemory_operand" "r,I,J")))]

  ""

  "@

   add %0,%2

   addi %0,%#%2

   add3 %0,%1,%#%2"

  [(set_attr "type" "int2,int2,int4")

   (set_attr "length" "2,2,4")])

;(define_split

;  [(set (match_operand:SI 0 "register_operand" "")

;       (plus:SI (match_operand:SI 1 "register_operand" "")

;                (match_operand:SI 2 "int8_operand" "")))]

;  "reload_completed

;   && REGNO (operands[0]) != REGNO (operands[1])

;   && INT8_P (INTVAL (operands[2]))

;   && INTVAL (operands[2]) != 0"

;  [(set (match_dup 0) (match_dup 1))

;   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]

;  "")

(define_insn "adddi3"

  [(set (match_operand:DI 0 "register_operand" "=r")

        (plus:DI (match_operand:DI 1 "register_operand" "%0")

                 (match_operand:DI 2 "register_operand" "r")))

   (clobber (reg:CC 17))]

  ""

  "#"

  [(set_attr "type" "multi")

   (set_attr "length" "6")])

;; ??? The cmp clears the condition bit.  Can we speed up somehow?

(define_split

  [(set (match_operand:DI 0 "register_operand" "")

        (plus:DI (match_operand:DI 1 "register_operand" "")

                 (match_operand:DI 2 "register_operand" "")))

   (clobber (reg:CC 17))]

  "reload_completed"

  [(parallel [(set (reg:CC 17)

                   (const_int 0))

              (use (match_dup 4))])

   (parallel [(set (match_dup 4)

                   (plus:SI (match_dup 4)

                            (plus:SI (match_dup 5)

                                     (ne:SI (reg:CC 17) (const_int 0)))))

              (set (reg:CC 17)

                   (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])

   (parallel [(set (match_dup 6)

                   (plus:SI (match_dup 6)

                            (plus:SI (match_dup 7)

                                     (ne:SI (reg:CC 17) (const_int 0)))))

              (set (reg:CC 17)

                   (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]

  "

{

  operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);

  operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);

  operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);

  operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);

}")

(define_insn "*clear_c"

  [(set (reg:CC 17)

        (const_int 0))

   (use (match_operand:SI 0 "register_operand" "r"))]

  ""

  "cmp %0,%0"

  [(set_attr "type" "int2")

   (set_attr "length" "2")])

(define_insn "*add_carry"

  [(set (match_operand:SI 0 "register_operand" "=r")

        (plus:SI (match_operand:SI 1 "register_operand" "%0")

                 (plus:SI (match_operand:SI 2 "register_operand" "r")

                          (ne:SI (reg:CC 17) (const_int 0)))))

   (set (reg:CC 17)

        (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]

  ""

  "addx %0,%2"

  [(set_attr "type" "int2")

   (set_attr "length" "2")])

(define_insn "subsi3"

  [(set (match_operand:SI 0 "register_operand" "=r")

        (minus:SI (match_operand:SI 1 "register_operand" "0")

                  (match_operand:SI 2 "register_operand" "r")))]

  ""

  "sub %0,%2"

  [(set_attr "type" "int2")

   (set_attr "length" "2")])

(define_insn "subdi3"

  [(set (match_operand:DI 0 "register_operand" "=r")

        (minus:DI (match_operand:DI 1 "register_operand" "0")

                  (match_operand:DI 2 "register_operand" "r")))

   (clobber (reg:CC 17))]

  ""

  "#"

  [(set_attr "type" "multi")

   (set_attr "length" "6")])

;; ??? The cmp clears the condition bit.  Can we speed up somehow?

(define_split

  [(set (match_operand:DI 0 "register_operand" "")

        (minus:DI (match_operand:DI 1 "register_operand" "")

                  (match_operand:DI 2 "register_operand" "")))

   (clobber (reg:CC 17))]

  "reload_completed"

  [(parallel [(set (reg:CC 17)

                   (const_int 0))

              (use (match_dup 4))])

   (parallel [(set (match_dup 4)

                   (minus:SI (match_dup 4)

                             (minus:SI (match_dup 5)

                                       (ne:SI (reg:CC 17) (const_int 0)))))

              (set (reg:CC 17)

                   (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])

   (parallel [(set (match_dup 6)

                   (minus:SI (match_dup 6)

                             (minus:SI (match_dup 7)

                                       (ne:SI (reg:CC 17) (const_int 0)))))

              (set (reg:CC 17)

                   (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]

  "

{

  operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);

  operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);

  operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);