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/* Definitions of target machine for GNU compiler.

   Motorola 68HC11 and 68HC12.

   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007

   Free Software Foundation, Inc.

   Contributed by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3, or (at your option)

any later version.

GCC is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING3.  If not see

<http://www.gnu.org/licenses/>.

Note:

   A first 68HC11 port was made by Otto Lind (otto@coactive.com)

   on gcc 2.6.3.  I have used it as a starting point for this port.

   However, this new port is a complete re-write.  Its internal

   design is completely different.  The generated code is not

   compatible with the gcc 2.6.3 port.

   The gcc 2.6.3 port is available at:

   ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz

*/

/*****************************************************************************

**

** Controlling the Compilation Driver, `gcc'

**

*****************************************************************************/

#undef ENDFILE_SPEC

/* Compile and assemble for a 68hc11 unless there is a -m68hc12 option.  */

#ifndef ASM_SPEC

#define ASM_SPEC                                                \

"%{m68hc12:-m68hc12}"                                           \

"%{m68hcs12:-m68hcs12}"                                         \

"%{!m68hc12:%{!m68hcs12:-m68hc11}} "                            \

"%{mshort:-mshort}%{!mshort:-mlong} "                           \

"%{fshort-double:-mshort-double}%{!fshort-double:-mlong-double}"

#endif

/* We need to tell the linker the target elf format.  Just pass an

   emulation option.  This can be overridden by -Wl option of gcc.  */

#ifndef LINK_SPEC

#define LINK_SPEC                                               \

"%{m68hc12:-m m68hc12elf}"                                      \

"%{m68hcs12:-m m68hc12elf}"                                     \

"%{!m68hc12:%{!m68hcs12:-m m68hc11elf}} "                       \

"%{!mnorelax:%{!m68hc12:%{!m68hcs12:-relax}}}"

#endif

#ifndef LIB_SPEC

#define LIB_SPEC       ""

#endif

#ifndef CC1_SPEC

#define CC1_SPEC       ""

#endif

#ifndef CPP_SPEC

#define CPP_SPEC  \

"%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\

 %{!mshort:-D__INT__=32}\

 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\

 %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\

 %{!m68hc12:%{!m68hcs12:-Dmc6811 -DMC6811 -Dmc68hc11}}\

 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\

 %{mlong-calls:-D__USE_RTC__}"

#endif

#undef STARTFILE_SPEC

#define STARTFILE_SPEC "crt1%O%s"

/* Names to predefine in the preprocessor for this target machine.  */

#define TARGET_CPU_CPP_BUILTINS()               \

  do                                            \

    {                                           \

      builtin_define_std ("mc68hc1x");          \

    }                                           \

  while (0)

/* As an embedded target, we have no libc.  */

#ifndef inhibit_libc

#  define inhibit_libc

#endif

/* Forward type declaration for prototypes definitions.

   rtx_ptr is equivalent to rtx. Can't use the same name.  */

struct rtx_def;

typedef struct rtx_def *rtx_ptr;

union tree_node;

typedef union tree_node *tree_ptr;

/* We can't declare enum machine_mode forward nor include 'machmode.h' here.

   Prototypes defined here will use an int instead. It's better than no

   prototype at all.  */

typedef int enum_machine_mode;

/*****************************************************************************

**

** Run-time Target Specification

**

*****************************************************************************/

/* Run-time compilation parameters selecting different hardware subsets.  */

extern short *reg_renumber;     /* def in local_alloc.c */

#define TARGET_OP_TIME          (optimize && optimize_size == 0)

#define TARGET_RELAX            (TARGET_NO_DIRECT_MODE)

/* Default target_flags if no switches specified.  */

#ifndef TARGET_DEFAULT

# define TARGET_DEFAULT         0

#endif

/* Define this macro as a C expression for the initializer of an

   array of string to tell the driver program which options are

   defaults for this target and thus do not need to be handled

   specially when using `MULTILIB_OPTIONS'.  */

#ifndef MULTILIB_DEFAULTS

# if TARGET_DEFAULT & MASK_M6811

#  define MULTILIB_DEFAULTS { "m68hc11" }

# else

#  define MULTILIB_DEFAULTS { "m68hc12" }

# endif

#endif

/* Print subsidiary information on the compiler version in use.  */

#define TARGET_VERSION  fprintf (stderr, " (MC68HC11/MC68HC12/MC68HCS12)")

/* Sometimes certain combinations of command options do not make

   sense on a particular target machine.  You can define a macro

   `OVERRIDE_OPTIONS' to take account of this.  This macro, if

   defined, is executed once just after all the command options have

   been parsed.

   Don't use this macro to turn on various extra optimizations for

   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */

#define OVERRIDE_OPTIONS        m68hc11_override_options ();

/* Define cost parameters for a given processor variant.  */

struct processor_costs {

  const int add;                /* cost of an add instruction */

  const int logical;          /* cost of a logical instruction */

  const int shift_var;

  const int shiftQI_const[8];

  const int shiftHI_const[16];

  const int multQI;

  const int multHI;

  const int multSI;

  const int divQI;

  const int divHI;

  const int divSI;

};

/* Costs for the current processor.  */

extern const struct processor_costs *m68hc11_cost;

/* target machine storage layout */

/* Define this if most significant byte of a word is the lowest numbered.  */

#define BYTES_BIG_ENDIAN        1

/* Define this if most significant bit is lowest numbered

   in instructions that operate on numbered bit-fields.  */

#define BITS_BIG_ENDIAN         0

/* Define this if most significant word of a multiword number is numbered.  */

#define WORDS_BIG_ENDIAN        1

/* Width of a word, in units (bytes).  */

#define UNITS_PER_WORD          2

/* Definition of size_t.  This is really an unsigned short as the

   68hc11 only handles a 64K address space.  */

#define SIZE_TYPE               "short unsigned int"

/* A C expression for a string describing the name of the data type

   to use for the result of subtracting two pointers.  The typedef

   name `ptrdiff_t' is defined using the contents of the string.

   The 68hc11 only has a 64K address space.  */

#define PTRDIFF_TYPE            "short int"

/* Allocation boundary (bits) for storing pointers in memory.  */

#define POINTER_BOUNDARY        8

/* Normal alignment required for function parameters on the stack, in bits.

   This can't be less than BITS_PER_WORD */

#define PARM_BOUNDARY           (BITS_PER_WORD)

/* Boundary (bits) on which stack pointer should be aligned.  */

#define STACK_BOUNDARY          8

/* Allocation boundary (bits) for the code of a function.  */

#define FUNCTION_BOUNDARY       8

#define BIGGEST_ALIGNMENT       8

/* Alignment of field after `int : 0' in a structure.  */

#define EMPTY_FIELD_BOUNDARY    8

/* Every structure's size must be a multiple of this.  */

#define STRUCTURE_SIZE_BOUNDARY 8

/* Define this if instructions will fail to work if given data not

   on the nominal alignment.  If instructions will merely go slower

   in that case, do not define this macro.  */

#define STRICT_ALIGNMENT        0

/* An integer expression for the size in bits of the largest integer

   machine mode that should actually be used.  All integer machine modes of

   this size or smaller can be used for structures and unions with the

   appropriate sizes.  */

#define MAX_FIXED_MODE_SIZE     64

/* target machine storage layout */

/* Size (bits) of the type "int" on target machine

   (If undefined, default is BITS_PER_WORD).  */

#define INT_TYPE_SIZE           (TARGET_SHORT ? 16 : 32)

/* Size (bits) of the type "short" on target machine */

#define SHORT_TYPE_SIZE         16

/* Size (bits) of the type "long" on target machine */

#define LONG_TYPE_SIZE          32

/* Size (bits) of the type "long long" on target machine */

#define LONG_LONG_TYPE_SIZE     64

/* A C expression for the size in bits of the type `float' on the

   target machine. If you don't define this, the default is one word.

   Don't use default: a word is only 16.  */

#define FLOAT_TYPE_SIZE         32

/* A C expression for the size in bits of the type double on the target

   machine. If you don't define this, the default is two words.

   Be IEEE compliant.  */

#define DOUBLE_TYPE_SIZE        64

#define LONG_DOUBLE_TYPE_SIZE   64

/* Define this as 1 if `char' should by default be signed; else as 0.  */

#define DEFAULT_SIGNED_CHAR     0

/* Define these to avoid dependence on meaning of `int'.

   Note that WCHAR_TYPE_SIZE is used in cexp.y,

   where TARGET_SHORT is not available.  */

#define WCHAR_TYPE              "short int"

#define WCHAR_TYPE_SIZE         16

/* Standard register usage.  */

#define HARD_REG_SIZE           (UNITS_PER_WORD)

/* Assign names to real MC68HC11 registers.

   A and B registers are not really used (A+B = D)

   X register is first so that GCC allocates X+D for 32-bit integers and

   the lowpart of that integer will be D.  Having the lower part in D is

   better for 32<->16bit conversions and for many arithmetic operations.  */

#define HARD_X_REGNUM           0

#define HARD_D_REGNUM           1

#define HARD_Y_REGNUM           2

#define HARD_SP_REGNUM          3

#define HARD_PC_REGNUM          4

#define HARD_A_REGNUM           5

#define HARD_B_REGNUM           6

#define HARD_CCR_REGNUM         7

/* The Z register does not really exist in the 68HC11.  This a fake register

   for GCC.  It is treated exactly as an index register (X or Y).  It is only

   in the A_REGS class, which is the BASE_REG_CLASS for GCC.  Defining this

   register helps the reload pass of GCC.  Otherwise, the reload often dies

   with register spill failures.

   The Z register is replaced by either X or Y during the machine specific

   reorg (m68hc11_reorg).  It is saved in the SOFT_Z_REGNUM soft-register

   when this is necessary.

   It's possible to tell GCC not to use this register with -ffixed-z.  */

#define HARD_Z_REGNUM           8

/* The frame pointer is a soft-register.  It's treated as such by GCC:

   it is not and must not be part of the BASE_REG_CLASS.  */

#define DEFAULT_HARD_FP_REGNUM  (9)

#define HARD_FP_REGNUM          (9)

#define HARD_AP_REGNUM          (HARD_FP_REGNUM)

/* Temporary soft-register used in some cases when an operand came

   up into a bad register class (D, X, Y, SP) and gcc failed to

   recognize this. This register is never allocated by GCC.  */

#define SOFT_TMP_REGNUM          10

/* The soft-register which is used to save the Z register

   (see Z register replacement notes in m68hc11.c).  */

#define SOFT_Z_REGNUM            11

/* The soft-register which is used to save either X or Y.  */

#define SOFT_SAVED_XY_REGNUM     12

/* A fake clobber register for 68HC12 patterns.  */

#define FAKE_CLOBBER_REGNUM     (13)

/* Define 32 soft-registers of 16-bit each.  By default,

   only 12 of them are enabled and can be used by GCC.  The

   -msoft-reg-count=<n> option allows to control the number of valid

   soft-registers. GCC can put 32-bit values in them

   by allocating consecutive registers.  The first 3 soft-registers

   are never allocated by GCC.  They are used in case the insn template needs

   a temporary register, or for the Z register replacement.  */

#define MAX_SOFT_REG_COUNT      (32)

#define SOFT_REG_FIXED          0, 0, 0, 0, 0, 0, 0, 0, \

                                0, 0, 0, 0, 1, 1, 1, 1, \

                                1, 1, 1, 1, 1, 1, 1, 1, \

                                1, 1, 1, 1, 1, 1, 1, 1

#define SOFT_REG_USED           0, 0, 0, 0, 0, 0, 0, 0, \

                                0, 0, 0, 0, 1, 1, 1, 1, \

                                1, 1, 1, 1, 1, 1, 1, 1, \

                                1, 1, 1, 1, 1, 1, 1, 1

#define SOFT_REG_ORDER          \

SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\

SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\

SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\

SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\

SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\

SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\

SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\

SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31

#define SOFT_REG_NAMES                                                  \

"*_.d1",  "*_.d2",  "*_.d3",  "*_.d4", \

"*_.d5",  "*_.d6",  "*_.d7",  "*_.d8",  \

"*_.d9",  "*_.d10", "*_.d11", "*_.d12", \

"*_.d13", "*_.d14", "*_.d15", "*_.d16", \

"*_.d17", "*_.d18", "*_.d19", "*_.d20", \

"*_.d21", "*_.d22", "*_.d23", "*_.d24", \

"*_.d25", "*_.d26", "*_.d27", "*_.d28", \

"*_.d29", "*_.d30", "*_.d31", "*_.d32"

/* First available soft-register for GCC.  */

#define SOFT_REG_FIRST          (SOFT_SAVED_XY_REGNUM+2)

/* Last available soft-register for GCC.  */

#define SOFT_REG_LAST           (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT)

#define SOFT_FP_REGNUM          (SOFT_REG_LAST)

#define SOFT_AP_REGNUM          (SOFT_FP_REGNUM+1)

/* Number of actual hardware registers. The hardware registers are assigned

   numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER.

   All registers that the compiler knows about must be given numbers, even

   those that are not normally considered general registers.  */

#define FIRST_PSEUDO_REGISTER   (SOFT_REG_LAST+2)

/* 1 for registers that have pervasive standard uses and are not available

   for the register allocator.  */

#define FIXED_REGISTERS \

  {0, 0, 0, 1, 1, 1, 1, 1,   0, 1,  1,   1,1, 1, SOFT_REG_FIXED, 1, 1}

/* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */

/* 1 for registers not available across function calls. For our pseudo

   registers, all are available.  */

#define CALL_USED_REGISTERS \

  {1, 1, 1, 1, 1, 1, 1, 1,   1, 1,  1,   1,1, 1, SOFT_REG_USED, 1, 1}

/* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32,     SOFT-FP, AP */

/* Define this macro to change register usage conditional on target flags.

   The soft-registers are disabled or enabled according to the

  -msoft-reg-count=<n> option.  */

#define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ())

/* List the order in which to allocate registers.  Each register must be

   listed once, even those in FIXED_REGISTERS.  */

#define REG_ALLOC_ORDER                                                 \

{ HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM,                          \

  SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM,         \

  HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM,       \

  HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \

  SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM  }

/* A C expression for the number of consecutive hard registers,

   starting at register number REGNO, required to hold a value of

   mode MODE.  */

#define HARD_REGNO_NREGS(REGNO, MODE) \

((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \

   ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.

    - 8 bit values are stored anywhere (except the SP register).

    - 16 bit values can be stored in any register whose mode is 16

    - 32 bit values can be stored in D, X registers or in a soft register

      (except the last one because we need 2 soft registers)

    - Values whose size is > 32 bit are not stored in real hard

      registers.  They may be stored in soft registers if there are

      enough of them.  */

#define HARD_REGNO_MODE_OK(REGNO, MODE) \

     hard_regno_mode_ok (REGNO,MODE)

/* Value is 1 if it is a good idea to tie two pseudo registers when one has

   mode MODE1 and one has mode MODE2.  If HARD_REGNO_MODE_OK could produce

   different values for MODE1 and MODE2, for any hard reg, then this must be

   All modes are tieable except QImode.  */

#define MODES_TIEABLE_P(MODE1, MODE2)                   \

     (((MODE1) == (MODE2))                              \

      || ((MODE1) != QImode && (MODE2) != QImode))

/* Define the classes of registers for register constraints in the

   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.

   If there is more than one class, another class must be named NO_REGS

   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for

   another name such as ALL_REGS).  This is the class of registers

   that is allowed by "g" or "r" in a register constraint.

   Also, registers outside this class are allocated only when

   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,

   a larger-numbered class must never be contained completely

   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another

   class that represents their union.  */

/* The M68hc11 has so few registers that it's not possible for GCC to

   do any register allocation without breaking. We extend the processor

   registers by having soft registers. These registers are treated as

   hard registers by GCC but they are located in memory and accessed by page0

   accesses (IND mode).  */

enum reg_class

{

  NO_REGS,

  D_REGS,                       /* 16-bit data register */

  X_REGS,                       /* 16-bit X register */

  Y_REGS,                       /* 16-bit Y register */

  SP_REGS,                      /* 16 bit stack pointer */

  DA_REGS,                      /* 8-bit A reg.  */

  DB_REGS,                      /* 8-bit B reg.  */

  Z_REGS,                       /* 16-bit fake Z register */

  D8_REGS,                      /* 8-bit A or B reg.  */

  Q_REGS,                       /* 8-bit (byte (QI)) data (A, B or D) */

  D_OR_X_REGS,                  /* D or X register */

  D_OR_Y_REGS,                  /* D or Y register */

  D_OR_SP_REGS,                 /* D or SP register */

  X_OR_Y_REGS,                  /* IX or Y register */

  A_REGS,                       /* 16-bit address register (X, Y, Z) */

  X_OR_SP_REGS,                 /* X or SP register */

  Y_OR_SP_REGS,                 /* Y or SP register */

  X_OR_Y_OR_D_REGS,             /* X, Y or D */

  A_OR_D_REGS,                  /* X, Y, Z or D */

  A_OR_SP_REGS,                 /* X, Y, Z or SP */

  H_REGS,                       /* 16-bit hard register (D, X, Y, Z, SP) */

  S_REGS,                       /* 16-bit soft register */

  D_OR_S_REGS,                  /* 16-bit soft register or D register */

  X_OR_S_REGS,                  /* 16-bit soft register or X register */

  Y_OR_S_REGS,                  /* 16-bit soft register or Y register */

  Z_OR_S_REGS,                  /* 16-bit soft register or Z register */

  SP_OR_S_REGS,                 /* 16-bit soft register or SP register */

  D_OR_X_OR_S_REGS,             /* 16-bit soft register or D or X register */

  D_OR_Y_OR_S_REGS,             /* 16-bit soft register or D or Y register */

  D_OR_SP_OR_S_REGS,            /* 16-bit soft register or D or SP register */

  A_OR_S_REGS,                  /* 16-bit soft register or X, Y registers */

  D_OR_A_OR_S_REGS,             /* 16-bit soft register or D, X, Y registers */

  TMP_REGS,                     /* 16 bit fake scratch register */

  D_OR_A_OR_TMP_REGS,           /* General scratch register */

  G_REGS,                       /* 16-bit general register

                                   (H_REGS + soft registers) */

  ALL_REGS,

  LIM_REG_CLASSES

};

/* alias GENERAL_REGS to G_REGS.  */

#define GENERAL_REGS    G_REGS

#define N_REG_CLASSES   (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.  */

#define REG_CLASS_NAMES \

{ "NO_REGS",                                    \

      "D_REGS",                                 \

      "X_REGS",                                 \

      "Y_REGS",                                 \

      "SP_REGS",                                \

      "DA_REGS",                                \

      "DB_REGS",                                \

      "D8_REGS",                                \

      "Z_REGS",                                 \

      "Q_REGS",                                 \

      "D_OR_X_REGS",                            \

      "D_OR_Y_REGS",                            \

      "D_OR_SP_REGS",                           \

      "X_OR_Y_REGS",                            \

      "A_REGS",                                 \

      "X_OR_SP_REGS",                           \

      "Y_OR_SP_REGS",                           \

      "X_OR_Y_OR_D_REGS",                       \

      "A_OR_D_REGS",                            \

      "A_OR_SP_REGS",                           \

      "H_REGS",                                 \

      "S_REGS",                                 \

      "D_OR_S_REGS",                            \

      "X_OR_S_REGS",                            \

      "Y_OR_S_REGS",                            \

      "Z_OR_S_REGS",                            \

      "SP_OR_S_REGS",                           \

      "D_OR_X_OR_S_REGS",                       \

      "D_OR_Y_OR_S_REGS",                       \

      "D_OR_SP_OR_S_REGS",                      \

      "A_OR_S_REGS",                            \

      "D_OR_A_OR_S_REGS",                       \

      "TMP_REGS",                               \

      "D_OR_A_OR_TMP_REGS",                     \

      "G_REGS",                                 \

      "ALL_REGS" }

/* An initializer containing the contents of the register classes,

   as integers which are bit masks.  The Nth integer specifies the

   contents of class N.  The way the integer MASK is interpreted is

   that register R is in the class if `MASK & (1 << R)' is 1.  */

/*--------------------------------------------------------------

   X            0x00000001

   D            0x00000002

   Y            0x00000004

   SP           0x00000008

   PC           0x00000010

   A            0x00000020

   B            0x00000040

   CCR          0x00000080

   Z            0x00000100

   FRAME        0x00000200

   ZTMP         0x00000400

   ZREG         0x00000800

   XYREG        0x00001000

   FAKE         0x00002000

   Di           0xFFFFc000, 0x03FFF

   SFRAME       0x00000000, 0x04000

   AP           0x00000000, 0x08000

   D_OR_X_REGS represents D+X. It is used for 32-bits numbers.

   A_REGS      represents a valid base register for indexing. It represents

               X,Y and the Z register.

   S_REGS      represents the soft-registers. This includes the hard frame

               and soft frame registers.

--------------------------------------------------------------*/

#define REG_CLASS_CONTENTS \

/* NO_REGS */           {{ 0x00000000, 0x00000000 },                    \

/* D_REGS  */            { 0x00000002, 0x00000000 }, /* D */            \

/* X_REGS  */            { 0x00000001, 0x00000000 }, /* X */            \

/* Y_REGS  */            { 0x00000004, 0x00000000 }, /* Y */            \

/* SP_REGS */            { 0x00000008, 0x00000000 }, /* SP */           \

/* DA_REGS */            { 0x00000020, 0x00000000 }, /* A */            \

/* DB_REGS */            { 0x00000040, 0x00000000 }, /* B */            \

/* Z_REGS  */            { 0x00000100, 0x00000000 }, /* Z */            \

/* D8_REGS */            { 0x00000060, 0x00000000 }, /* A B */          \

/* Q_REGS  */            { 0x00000062, 0x00000000 }, /* A B D */        \

/* D_OR_X_REGS */        { 0x00000003, 0x00000000 }, /* D X */          \

/* D_OR_Y_REGS */        { 0x00000006, 0x00000000 }, /* D Y */          \

/* D_OR_SP_REGS */       { 0x0000000A, 0x00000000 }, /* D SP */         \

/* X_OR_Y_REGS  */       { 0x00000005, 0x00000000 }, /* X Y */          \

/* A_REGS  */            { 0x00000105, 0x00000000 }, /* X Y Z */        \

/* X_OR_SP_REGS */       { 0x00000009, 0x00000000 }, /* X SP */         \

/* Y_OR_SP_REGS */       { 0x0000000C, 0x00000000 }, /* Y SP */         \

/* X_OR_Y_OR_D_REGS */   { 0x00000007, 0x00000000 }, /* D X Y */        \

/* A_OR_D_REGS  */       { 0x00000107, 0x00000000 }, /* D X Y Z */      \

/* A_OR_SP_REGS */       { 0x0000010D, 0x00000000 }, /* X Y SP */       \

/* H_REGS  */            { 0x0000010F, 0x00000000 }, /* D X Y SP */     \

/* S_REGS  */            { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z*  */  \

/* D_OR_S_REGS */        { 0xFFFFDE02, 0x00007FFF }, /* D _.D */        \

/* X_OR_S_REGS */        { 0xFFFFDE01, 0x00007FFF }, /* X _.D */        \

/* Y_OR_S_REGS */        { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */        \

/* Z_OR_S_REGS */        { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */        \

/* SP_OR_S_REGS */       { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */       \

/* D_OR_X_OR_S_REGS */   { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */      \

/* D_OR_Y_OR_S_REGS */   { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */      \

/* D_OR_SP_OR_S_REGS */  { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */     \

/* A_OR_S_REGS */        { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */      \

/* D_OR_A_OR_S_REGS */   { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */    \

/* TMP_REGS  */          { 0x00002000, 0x00000000 }, /* FAKE */         \

/* D_OR_A_OR_TMP_REGS*/  { 0x00002107, 0x00000000 }, /* D X Y Z Fake */  \

/* G_REGS  */            { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */   \

/* ALL_REGS*/            { 0xFFFFFFFF, 0x00007FFF }}

/* set up a C expression whose value is a register class containing hard

   register REGNO */

#define Q_REGNO_P(REGNO)        ((REGNO) == HARD_A_REGNUM \

                                 || (REGNO) == HARD_B_REGNUM)

#define Q_REG_P(X)              (REG_P (X) && Q_REGNO_P (REGNO (X)))

#define D_REGNO_P(REGNO)        ((REGNO) == HARD_D_REGNUM)

#define D_REG_P(X)              (REG_P (X) && D_REGNO_P (REGNO (X)))

#define DB_REGNO_P(REGNO)       ((REGNO) == HARD_B_REGNUM)

#define DB_REG_P(X)             (REG_P (X) && DB_REGNO_P (REGNO (X)))

#define DA_REGNO_P(REGNO)       ((REGNO) == HARD_A_REGNUM)

#define DA_REG_P(X)             (REG_P (X) && DA_REGNO_P (REGNO (X)))

#define X_REGNO_P(REGNO)        ((REGNO) == HARD_X_REGNUM)

#define X_REG_P(X)              (REG_P (X) && X_REGNO_P (REGNO (X)))

#define Y_REGNO_P(REGNO)        ((REGNO) == HARD_Y_REGNUM)

#define Y_REG_P(X)              (REG_P (X) && Y_REGNO_P (REGNO (X)))

#define Z_REGNO_P(REGNO)        ((REGNO) == HARD_Z_REGNUM)

#define Z_REG_P(X)              (REG_P (X) && Z_REGNO_P (REGNO (X)))

#define SP_REGNO_P(REGNO)       ((REGNO) == HARD_SP_REGNUM)

#define SP_REG_P(X)             (REG_P (X) && SP_REGNO_P (REGNO (X)))

/* Address register.  */

#define A_REGNO_P(REGNO)        ((REGNO) == HARD_X_REGNUM \

                                 || (REGNO) == HARD_Y_REGNUM \

                                 || (REGNO) == HARD_Z_REGNUM)

#define A_REG_P(X)              (REG_P (X) && A_REGNO_P (REGNO (X)))

/* M68hc11 hard registers.  */

#define H_REGNO_P(REGNO)        (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \

                                 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO))

#define H_REG_P(X)              (REG_P (X) && H_REGNO_P (REGNO (X)))

#define FAKE_REGNO_P(REGNO)     ((REGNO) == FAKE_CLOBBER_REGNUM)

#define FAKE_REG_P(X)           (REG_P (X) && FAKE_REGNO_P (REGNO (X)))

/* Soft registers (or register emulation for gcc).  The temporary register

   used by insn template must be part of the S_REGS class so that it

   matches the 'u' constraint.  */

#define S_REGNO_P(REGNO)        ((REGNO) >= SOFT_TMP_REGNUM \

                                 && (REGNO) <= SOFT_REG_LAST \

                                 && (REGNO) != FAKE_CLOBBER_REGNUM)

#define S_REG_P(X)              (REG_P (X) && S_REGNO_P (REGNO (X)))

#define Z_REGNO_P(REGNO)        ((REGNO) == HARD_Z_REGNUM)

#define Z_REG_P(X)              (REG_P (X) && Z_REGNO_P (REGNO (X)))

/* General register.  */

#define G_REGNO_P(REGNO)        (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \

                                 || ((REGNO) == HARD_PC_REGNUM) \

                                 || ((REGNO) == HARD_FP_REGNUM) \

                                 || ((REGNO) == SOFT_FP_REGNUM) \

                                 || ((REGNO) == FAKE_CLOBBER_REGNUM) \

                                 || ((REGNO) == SOFT_AP_REGNUM))

#define G_REG_P(X)              (REG_P (X) && G_REGNO_P (REGNO (X)))

#define REGNO_REG_CLASS(REGNO) \

  (D_REGNO_P (REGNO) ? D_REGS : \

   (X_REGNO_P (REGNO) ? X_REGS : \

    (Y_REGNO_P (REGNO) ? Y_REGS : \

     (SP_REGNO_P (REGNO) ? SP_REGS : \

      (Z_REGNO_P (REGNO) ? Z_REGS : \

       (H_REGNO_P (REGNO) ? H_REGS : \

        (FAKE_REGNO_P (REGNO) ? TMP_REGS : \

         (S_REGNO_P (REGNO) ? S_REGS : \

          (DA_REGNO_P (REGNO) ? DA_REGS: \

           (DB_REGNO_P (REGNO) ? DB_REGS: \

            (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS)))))))))))

/* Get reg_class from a letter in the machine description.  */

extern enum reg_class m68hc11_tmp_regs_class;

#define REG_CLASS_FROM_LETTER(C) \

   ((C) == 'a' ? DA_REGS : \

    (C) == 'A' ? A_REGS : \

    (C) == 'b' ? DB_REGS : \

    (C) == 'B' ? X_OR_Y_REGS : \

    (C) == 'd' ? D_REGS : \

    (C) == 'D' ? D_OR_X_REGS : \

    (C) == 'q' ? Q_REGS : \

    (C) == 'h' ? H_REGS : \

    (C) == 't' ? TMP_REGS : \

    (C) == 'u' ? S_REGS : \

    (C) == 'v' ? m68hc11_tmp_regs_class : \

    (C) == 'w' ? SP_REGS : \

    (C) == 'x' ? X_REGS : \

    (C) == 'y' ? Y_REGS : \

    (C) == 'z' ? Z_REGS : NO_REGS)

#define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS)

#define SMALL_REGISTER_CLASSES 1

/* A C expression that is nonzero if hard register number REGNO2 can be

   considered for use as a rename register for REGNO1 */

#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \

  m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2))

/* A C expression whose value is nonzero if pseudos that have been

   assigned to registers of class CLASS would likely be spilled

   because registers of CLASS are needed for spill registers.

   The default value of this macro returns 1 if CLASS has exactly one

   register and zero otherwise.  On most machines, this default

   should be used.  Only define this macro to some other expression

   if pseudo allocated by `local-alloc.c' end up in memory because

   their hard registers were needed for spill registers.  If this

   macro returns nonzero for those classes, those pseudos will only

   be allocated by `global.c', which knows how to reallocate the

   pseudo to another register.  If there would not be another

   register available for reallocation, you should not change the

   definition of this macro since the only effect of such a

   definition would be to slow down register allocation.  */

#define CLASS_LIKELY_SPILLED_P(CLASS)                                   \

  (((CLASS) == D_REGS)                                                  \

   || ((CLASS) == X_REGS)                                               \

   || ((CLASS) == Y_REGS)                                               \

   || ((CLASS) == A_REGS)                                               \

   || ((CLASS) == SP_REGS)                                              \

   || ((CLASS) == D_OR_X_REGS)                                          \

   || ((CLASS) == D_OR_Y_REGS)                                          \