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julius |
;; DFA-based pipeline description for the RM7000.
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;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .........................
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;;
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;; The RM7000 is a dual-issue processor that can bundle instructions as:
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;; {arith|load|store}{arith|imul|idiv|branch|float}
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;;
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;; Reference:
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;; "RM7000 Family User Manual, PMC-2002296"
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;;
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;; .........................
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;; Use three automata to isolate long latency operations, reducing space.
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(define_automaton "rm7000_other, rm7000_fdiv, rm7000_idiv")
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;;
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;; Describe the resources.
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;;
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;; Global
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(define_cpu_unit "rm7_iss0,rm7_iss1" "rm7000_other")
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;; Integer execution unit (M-Pipe).
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(define_cpu_unit "ixum_addsub_agen" "rm7000_other")
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;; Integer execution unit (F-Pipe).
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(define_cpu_unit "ixuf_addsub" "rm7000_other")
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(define_cpu_unit "ixuf_branch" "rm7000_other")
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(define_cpu_unit "ixuf_mpydiv" "rm7000_other")
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(define_cpu_unit "ixuf_mpydiv_iter" "rm7000_idiv")
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;; Floating-point unit (F-Pipe).
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(define_cpu_unit "fxuf_add" "rm7000_other")
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(define_cpu_unit "fxuf_mpy" "rm7000_other")
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(define_cpu_unit "fxuf_mpy_iter" "rm7000_fdiv")
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(define_cpu_unit "fxuf_divsqrt" "rm7000_other")
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(define_cpu_unit "fxuf_divsqrt_iter" "rm7000_fdiv")
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(exclusion_set "ixuf_addsub"
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"ixuf_branch,ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "ixuf_branch" "ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "ixuf_mpydiv" "fxuf_add,fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
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(exclusion_set "fxuf_mpy" "fxuf_divsqrt")
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;; After branch any insn cannot be issued.
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(absence_set "rm7_iss0,rm7_iss1" "ixuf_branch")
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;;
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;; Define reservations for unit name mnemonics or combinations.
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;;
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(define_reservation "rm7_iss" "rm7_iss0|rm7_iss1")
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(define_reservation "rm7_single_dispatch" "rm7_iss0+rm7_iss1")
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(define_reservation "rm7_iaddsub" "rm7_iss+(ixum_addsub_agen|ixuf_addsub)")
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(define_reservation "rm7_imem" "rm7_iss+ixum_addsub_agen")
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(define_reservation "rm7_impydiv" "rm7_iss+ixuf_mpydiv")
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(define_reservation "rm7_impydiv_iter" "ixuf_mpydiv_iter")
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(define_reservation "rm7_branch" "rm7_iss+ixuf_branch")
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(define_reservation "rm7_fpadd" "rm7_iss+fxuf_add")
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(define_reservation "rm7_fpmpy" "rm7_iss+fxuf_mpy")
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(define_reservation "rm7_fpmpy_iter" "fxuf_mpy_iter")
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(define_reservation "rm7_fpdivsqr" "rm7_iss+fxuf_divsqrt")
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(define_reservation "rm7_fpdivsqr_iter" "fxuf_divsqrt_iter")
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;;
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;; Describe instruction reservations for integer operations.
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;;
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(define_insn_reservation "rm7_int_other" 1
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
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"rm7_iaddsub")
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(define_insn_reservation "rm7_ld" 2
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "load,fpload,fpidxload"))
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"rm7_imem")
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(define_insn_reservation "rm7_st" 1
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "store,fpstore,fpidxstore"))
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"rm7_imem")
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(define_insn_reservation "rm7_idiv_si" 36
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "SI")))
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"rm7_impydiv+(rm7_impydiv_iter*36)")
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(define_insn_reservation "rm7_idiv_di" 68
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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"rm7_impydiv+(rm7_impydiv_iter*68)")
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(define_insn_reservation "rm7_impy_si_mult" 5
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul,imadd")
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(eq_attr "mode" "SI")))
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"rm7_impydiv+(rm7_impydiv_iter*3)")
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;; There are an additional 2 stall cycles.
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(define_insn_reservation "rm7_impy_si_mul" 2
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul3")
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(eq_attr "mode" "SI")))
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"rm7_impydiv")
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(define_insn_reservation "rm7_impy_di" 9
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "imul,imul3")
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(eq_attr "mode" "DI")))
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"rm7_impydiv+(rm7_impydiv_iter*8)")
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;; Move to/from HI/LO.
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(define_insn_reservation "rm7_mthilo" 3
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "mthilo"))
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"rm7_impydiv")
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(define_insn_reservation "rm7_mfhilo" 1
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "mfhilo"))
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"rm7_impydiv")
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;; Move to/from fp coprocessor.
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(define_insn_reservation "rm7_ixfer" 2
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "xfer"))
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"rm7_iaddsub")
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(define_insn_reservation "rm7_ibr" 3
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "branch,jump,call"))
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"rm7_branch")
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;;
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;; Describe instruction reservations for the floating-point operations.
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;;
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(define_insn_reservation "rm7_fp_quick" 4
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fneg,fcmp,fabs,fmove"))
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"rm7_fpadd")
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(define_insn_reservation "rm7_fp_other" 4
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fadd"))
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"rm7_fpadd")
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(define_insn_reservation "rm7_fp_cvt" 4
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "fcvt"))
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"rm7_fpadd")
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(define_insn_reservation "rm7_fp_divsqrt_df" 36
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fdiv,frdiv,fsqrt")
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(eq_attr "mode" "DF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
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(define_insn_reservation "rm7_fp_divsqrt_sf" 21
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fdiv,frdiv,fsqrt")
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(eq_attr "mode" "SF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
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(define_insn_reservation "rm7_fp_rsqrt_df" 68
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
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(define_insn_reservation "rm7_fp_rsqrt_sf" 38
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "SF")))
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"rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
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(define_insn_reservation "rm7_fp_mpy_sf" 4
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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"rm7_fpmpy+rm7_fpmpy_iter")
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(define_insn_reservation "rm7_fp_mpy_df" 5
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(and (eq_attr "cpu" "r7000")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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"rm7_fpmpy+(rm7_fpmpy_iter*2)")
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;; Force single-dispatch for unknown or multi.
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(define_insn_reservation "rm7_unknown" 1
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(and (eq_attr "cpu" "r7000")
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(eq_attr "type" "unknown,multi"))
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"rm7_single_dispatch")
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