| 1 |
38 |
julius |
;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
|
| 2 |
|
|
;; and PowerPC 630 processors.
|
| 3 |
|
|
;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
|
| 4 |
|
|
;;
|
| 5 |
|
|
;; This file is part of GCC.
|
| 6 |
|
|
|
| 7 |
|
|
;; GCC is free software; you can redistribute it and/or modify it
|
| 8 |
|
|
;; under the terms of the GNU General Public License as published
|
| 9 |
|
|
;; by the Free Software Foundation; either version 3, or (at your
|
| 10 |
|
|
;; option) any later version.
|
| 11 |
|
|
|
| 12 |
|
|
;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
| 13 |
|
|
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
| 14 |
|
|
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
| 15 |
|
|
;; License for more details.
|
| 16 |
|
|
|
| 17 |
|
|
;; You should have received a copy of the GNU General Public License
|
| 18 |
|
|
;; along with GCC; see the file COPYING3. If not see
|
| 19 |
|
|
;; .
|
| 20 |
|
|
|
| 21 |
|
|
(define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
|
| 22 |
|
|
(define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
|
| 23 |
|
|
(define_cpu_unit "fpu_6xx" "ppc6xxfp")
|
| 24 |
|
|
(define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
|
| 25 |
|
|
(define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
|
| 26 |
|
|
|
| 27 |
|
|
;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
|
| 28 |
|
|
;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
|
| 29 |
|
|
;; MCIU used for imul/idiv and moves from/to spr
|
| 30 |
|
|
;; LSU 2 stage pipelined
|
| 31 |
|
|
;; FPU 3 stage pipelined
|
| 32 |
|
|
;; Max issue 4 insns/clock cycle
|
| 33 |
|
|
|
| 34 |
|
|
;; PPC604e is PPC604 with larger caches and a CRU. In the 604
|
| 35 |
|
|
;; the CR logical operations are handled in the BPU.
|
| 36 |
|
|
;; In the 604e, the CRU shares bus with BPU so only one condition
|
| 37 |
|
|
;; register or branch insn can be issued per clock. Not modelled.
|
| 38 |
|
|
|
| 39 |
|
|
;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
|
| 40 |
|
|
;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
|
| 41 |
|
|
;; Max issue 4 insns/clock cycle
|
| 42 |
|
|
;; Out-of-order execution, in-order completion
|
| 43 |
|
|
|
| 44 |
|
|
;; No following instruction can dispatch in the same cycle as a branch
|
| 45 |
|
|
;; instruction. Not modelled. This is no problem if RCSP is not
|
| 46 |
|
|
;; enabled since the scheduler stops a schedule when it gets to a branch.
|
| 47 |
|
|
|
| 48 |
|
|
;; Four insns can be dispatched per cycle.
|
| 49 |
|
|
|
| 50 |
|
|
(define_insn_reservation "ppc604-load" 2
|
| 51 |
|
|
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
|
| 52 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 53 |
|
|
"lsu_6xx")
|
| 54 |
|
|
|
| 55 |
|
|
(define_insn_reservation "ppc604-fpload" 3
|
| 56 |
|
|
(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
|
| 57 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 58 |
|
|
"lsu_6xx")
|
| 59 |
|
|
|
| 60 |
|
|
(define_insn_reservation "ppc604-store" 3
|
| 61 |
|
|
(and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
|
| 62 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 63 |
|
|
"lsu_6xx")
|
| 64 |
|
|
|
| 65 |
|
|
(define_insn_reservation "ppc604-llsc" 3
|
| 66 |
|
|
(and (eq_attr "type" "load_l,store_c")
|
| 67 |
|
|
(eq_attr "cpu" "ppc604,ppc604e"))
|
| 68 |
|
|
"lsu_6xx")
|
| 69 |
|
|
|
| 70 |
|
|
(define_insn_reservation "ppc630-llsc" 4
|
| 71 |
|
|
(and (eq_attr "type" "load_l,store_c")
|
| 72 |
|
|
(eq_attr "cpu" "ppc620,ppc630"))
|
| 73 |
|
|
"lsu_6xx")
|
| 74 |
|
|
|
| 75 |
|
|
(define_insn_reservation "ppc604-integer" 1
|
| 76 |
|
|
(and (eq_attr "type" "integer,insert_word")
|
| 77 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 78 |
|
|
"iu1_6xx|iu2_6xx")
|
| 79 |
|
|
|
| 80 |
|
|
(define_insn_reservation "ppc604-two" 1
|
| 81 |
|
|
(and (eq_attr "type" "two")
|
| 82 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 83 |
|
|
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
|
| 84 |
|
|
|
| 85 |
|
|
(define_insn_reservation "ppc604-three" 1
|
| 86 |
|
|
(and (eq_attr "type" "three")
|
| 87 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 88 |
|
|
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
|
| 89 |
|
|
|
| 90 |
|
|
(define_insn_reservation "ppc604-imul" 4
|
| 91 |
|
|
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
|
| 92 |
|
|
(eq_attr "cpu" "ppc604"))
|
| 93 |
|
|
"mciu_6xx*2")
|
| 94 |
|
|
|
| 95 |
|
|
(define_insn_reservation "ppc604e-imul" 2
|
| 96 |
|
|
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
|
| 97 |
|
|
(eq_attr "cpu" "ppc604e"))
|
| 98 |
|
|
"mciu_6xx")
|
| 99 |
|
|
|
| 100 |
|
|
(define_insn_reservation "ppc620-imul" 5
|
| 101 |
|
|
(and (eq_attr "type" "imul,imul_compare")
|
| 102 |
|
|
(eq_attr "cpu" "ppc620,ppc630"))
|
| 103 |
|
|
"mciu_6xx*3")
|
| 104 |
|
|
|
| 105 |
|
|
(define_insn_reservation "ppc620-imul2" 4
|
| 106 |
|
|
(and (eq_attr "type" "imul2")
|
| 107 |
|
|
(eq_attr "cpu" "ppc620,ppc630"))
|
| 108 |
|
|
"mciu_6xx*3")
|
| 109 |
|
|
|
| 110 |
|
|
(define_insn_reservation "ppc620-imul3" 3
|
| 111 |
|
|
(and (eq_attr "type" "imul3")
|
| 112 |
|
|
(eq_attr "cpu" "ppc620,ppc630"))
|
| 113 |
|
|
"mciu_6xx*3")
|
| 114 |
|
|
|
| 115 |
|
|
(define_insn_reservation "ppc620-lmul" 7
|
| 116 |
|
|
(and (eq_attr "type" "lmul,lmul_compare")
|
| 117 |
|
|
(eq_attr "cpu" "ppc620,ppc630"))
|
| 118 |
|
|
"mciu_6xx*5")
|
| 119 |
|
|
|
| 120 |
|
|
(define_insn_reservation "ppc604-idiv" 20
|
| 121 |
|
|
(and (eq_attr "type" "idiv")
|
| 122 |
|
|
(eq_attr "cpu" "ppc604,ppc604e"))
|
| 123 |
|
|
"mciu_6xx*19")
|
| 124 |
|
|
|
| 125 |
|
|
(define_insn_reservation "ppc620-idiv" 37
|
| 126 |
|
|
(and (eq_attr "type" "idiv")
|
| 127 |
|
|
(eq_attr "cpu" "ppc620"))
|
| 128 |
|
|
"mciu_6xx*36")
|
| 129 |
|
|
|
| 130 |
|
|
(define_insn_reservation "ppc630-idiv" 21
|
| 131 |
|
|
(and (eq_attr "type" "idiv")
|
| 132 |
|
|
(eq_attr "cpu" "ppc630"))
|
| 133 |
|
|
"mciu_6xx*20")
|
| 134 |
|
|
|
| 135 |
|
|
(define_insn_reservation "ppc620-ldiv" 37
|
| 136 |
|
|
(and (eq_attr "type" "ldiv")
|
| 137 |
|
|
(eq_attr "cpu" "ppc620,ppc630"))
|
| 138 |
|
|
"mciu_6xx*36")
|
| 139 |
|
|
|
| 140 |
|
|
(define_insn_reservation "ppc604-compare" 3
|
| 141 |
|
|
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
|
| 142 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 143 |
|
|
"(iu1_6xx|iu2_6xx)")
|
| 144 |
|
|
|
| 145 |
|
|
; FPU PPC604{,e},PPC620
|
| 146 |
|
|
(define_insn_reservation "ppc604-fpcompare" 5
|
| 147 |
|
|
(and (eq_attr "type" "fpcompare")
|
| 148 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
|
| 149 |
|
|
"fpu_6xx")
|
| 150 |
|
|
|
| 151 |
|
|
(define_insn_reservation "ppc604-fp" 3
|
| 152 |
|
|
(and (eq_attr "type" "fp")
|
| 153 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
|
| 154 |
|
|
"fpu_6xx")
|
| 155 |
|
|
|
| 156 |
|
|
(define_insn_reservation "ppc604-dmul" 3
|
| 157 |
|
|
(and (eq_attr "type" "dmul")
|
| 158 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
|
| 159 |
|
|
"fpu_6xx")
|
| 160 |
|
|
|
| 161 |
|
|
; Divides are not pipelined
|
| 162 |
|
|
(define_insn_reservation "ppc604-sdiv" 18
|
| 163 |
|
|
(and (eq_attr "type" "sdiv")
|
| 164 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
|
| 165 |
|
|
"fpu_6xx*18")
|
| 166 |
|
|
|
| 167 |
|
|
(define_insn_reservation "ppc604-ddiv" 32
|
| 168 |
|
|
(and (eq_attr "type" "ddiv")
|
| 169 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
|
| 170 |
|
|
"fpu_6xx*32")
|
| 171 |
|
|
|
| 172 |
|
|
(define_insn_reservation "ppc620-ssqrt" 31
|
| 173 |
|
|
(and (eq_attr "type" "ssqrt")
|
| 174 |
|
|
(eq_attr "cpu" "ppc620"))
|
| 175 |
|
|
"fpu_6xx*31")
|
| 176 |
|
|
|
| 177 |
|
|
(define_insn_reservation "ppc620-dsqrt" 31
|
| 178 |
|
|
(and (eq_attr "type" "dsqrt")
|
| 179 |
|
|
(eq_attr "cpu" "ppc620"))
|
| 180 |
|
|
"fpu_6xx*31")
|
| 181 |
|
|
|
| 182 |
|
|
|
| 183 |
|
|
; 2xFPU PPC630
|
| 184 |
|
|
(define_insn_reservation "ppc630-fpcompare" 5
|
| 185 |
|
|
(and (eq_attr "type" "fpcompare")
|
| 186 |
|
|
(eq_attr "cpu" "ppc630"))
|
| 187 |
|
|
"fpu1_6xx|fpu2_6xx")
|
| 188 |
|
|
|
| 189 |
|
|
(define_insn_reservation "ppc630-fp" 3
|
| 190 |
|
|
(and (eq_attr "type" "fp,dmul")
|
| 191 |
|
|
(eq_attr "cpu" "ppc630"))
|
| 192 |
|
|
"fpu1_6xx|fpu2_6xx")
|
| 193 |
|
|
|
| 194 |
|
|
(define_insn_reservation "ppc630-sdiv" 17
|
| 195 |
|
|
(and (eq_attr "type" "sdiv")
|
| 196 |
|
|
(eq_attr "cpu" "ppc630"))
|
| 197 |
|
|
"fpu1_6xx*17|fpu2_6xx*17")
|
| 198 |
|
|
|
| 199 |
|
|
(define_insn_reservation "ppc630-ddiv" 21
|
| 200 |
|
|
(and (eq_attr "type" "ddiv")
|
| 201 |
|
|
(eq_attr "cpu" "ppc630"))
|
| 202 |
|
|
"fpu1_6xx*21|fpu2_6xx*21")
|
| 203 |
|
|
|
| 204 |
|
|
(define_insn_reservation "ppc630-ssqrt" 18
|
| 205 |
|
|
(and (eq_attr "type" "ssqrt")
|
| 206 |
|
|
(eq_attr "cpu" "ppc630"))
|
| 207 |
|
|
"fpu1_6xx*18|fpu2_6xx*18")
|
| 208 |
|
|
|
| 209 |
|
|
(define_insn_reservation "ppc630-dsqrt" 25
|
| 210 |
|
|
(and (eq_attr "type" "dsqrt")
|
| 211 |
|
|
(eq_attr "cpu" "ppc630"))
|
| 212 |
|
|
"fpu1_6xx*25|fpu2_6xx*25")
|
| 213 |
|
|
|
| 214 |
|
|
(define_insn_reservation "ppc604-mfcr" 3
|
| 215 |
|
|
(and (eq_attr "type" "mfcr")
|
| 216 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 217 |
|
|
"mciu_6xx")
|
| 218 |
|
|
|
| 219 |
|
|
(define_insn_reservation "ppc604-mtcr" 2
|
| 220 |
|
|
(and (eq_attr "type" "mtcr")
|
| 221 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 222 |
|
|
"iu1_6xx|iu2_6xx")
|
| 223 |
|
|
|
| 224 |
|
|
(define_insn_reservation "ppc604-crlogical" 2
|
| 225 |
|
|
(and (eq_attr "type" "cr_logical,delayed_cr")
|
| 226 |
|
|
(eq_attr "cpu" "ppc604"))
|
| 227 |
|
|
"bpu_6xx")
|
| 228 |
|
|
|
| 229 |
|
|
(define_insn_reservation "ppc604e-crlogical" 2
|
| 230 |
|
|
(and (eq_attr "type" "cr_logical,delayed_cr")
|
| 231 |
|
|
(eq_attr "cpu" "ppc604e,ppc620,ppc630"))
|
| 232 |
|
|
"cru_6xx")
|
| 233 |
|
|
|
| 234 |
|
|
(define_insn_reservation "ppc604-mtjmpr" 2
|
| 235 |
|
|
(and (eq_attr "type" "mtjmpr")
|
| 236 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 237 |
|
|
"mciu_6xx")
|
| 238 |
|
|
|
| 239 |
|
|
(define_insn_reservation "ppc604-mfjmpr" 3
|
| 240 |
|
|
(and (eq_attr "type" "mfjmpr")
|
| 241 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
|
| 242 |
|
|
"mciu_6xx")
|
| 243 |
|
|
|
| 244 |
|
|
(define_insn_reservation "ppc630-mfjmpr" 2
|
| 245 |
|
|
(and (eq_attr "type" "mfjmpr")
|
| 246 |
|
|
(eq_attr "cpu" "ppc630"))
|
| 247 |
|
|
"mciu_6xx")
|
| 248 |
|
|
|
| 249 |
|
|
(define_insn_reservation "ppc604-jmpreg" 1
|
| 250 |
|
|
(and (eq_attr "type" "jmpreg,branch")
|
| 251 |
|
|
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
|
| 252 |
|
|
"bpu_6xx")
|
| 253 |
|
|
|
| 254 |
|
|
(define_insn_reservation "ppc604-isync" 0
|
| 255 |
|
|
(and (eq_attr "type" "isync")
|
| 256 |
|
|
(eq_attr "cpu" "ppc604,ppc604e"))
|
| 257 |
|
|
"bpu_6xx")
|
| 258 |
|
|
|
| 259 |
|
|
(define_insn_reservation "ppc630-isync" 6
|
| 260 |
|
|
(and (eq_attr "type" "isync")
|
| 261 |
|
|
(eq_attr "cpu" "ppc620,ppc630"))
|
| 262 |
|
|
"bpu_6xx")
|
| 263 |
|
|
|
| 264 |
|
|
(define_insn_reservation "ppc604-sync" 35
|
| 265 |
|
|
(and (eq_attr "type" "sync")
|
| 266 |
|
|
(eq_attr "cpu" "ppc604,ppc604e"))
|
| 267 |
|
|
"lsu_6xx")
|
| 268 |
|
|
|
| 269 |
|
|
(define_insn_reservation "ppc630-sync" 26
|
| 270 |
|
|
(and (eq_attr "type" "sync")
|
| 271 |
|
|
(eq_attr "cpu" "ppc620,ppc630"))
|
| 272 |
|
|
"lsu_6xx")
|
| 273 |
|
|
|
