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julius |
/* Machine description patterns for PowerPC running Darwin (Mac OS X).
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Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
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Contributed by Apple Computer Inc.
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This file is part of GCC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; . */
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(define_insn "adddi3_high"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
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(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(high:DI (match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_64BIT"
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"{cau|addis} %0,%1,ha16(%2)"
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[(set_attr "length" "4")])
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(define_insn "movdf_low_si"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
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"*
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{
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switch (which_alternative)
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{
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case 0:
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return \"lfd %0,lo16(%2)(%1)\";
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case 1:
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{
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if (TARGET_POWERPC64 && TARGET_32BIT)
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/* Note, old assemblers didn't support relocation here. */
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return \"ld %0,lo16(%2)(%1)\";
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else
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{
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output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands);
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output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands);
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return (\"{l|lwz} %0,0(%0)\");
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}
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}
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default:
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gcc_unreachable ();
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}
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4,12")])
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(define_insn "movdf_low_di"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"*
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{
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switch (which_alternative)
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{
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case 0:
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return \"lfd %0,lo16(%2)(%1)\";
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case 1:
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return \"ld %0,lo16(%2)(%1)\";
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default:
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gcc_unreachable ();
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}
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4,4")])
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(define_insn "movdf_low_st_si"
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[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand:DF 0 "gpc_reg_operand" "f"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"stfd %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(define_insn "movdf_low_st_di"
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[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand:DF 0 "gpc_reg_operand" "f"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"stfd %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(define_insn "movsf_low_si"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"@
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lfs %0,lo16(%2)(%1)
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{l|lwz} %0,lo16(%2)(%1)"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn "movsf_low_di"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"@
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lfs %0,lo16(%2)(%1)
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{l|lwz} %0,lo16(%2)(%1)"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn "movsf_low_st_si"
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[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" "")))
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(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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"@
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stfs %0,lo16(%2)(%1)
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{st|stw} %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(define_insn "movsf_low_st_di"
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[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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(match_operand 2 "" "")))
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(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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"@
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stfs %0,lo16(%2)(%1)
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{st|stw} %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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;; 64-bit MachO load/store support
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(define_insn "movdi_low"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" ""))))]
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"TARGET_MACHO && TARGET_64BIT"
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"{l|ld} %0,lo16(%2)(%1)"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn "movsi_low_st"
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[(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand:SI 0 "gpc_reg_operand" "r"))]
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"TARGET_MACHO && ! TARGET_64BIT"
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"{st|stw} %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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(define_insn "movdi_low_st"
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[(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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(match_operand 2 "" "")))
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(match_operand:DI 0 "gpc_reg_operand" "r"))]
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"TARGET_MACHO && TARGET_64BIT"
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"{st|std} %0,lo16(%2)(%1)"
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[(set_attr "type" "store")
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(set_attr "length" "4")])
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;; Mach-O PIC trickery.
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(define_expand "macho_high"
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[(set (match_operand 0 "" "")
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(high (match_operand 1 "" "")))]
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"TARGET_MACHO"
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{
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if (TARGET_64BIT)
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emit_insn (gen_macho_high_di (operands[0], operands[1]));
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else
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emit_insn (gen_macho_high_si (operands[0], operands[1]));
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DONE;
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})
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(define_insn "macho_high_si"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
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(high:SI (match_operand 1 "" "")))]
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"TARGET_MACHO && ! TARGET_64BIT"
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"{liu|lis} %0,ha16(%1)")
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(define_insn "macho_high_di"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
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(high:DI (match_operand 1 "" "")))]
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"TARGET_MACHO && TARGET_64BIT"
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"{liu|lis} %0,ha16(%1)")
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(define_expand "macho_low"
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[(set (match_operand 0 "" "")
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(lo_sum (match_operand 1 "" "")
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(match_operand 2 "" "")))]
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"TARGET_MACHO"
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{
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if (TARGET_64BIT)
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emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn "macho_low_si"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
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(match_operand 2 "" "")))]
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"TARGET_MACHO && ! TARGET_64BIT"
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"@
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{cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
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{cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
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(define_insn "macho_low_di"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
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| 223 |
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(match_operand 2 "" "")))]
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"TARGET_MACHO && TARGET_64BIT"
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"@
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{cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
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{cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
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(define_split
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[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
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(match_operand:DI 1 "short_cint_operand" "")))
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| 232 |
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(match_operand:V4SI 2 "register_operand" ""))
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(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
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"TARGET_MACHO && TARGET_64BIT"
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| 235 |
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[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
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| 236 |
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(set (mem:V4SI (match_dup 3))
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| 237 |
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(match_dup 2))]
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| 238 |
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"")
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| 239 |
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| 240 |
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(define_expand "load_macho_picbase"
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| 241 |
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[(set (match_operand 0 "" "")
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| 242 |
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(unspec [(match_operand 1 "" "")]
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| 243 |
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UNSPEC_LD_MPIC))]
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| 244 |
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"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
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| 245 |
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{
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| 246 |
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if (TARGET_32BIT)
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| 247 |
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emit_insn (gen_load_macho_picbase_si (operands[0], operands[1]));
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| 248 |
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else
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| 249 |
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emit_insn (gen_load_macho_picbase_di (operands[0], operands[1]));
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| 250 |
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| 251 |
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DONE;
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| 252 |
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})
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| 253 |
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| 254 |
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(define_insn "load_macho_picbase_si"
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| 255 |
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[(set (match_operand:SI 0 "register_operand" "=l")
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| 256 |
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(unspec:SI [(match_operand:SI 1 "immediate_operand" "s")
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| 257 |
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(pc)] UNSPEC_LD_MPIC))]
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| 258 |
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"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
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| 259 |
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"bcl 20,31,%1\\n%1:"
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| 260 |
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[(set_attr "type" "branch")
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| 261 |
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(set_attr "length" "4")])
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| 262 |
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| 263 |
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(define_insn "load_macho_picbase_di"
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| 264 |
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[(set (match_operand:DI 0 "register_operand" "=l")
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| 265 |
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(unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
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| 266 |
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(pc)] UNSPEC_LD_MPIC))]
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| 267 |
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"(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
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| 268 |
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"bcl 20,31,%1\\n%1:"
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| 269 |
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[(set_attr "type" "branch")
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| 270 |
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(set_attr "length" "4")])
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| 271 |
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| 272 |
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(define_expand "macho_correct_pic"
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| 273 |
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[(set (match_operand 0 "" "")
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| 274 |
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(plus (match_operand 1 "" "")
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| 275 |
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(unspec [(match_operand 2 "" "")
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| 276 |
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(match_operand 3 "" "")]
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| 277 |
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UNSPEC_MPIC_CORRECT)))]
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| 278 |
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"DEFAULT_ABI == ABI_DARWIN"
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| 279 |
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{
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| 280 |
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if (TARGET_32BIT)
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| 281 |
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emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
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| 282 |
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operands[3]));
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| 283 |
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else
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| 284 |
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emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
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| 285 |
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operands[3]));
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| 286 |
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| 287 |
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DONE;
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| 288 |
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})
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| 289 |
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| 290 |
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(define_insn "macho_correct_pic_si"
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| 291 |
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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| 292 |
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(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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| 293 |
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(unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
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| 294 |
|
|
(match_operand:SI 3 "immediate_operand" "s")]
|
| 295 |
|
|
UNSPEC_MPIC_CORRECT)))]
|
| 296 |
|
|
"DEFAULT_ABI == ABI_DARWIN"
|
| 297 |
|
|
"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
|
| 298 |
|
|
[(set_attr "length" "8")])
|
| 299 |
|
|
|
| 300 |
|
|
(define_insn "macho_correct_pic_di"
|
| 301 |
|
|
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
| 302 |
|
|
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
|
| 303 |
|
|
(unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
|
| 304 |
|
|
(match_operand:DI 3 "immediate_operand" "s")]
|
| 305 |
|
|
16)))]
|
| 306 |
|
|
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
|
| 307 |
|
|
"addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
|
| 308 |
|
|
[(set_attr "length" "8")])
|
| 309 |
|
|
|
| 310 |
|
|
(define_insn "*call_indirect_nonlocal_darwin64"
|
| 311 |
|
|
[(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
|
| 312 |
|
|
(match_operand 1 "" "g,g,g,g"))
|
| 313 |
|
|
(use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
|
| 314 |
|
|
(clobber (match_scratch:SI 3 "=l,l,l,l"))]
|
| 315 |
|
|
"DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
|
| 316 |
|
|
{
|
| 317 |
|
|
return "b%T0l";
|
| 318 |
|
|
}
|
| 319 |
|
|
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
|
| 320 |
|
|
(set_attr "length" "4,4,8,8")])
|
| 321 |
|
|
|
| 322 |
|
|
(define_insn "*call_nonlocal_darwin64"
|
| 323 |
|
|
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
|
| 324 |
|
|
(match_operand 1 "" "g,g"))
|
| 325 |
|
|
(use (match_operand:SI 2 "immediate_operand" "O,n"))
|
| 326 |
|
|
(clobber (match_scratch:SI 3 "=l,l"))]
|
| 327 |
|
|
"(DEFAULT_ABI == ABI_DARWIN)
|
| 328 |
|
|
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
|
| 329 |
|
|
{
|
| 330 |
|
|
#if TARGET_MACHO
|
| 331 |
|
|
return output_call(insn, operands, 0, 2);
|
| 332 |
|
|
#else
|
| 333 |
|
|
gcc_unreachable ();
|
| 334 |
|
|
#endif
|
| 335 |
|
|
}
|
| 336 |
|
|
[(set_attr "type" "branch,branch")
|
| 337 |
|
|
(set_attr "length" "4,8")])
|
| 338 |
|
|
|
| 339 |
|
|
(define_insn "*call_value_indirect_nonlocal_darwin64"
|
| 340 |
|
|
[(set (match_operand 0 "" "")
|
| 341 |
|
|
(call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
|
| 342 |
|
|
(match_operand 2 "" "g,g,g,g")))
|
| 343 |
|
|
(use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
|
| 344 |
|
|
(clobber (match_scratch:SI 4 "=l,l,l,l"))]
|
| 345 |
|
|
"DEFAULT_ABI == ABI_DARWIN"
|
| 346 |
|
|
{
|
| 347 |
|
|
return "b%T1l";
|
| 348 |
|
|
}
|
| 349 |
|
|
[(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
|
| 350 |
|
|
(set_attr "length" "4,4,8,8")])
|
| 351 |
|
|
|
| 352 |
|
|
(define_insn "*call_value_nonlocal_darwin64"
|
| 353 |
|
|
[(set (match_operand 0 "" "")
|
| 354 |
|
|
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
|
| 355 |
|
|
(match_operand 2 "" "g,g")))
|
| 356 |
|
|
(use (match_operand:SI 3 "immediate_operand" "O,n"))
|
| 357 |
|
|
(clobber (match_scratch:SI 4 "=l,l"))]
|
| 358 |
|
|
"(DEFAULT_ABI == ABI_DARWIN)
|
| 359 |
|
|
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
|
| 360 |
|
|
{
|
| 361 |
|
|
#if TARGET_MACHO
|
| 362 |
|
|
return output_call(insn, operands, 1, 3);
|
| 363 |
|
|
#else
|
| 364 |
|
|
gcc_unreachable ();
|
| 365 |
|
|
#endif
|
| 366 |
|
|
}
|
| 367 |
|
|
[(set_attr "type" "branch,branch")
|
| 368 |
|
|
(set_attr "length" "4,8")])
|
| 369 |
|
|
|
| 370 |
|
|
(define_insn "*sibcall_nonlocal_darwin64"
|
| 371 |
|
|
[(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
|
| 372 |
|
|
(match_operand 1 "" ""))
|
| 373 |
|
|
(use (match_operand 2 "immediate_operand" "O,n"))
|
| 374 |
|
|
(use (match_operand:SI 3 "register_operand" "l,l"))
|
| 375 |
|
|
(return)]
|
| 376 |
|
|
"(DEFAULT_ABI == ABI_DARWIN)
|
| 377 |
|
|
&& (INTVAL (operands[2]) & CALL_LONG) == 0"
|
| 378 |
|
|
{
|
| 379 |
|
|
return "b %z0";
|
| 380 |
|
|
}
|
| 381 |
|
|
[(set_attr "type" "branch,branch")
|
| 382 |
|
|
(set_attr "length" "4,8")])
|
| 383 |
|
|
|
| 384 |
|
|
(define_insn "*sibcall_value_nonlocal_darwin64"
|
| 385 |
|
|
[(set (match_operand 0 "" "")
|
| 386 |
|
|
(call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
|
| 387 |
|
|
(match_operand 2 "" "")))
|
| 388 |
|
|
(use (match_operand:SI 3 "immediate_operand" "O,n"))
|
| 389 |
|
|
(use (match_operand:SI 4 "register_operand" "l,l"))
|
| 390 |
|
|
(return)]
|
| 391 |
|
|
"(DEFAULT_ABI == ABI_DARWIN)
|
| 392 |
|
|
&& (INTVAL (operands[3]) & CALL_LONG) == 0"
|
| 393 |
|
|
"*
|
| 394 |
|
|
{
|
| 395 |
|
|
return \"b %z1\";
|
| 396 |
|
|
}"
|
| 397 |
|
|
[(set_attr "type" "branch,branch")
|
| 398 |
|
|
(set_attr "length" "4,8")])
|
| 399 |
|
|
|
| 400 |
|
|
|
| 401 |
|
|
(define_insn "*sibcall_symbolic_64"
|
| 402 |
|
|
[(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64
|
| 403 |
|
|
(match_operand 1 "" ""))
|
| 404 |
|
|
(use (match_operand 2 "" ""))
|
| 405 |
|
|
(use (match_operand:SI 3 "register_operand" "l,l"))
|
| 406 |
|
|
(return)]
|
| 407 |
|
|
"TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
|
| 408 |
|
|
"*
|
| 409 |
|
|
{
|
| 410 |
|
|
switch (which_alternative)
|
| 411 |
|
|
{
|
| 412 |
|
|
case 0: return \"b %z0\";
|
| 413 |
|
|
case 1: return \"b%T0\";
|
| 414 |
|
|
default: gcc_unreachable ();
|
| 415 |
|
|
}
|
| 416 |
|
|
}"
|
| 417 |
|
|
[(set_attr "type" "branch")
|
| 418 |
|
|
(set_attr "length" "4")])
|
| 419 |
|
|
|
| 420 |
|
|
(define_insn "*sibcall_value_symbolic_64"
|
| 421 |
|
|
[(set (match_operand 0 "" "")
|
| 422 |
|
|
(call (mem:SI (match_operand:DI 1 "call_operand" "s,c"))
|
| 423 |
|
|
(match_operand 2 "" "")))
|
| 424 |
|
|
(use (match_operand:SI 3 "" ""))
|
| 425 |
|
|
(use (match_operand:SI 4 "register_operand" "l,l"))
|
| 426 |
|
|
(return)]
|
| 427 |
|
|
"TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
|
| 428 |
|
|
"*
|
| 429 |
|
|
{
|
| 430 |
|
|
switch (which_alternative)
|
| 431 |
|
|
{
|
| 432 |
|
|
case 0: return \"b %z1\";
|
| 433 |
|
|
case 1: return \"b%T1\";
|
| 434 |
|
|
default: gcc_unreachable ();
|
| 435 |
|
|
}
|
| 436 |
|
|
}"
|
| 437 |
|
|
[(set_attr "type" "branch")
|
| 438 |
|
|
(set_attr "length" "4")])
|
| 439 |
|
|
|
