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julius |
;; Scheduling description for Motorola PowerPC processor cores.
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;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "mpc,mpcfp")
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(define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
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(define_cpu_unit "fpu_mpc" "mpcfp")
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(define_cpu_unit "lsu_mpc,bpu_mpc" "mpc")
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;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
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;; 505/801/821/823
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(define_insn_reservation "mpccore-load" 2
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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load_l,store_c,sync")
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(eq_attr "cpu" "mpccore"))
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"lsu_mpc")
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(define_insn_reservation "mpccore-store" 2
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(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "mpccore"))
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"lsu_mpc")
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(define_insn_reservation "mpccore-fpload" 2
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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(eq_attr "cpu" "mpccore"))
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"lsu_mpc")
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(define_insn_reservation "mpccore-integer" 1
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(and (eq_attr "type" "integer,insert_word")
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(eq_attr "cpu" "mpccore"))
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"iu_mpc")
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(define_insn_reservation "mpccore-two" 1
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "mpccore"))
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"iu_mpc,iu_mpc")
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(define_insn_reservation "mpccore-three" 1
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "mpccore"))
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"iu_mpc,iu_mpc,iu_mpc")
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(define_insn_reservation "mpccore-imul" 2
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "mpccore"))
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"mciu_mpc")
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; Divide latency varies greatly from 2-11, use 6 as average
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(define_insn_reservation "mpccore-idiv" 6
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "mpccore"))
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"mciu_mpc*6")
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(define_insn_reservation "mpccore-compare" 3
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(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
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(eq_attr "cpu" "mpccore"))
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"iu_mpc,nothing,bpu_mpc")
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(define_insn_reservation "mpccore-fpcompare" 2
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "mpccore"))
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"fpu_mpc,bpu_mpc")
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(define_insn_reservation "mpccore-fp" 4
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "mpccore"))
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"fpu_mpc*2")
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(define_insn_reservation "mpccore-dmul" 5
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "mpccore"))
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"fpu_mpc*5")
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(define_insn_reservation "mpccore-sdiv" 10
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "mpccore"))
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"fpu_mpc*10")
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(define_insn_reservation "mpccore-ddiv" 17
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "mpccore"))
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"fpu_mpc*17")
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(define_insn_reservation "mpccore-mtjmpr" 4
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(eq_attr "cpu" "mpccore"))
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"bpu_mpc")
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(define_insn_reservation "mpccore-jmpreg" 1
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(and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync")
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(eq_attr "cpu" "mpccore"))
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"bpu_mpc")
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