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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [rs6000/] [power4.md] - Blame information for rev 38

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;; Scheduling description for IBM Power4 and PowerPC 970 processors.
2
;;   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
3
;;
4
;; This file is part of GCC.
5
;;
6
;; GCC is free software; you can redistribute it and/or modify it
7
;; under the terms of the GNU General Public License as published
8
;; by the Free Software Foundation; either version 3, or (at your
9
;; option) any later version.
10
;;
11
;; GCC is distributed in the hope that it will be useful, but WITHOUT
12
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
;; License for more details.
15
;;
16
;; You should have received a copy of the GNU General Public License
17
;; along with GCC; see the file COPYING3.  If not see
18
;; .
19
 
20
;; Sources: IBM Red Book and White Paper on POWER4
21
 
22
;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
23
;; Instructions that update more than one register get broken into two
24
;; (split) or more internal ops.  The chip can issue up to 5
25
;; internal ops per cycle.
26
 
27
(define_automaton "power4iu,power4fpu,power4vec,power4misc")
28
 
29
(define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
30
(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
31
(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
32
(define_cpu_unit "bpu_power4,cru_power4" "power4misc")
33
(define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
34
(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
35
                 "power4misc")
36
 
37
(define_reservation "lsq_power4"
38
                    "(du1_power4,lsu1_power4)\
39
                    |(du2_power4,lsu2_power4)\
40
                    |(du3_power4,lsu2_power4)\
41
                    |(du4_power4,lsu1_power4)")
42
 
43
(define_reservation "lsuq_power4"
44
                    "(du1_power4+du2_power4,lsu1_power4+iu2_power4)\
45
                    |(du2_power4+du3_power4,lsu2_power4+iu2_power4)\
46
                    |(du3_power4+du4_power4,lsu2_power4+iu1_power4)")
47
 
48
(define_reservation "iq_power4"
49
                    "(du1_power4,iu1_power4)\
50
                    |(du2_power4,iu2_power4)\
51
                    |(du3_power4,iu2_power4)\
52
                    |(du4_power4,iu1_power4)")
53
 
54
(define_reservation "fpq_power4"
55
                    "(du1_power4,fpu1_power4)\
56
                    |(du2_power4,fpu2_power4)\
57
                    |(du3_power4,fpu2_power4)\
58
                    |(du4_power4,fpu1_power4)")
59
 
60
(define_reservation "vq_power4"
61
                    "(du1_power4,vec_power4)\
62
                    |(du2_power4,vec_power4)\
63
                    |(du3_power4,vec_power4)\
64
                    |(du4_power4,vec_power4)")
65
 
66
(define_reservation "vpq_power4"
67
                    "(du1_power4,vecperm_power4)\
68
                    |(du2_power4,vecperm_power4)\
69
                    |(du3_power4,vecperm_power4)\
70
                    |(du4_power4,vecperm_power4)")
71
 
72
 
73
; Dispatch slots are allocated in order conforming to program order.
74
(absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
75
(absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
76
(absence_set "du3_power4" "du4_power4,du5_power4")
77
(absence_set "du4_power4" "du5_power4")
78
 
79
 
80
; Load/store
81
(define_insn_reservation "power4-load" 4 ; 3
82
  (and (eq_attr "type" "load")
83
       (eq_attr "cpu" "power4"))
84
  "lsq_power4")
85
 
86
(define_insn_reservation "power4-load-ext" 5
87
  (and (eq_attr "type" "load_ext")
88
       (eq_attr "cpu" "power4"))
89
  "(du1_power4+du2_power4,lsu1_power4,nothing,nothing,iu2_power4)\
90
  |(du2_power4+du3_power4,lsu2_power4,nothing,nothing,iu2_power4)\
91
  |(du3_power4+du4_power4,lsu2_power4,nothing,nothing,iu1_power4)")
92
 
93
(define_insn_reservation "power4-load-ext-update" 5
94
  (and (eq_attr "type" "load_ext_u")
95
       (eq_attr "cpu" "power4"))
96
  "du1_power4+du2_power4+du3_power4+du4_power4,\
97
   lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
98
 
99
(define_insn_reservation "power4-load-ext-update-indexed" 5
100
  (and (eq_attr "type" "load_ext_ux")
101
       (eq_attr "cpu" "power4"))
102
  "du1_power4+du2_power4+du3_power4+du4_power4,\
103
   iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
104
 
105
(define_insn_reservation "power4-load-update-indexed" 3
106
  (and (eq_attr "type" "load_ux")
107
       (eq_attr "cpu" "power4"))
108
  "du1_power4+du2_power4+du3_power4+du4_power4,\
109
   iu1_power4,lsu2_power4+iu2_power4")
110
 
111
(define_insn_reservation "power4-load-update" 4 ; 3
112
  (and (eq_attr "type" "load_u")
113
       (eq_attr "cpu" "power4"))
114
  "lsuq_power4")
115
 
116
(define_insn_reservation "power4-fpload" 6 ; 5
117
  (and (eq_attr "type" "fpload")
118
       (eq_attr "cpu" "power4"))
119
  "lsq_power4")
120
 
121
(define_insn_reservation "power4-fpload-update" 6 ; 5
122
  (and (eq_attr "type" "fpload_u,fpload_ux")
123
       (eq_attr "cpu" "power4"))
124
  "lsuq_power4")
125
 
126
(define_insn_reservation "power4-vecload" 6 ; 5
127
  (and (eq_attr "type" "vecload")
128
       (eq_attr "cpu" "power4"))
129
  "lsq_power4")
130
 
131
(define_insn_reservation "power4-store" 12
132
  (and (eq_attr "type" "store")
133
       (eq_attr "cpu" "power4"))
134
  "(du1_power4,lsu1_power4,iu1_power4)\
135
  |(du2_power4,lsu2_power4,iu2_power4)\
136
  |(du3_power4,lsu2_power4,iu2_power4)\
137
  |(du4_power4,lsu1_power4,iu1_power4)")
138
 
139
(define_insn_reservation "power4-store-update" 12
140
  (and (eq_attr "type" "store_u")
141
       (eq_attr "cpu" "power4"))
142
  "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\
143
  |(du2_power4+du3_power4,lsu2_power4+iu2_power4,iu2_power4)\
144
  |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\
145
  |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)")
146
 
147
(define_insn_reservation "power4-store-update-indexed" 12
148
  (and (eq_attr "type" "store_ux")
149
       (eq_attr "cpu" "power4"))
150
   "du1_power4+du2_power4+du3_power4+du4_power4,\
151
    iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
152
 
153
(define_insn_reservation "power4-fpstore" 12
154
  (and (eq_attr "type" "fpstore")
155
       (eq_attr "cpu" "power4"))
156
  "(du1_power4,lsu1_power4,fpu1_power4)\
157
  |(du2_power4,lsu2_power4,fpu2_power4)\
158
  |(du3_power4,lsu2_power4,fpu2_power4)\
159
  |(du4_power4,lsu1_power4,fpu1_power4)")
160
 
161
(define_insn_reservation "power4-fpstore-update" 12
162
  (and (eq_attr "type" "fpstore_u,fpstore_ux")
163
       (eq_attr "cpu" "power4"))
164
  "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\
165
  |(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\
166
  |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)")
167
 
168
(define_insn_reservation "power4-vecstore" 12
169
  (and (eq_attr "type" "vecstore")
170
       (eq_attr "cpu" "power4"))
171
  "(du1_power4,lsu1_power4,vec_power4)\
172
  |(du2_power4,lsu2_power4,vec_power4)\
173
  |(du3_power4,lsu2_power4,vec_power4)\
174
  |(du4_power4,lsu1_power4,vec_power4)")
175
 
176
(define_insn_reservation "power4-llsc" 11
177
  (and (eq_attr "type" "load_l,store_c,sync")
178
       (eq_attr "cpu" "power4"))
179
  "du1_power4+du2_power4+du3_power4+du4_power4,\
180
  lsu1_power4")
181
 
182
 
183
; Integer latency is 2 cycles
184
(define_insn_reservation "power4-integer" 2
185
  (and (eq_attr "type" "integer")
186
       (eq_attr "cpu" "power4"))
187
  "iq_power4")
188
 
189
(define_insn_reservation "power4-two" 2
190
  (and (eq_attr "type" "two")
191
       (eq_attr "cpu" "power4"))
192
  "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
193
  |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
194
  |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\
195
  |(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)")
196
 
197
(define_insn_reservation "power4-three" 2
198
  (and (eq_attr "type" "three")
199
       (eq_attr "cpu" "power4"))
200
  "(du1_power4+du2_power4+du3_power4,\
201
    iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
202
  |(du2_power4+du3_power4+du4_power4,\
203
    iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
204
  |(du3_power4+du4_power4+du1_power4,\
205
    iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
206
  |(du4_power4+du1_power4+du2_power4,\
207
    iu1_power4,nothing,iu2_power4,nothing,iu2_power4)")
208
 
209
(define_insn_reservation "power4-insert" 4
210
  (and (eq_attr "type" "insert_word")
211
       (eq_attr "cpu" "power4"))
212
  "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
213
  |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
214
  |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)")
215
 
216
(define_insn_reservation "power4-cmp" 3
217
  (and (eq_attr "type" "cmp,fast_compare")
218
       (eq_attr "cpu" "power4"))
219
  "iq_power4")
220
 
221
(define_insn_reservation "power4-compare" 2
222
  (and (eq_attr "type" "compare,delayed_compare")
223
       (eq_attr "cpu" "power4"))
224
  "(du1_power4+du2_power4,iu1_power4,iu2_power4)\
225
  |(du2_power4+du3_power4,iu2_power4,iu2_power4)\
226
  |(du3_power4+du4_power4,iu2_power4,iu1_power4)")
227
 
228
(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
229
 
230
(define_insn_reservation "power4-lmul-cmp" 7
231
  (and (eq_attr "type" "lmul_compare")
232
       (eq_attr "cpu" "power4"))
233
  "(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\
234
  |(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\
235
  |(du3_power4+du4_power4,iu2_power4*6,iu1_power4)")
236
 
237
(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
238
 
239
(define_insn_reservation "power4-imul-cmp" 5
240
  (and (eq_attr "type" "imul_compare")
241
       (eq_attr "cpu" "power4"))
242
  "(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\
243
  |(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\
244
  |(du3_power4+du4_power4,iu2_power4*4,iu1_power4)")
245
 
246
(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
247
 
248
(define_insn_reservation "power4-lmul" 7
249
  (and (eq_attr "type" "lmul")
250
       (eq_attr "cpu" "power4"))
251
  "(du1_power4,iu1_power4*6)\
252
  |(du2_power4,iu2_power4*6)\
253
  |(du3_power4,iu2_power4*6)\
254
  |(du4_power4,iu1_power4*6)")
255
 
256
(define_insn_reservation "power4-imul" 5
257
  (and (eq_attr "type" "imul")
258
       (eq_attr "cpu" "power4"))
259
  "(du1_power4,iu1_power4*4)\
260
  |(du2_power4,iu2_power4*4)\
261
  |(du3_power4,iu2_power4*4)\
262
  |(du4_power4,iu1_power4*4)")
263
 
264
(define_insn_reservation "power4-imul3" 4
265
  (and (eq_attr "type" "imul2,imul3")
266
       (eq_attr "cpu" "power4"))
267
  "(du1_power4,iu1_power4*3)\
268
  |(du2_power4,iu2_power4*3)\
269
  |(du3_power4,iu2_power4*3)\
270
  |(du4_power4,iu1_power4*3)")
271
 
272
 
273
; SPR move only executes in first IU.
274
; Integer division only executes in second IU.
275
(define_insn_reservation "power4-idiv" 36
276
  (and (eq_attr "type" "idiv")
277
       (eq_attr "cpu" "power4"))
278
  "du1_power4+du2_power4,iu2_power4*35")
279
 
280
(define_insn_reservation "power4-ldiv" 68
281
  (and (eq_attr "type" "ldiv")
282
       (eq_attr "cpu" "power4"))
283
  "du1_power4+du2_power4,iu2_power4*67")
284
 
285
 
286
(define_insn_reservation "power4-mtjmpr" 3
287
  (and (eq_attr "type" "mtjmpr,mfjmpr")
288
       (eq_attr "cpu" "power4"))
289
  "du1_power4,bpu_power4")
290
 
291
 
292
; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
293
; grabbing previous dispatch slots once this is assigned.
294
(define_insn_reservation "power4-branch" 2
295
  (and (eq_attr "type" "jmpreg,branch")
296
       (eq_attr "cpu" "power4"))
297
  "(du5_power4\
298
   |du4_power4+du5_power4\
299
   |du3_power4+du4_power4+du5_power4\
300
   |du2_power4+du3_power4+du4_power4+du5_power4\
301
   |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
302
 
303
 
304
; Condition Register logical ops are split if non-destructive (RT != RB)
305
(define_insn_reservation "power4-crlogical" 2
306
  (and (eq_attr "type" "cr_logical")
307
       (eq_attr "cpu" "power4"))
308
  "du1_power4,cru_power4")
309
 
310
(define_insn_reservation "power4-delayedcr" 4
311
  (and (eq_attr "type" "delayed_cr")
312
       (eq_attr "cpu" "power4"))
313
  "du1_power4+du2_power4,cru_power4,cru_power4")
314
 
315
; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
316
(define_insn_reservation "power4-mfcr" 6
317
  (and (eq_attr "type" "mfcr")
318
       (eq_attr "cpu" "power4"))
319
  "du1_power4+du2_power4+du3_power4+du4_power4,\
320
   du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
321
   cru_power4,cru_power4,cru_power4")
322
 
323
; mfcrf (1 field)
324
(define_insn_reservation "power4-mfcrf" 3
325
  (and (eq_attr "type" "mfcrf")
326
       (eq_attr "cpu" "power4"))
327
  "du1_power4,cru_power4")
328
 
329
; mtcrf (1 field)
330
(define_insn_reservation "power4-mtcr" 4
331
  (and (eq_attr "type" "mtcr")
332
       (eq_attr "cpu" "power4"))
333
  "du1_power4,iu1_power4")
334
 
335
; Basic FP latency is 6 cycles
336
(define_insn_reservation "power4-fp" 6
337
  (and (eq_attr "type" "fp,dmul")
338
       (eq_attr "cpu" "power4"))
339
  "fpq_power4")
340
 
341
(define_insn_reservation "power4-fpcompare" 5
342
  (and (eq_attr "type" "fpcompare")
343
       (eq_attr "cpu" "power4"))
344
  "fpq_power4")
345
 
346
(define_insn_reservation "power4-sdiv" 33
347
  (and (eq_attr "type" "sdiv,ddiv")
348
       (eq_attr "cpu" "power4"))
349
  "(du1_power4,fpu1_power4*28)\
350
  |(du2_power4,fpu2_power4*28)\
351
  |(du3_power4,fpu2_power4*28)\
352
  |(du4_power4,fpu1_power4*28)")
353
 
354
(define_insn_reservation "power4-sqrt" 40
355
  (and (eq_attr "type" "ssqrt,dsqrt")
356
       (eq_attr "cpu" "power4"))
357
  "(du1_power4,fpu1_power4*35)\
358
  |(du2_power4,fpu2_power4*35)\
359
  |(du3_power4,fpu2_power4*35)\
360
  |(du4_power4,fpu2_power4*35)")
361
 
362
(define_insn_reservation "power4-isync" 2
363
  (and (eq_attr "type" "isync")
364
       (eq_attr "cpu" "power4"))
365
  "du1_power4+du2_power4+du3_power4+du4_power4,\
366
  lsu1_power4")
367
 
368
 
369
; VMX
370
(define_insn_reservation "power4-vecsimple" 2
371
  (and (eq_attr "type" "vecsimple")
372
       (eq_attr "cpu" "power4"))
373
  "vq_power4")
374
 
375
(define_insn_reservation "power4-veccomplex" 5
376
  (and (eq_attr "type" "veccomplex")
377
       (eq_attr "cpu" "power4"))
378
  "vq_power4")
379
 
380
; vecfp compare
381
(define_insn_reservation "power4-veccmp" 8
382
  (and (eq_attr "type" "veccmp")
383
       (eq_attr "cpu" "power4"))
384
  "vq_power4")
385
 
386
(define_insn_reservation "power4-vecfloat" 8
387
  (and (eq_attr "type" "vecfloat")
388
       (eq_attr "cpu" "power4"))
389
  "vq_power4")
390
 
391
(define_insn_reservation "power4-vecperm" 2
392
  (and (eq_attr "type" "vecperm")
393
       (eq_attr "cpu" "power4"))
394
  "vpq_power4")
395
 
396
(define_bypass 4 "power4-vecload" "power4-vecperm")
397
 
398
(define_bypass 3 "power4-vecsimple" "power4-vecperm")
399
(define_bypass 6 "power4-veccomplex" "power4-vecperm")
400
(define_bypass 3 "power4-vecperm"
401
                 "power4-vecsimple,power4-veccomplex,power4-vecfloat")
402
(define_bypass 9 "power4-vecfloat" "power4-vecperm")
403
 
404
(define_bypass 5 "power4-vecsimple,power4-veccomplex"
405
                 "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
406
 
407
(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
408
(define_bypass 7 "power4-veccomplex" "power4-vecstore")
409
(define_bypass 10 "power4-vecfloat" "power4-vecstore")

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