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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [rs6000/] [power5.md] - Blame information for rev 816

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;; Scheduling description for IBM POWER5 processor.
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;;   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
3
;;
4
;; This file is part of GCC.
5
;;
6
;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
9
;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
15
;;
16
;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
19
 
20
;; Sources: IBM Red Book and White Paper on POWER5
21
 
22
;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
23
;; Instructions that update more than one register get broken into two
24
;; (split) or more internal ops.  The chip can issue up to 5
25
;; internal ops per cycle.
26
 
27
(define_automaton "power5iu,power5fpu,power5misc")
28
 
29
(define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
30
(define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
31
(define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
32
(define_cpu_unit "bpu_power5,cru_power5" "power5misc")
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(define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
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                 "power5misc")
35
 
36
(define_reservation "lsq_power5"
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                    "(du1_power5,lsu1_power5)\
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                    |(du2_power5,lsu2_power5)\
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                    |(du3_power5,lsu2_power5)\
40
                    |(du4_power5,lsu1_power5)")
41
 
42
(define_reservation "iq_power5"
43
                    "(du1_power5,iu1_power5)\
44
                    |(du2_power5,iu2_power5)\
45
                    |(du3_power5,iu2_power5)\
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                    |(du4_power5,iu1_power5)")
47
 
48
(define_reservation "fpq_power5"
49
                    "(du1_power5,fpu1_power5)\
50
                    |(du2_power5,fpu2_power5)\
51
                    |(du3_power5,fpu2_power5)\
52
                    |(du4_power5,fpu1_power5)")
53
 
54
; Dispatch slots are allocated in order conforming to program order.
55
(absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
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(absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
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(absence_set "du3_power5" "du4_power5,du5_power5")
58
(absence_set "du4_power5" "du5_power5")
59
 
60
 
61
; Load/store
62
(define_insn_reservation "power5-load" 4 ; 3
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  (and (eq_attr "type" "load")
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       (eq_attr "cpu" "power5"))
65
  "lsq_power5")
66
 
67
(define_insn_reservation "power5-load-ext" 5
68
  (and (eq_attr "type" "load_ext")
69
       (eq_attr "cpu" "power5"))
70
  "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
71
 
72
(define_insn_reservation "power5-load-ext-update" 5
73
  (and (eq_attr "type" "load_ext_u")
74
       (eq_attr "cpu" "power5"))
75
  "du1_power5+du2_power5+du3_power5+du4_power5,\
76
   lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
77
 
78
(define_insn_reservation "power5-load-ext-update-indexed" 5
79
  (and (eq_attr "type" "load_ext_ux")
80
       (eq_attr "cpu" "power5"))
81
  "du1_power5+du2_power5+du3_power5+du4_power5,\
82
   iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
83
 
84
(define_insn_reservation "power5-load-update-indexed" 3
85
  (and (eq_attr "type" "load_ux")
86
       (eq_attr "cpu" "power5"))
87
  "du1_power5+du2_power5+du3_power5+du4_power5,\
88
   iu1_power5,lsu2_power5+iu2_power5")
89
 
90
(define_insn_reservation "power5-load-update" 4 ; 3
91
  (and (eq_attr "type" "load_u")
92
       (eq_attr "cpu" "power5"))
93
  "du1_power5+du2_power5,lsu1_power5+iu2_power5")
94
 
95
(define_insn_reservation "power5-fpload" 6 ; 5
96
  (and (eq_attr "type" "fpload")
97
       (eq_attr "cpu" "power5"))
98
  "lsq_power5")
99
 
100
(define_insn_reservation "power5-fpload-update" 6 ; 5
101
  (and (eq_attr "type" "fpload_u,fpload_ux")
102
       (eq_attr "cpu" "power5"))
103
  "du1_power5+du2_power5,lsu1_power5+iu2_power5")
104
 
105
(define_insn_reservation "power5-store" 12
106
  (and (eq_attr "type" "store")
107
       (eq_attr "cpu" "power5"))
108
  "(du1_power5,lsu1_power5,iu1_power5)\
109
  |(du2_power5,lsu2_power5,iu2_power5)\
110
  |(du3_power5,lsu2_power5,iu2_power5)\
111
  |(du4_power5,lsu1_power5,iu1_power5)")
112
 
113
(define_insn_reservation "power5-store-update" 12
114
  (and (eq_attr "type" "store_u")
115
       (eq_attr "cpu" "power5"))
116
  "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
117
 
118
(define_insn_reservation "power5-store-update-indexed" 12
119
  (and (eq_attr "type" "store_ux")
120
       (eq_attr "cpu" "power5"))
121
   "du1_power5+du2_power5+du3_power5+du4_power5,\
122
    iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
123
 
124
(define_insn_reservation "power5-fpstore" 12
125
  (and (eq_attr "type" "fpstore")
126
       (eq_attr "cpu" "power5"))
127
  "(du1_power5,lsu1_power5,fpu1_power5)\
128
  |(du2_power5,lsu2_power5,fpu2_power5)\
129
  |(du3_power5,lsu2_power5,fpu2_power5)\
130
  |(du4_power5,lsu1_power5,fpu1_power5)")
131
 
132
(define_insn_reservation "power5-fpstore-update" 12
133
  (and (eq_attr "type" "fpstore_u,fpstore_ux")
134
       (eq_attr "cpu" "power5"))
135
  "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
136
 
137
(define_insn_reservation "power5-llsc" 11
138
  (and (eq_attr "type" "load_l,store_c,sync")
139
       (eq_attr "cpu" "power5"))
140
  "du1_power5+du2_power5+du3_power5+du4_power5,\
141
  lsu1_power5")
142
 
143
 
144
; Integer latency is 2 cycles
145
(define_insn_reservation "power5-integer" 2
146
  (and (eq_attr "type" "integer")
147
       (eq_attr "cpu" "power5"))
148
  "iq_power5")
149
 
150
(define_insn_reservation "power5-two" 2
151
  (and (eq_attr "type" "two")
152
       (eq_attr "cpu" "power5"))
153
  "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\
154
  |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\
155
  |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\
156
  |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)")
157
 
158
(define_insn_reservation "power5-three" 2
159
  (and (eq_attr "type" "three")
160
       (eq_attr "cpu" "power5"))
161
  "(du1_power5+du2_power5+du3_power5,\
162
    iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
163
  |(du2_power5+du3_power5+du4_power5,\
164
    iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
165
  |(du3_power5+du4_power5+du1_power5,\
166
    iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
167
  |(du4_power5+du1_power5+du2_power5,\
168
    iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
169
 
170
(define_insn_reservation "power5-insert" 4
171
  (and (eq_attr "type" "insert_word")
172
       (eq_attr "cpu" "power5"))
173
  "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
174
 
175
(define_insn_reservation "power5-cmp" 3
176
  (and (eq_attr "type" "cmp,fast_compare")
177
       (eq_attr "cpu" "power5"))
178
  "iq_power5")
179
 
180
(define_insn_reservation "power5-compare" 2
181
  (and (eq_attr "type" "compare,delayed_compare")
182
       (eq_attr "cpu" "power5"))
183
  "du1_power5+du2_power5,iu1_power5,iu2_power5")
184
 
185
(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
186
 
187
(define_insn_reservation "power5-lmul-cmp" 7
188
  (and (eq_attr "type" "lmul_compare")
189
       (eq_attr "cpu" "power5"))
190
  "du1_power5+du2_power5,iu1_power5*6,iu2_power5")
191
 
192
(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
193
 
194
(define_insn_reservation "power5-imul-cmp" 5
195
  (and (eq_attr "type" "imul_compare")
196
       (eq_attr "cpu" "power5"))
197
  "du1_power5+du2_power5,iu1_power5*4,iu2_power5")
198
 
199
(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
200
 
201
(define_insn_reservation "power5-lmul" 7
202
  (and (eq_attr "type" "lmul")
203
       (eq_attr "cpu" "power5"))
204
  "(du1_power5,iu1_power5*6)\
205
  |(du2_power5,iu2_power5*6)\
206
  |(du3_power5,iu2_power5*6)\
207
  |(du4_power5,iu1_power5*6)")
208
 
209
(define_insn_reservation "power5-imul" 5
210
  (and (eq_attr "type" "imul")
211
       (eq_attr "cpu" "power5"))
212
  "(du1_power5,iu1_power5*4)\
213
  |(du2_power5,iu2_power5*4)\
214
  |(du3_power5,iu2_power5*4)\
215
  |(du4_power5,iu1_power5*4)")
216
 
217
(define_insn_reservation "power5-imul3" 4
218
  (and (eq_attr "type" "imul2,imul3")
219
       (eq_attr "cpu" "power5"))
220
  "(du1_power5,iu1_power5*3)\
221
  |(du2_power5,iu2_power5*3)\
222
  |(du3_power5,iu2_power5*3)\
223
  |(du4_power5,iu1_power5*3)")
224
 
225
 
226
; SPR move only executes in first IU.
227
; Integer division only executes in second IU.
228
(define_insn_reservation "power5-idiv" 36
229
  (and (eq_attr "type" "idiv")
230
       (eq_attr "cpu" "power5"))
231
  "du1_power5+du2_power5,iu2_power5*35")
232
 
233
(define_insn_reservation "power5-ldiv" 68
234
  (and (eq_attr "type" "ldiv")
235
       (eq_attr "cpu" "power5"))
236
  "du1_power5+du2_power5,iu2_power5*67")
237
 
238
 
239
(define_insn_reservation "power5-mtjmpr" 3
240
  (and (eq_attr "type" "mtjmpr,mfjmpr")
241
       (eq_attr "cpu" "power5"))
242
  "du1_power5,bpu_power5")
243
 
244
 
245
; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
246
; grabbing previous dispatch slots once this is assigned.
247
(define_insn_reservation "power5-branch" 2
248
  (and (eq_attr "type" "jmpreg,branch")
249
       (eq_attr "cpu" "power5"))
250
  "(du5_power5\
251
   |du4_power5+du5_power5\
252
   |du3_power5+du4_power5+du5_power5\
253
   |du2_power5+du3_power5+du4_power5+du5_power5\
254
   |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
255
 
256
 
257
; Condition Register logical ops are split if non-destructive (RT != RB)
258
(define_insn_reservation "power5-crlogical" 2
259
  (and (eq_attr "type" "cr_logical")
260
       (eq_attr "cpu" "power5"))
261
  "du1_power5,cru_power5")
262
 
263
(define_insn_reservation "power5-delayedcr" 4
264
  (and (eq_attr "type" "delayed_cr")
265
       (eq_attr "cpu" "power5"))
266
  "du1_power5+du2_power5,cru_power5,cru_power5")
267
 
268
; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
269
(define_insn_reservation "power5-mfcr" 6
270
  (and (eq_attr "type" "mfcr")
271
       (eq_attr "cpu" "power5"))
272
  "du1_power5+du2_power5+du3_power5+du4_power5,\
273
   du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
274
   cru_power5,cru_power5,cru_power5")
275
 
276
; mfcrf (1 field)
277
(define_insn_reservation "power5-mfcrf" 3
278
  (and (eq_attr "type" "mfcrf")
279
       (eq_attr "cpu" "power5"))
280
  "du1_power5,cru_power5")
281
 
282
; mtcrf (1 field)
283
(define_insn_reservation "power5-mtcr" 4
284
  (and (eq_attr "type" "mtcr")
285
       (eq_attr "cpu" "power5"))
286
  "du1_power5,iu1_power5")
287
 
288
; Basic FP latency is 6 cycles
289
(define_insn_reservation "power5-fp" 6
290
  (and (eq_attr "type" "fp,dmul")
291
       (eq_attr "cpu" "power5"))
292
  "fpq_power5")
293
 
294
(define_insn_reservation "power5-fpcompare" 5
295
  (and (eq_attr "type" "fpcompare")
296
       (eq_attr "cpu" "power5"))
297
  "fpq_power5")
298
 
299
(define_insn_reservation "power5-sdiv" 33
300
  (and (eq_attr "type" "sdiv,ddiv")
301
       (eq_attr "cpu" "power5"))
302
  "(du1_power5,fpu1_power5*28)\
303
  |(du2_power5,fpu2_power5*28)\
304
  |(du3_power5,fpu2_power5*28)\
305
  |(du4_power5,fpu1_power5*28)")
306
 
307
(define_insn_reservation "power5-sqrt" 40
308
  (and (eq_attr "type" "ssqrt,dsqrt")
309
       (eq_attr "cpu" "power5"))
310
  "(du1_power5,fpu1_power5*35)\
311
  |(du2_power5,fpu2_power5*35)\
312
  |(du3_power5,fpu2_power5*35)\
313
  |(du4_power5,fpu2_power5*35)")
314
 
315
(define_insn_reservation "power5-isync" 2
316
  (and (eq_attr "type" "isync")
317
       (eq_attr "cpu" "power5"))
318
  "du1_power5+du2_power5+du3_power5+du4_power5,\
319
  lsu1_power5")
320
 

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