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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [rs6000/] [rs6000.md] - Blame information for rev 816

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1 38 julius 
;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 
;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 
;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 
;; Free Software Foundation, Inc.
5 
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 
 
7 
;; This file is part of GCC.
8 
 
9 
;; GCC is free software; you can redistribute it and/or modify it
10 
;; under the terms of the GNU General Public License as published
11 
;; by the Free Software Foundation; either version 3, or (at your
12 
;; option) any later version.
13 
 
14 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
;; License for more details.
18 
 
19 
;; You should have received a copy of the GNU General Public License
20 
;; along with GCC; see the file COPYING3.  If not see
21 
;; .
22 
 
23 
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 
 
25 
;;
26 
;; UNSPEC usage
27 
;;
28 
 
29 
(define_constants
30 
  [(UNSPEC_FRSP                 0)      ; frsp for POWER machines
31 
   (UNSPEC_TIE                  5)      ; tie stack contents and stack pointer
32 
   (UNSPEC_TOCPTR               6)      ; address of a word pointing to the TOC
33 
   (UNSPEC_TOC                  7)      ; address of the TOC (more-or-less)
34 
   (UNSPEC_MOVSI_GOT            8)
35 
   (UNSPEC_MV_CR_OV             9)      ; move_from_CR_ov_bit
36 
   (UNSPEC_FCTIWZ               10)
37 
   (UNSPEC_FRIM                 11)
38 
   (UNSPEC_FRIN                 12)
39 
   (UNSPEC_FRIP                 13)
40 
   (UNSPEC_FRIZ                 14)
41 
   (UNSPEC_LD_MPIC              15)     ; load_macho_picbase
42 
   (UNSPEC_MPIC_CORRECT         16)     ; macho_correct_pic
43 
   (UNSPEC_TLSGD                17)
44 
   (UNSPEC_TLSLD                18)
45 
   (UNSPEC_MOVESI_FROM_CR       19)
46 
   (UNSPEC_MOVESI_TO_CR         20)
47 
   (UNSPEC_TLSDTPREL            21)
48 
   (UNSPEC_TLSDTPRELHA          22)
49 
   (UNSPEC_TLSDTPRELLO          23)
50 
   (UNSPEC_TLSGOTDTPREL         24)
51 
   (UNSPEC_TLSTPREL             25)
52 
   (UNSPEC_TLSTPRELHA           26)
53 
   (UNSPEC_TLSTPRELLO           27)
54 
   (UNSPEC_TLSGOTTPREL          28)
55 
   (UNSPEC_TLSTLS               29)
56 
   (UNSPEC_FIX_TRUNC_TF         30)     ; fadd, rounding towards zero
57 
   (UNSPEC_MV_CR_GT             31)     ; move_from_CR_gt_bit
58 
   (UNSPEC_STFIWX               32)
59 
   (UNSPEC_POPCNTB              33)
60 
   (UNSPEC_FRES                 34)
61 
   (UNSPEC_SP_SET               35)
62 
   (UNSPEC_SP_TEST              36)
63 
   (UNSPEC_SYNC                 37)
64 
   (UNSPEC_LWSYNC               38)
65 
   (UNSPEC_ISYNC                39)
66 
   (UNSPEC_SYNC_OP              40)
67 
   (UNSPEC_ATOMIC               41)
68 
   (UNSPEC_CMPXCHG              42)
69 
   (UNSPEC_XCHG                 43)
70 
   (UNSPEC_AND                  44)
71 
   (UNSPEC_DLMZB                45)
72 
   (UNSPEC_DLMZB_CR             46)
73 
   (UNSPEC_DLMZB_STRLEN         47)
74 
  ])
75 
 
76 
;;
77 
;; UNSPEC_VOLATILE usage
78 
;;
79 
 
80 
(define_constants
81 
  [(UNSPECV_BLOCK               0)
82 
   (UNSPECV_LL                  1)      ; load-locked
83 
   (UNSPECV_SC                  2)      ; store-conditional
84 
   (UNSPECV_EH_RR               9)      ; eh_reg_restore
85 
  ])
86 
 
87 
;; Define an insn type attribute.  This is used in function unit delay
88 
;; computations.
89 
(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
90 
  (const_string "integer"))
91 
 
92 
;; Length (in bytes).
93 
; '(pc)' in the following doesn't include the instruction itself; it is
94 
; calculated as if the instruction had zero size.
95 
(define_attr "length" ""
96 
  (if_then_else (eq_attr "type" "branch")
97 
                (if_then_else (and (ge (minus (match_dup 0) (pc))
98 
                                       (const_int -32768))
99 
                                   (lt (minus (match_dup 0) (pc))
100 
                                       (const_int 32764)))
101 
                              (const_int 4)
102 
                              (const_int 8))
103 
                (const_int 4)))
104 
 
105 
;; Processor type -- this attribute must exactly match the processor_type
106 
;; enumeration in rs6000.h.
107 
 
108 
(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
109 
  (const (symbol_ref "rs6000_cpu_attr")))
110 
 
111 
(automata_option "ndfa")
112 
 
113 
(include "rios1.md")
114 
(include "rios2.md")
115 
(include "rs64.md")
116 
(include "mpc.md")
117 
(include "40x.md")
118 
(include "440.md")
119 
(include "603.md")
120 
(include "6xx.md")
121 
(include "7xx.md")
122 
(include "7450.md")
123 
(include "8540.md")
124 
(include "power4.md")
125 
(include "power5.md")
126 
 
127 
(include "predicates.md")
128 
(include "constraints.md")
129 
 
130 
(include "darwin.md")
131 
 
132 
 
133 
;; Mode macros
134 
 
135 
; This mode macro allows :GPR to be used to indicate the allowable size
136 
; of whole values in GPRs.
137 
(define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
138 
 
139 
; Any supported integer mode.
140 
(define_mode_macro INT [QI HI SI DI TI])
141 
 
142 
; Any supported integer mode that fits in one register.
143 
(define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
144 
 
145 
; extend modes for DImode
146 
(define_mode_macro QHSI [QI HI SI])
147 
 
148 
; SImode or DImode, even if DImode doesn't fit in GPRs.
149 
(define_mode_macro SDI [SI DI])
150 
 
151 
; The size of a pointer.  Also, the size of the value that a record-condition
152 
; (one with a '.') will compare.
153 
(define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
154 
 
155 
; Any hardware-supported floating-point mode
156 
(define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
157 
  (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
158 
  (TF "!TARGET_IEEEQUAD
159 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
160 
 
161 
; Various instructions that come in SI and DI forms.
162 
; A generic w/d attribute, for things like cmpw/cmpd.
163 
(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
164 
 
165 
; DImode bits
166 
(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
167 
 
168 
 
169 
;; Start with fixed-point load and store insns.  Here we put only the more
170 
;; complex forms.  Basic data transfer is done later.
171 
 
172 
(define_expand "zero_extenddi2"
173 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
174 
        (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
175 
  "TARGET_POWERPC64"
176 
  "")
177 
 
178 
(define_insn "*zero_extenddi2_internal1"
179 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
180 
        (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
181 
  "TARGET_POWERPC64"
182 
  "@
183 
   lz%U1%X1 %0,%1
184 
   rldicl %0,%1,0,"
185 
  [(set_attr "type" "load,*")])
186 
 
187 
(define_insn "*zero_extenddi2_internal2"
188 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
189 
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
190 
                    (const_int 0)))
191 
   (clobber (match_scratch:DI 2 "=r,r"))]
192 
  "TARGET_64BIT"
193 
  "@
194 
   rldicl. %2,%1,0,
195 
   #"
196 
  [(set_attr "type" "compare")
197 
   (set_attr "length" "4,8")])
198 
 
199 
(define_split
200 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
201 
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
202 
                    (const_int 0)))
203 
   (clobber (match_scratch:DI 2 ""))]
204 
  "TARGET_POWERPC64 && reload_completed"
205 
  [(set (match_dup 2)
206 
        (zero_extend:DI (match_dup 1)))
207 
   (set (match_dup 0)
208 
        (compare:CC (match_dup 2)
209 
                    (const_int 0)))]
210 
  "")
211 
 
212 
(define_insn "*zero_extenddi2_internal3"
213 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
214 
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
215 
                    (const_int 0)))
216 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
217 
        (zero_extend:DI (match_dup 1)))]
218 
  "TARGET_64BIT"
219 
  "@
220 
   rldicl. %0,%1,0,
221 
   #"
222 
  [(set_attr "type" "compare")
223 
   (set_attr "length" "4,8")])
224 
 
225 
(define_split
226 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
227 
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
228 
                    (const_int 0)))
229 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
230 
        (zero_extend:DI (match_dup 1)))]
231 
  "TARGET_POWERPC64 && reload_completed"
232 
  [(set (match_dup 0)
233 
        (zero_extend:DI (match_dup 1)))
234 
   (set (match_dup 2)
235 
        (compare:CC (match_dup 0)
236 
                    (const_int 0)))]
237 
  "")
238 
 
239 
(define_insn "extendqidi2"
240 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
241 
        (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
242 
  "TARGET_POWERPC64"
243 
  "extsb %0,%1")
244 
 
245 
(define_insn ""
246 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
247 
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
248 
                    (const_int 0)))
249 
   (clobber (match_scratch:DI 2 "=r,r"))]
250 
  "TARGET_64BIT"
251 
  "@
252 
   extsb. %2,%1
253 
   #"
254 
  [(set_attr "type" "compare")
255 
   (set_attr "length" "4,8")])
256 
 
257 
(define_split
258 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
259 
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
260 
                    (const_int 0)))
261 
   (clobber (match_scratch:DI 2 ""))]
262 
  "TARGET_POWERPC64 && reload_completed"
263 
  [(set (match_dup 2)
264 
        (sign_extend:DI (match_dup 1)))
265 
   (set (match_dup 0)
266 
        (compare:CC (match_dup 2)
267 
                    (const_int 0)))]
268 
  "")
269 
 
270 
(define_insn ""
271 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
272 
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
273 
                    (const_int 0)))
274 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
275 
        (sign_extend:DI (match_dup 1)))]
276 
  "TARGET_64BIT"
277 
  "@
278 
   extsb. %0,%1
279 
   #"
280 
  [(set_attr "type" "compare")
281 
   (set_attr "length" "4,8")])
282 
 
283 
(define_split
284 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
285 
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
286 
                    (const_int 0)))
287 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
288 
        (sign_extend:DI (match_dup 1)))]
289 
  "TARGET_POWERPC64 && reload_completed"
290 
  [(set (match_dup 0)
291 
        (sign_extend:DI (match_dup 1)))
292 
   (set (match_dup 2)
293 
        (compare:CC (match_dup 0)
294 
                    (const_int 0)))]
295 
  "")
296 
 
297 
(define_expand "extendhidi2"
298 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
299 
        (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
300 
  "TARGET_POWERPC64"
301 
  "")
302 
 
303 
(define_insn ""
304 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
305 
        (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
306 
  "TARGET_POWERPC64"
307 
  "@
308 
   lha%U1%X1 %0,%1
309 
   extsh %0,%1"
310 
  [(set_attr "type" "load_ext,*")])
311 
 
312 
(define_insn ""
313 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
314 
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
315 
                    (const_int 0)))
316 
   (clobber (match_scratch:DI 2 "=r,r"))]
317 
  "TARGET_64BIT"
318 
  "@
319 
   extsh. %2,%1
320 
   #"
321 
  [(set_attr "type" "compare")
322 
   (set_attr "length" "4,8")])
323 
 
324 
(define_split
325 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
326 
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
327 
                    (const_int 0)))
328 
   (clobber (match_scratch:DI 2 ""))]
329 
  "TARGET_POWERPC64 && reload_completed"
330 
  [(set (match_dup 2)
331 
        (sign_extend:DI (match_dup 1)))
332 
   (set (match_dup 0)
333 
        (compare:CC (match_dup 2)
334 
                    (const_int 0)))]
335 
  "")
336 
 
337 
(define_insn ""
338 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
339 
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
340 
                    (const_int 0)))
341 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
342 
        (sign_extend:DI (match_dup 1)))]
343 
  "TARGET_64BIT"
344 
  "@
345 
   extsh. %0,%1
346 
   #"
347 
  [(set_attr "type" "compare")
348 
   (set_attr "length" "4,8")])
349 
 
350 
(define_split
351 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
352 
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
353 
                    (const_int 0)))
354 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
355 
        (sign_extend:DI (match_dup 1)))]
356 
  "TARGET_POWERPC64 && reload_completed"
357 
  [(set (match_dup 0)
358 
        (sign_extend:DI (match_dup 1)))
359 
   (set (match_dup 2)
360 
        (compare:CC (match_dup 0)
361 
                    (const_int 0)))]
362 
  "")
363 
 
364 
(define_expand "extendsidi2"
365 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
366 
        (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
367 
  "TARGET_POWERPC64"
368 
  "")
369 
 
370 
(define_insn ""
371 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
372 
        (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
373 
  "TARGET_POWERPC64"
374 
  "@
375 
   lwa%U1%X1 %0,%1
376 
   extsw %0,%1"
377 
  [(set_attr "type" "load_ext,*")])
378 
 
379 
(define_insn ""
380 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
381 
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
382 
                    (const_int 0)))
383 
   (clobber (match_scratch:DI 2 "=r,r"))]
384 
  "TARGET_64BIT"
385 
  "@
386 
   extsw. %2,%1
387 
   #"
388 
  [(set_attr "type" "compare")
389 
   (set_attr "length" "4,8")])
390 
 
391 
(define_split
392 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
393 
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
394 
                    (const_int 0)))
395 
   (clobber (match_scratch:DI 2 ""))]
396 
  "TARGET_POWERPC64 && reload_completed"
397 
  [(set (match_dup 2)
398 
        (sign_extend:DI (match_dup 1)))
399 
   (set (match_dup 0)
400 
        (compare:CC (match_dup 2)
401 
                    (const_int 0)))]
402 
  "")
403 
 
404 
(define_insn ""
405 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
406 
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
407 
                    (const_int 0)))
408 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
409 
        (sign_extend:DI (match_dup 1)))]
410 
  "TARGET_64BIT"
411 
  "@
412 
   extsw. %0,%1
413 
   #"
414 
  [(set_attr "type" "compare")
415 
   (set_attr "length" "4,8")])
416 
 
417 
(define_split
418 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
419 
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
420 
                    (const_int 0)))
421 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
422 
        (sign_extend:DI (match_dup 1)))]
423 
  "TARGET_POWERPC64 && reload_completed"
424 
  [(set (match_dup 0)
425 
        (sign_extend:DI (match_dup 1)))
426 
   (set (match_dup 2)
427 
        (compare:CC (match_dup 0)
428 
                    (const_int 0)))]
429 
  "")
430 
 
431 
(define_expand "zero_extendqisi2"
432 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
433 
        (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
434 
  ""
435 
  "")
436 
 
437 
(define_insn ""
438 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
439 
        (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
440 
  ""
441 
  "@
442 
   lbz%U1%X1 %0,%1
443 
   {rlinm|rlwinm} %0,%1,0,0xff"
444 
  [(set_attr "type" "load,*")])
445 
 
446 
(define_insn ""
447 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
448 
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
449 
                    (const_int 0)))
450 
   (clobber (match_scratch:SI 2 "=r,r"))]
451 
  ""
452 
  "@
453 
   {andil.|andi.} %2,%1,0xff
454 
   #"
455 
  [(set_attr "type" "compare")
456 
   (set_attr "length" "4,8")])
457 
 
458 
(define_split
459 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
460 
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
461 
                    (const_int 0)))
462 
   (clobber (match_scratch:SI 2 ""))]
463 
  "reload_completed"
464 
  [(set (match_dup 2)
465 
        (zero_extend:SI (match_dup 1)))
466 
   (set (match_dup 0)
467 
        (compare:CC (match_dup 2)
468 
                    (const_int 0)))]
469 
  "")
470 
 
471 
(define_insn ""
472 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
473 
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
474 
                    (const_int 0)))
475 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
476 
        (zero_extend:SI (match_dup 1)))]
477 
  ""
478 
  "@
479 
   {andil.|andi.} %0,%1,0xff
480 
   #"
481 
  [(set_attr "type" "compare")
482 
   (set_attr "length" "4,8")])
483 
 
484 
(define_split
485 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
486 
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
487 
                    (const_int 0)))
488 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
489 
        (zero_extend:SI (match_dup 1)))]
490 
  "reload_completed"
491 
  [(set (match_dup 0)
492 
        (zero_extend:SI (match_dup 1)))
493 
   (set (match_dup 2)
494 
        (compare:CC (match_dup 0)
495 
                    (const_int 0)))]
496 
  "")
497 
 
498 
(define_expand "extendqisi2"
499 
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
500 
   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
501 
  ""
502 
  "
503 
{
504 
  if (TARGET_POWERPC)
505 
    emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
506 
  else if (TARGET_POWER)
507 
    emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
508 
  else
509 
    emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
510 
  DONE;
511 
}")
512 
 
513 
(define_insn "extendqisi2_ppc"
514 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
515 
        (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
516 
  "TARGET_POWERPC"
517 
  "extsb %0,%1")
518 
 
519 
(define_insn ""
520 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
521 
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
522 
                    (const_int 0)))
523 
   (clobber (match_scratch:SI 2 "=r,r"))]
524 
  "TARGET_POWERPC"
525 
  "@
526 
   extsb. %2,%1
527 
   #"
528 
  [(set_attr "type" "compare")
529 
   (set_attr "length" "4,8")])
530 
 
531 
(define_split
532 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
533 
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
534 
                    (const_int 0)))
535 
   (clobber (match_scratch:SI 2 ""))]
536 
  "TARGET_POWERPC && reload_completed"
537 
  [(set (match_dup 2)
538 
        (sign_extend:SI (match_dup 1)))
539 
   (set (match_dup 0)
540 
        (compare:CC (match_dup 2)
541 
                    (const_int 0)))]
542 
  "")
543 
 
544 
(define_insn ""
545 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
546 
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
547 
                    (const_int 0)))
548 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
549 
        (sign_extend:SI (match_dup 1)))]
550 
  "TARGET_POWERPC"
551 
  "@
552 
   extsb. %0,%1
553 
   #"
554 
  [(set_attr "type" "compare")
555 
   (set_attr "length" "4,8")])
556 
 
557 
(define_split
558 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
559 
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
560 
                    (const_int 0)))
561 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
562 
        (sign_extend:SI (match_dup 1)))]
563 
  "TARGET_POWERPC && reload_completed"
564 
  [(set (match_dup 0)
565 
        (sign_extend:SI (match_dup 1)))
566 
   (set (match_dup 2)
567 
        (compare:CC (match_dup 0)
568 
                    (const_int 0)))]
569 
  "")
570 
 
571 
(define_expand "extendqisi2_power"
572 
  [(parallel [(set (match_dup 2)
573 
                   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
574 
                              (const_int 24)))
575 
              (clobber (scratch:SI))])
576 
   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
577 
                   (ashiftrt:SI (match_dup 2)
578 
                                (const_int 24)))
579 
              (clobber (scratch:SI))])]
580 
  "TARGET_POWER"
581 
  "
582 
{ operands[1] = gen_lowpart (SImode, operands[1]);
583 
  operands[2] = gen_reg_rtx (SImode); }")
584 
 
585 
(define_expand "extendqisi2_no_power"
586 
  [(set (match_dup 2)
587 
        (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
588 
                   (const_int 24)))
589 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
590 
        (ashiftrt:SI (match_dup 2)
591 
                     (const_int 24)))]
592 
  "! TARGET_POWER && ! TARGET_POWERPC"
593 
  "
594 
{ operands[1] = gen_lowpart (SImode, operands[1]);
595 
  operands[2] = gen_reg_rtx (SImode); }")
596 
 
597 
(define_expand "zero_extendqihi2"
598 
  [(set (match_operand:HI 0 "gpc_reg_operand" "")
599 
        (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
600 
  ""
601 
  "")
602 
 
603 
(define_insn ""
604 
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
605 
        (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
606 
  ""
607 
  "@
608 
   lbz%U1%X1 %0,%1
609 
   {rlinm|rlwinm} %0,%1,0,0xff"
610 
  [(set_attr "type" "load,*")])
611 
 
612 
(define_insn ""
613 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
614 
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
615 
                    (const_int 0)))
616 
   (clobber (match_scratch:HI 2 "=r,r"))]
617 
  ""
618 
  "@
619 
   {andil.|andi.} %2,%1,0xff
620 
   #"
621 
  [(set_attr "type" "compare")
622 
   (set_attr "length" "4,8")])
623 
 
624 
(define_split
625 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
626 
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
627 
                    (const_int 0)))
628 
   (clobber (match_scratch:HI 2 ""))]
629 
  "reload_completed"
630 
  [(set (match_dup 2)
631 
        (zero_extend:HI (match_dup 1)))
632 
   (set (match_dup 0)
633 
        (compare:CC (match_dup 2)
634 
                    (const_int 0)))]
635 
  "")
636 
 
637 
(define_insn ""
638 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
639 
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
640 
                    (const_int 0)))
641 
   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
642 
        (zero_extend:HI (match_dup 1)))]
643 
  ""
644 
  "@
645 
   {andil.|andi.} %0,%1,0xff
646 
   #"
647 
  [(set_attr "type" "compare")
648 
   (set_attr "length" "4,8")])
649 
 
650 
(define_split
651 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
652 
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
653 
                    (const_int 0)))
654 
   (set (match_operand:HI 0 "gpc_reg_operand" "")
655 
        (zero_extend:HI (match_dup 1)))]
656 
  "reload_completed"
657 
  [(set (match_dup 0)
658 
        (zero_extend:HI (match_dup 1)))
659 
   (set (match_dup 2)
660 
        (compare:CC (match_dup 0)
661 
                    (const_int 0)))]
662 
  "")
663 
 
664 
(define_expand "extendqihi2"
665 
  [(use (match_operand:HI 0 "gpc_reg_operand" ""))
666 
   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
667 
  ""
668 
  "
669 
{
670 
  if (TARGET_POWERPC)
671 
    emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
672 
  else if (TARGET_POWER)
673 
    emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
674 
  else
675 
    emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
676 
  DONE;
677 
}")
678 
 
679 
(define_insn "extendqihi2_ppc"
680 
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
681 
        (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
682 
  "TARGET_POWERPC"
683 
  "extsb %0,%1")
684 
 
685 
(define_insn ""
686 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
687 
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
688 
                    (const_int 0)))
689 
   (clobber (match_scratch:HI 2 "=r,r"))]
690 
  "TARGET_POWERPC"
691 
  "@
692 
   extsb. %2,%1
693 
   #"
694 
  [(set_attr "type" "compare")
695 
   (set_attr "length" "4,8")])
696 
 
697 
(define_split
698 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
699 
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
700 
                    (const_int 0)))
701 
   (clobber (match_scratch:HI 2 ""))]
702 
  "TARGET_POWERPC && reload_completed"
703 
  [(set (match_dup 2)
704 
        (sign_extend:HI (match_dup 1)))
705 
   (set (match_dup 0)
706 
        (compare:CC (match_dup 2)
707 
                    (const_int 0)))]
708 
  "")
709 
 
710 
(define_insn ""
711 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
712 
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
713 
                    (const_int 0)))
714 
   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
715 
        (sign_extend:HI (match_dup 1)))]
716 
  "TARGET_POWERPC"
717 
  "@
718 
   extsb. %0,%1
719 
   #"
720 
  [(set_attr "type" "compare")
721 
   (set_attr "length" "4,8")])
722 
 
723 
(define_split
724 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
725 
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
726 
                    (const_int 0)))
727 
   (set (match_operand:HI 0 "gpc_reg_operand" "")
728 
        (sign_extend:HI (match_dup 1)))]
729 
  "TARGET_POWERPC && reload_completed"
730 
  [(set (match_dup 0)
731 
        (sign_extend:HI (match_dup 1)))
732 
   (set (match_dup 2)
733 
        (compare:CC (match_dup 0)
734 
                    (const_int 0)))]
735 
  "")
736 
 
737 
(define_expand "extendqihi2_power"
738 
  [(parallel [(set (match_dup 2)
739 
                   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
740 
                              (const_int 24)))
741 
              (clobber (scratch:SI))])
742 
   (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
743 
                   (ashiftrt:SI (match_dup 2)
744 
                                (const_int 24)))
745 
              (clobber (scratch:SI))])]
746 
  "TARGET_POWER"
747 
  "
748 
{ operands[0] = gen_lowpart (SImode, operands[0]);
749 
  operands[1] = gen_lowpart (SImode, operands[1]);
750 
  operands[2] = gen_reg_rtx (SImode); }")
751 
 
752 
(define_expand "extendqihi2_no_power"
753 
  [(set (match_dup 2)
754 
        (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
755 
                   (const_int 24)))
756 
   (set (match_operand:HI 0 "gpc_reg_operand" "")
757 
        (ashiftrt:SI (match_dup 2)
758 
                     (const_int 24)))]
759 
  "! TARGET_POWER && ! TARGET_POWERPC"
760 
  "
761 
{ operands[0] = gen_lowpart (SImode, operands[0]);
762 
  operands[1] = gen_lowpart (SImode, operands[1]);
763 
  operands[2] = gen_reg_rtx (SImode); }")
764 
 
765 
(define_expand "zero_extendhisi2"
766 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
767 
        (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
768 
  ""
769 
  "")
770 
 
771 
(define_insn ""
772 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
773 
        (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
774 
  ""
775 
  "@
776 
   lhz%U1%X1 %0,%1
777 
   {rlinm|rlwinm} %0,%1,0,0xffff"
778 
  [(set_attr "type" "load,*")])
779 
 
780 
(define_insn ""
781 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
782 
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
783 
                    (const_int 0)))
784 
   (clobber (match_scratch:SI 2 "=r,r"))]
785 
  ""
786 
  "@
787 
   {andil.|andi.} %2,%1,0xffff
788 
   #"
789 
  [(set_attr "type" "compare")
790 
   (set_attr "length" "4,8")])
791 
 
792 
(define_split
793 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
794 
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
795 
                    (const_int 0)))
796 
   (clobber (match_scratch:SI 2 ""))]
797 
  "reload_completed"
798 
  [(set (match_dup 2)
799 
        (zero_extend:SI (match_dup 1)))
800 
   (set (match_dup 0)
801 
        (compare:CC (match_dup 2)
802 
                    (const_int 0)))]
803 
  "")
804 
 
805 
(define_insn ""
806 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
807 
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
808 
                    (const_int 0)))
809 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
810 
        (zero_extend:SI (match_dup 1)))]
811 
  ""
812 
  "@
813 
   {andil.|andi.} %0,%1,0xffff
814 
   #"
815 
  [(set_attr "type" "compare")
816 
   (set_attr "length" "4,8")])
817 
 
818 
(define_split
819 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
820 
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
821 
                    (const_int 0)))
822 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
823 
        (zero_extend:SI (match_dup 1)))]
824 
  "reload_completed"
825 
  [(set (match_dup 0)
826 
        (zero_extend:SI (match_dup 1)))
827 
   (set (match_dup 2)
828 
        (compare:CC (match_dup 0)
829 
                    (const_int 0)))]
830 
  "")
831 
 
832 
(define_expand "extendhisi2"
833 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
834 
        (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
835 
  ""
836 
  "")
837 
 
838 
(define_insn ""
839 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
840 
        (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
841 
  ""
842 
  "@
843 
   lha%U1%X1 %0,%1
844 
   {exts|extsh} %0,%1"
845 
  [(set_attr "type" "load_ext,*")])
846 
 
847 
(define_insn ""
848 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
849 
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
850 
                    (const_int 0)))
851 
   (clobber (match_scratch:SI 2 "=r,r"))]
852 
  ""
853 
  "@
854 
   {exts.|extsh.} %2,%1
855 
   #"
856 
  [(set_attr "type" "compare")
857 
   (set_attr "length" "4,8")])
858 
 
859 
(define_split
860 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
861 
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
862 
                    (const_int 0)))
863 
   (clobber (match_scratch:SI 2 ""))]
864 
  "reload_completed"
865 
  [(set (match_dup 2)
866 
        (sign_extend:SI (match_dup 1)))
867 
   (set (match_dup 0)
868 
        (compare:CC (match_dup 2)
869 
                    (const_int 0)))]
870 
  "")
871 
 
872 
(define_insn ""
873 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
874 
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
875 
                    (const_int 0)))
876 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
877 
        (sign_extend:SI (match_dup 1)))]
878 
  ""
879 
  "@
880 
   {exts.|extsh.} %0,%1
881 
   #"
882 
  [(set_attr "type" "compare")
883 
   (set_attr "length" "4,8")])
884 
 
885 
;; IBM 405 and 440 half-word multiplication operations.
886 
 
887 
(define_insn "*macchwc"
888 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
889 
        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
890 
                                       (match_operand:SI 2 "gpc_reg_operand" "r")
891 
                                       (const_int 16))
892 
                                      (sign_extend:SI
893 
                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
894 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
895 
                    (const_int 0)))
896 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
897 
        (plus:SI (mult:SI (ashiftrt:SI
898 
                           (match_dup 2)
899 
                           (const_int 16))
900 
                          (sign_extend:SI
901 
                           (match_dup 1)))
902 
                 (match_dup 4)))]
903 
  "TARGET_MULHW"
904 
  "macchw. %0, %1, %2"
905 
  [(set_attr "type" "imul3")])
906 
 
907 
(define_insn "*macchw"
908 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
909 
        (plus:SI (mult:SI (ashiftrt:SI
910 
                           (match_operand:SI 2 "gpc_reg_operand" "r")
911 
                           (const_int 16))
912 
                          (sign_extend:SI
913 
                           (match_operand:HI 1 "gpc_reg_operand" "r")))
914 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
915 
  "TARGET_MULHW"
916 
  "macchw %0, %1, %2"
917 
  [(set_attr "type" "imul3")])
918 
 
919 
(define_insn "*macchwuc"
920 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
921 
        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
922 
                                       (match_operand:SI 2 "gpc_reg_operand" "r")
923 
                                       (const_int 16))
924 
                                      (zero_extend:SI
925 
                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
926 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
927 
                    (const_int 0)))
928 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
929 
        (plus:SI (mult:SI (lshiftrt:SI
930 
                           (match_dup 2)
931 
                           (const_int 16))
932 
                          (zero_extend:SI
933 
                           (match_dup 1)))
934 
                 (match_dup 4)))]
935 
  "TARGET_MULHW"
936 
  "macchwu. %0, %1, %2"
937 
  [(set_attr "type" "imul3")])
938 
 
939 
(define_insn "*macchwu"
940 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
941 
        (plus:SI (mult:SI (lshiftrt:SI
942 
                           (match_operand:SI 2 "gpc_reg_operand" "r")
943 
                           (const_int 16))
944 
                          (zero_extend:SI
945 
                           (match_operand:HI 1 "gpc_reg_operand" "r")))
946 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
947 
  "TARGET_MULHW"
948 
  "macchwu %0, %1, %2"
949 
  [(set_attr "type" "imul3")])
950 
 
951 
(define_insn "*machhwc"
952 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
953 
        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
954 
                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
955 
                                       (const_int 16))
956 
                                      (ashiftrt:SI
957 
                                       (match_operand:SI 2 "gpc_reg_operand" "r")
958 
                                       (const_int 16)))
959 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
960 
                    (const_int 0)))
961 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
962 
        (plus:SI (mult:SI (ashiftrt:SI
963 
                           (match_dup 1)
964 
                           (const_int 16))
965 
                          (ashiftrt:SI
966 
                           (match_dup 2)
967 
                           (const_int 16)))
968 
                 (match_dup 4)))]
969 
  "TARGET_MULHW"
970 
  "machhw. %0, %1, %2"
971 
  [(set_attr "type" "imul3")])
972 
 
973 
(define_insn "*machhw"
974 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
975 
        (plus:SI (mult:SI (ashiftrt:SI
976 
                           (match_operand:SI 1 "gpc_reg_operand" "%r")
977 
                           (const_int 16))
978 
                          (ashiftrt:SI
979 
                           (match_operand:SI 2 "gpc_reg_operand" "r")
980 
                           (const_int 16)))
981 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
982 
  "TARGET_MULHW"
983 
  "machhw %0, %1, %2"
984 
  [(set_attr "type" "imul3")])
985 
 
986 
(define_insn "*machhwuc"
987 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
988 
        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
989 
                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
990 
                                       (const_int 16))
991 
                                      (lshiftrt:SI
992 
                                       (match_operand:SI 2 "gpc_reg_operand" "r")
993 
                                       (const_int 16)))
994 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
995 
                    (const_int 0)))
996 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
997 
        (plus:SI (mult:SI (lshiftrt:SI
998 
                           (match_dup 1)
999 
                           (const_int 16))
1000 
                          (lshiftrt:SI
1001 
                           (match_dup 2)
1002 
                           (const_int 16)))
1003 
                 (match_dup 4)))]
1004 
  "TARGET_MULHW"
1005 
  "machhwu. %0, %1, %2"
1006 
  [(set_attr "type" "imul3")])
1007 
 
1008 
(define_insn "*machhwu"
1009 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1010 
        (plus:SI (mult:SI (lshiftrt:SI
1011 
                           (match_operand:SI 1 "gpc_reg_operand" "%r")
1012 
                           (const_int 16))
1013 
                          (lshiftrt:SI
1014 
                           (match_operand:SI 2 "gpc_reg_operand" "r")
1015 
                           (const_int 16)))
1016 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1017 
  "TARGET_MULHW"
1018 
  "machhwu %0, %1, %2"
1019 
  [(set_attr "type" "imul3")])
1020 
 
1021 
(define_insn "*maclhwc"
1022 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1023 
        (compare:CC (plus:SI (mult:SI (sign_extend:SI
1024 
                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
1025 
                                      (sign_extend:SI
1026 
                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
1027 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
1028 
                    (const_int 0)))
1029 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1030 
        (plus:SI (mult:SI (sign_extend:SI
1031 
                           (match_dup 1))
1032 
                          (sign_extend:SI
1033 
                           (match_dup 2)))
1034 
                 (match_dup 4)))]
1035 
  "TARGET_MULHW"
1036 
  "maclhw. %0, %1, %2"
1037 
  [(set_attr "type" "imul3")])
1038 
 
1039 
(define_insn "*maclhw"
1040 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1041 
        (plus:SI (mult:SI (sign_extend:SI
1042 
                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
1043 
                          (sign_extend:SI
1044 
                           (match_operand:HI 2 "gpc_reg_operand" "r")))
1045 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1046 
  "TARGET_MULHW"
1047 
  "maclhw %0, %1, %2"
1048 
  [(set_attr "type" "imul3")])
1049 
 
1050 
(define_insn "*maclhwuc"
1051 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1052 
        (compare:CC (plus:SI (mult:SI (zero_extend:SI
1053 
                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
1054 
                                      (zero_extend:SI
1055 
                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
1056 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
1057 
                    (const_int 0)))
1058 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1059 
        (plus:SI (mult:SI (zero_extend:SI
1060 
                           (match_dup 1))
1061 
                          (zero_extend:SI
1062 
                           (match_dup 2)))
1063 
                 (match_dup 4)))]
1064 
  "TARGET_MULHW"
1065 
  "maclhwu. %0, %1, %2"
1066 
  [(set_attr "type" "imul3")])
1067 
 
1068 
(define_insn "*maclhwu"
1069 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1070 
        (plus:SI (mult:SI (zero_extend:SI
1071 
                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
1072 
                          (zero_extend:SI
1073 
                           (match_operand:HI 2 "gpc_reg_operand" "r")))
1074 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1075 
  "TARGET_MULHW"
1076 
  "maclhwu %0, %1, %2"
1077 
  [(set_attr "type" "imul3")])
1078 
 
1079 
(define_insn "*nmacchwc"
1080 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1081 
        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1082 
                              (mult:SI (ashiftrt:SI
1083 
                                        (match_operand:SI 2 "gpc_reg_operand" "r")
1084 
                                        (const_int 16))
1085 
                                       (sign_extend:SI
1086 
                                        (match_operand:HI 1 "gpc_reg_operand" "r"))))
1087 
                    (const_int 0)))
1088 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1089 
        (minus:SI (match_dup 4)
1090 
                  (mult:SI (ashiftrt:SI
1091 
                            (match_dup 2)
1092 
                            (const_int 16))
1093 
                           (sign_extend:SI
1094 
                            (match_dup 1)))))]
1095 
  "TARGET_MULHW"
1096 
  "nmacchw. %0, %1, %2"
1097 
  [(set_attr "type" "imul3")])
1098 
 
1099 
(define_insn "*nmacchw"
1100 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 
        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1102 
                  (mult:SI (ashiftrt:SI
1103 
                            (match_operand:SI 2 "gpc_reg_operand" "r")
1104 
                            (const_int 16))
1105 
                           (sign_extend:SI
1106 
                            (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1107 
  "TARGET_MULHW"
1108 
  "nmacchw %0, %1, %2"
1109 
  [(set_attr "type" "imul3")])
1110 
 
1111 
(define_insn "*nmachhwc"
1112 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1113 
        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1114 
                              (mult:SI (ashiftrt:SI
1115 
                                        (match_operand:SI 1 "gpc_reg_operand" "%r")
1116 
                                        (const_int 16))
1117 
                                       (ashiftrt:SI
1118 
                                        (match_operand:SI 2 "gpc_reg_operand" "r")
1119 
                                        (const_int 16))))
1120 
                    (const_int 0)))
1121 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1122 
        (minus:SI (match_dup 4)
1123 
                  (mult:SI (ashiftrt:SI
1124 
                            (match_dup 1)
1125 
                            (const_int 16))
1126 
                           (ashiftrt:SI
1127 
                            (match_dup 2)
1128 
                            (const_int 16)))))]
1129 
  "TARGET_MULHW"
1130 
  "nmachhw. %0, %1, %2"
1131 
  [(set_attr "type" "imul3")])
1132 
 
1133 
(define_insn "*nmachhw"
1134 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1135 
        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1136 
                  (mult:SI (ashiftrt:SI
1137 
                            (match_operand:SI 1 "gpc_reg_operand" "%r")
1138 
                            (const_int 16))
1139 
                           (ashiftrt:SI
1140 
                            (match_operand:SI 2 "gpc_reg_operand" "r")
1141 
                            (const_int 16)))))]
1142 
  "TARGET_MULHW"
1143 
  "nmachhw %0, %1, %2"
1144 
  [(set_attr "type" "imul3")])
1145 
 
1146 
(define_insn "*nmaclhwc"
1147 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1148 
        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1149 
                              (mult:SI (sign_extend:SI
1150 
                                        (match_operand:HI 1 "gpc_reg_operand" "%r"))
1151 
                                       (sign_extend:SI
1152 
                                        (match_operand:HI 2 "gpc_reg_operand" "r"))))
1153 
                    (const_int 0)))
1154 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1155 
        (minus:SI (match_dup 4)
1156 
                  (mult:SI (sign_extend:SI
1157 
                            (match_dup 1))
1158 
                           (sign_extend:SI
1159 
                            (match_dup 2)))))]
1160 
  "TARGET_MULHW"
1161 
  "nmaclhw. %0, %1, %2"
1162 
  [(set_attr "type" "imul3")])
1163 
 
1164 
(define_insn "*nmaclhw"
1165 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 
        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1167 
                  (mult:SI (sign_extend:SI
1168 
                            (match_operand:HI 1 "gpc_reg_operand" "%r"))
1169 
                           (sign_extend:SI
1170 
                            (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1171 
  "TARGET_MULHW"
1172 
  "nmaclhw %0, %1, %2"
1173 
  [(set_attr "type" "imul3")])
1174 
 
1175 
(define_insn "*mulchwc"
1176 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1177 
        (compare:CC (mult:SI (ashiftrt:SI
1178 
                              (match_operand:SI 2 "gpc_reg_operand" "r")
1179 
                              (const_int 16))
1180 
                             (sign_extend:SI
1181 
                              (match_operand:HI 1 "gpc_reg_operand" "r")))
1182 
                    (const_int 0)))
1183 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1184 
        (mult:SI (ashiftrt:SI
1185 
                  (match_dup 2)
1186 
                  (const_int 16))
1187 
                 (sign_extend:SI
1188 
                  (match_dup 1))))]
1189 
  "TARGET_MULHW"
1190 
  "mulchw. %0, %1, %2"
1191 
  [(set_attr "type" "imul3")])
1192 
 
1193 
(define_insn "*mulchw"
1194 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1195 
        (mult:SI (ashiftrt:SI
1196 
                  (match_operand:SI 2 "gpc_reg_operand" "r")
1197 
                  (const_int 16))
1198 
                 (sign_extend:SI
1199 
                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1200 
  "TARGET_MULHW"
1201 
  "mulchw %0, %1, %2"
1202 
  [(set_attr "type" "imul3")])
1203 
 
1204 
(define_insn "*mulchwuc"
1205 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1206 
        (compare:CC (mult:SI (lshiftrt:SI
1207 
                              (match_operand:SI 2 "gpc_reg_operand" "r")
1208 
                              (const_int 16))
1209 
                             (zero_extend:SI
1210 
                              (match_operand:HI 1 "gpc_reg_operand" "r")))
1211 
                    (const_int 0)))
1212 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1213 
        (mult:SI (lshiftrt:SI
1214 
                  (match_dup 2)
1215 
                  (const_int 16))
1216 
                 (zero_extend:SI
1217 
                  (match_dup 1))))]
1218 
  "TARGET_MULHW"
1219 
  "mulchwu. %0, %1, %2"
1220 
  [(set_attr "type" "imul3")])
1221 
 
1222 
(define_insn "*mulchwu"
1223 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1224 
        (mult:SI (lshiftrt:SI
1225 
                  (match_operand:SI 2 "gpc_reg_operand" "r")
1226 
                  (const_int 16))
1227 
                 (zero_extend:SI
1228 
                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1229 
  "TARGET_MULHW"
1230 
  "mulchwu %0, %1, %2"
1231 
  [(set_attr "type" "imul3")])
1232 
 
1233 
(define_insn "*mulhhwc"
1234 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1235 
        (compare:CC (mult:SI (ashiftrt:SI
1236 
                              (match_operand:SI 1 "gpc_reg_operand" "%r")
1237 
                              (const_int 16))
1238 
                             (ashiftrt:SI
1239 
                              (match_operand:SI 2 "gpc_reg_operand" "r")
1240 
                              (const_int 16)))
1241 
                    (const_int 0)))
1242 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 
        (mult:SI (ashiftrt:SI
1244 
                  (match_dup 1)
1245 
                  (const_int 16))
1246 
                 (ashiftrt:SI
1247 
                  (match_dup 2)
1248 
                  (const_int 16))))]
1249 
  "TARGET_MULHW"
1250 
  "mulhhw. %0, %1, %2"
1251 
  [(set_attr "type" "imul3")])
1252 
 
1253 
(define_insn "*mulhhw"
1254 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 
        (mult:SI (ashiftrt:SI
1256 
                  (match_operand:SI 1 "gpc_reg_operand" "%r")
1257 
                  (const_int 16))
1258 
                 (ashiftrt:SI
1259 
                  (match_operand:SI 2 "gpc_reg_operand" "r")
1260 
                  (const_int 16))))]
1261 
  "TARGET_MULHW"
1262 
  "mulhhw %0, %1, %2"
1263 
  [(set_attr "type" "imul3")])
1264 
 
1265 
(define_insn "*mulhhwuc"
1266 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1267 
        (compare:CC (mult:SI (lshiftrt:SI
1268 
                              (match_operand:SI 1 "gpc_reg_operand" "%r")
1269 
                              (const_int 16))
1270 
                             (lshiftrt:SI
1271 
                              (match_operand:SI 2 "gpc_reg_operand" "r")
1272 
                              (const_int 16)))
1273 
                    (const_int 0)))
1274 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 
        (mult:SI (lshiftrt:SI
1276 
                  (match_dup 1)
1277 
                  (const_int 16))
1278 
                 (lshiftrt:SI
1279 
                  (match_dup 2)
1280 
                  (const_int 16))))]
1281 
  "TARGET_MULHW"
1282 
  "mulhhwu. %0, %1, %2"
1283 
  [(set_attr "type" "imul3")])
1284 
 
1285 
(define_insn "*mulhhwu"
1286 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 
        (mult:SI (lshiftrt:SI
1288 
                  (match_operand:SI 1 "gpc_reg_operand" "%r")
1289 
                  (const_int 16))
1290 
                 (lshiftrt:SI
1291 
                  (match_operand:SI 2 "gpc_reg_operand" "r")
1292 
                  (const_int 16))))]
1293 
  "TARGET_MULHW"
1294 
  "mulhhwu %0, %1, %2"
1295 
  [(set_attr "type" "imul3")])
1296 
 
1297 
(define_insn "*mullhwc"
1298 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1299 
        (compare:CC (mult:SI (sign_extend:SI
1300 
                              (match_operand:HI 1 "gpc_reg_operand" "%r"))
1301 
                             (sign_extend:SI
1302 
                              (match_operand:HI 2 "gpc_reg_operand" "r")))
1303 
                    (const_int 0)))
1304 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1305 
        (mult:SI (sign_extend:SI
1306 
                  (match_dup 1))
1307 
                 (sign_extend:SI
1308 
                  (match_dup 2))))]
1309 
  "TARGET_MULHW"
1310 
  "mullhw. %0, %1, %2"
1311 
  [(set_attr "type" "imul3")])
1312 
 
1313 
(define_insn "*mullhw"
1314 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 
        (mult:SI (sign_extend:SI
1316 
                  (match_operand:HI 1 "gpc_reg_operand" "%r"))
1317 
                 (sign_extend:SI
1318 
                  (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1319 
  "TARGET_MULHW"
1320 
  "mullhw %0, %1, %2"
1321 
  [(set_attr "type" "imul3")])
1322 
 
1323 
(define_insn "*mullhwuc"
1324 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1325 
        (compare:CC (mult:SI (zero_extend:SI
1326 
                              (match_operand:HI 1 "gpc_reg_operand" "%r"))
1327 
                             (zero_extend:SI
1328 
                              (match_operand:HI 2 "gpc_reg_operand" "r")))
1329 
                    (const_int 0)))
1330 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1331 
        (mult:SI (zero_extend:SI
1332 
                  (match_dup 1))
1333 
                 (zero_extend:SI
1334 
                  (match_dup 2))))]
1335 
  "TARGET_MULHW"
1336 
  "mullhwu. %0, %1, %2"
1337 
  [(set_attr "type" "imul3")])
1338 
 
1339 
(define_insn "*mullhwu"
1340 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1341 
        (mult:SI (zero_extend:SI
1342 
                  (match_operand:HI 1 "gpc_reg_operand" "%r"))
1343 
                 (zero_extend:SI
1344 
                  (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1345 
  "TARGET_MULHW"
1346 
  "mullhwu %0, %1, %2"
1347 
  [(set_attr "type" "imul3")])
1348 
 
1349 
;; IBM 405 and 440 string-search dlmzb instruction support.
1350 
(define_insn "dlmzb"
1351 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1352 
        (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1353 
                    (match_operand:SI 2 "gpc_reg_operand" "r")]
1354 
                   UNSPEC_DLMZB_CR))
1355 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 
        (unspec:SI [(match_dup 1)
1357 
                    (match_dup 2)]
1358 
                   UNSPEC_DLMZB))]
1359 
  "TARGET_DLMZB"
1360 
  "dlmzb. %0, %1, %2")
1361 
 
1362 
(define_expand "strlensi"
1363 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
1364 
        (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1365 
                    (match_operand:QI 2 "const_int_operand" "")
1366 
                    (match_operand 3 "const_int_operand" "")]
1367 
                   UNSPEC_DLMZB_STRLEN))
1368 
   (clobber (match_scratch:CC 4 "=x"))]
1369 
  "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1370 
{
1371 
  rtx result = operands[0];
1372 
  rtx src = operands[1];
1373 
  rtx search_char = operands[2];
1374 
  rtx align = operands[3];
1375 
  rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1376 
  rtx loop_label, end_label, mem, cr0, cond;
1377 
  if (search_char != const0_rtx
1378 
      || GET_CODE (align) != CONST_INT
1379 
      || INTVAL (align) < 8)
1380 
        FAIL;
1381 
  word1 = gen_reg_rtx (SImode);
1382 
  word2 = gen_reg_rtx (SImode);
1383 
  scratch_dlmzb = gen_reg_rtx (SImode);
1384 
  scratch_string = gen_reg_rtx (Pmode);
1385 
  loop_label = gen_label_rtx ();
1386 
  end_label = gen_label_rtx ();
1387 
  addr = force_reg (Pmode, XEXP (src, 0));
1388 
  emit_move_insn (scratch_string, addr);
1389 
  emit_label (loop_label);
1390 
  mem = change_address (src, SImode, scratch_string);
1391 
  emit_move_insn (word1, mem);
1392 
  emit_move_insn (word2, adjust_address (mem, SImode, 4));
1393 
  cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1394 
  emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1395 
  cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1396 
  emit_jump_insn (gen_rtx_SET (VOIDmode,
1397 
                               pc_rtx,
1398 
                               gen_rtx_IF_THEN_ELSE (VOIDmode,
1399 
                                                     cond,
1400 
                                                     gen_rtx_LABEL_REF
1401 
                                                       (VOIDmode,
1402 
                                                        end_label),
1403 
                                                     pc_rtx)));
1404 
  emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1405 
  emit_jump_insn (gen_rtx_SET (VOIDmode,
1406 
                               pc_rtx,
1407 
                               gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1408 
  emit_barrier ();
1409 
  emit_label (end_label);
1410 
  emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1411 
  emit_insn (gen_subsi3 (result, scratch_string, addr));
1412 
  emit_insn (gen_subsi3 (result, result, const1_rtx));
1413 
  DONE;
1414 
})
1415 
 
1416 
(define_split
1417 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1418 
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1419 
                    (const_int 0)))
1420 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1421 
        (sign_extend:SI (match_dup 1)))]
1422 
  "reload_completed"
1423 
  [(set (match_dup 0)
1424 
        (sign_extend:SI (match_dup 1)))
1425 
   (set (match_dup 2)
1426 
        (compare:CC (match_dup 0)
1427 
                    (const_int 0)))]
1428 
  "")
1429 
 
1430 
;; Fixed-point arithmetic insns.
1431 
 
1432 
(define_expand "add3"
1433 
  [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1434 
        (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1435 
                  (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1436 
  ""
1437 
{
1438 
  if (mode == DImode && ! TARGET_POWERPC64)
1439 
    {
1440 
      if (non_short_cint_operand (operands[2], DImode))
1441 
        FAIL;
1442 
    }
1443 
  else if (GET_CODE (operands[2]) == CONST_INT
1444 
           && ! add_operand (operands[2], mode))
1445 
    {
1446 
      rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1447 
                 ? operands[0] : gen_reg_rtx (mode));
1448 
 
1449 
      HOST_WIDE_INT val = INTVAL (operands[2]);
1450 
      HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1451 
      HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode);
1452 
 
1453 
      if (mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1454 
        FAIL;
1455 
 
1456 
      /* The ordering here is important for the prolog expander.
1457 
         When space is allocated from the stack, adding 'low' first may
1458 
         produce a temporary deallocation (which would be bad).  */
1459 
      emit_insn (gen_add3 (tmp, operands[1], GEN_INT (rest)));
1460 
      emit_insn (gen_add3 (operands[0], tmp, GEN_INT (low)));
1461 
      DONE;
1462 
    }
1463 
})
1464 
 
1465 
;; Discourage ai/addic because of carry but provide it in an alternative
1466 
;; allowing register zero as source.
1467 
(define_insn "*add3_internal1"
1468 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1469 
        (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1470 
                  (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1471 
  ""
1472 
  "@
1473 
   {cax|add} %0,%1,%2
1474 
   {cal %0,%2(%1)|addi %0,%1,%2}
1475 
   {ai|addic} %0,%1,%2
1476 
   {cau|addis} %0,%1,%v2"
1477 
  [(set_attr "length" "4,4,4,4")])
1478 
 
1479 
(define_insn "addsi3_high"
1480 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1481 
        (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1482 
                 (high:SI (match_operand 2 "" ""))))]
1483 
  "TARGET_MACHO && !TARGET_64BIT"
1484 
  "{cau|addis} %0,%1,ha16(%2)"
1485 
  [(set_attr "length" "4")])
1486 
 
1487 
(define_insn "*add3_internal2"
1488 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1489 
        (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1490 
                            (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1491 
                    (const_int 0)))
1492 
   (clobber (match_scratch:P 3 "=r,r,r,r"))]
1493 
  ""
1494 
  "@
1495 
   {cax.|add.} %3,%1,%2
1496 
   {ai.|addic.} %3,%1,%2
1497 
   #
1498 
   #"
1499 
  [(set_attr "type" "fast_compare,compare,compare,compare")
1500 
   (set_attr "length" "4,4,8,8")])
1501 
 
1502 
(define_split
1503 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1504 
        (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1505 
                              (match_operand:GPR 2 "reg_or_short_operand" ""))
1506 
                    (const_int 0)))
1507 
   (clobber (match_scratch:GPR 3 ""))]
1508 
  "reload_completed"
1509 
  [(set (match_dup 3)
1510 
        (plus:GPR (match_dup 1)
1511 
                 (match_dup 2)))
1512 
   (set (match_dup 0)
1513 
        (compare:CC (match_dup 3)
1514 
                    (const_int 0)))]
1515 
  "")
1516 
 
1517 
(define_insn "*add3_internal3"
1518 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1519 
        (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1520 
                            (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1521 
                    (const_int 0)))
1522 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1523 
        (plus:P (match_dup 1)
1524 
                (match_dup 2)))]
1525 
  ""
1526 
  "@
1527 
   {cax.|add.} %0,%1,%2
1528 
   {ai.|addic.} %0,%1,%2
1529 
   #
1530 
   #"
1531 
  [(set_attr "type" "fast_compare,compare,compare,compare")
1532 
   (set_attr "length" "4,4,8,8")])
1533 
 
1534 
(define_split
1535 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1536 
        (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1537 
                            (match_operand:P 2 "reg_or_short_operand" ""))
1538 
                    (const_int 0)))
1539 
   (set (match_operand:P 0 "gpc_reg_operand" "")
1540 
        (plus:P (match_dup 1) (match_dup 2)))]
1541 
  "reload_completed"
1542 
  [(set (match_dup 0)
1543 
        (plus:P (match_dup 1)
1544 
                (match_dup 2)))
1545 
   (set (match_dup 3)
1546 
        (compare:CC (match_dup 0)
1547 
                    (const_int 0)))]
1548 
  "")
1549 
 
1550 
;; Split an add that we can't do in one insn into two insns, each of which
1551 
;; does one 16-bit part.  This is used by combine.  Note that the low-order
1552 
;; add should be last in case the result gets used in an address.
1553 
 
1554 
(define_split
1555 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1556 
        (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1557 
                  (match_operand:GPR 2 "non_add_cint_operand" "")))]
1558 
  ""
1559 
  [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1560 
   (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1561 
{
1562 
  HOST_WIDE_INT val = INTVAL (operands[2]);
1563 
  HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1564 
  HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode);
1565 
 
1566 
  operands[4] = GEN_INT (low);
1567 
  if (mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1568 
    operands[3] = GEN_INT (rest);
1569 
  else if (! no_new_pseudos)
1570 
    {
1571 
      operands[3] = gen_reg_rtx (DImode);
1572 
      emit_move_insn (operands[3], operands[2]);
1573 
      emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1574 
      DONE;
1575 
    }
1576 
  else
1577 
    FAIL;
1578 
})
1579 
 
1580 
(define_insn "one_cmpl2"
1581 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1582 
        (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1583 
  ""
1584 
  "nor %0,%1,%1")
1585 
 
1586 
(define_insn ""
1587 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1588 
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1589 
                    (const_int 0)))
1590 
   (clobber (match_scratch:P 2 "=r,r"))]
1591 
  ""
1592 
  "@
1593 
   nor. %2,%1,%1
1594 
   #"
1595 
  [(set_attr "type" "compare")
1596 
   (set_attr "length" "4,8")])
1597 
 
1598 
(define_split
1599 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1600 
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1601 
                    (const_int 0)))
1602 
   (clobber (match_scratch:P 2 ""))]
1603 
  "reload_completed"
1604 
  [(set (match_dup 2)
1605 
        (not:P (match_dup 1)))
1606 
   (set (match_dup 0)
1607 
        (compare:CC (match_dup 2)
1608 
                    (const_int 0)))]
1609 
  "")
1610 
 
1611 
(define_insn ""
1612 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1613 
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1614 
                    (const_int 0)))
1615 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1616 
        (not:P (match_dup 1)))]
1617 
  ""
1618 
  "@
1619 
   nor. %0,%1,%1
1620 
   #"
1621 
  [(set_attr "type" "compare")
1622 
   (set_attr "length" "4,8")])
1623 
 
1624 
(define_split
1625 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1626 
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1627 
                    (const_int 0)))
1628 
   (set (match_operand:P 0 "gpc_reg_operand" "")
1629 
        (not:P (match_dup 1)))]
1630 
  "reload_completed"
1631 
  [(set (match_dup 0)
1632 
        (not:P (match_dup 1)))
1633 
   (set (match_dup 2)
1634 
        (compare:CC (match_dup 0)
1635 
                    (const_int 0)))]
1636 
  "")
1637 
 
1638 
(define_insn ""
1639 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1640 
        (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1641 
                  (match_operand:SI 2 "gpc_reg_operand" "r")))]
1642 
  "! TARGET_POWERPC"
1643 
  "{sf%I1|subf%I1c} %0,%2,%1")
1644 
 
1645 
(define_insn ""
1646 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1647 
        (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1648 
                   (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1649 
  "TARGET_POWERPC"
1650 
  "@
1651 
   subf %0,%2,%1
1652 
   subfic %0,%2,%1")
1653 
 
1654 
(define_insn ""
1655 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1656 
        (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1657 
                              (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1658 
                    (const_int 0)))
1659 
   (clobber (match_scratch:SI 3 "=r,r"))]
1660 
  "! TARGET_POWERPC"
1661 
  "@
1662 
   {sf.|subfc.} %3,%2,%1
1663 
   #"
1664 
  [(set_attr "type" "compare")
1665 
   (set_attr "length" "4,8")])
1666 
 
1667 
(define_insn ""
1668 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1669 
        (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1670 
                             (match_operand:P 2 "gpc_reg_operand" "r,r"))
1671 
                    (const_int 0)))
1672 
   (clobber (match_scratch:P 3 "=r,r"))]
1673 
  "TARGET_POWERPC"
1674 
  "@
1675 
   subf. %3,%2,%1
1676 
   #"
1677 
  [(set_attr "type" "fast_compare")
1678 
   (set_attr "length" "4,8")])
1679 
 
1680 
(define_split
1681 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1682 
        (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1683 
                             (match_operand:P 2 "gpc_reg_operand" ""))
1684 
                    (const_int 0)))
1685 
   (clobber (match_scratch:P 3 ""))]
1686 
  "reload_completed"
1687 
  [(set (match_dup 3)
1688 
        (minus:P (match_dup 1)
1689 
                  (match_dup 2)))
1690 
   (set (match_dup 0)
1691 
        (compare:CC (match_dup 3)
1692 
                    (const_int 0)))]
1693 
  "")
1694 
 
1695 
(define_insn ""
1696 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1697 
        (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1698 
                              (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1699 
                    (const_int 0)))
1700 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1701 
        (minus:SI (match_dup 1) (match_dup 2)))]
1702 
  "! TARGET_POWERPC"
1703 
  "@
1704 
   {sf.|subfc.} %0,%2,%1
1705 
   #"
1706 
  [(set_attr "type" "compare")
1707 
   (set_attr "length" "4,8")])
1708 
 
1709 
(define_insn ""
1710 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1711 
        (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1712 
                             (match_operand:P 2 "gpc_reg_operand" "r,r"))
1713 
                    (const_int 0)))
1714 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1715 
        (minus:P (match_dup 1)
1716 
                  (match_dup 2)))]
1717 
  "TARGET_POWERPC"
1718 
  "@
1719 
   subf. %0,%2,%1
1720 
   #"
1721 
  [(set_attr "type" "fast_compare")
1722 
   (set_attr "length" "4,8")])
1723 
 
1724 
(define_split
1725 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1726 
        (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1727 
                             (match_operand:P 2 "gpc_reg_operand" ""))
1728 
                    (const_int 0)))
1729 
   (set (match_operand:P 0 "gpc_reg_operand" "")
1730 
        (minus:P (match_dup 1)
1731 
                  (match_dup 2)))]
1732 
  "reload_completed"
1733 
  [(set (match_dup 0)
1734 
        (minus:P (match_dup 1)
1735 
                  (match_dup 2)))
1736 
   (set (match_dup 3)
1737 
        (compare:CC (match_dup 0)
1738 
                    (const_int 0)))]
1739 
  "")
1740 
 
1741 
(define_expand "sub3"
1742 
  [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1743 
        (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1744 
                   (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1745 
  ""
1746 
  "
1747 
{
1748 
  if (GET_CODE (operands[2]) == CONST_INT)
1749 
    {
1750 
      emit_insn (gen_add3 (operands[0], operands[1],
1751 
                                 negate_rtx (mode, operands[2])));
1752 
      DONE;
1753 
    }
1754 
}")
1755 
 
1756 
;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1757 
;; instruction and some auxiliary computations.  Then we just have a single
1758 
;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1759 
;; combine.
1760 
 
1761 
(define_expand "sminsi3"
1762 
  [(set (match_dup 3)
1763 
        (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1764 
                                (match_operand:SI 2 "reg_or_short_operand" ""))
1765 
                         (const_int 0)
1766 
                         (minus:SI (match_dup 2) (match_dup 1))))
1767 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1768 
        (minus:SI (match_dup 2) (match_dup 3)))]
1769 
  "TARGET_POWER || TARGET_ISEL"
1770 
  "
1771 
{
1772 
  if (TARGET_ISEL)
1773 
    {
1774 
      operands[2] = force_reg (SImode, operands[2]);
1775 
      rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1776 
      DONE;
1777 
    }
1778 
 
1779 
  operands[3] = gen_reg_rtx (SImode);
1780 
}")
1781 
 
1782 
(define_split
1783 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
1784 
        (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1785 
                 (match_operand:SI 2 "reg_or_short_operand" "")))
1786 
   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1787 
  "TARGET_POWER"
1788 
  [(set (match_dup 3)
1789 
        (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1790 
                         (const_int 0)
1791 
                         (minus:SI (match_dup 2) (match_dup 1))))
1792 
   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1793 
  "")
1794 
 
1795 
(define_expand "smaxsi3"
1796 
  [(set (match_dup 3)
1797 
        (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1798 
                                (match_operand:SI 2 "reg_or_short_operand" ""))
1799 
                         (const_int 0)
1800 
                         (minus:SI (match_dup 2) (match_dup 1))))
1801 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1802 
        (plus:SI (match_dup 3) (match_dup 1)))]
1803 
  "TARGET_POWER || TARGET_ISEL"
1804 
  "
1805 
{
1806 
  if (TARGET_ISEL)
1807 
    {
1808 
      operands[2] = force_reg (SImode, operands[2]);
1809 
      rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1810 
      DONE;
1811 
    }
1812 
  operands[3] = gen_reg_rtx (SImode);
1813 
}")
1814 
 
1815 
(define_split
1816 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
1817 
        (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1818 
                 (match_operand:SI 2 "reg_or_short_operand" "")))
1819 
   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1820 
  "TARGET_POWER"
1821 
  [(set (match_dup 3)
1822 
        (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1823 
                         (const_int 0)
1824 
                         (minus:SI (match_dup 2) (match_dup 1))))
1825 
   (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1826 
  "")
1827 
 
1828 
(define_expand "uminsi3"
1829 
  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1830 
                              (match_dup 5)))
1831 
   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1832 
                              (match_dup 5)))
1833 
   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1834 
                                       (const_int 0)
1835 
                                       (minus:SI (match_dup 4) (match_dup 3))))
1836 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1837 
        (minus:SI (match_dup 2) (match_dup 3)))]
1838 
  "TARGET_POWER || TARGET_ISEL"
1839 
  "
1840 
{
1841 
  if (TARGET_ISEL)
1842 
    {
1843 
      rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1844 
      DONE;
1845 
    }
1846 
  operands[3] = gen_reg_rtx (SImode);
1847 
  operands[4] = gen_reg_rtx (SImode);
1848 
  operands[5] = GEN_INT (-2147483647 - 1);
1849 
}")
1850 
 
1851 
(define_expand "umaxsi3"
1852 
  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1853 
                              (match_dup 5)))
1854 
   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1855 
                              (match_dup 5)))
1856 
   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1857 
                                       (const_int 0)
1858 
                                       (minus:SI (match_dup 4) (match_dup 3))))
1859 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1860 
        (plus:SI (match_dup 3) (match_dup 1)))]
1861 
  "TARGET_POWER || TARGET_ISEL"
1862 
  "
1863 
{
1864 
  if (TARGET_ISEL)
1865 
    {
1866 
      rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1867 
      DONE;
1868 
    }
1869 
  operands[3] = gen_reg_rtx (SImode);
1870 
  operands[4] = gen_reg_rtx (SImode);
1871 
  operands[5] = GEN_INT (-2147483647 - 1);
1872 
}")
1873 
 
1874 
(define_insn ""
1875 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1876 
        (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1877 
                             (match_operand:SI 2 "reg_or_short_operand" "rI"))
1878 
                         (const_int 0)
1879 
                         (minus:SI (match_dup 2) (match_dup 1))))]
1880 
  "TARGET_POWER"
1881 
  "doz%I2 %0,%1,%2")
1882 
 
1883 
(define_insn ""
1884 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1885 
        (compare:CC
1886 
         (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1887 
                              (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1888 
                          (const_int 0)
1889 
                          (minus:SI (match_dup 2) (match_dup 1)))
1890 
         (const_int 0)))
1891 
   (clobber (match_scratch:SI 3 "=r,r"))]
1892 
  "TARGET_POWER"
1893 
  "@
1894 
   doz%I2. %3,%1,%2
1895 
   #"
1896 
  [(set_attr "type" "delayed_compare")
1897 
   (set_attr "length" "4,8")])
1898 
 
1899 
(define_split
1900 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1901 
        (compare:CC
1902 
         (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1903 
                              (match_operand:SI 2 "reg_or_short_operand" ""))
1904 
                          (const_int 0)
1905 
                          (minus:SI (match_dup 2) (match_dup 1)))
1906 
         (const_int 0)))
1907 
   (clobber (match_scratch:SI 3 ""))]
1908 
  "TARGET_POWER && reload_completed"
1909 
  [(set (match_dup 3)
1910 
        (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1911 
                          (const_int 0)
1912 
                          (minus:SI (match_dup 2) (match_dup 1))))
1913 
   (set (match_dup 0)
1914 
        (compare:CC (match_dup 3)
1915 
                    (const_int 0)))]
1916 
  "")
1917 
 
1918 
(define_insn ""
1919 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1920 
        (compare:CC
1921 
         (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1922 
                              (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1923 
                          (const_int 0)
1924 
                          (minus:SI (match_dup 2) (match_dup 1)))
1925 
         (const_int 0)))
1926 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1927 
        (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1928 
                         (const_int 0)
1929 
                         (minus:SI (match_dup 2) (match_dup 1))))]
1930 
  "TARGET_POWER"
1931 
  "@
1932 
   doz%I2. %0,%1,%2
1933 
   #"
1934 
  [(set_attr "type" "delayed_compare")
1935 
   (set_attr "length" "4,8")])
1936 
 
1937 
(define_split
1938 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1939 
        (compare:CC
1940 
         (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1941 
                              (match_operand:SI 2 "reg_or_short_operand" ""))
1942 
                          (const_int 0)
1943 
                          (minus:SI (match_dup 2) (match_dup 1)))
1944 
         (const_int 0)))
1945 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1946 
        (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1947 
                         (const_int 0)
1948 
                         (minus:SI (match_dup 2) (match_dup 1))))]
1949 
  "TARGET_POWER && reload_completed"
1950 
  [(set (match_dup 0)
1951 
        (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1952 
                         (const_int 0)
1953 
                         (minus:SI (match_dup 2) (match_dup 1))))
1954 
   (set (match_dup 3)
1955 
        (compare:CC (match_dup 0)
1956 
                    (const_int 0)))]
1957 
  "")
1958 
 
1959 
;; We don't need abs with condition code because such comparisons should
1960 
;; never be done.
1961 
(define_expand "abssi2"
1962 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
1963 
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1964 
  ""
1965 
  "
1966 
{
1967 
  if (TARGET_ISEL)
1968 
    {
1969 
      emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1970 
      DONE;
1971 
    }
1972 
  else if (! TARGET_POWER)
1973 
    {
1974 
      emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1975 
      DONE;
1976 
    }
1977 
}")
1978 
 
1979 
(define_insn "*abssi2_power"
1980 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1981 
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1982 
  "TARGET_POWER"
1983 
  "abs %0,%1")
1984 
 
1985 
(define_insn_and_split "abssi2_isel"
1986 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1987 
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1988 
   (clobber (match_scratch:SI 2 "=&b"))
1989 
   (clobber (match_scratch:CC 3 "=y"))]
1990 
  "TARGET_ISEL"
1991 
  "#"
1992 
  "&& reload_completed"
1993 
  [(set (match_dup 2) (neg:SI (match_dup 1)))
1994 
   (set (match_dup 3)
1995 
        (compare:CC (match_dup 1)
1996 
                    (const_int 0)))
1997 
   (set (match_dup 0)
1998 
        (if_then_else:SI (ge (match_dup 3)
1999 
                             (const_int 0))
2000 
                         (match_dup 1)
2001 
                         (match_dup 2)))]
2002 
  "")
2003 
 
2004 
(define_insn_and_split "abssi2_nopower"
2005 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2006 
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2007 
   (clobber (match_scratch:SI 2 "=&r,&r"))]
2008 
  "! TARGET_POWER && ! TARGET_ISEL"
2009 
  "#"
2010 
  "&& reload_completed"
2011 
  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2012 
   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2013 
   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2014 
  "")
2015 
 
2016 
(define_insn "*nabs_power"
2017 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2018 
        (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2019 
  "TARGET_POWER"
2020 
  "nabs %0,%1")
2021 
 
2022 
(define_insn_and_split "*nabs_nopower"
2023 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2024 
        (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2025 
   (clobber (match_scratch:SI 2 "=&r,&r"))]
2026 
  "! TARGET_POWER"
2027 
  "#"
2028 
  "&& reload_completed"
2029 
  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2030 
   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2031 
   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2032 
  "")
2033 
 
2034 
(define_expand "neg2"
2035 
  [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2036 
        (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2037 
  ""
2038 
  "")
2039 
 
2040 
(define_insn "*neg2_internal"
2041 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2042 
        (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2043 
  ""
2044 
  "neg %0,%1")
2045 
 
2046 
(define_insn ""
2047 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2048 
        (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2049 
                    (const_int 0)))
2050 
   (clobber (match_scratch:P 2 "=r,r"))]
2051 
  ""
2052 
  "@
2053 
   neg. %2,%1
2054 
   #"
2055 
  [(set_attr "type" "fast_compare")
2056 
   (set_attr "length" "4,8")])
2057 
 
2058 
(define_split
2059 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2060 
        (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2061 
                    (const_int 0)))
2062 
   (clobber (match_scratch:P 2 ""))]
2063 
  "reload_completed"
2064 
  [(set (match_dup 2)
2065 
        (neg:P (match_dup 1)))
2066 
   (set (match_dup 0)
2067 
        (compare:CC (match_dup 2)
2068 
                    (const_int 0)))]
2069 
  "")
2070 
 
2071 
(define_insn ""
2072 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2073 
        (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2074 
                    (const_int 0)))
2075 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2076 
        (neg:P (match_dup 1)))]
2077 
  ""
2078 
  "@
2079 
   neg. %0,%1
2080 
   #"
2081 
  [(set_attr "type" "fast_compare")
2082 
   (set_attr "length" "4,8")])
2083 
 
2084 
(define_split
2085 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2086 
        (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2087 
                    (const_int 0)))
2088 
   (set (match_operand:P 0 "gpc_reg_operand" "")
2089 
        (neg:P (match_dup 1)))]
2090 
  "reload_completed"
2091 
  [(set (match_dup 0)
2092 
        (neg:P (match_dup 1)))
2093 
   (set (match_dup 2)
2094 
        (compare:CC (match_dup 0)
2095 
                    (const_int 0)))]
2096 
  "")
2097 
 
2098 
(define_insn "clz2"
2099 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2100 
        (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2101 
  ""
2102 
  "{cntlz|cntlz} %0,%1")
2103 
 
2104 
(define_expand "ctz2"
2105 
  [(set (match_dup 2)
2106 
        (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2107 
   (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2108 
                                          (match_dup 2)))
2109 
              (clobber (scratch:CC))])
2110 
   (set (match_dup 4) (clz:GPR (match_dup 3)))
2111 
   (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2112 
        (minus:GPR (match_dup 5) (match_dup 4)))]
2113 
  ""
2114 
  {
2115 
     operands[2] = gen_reg_rtx (mode);
2116 
     operands[3] = gen_reg_rtx (mode);
2117 
     operands[4] = gen_reg_rtx (mode);
2118 
     operands[5] = GEN_INT (GET_MODE_BITSIZE (mode) - 1);
2119 
  })
2120 
 
2121 
(define_expand "ffs2"
2122 
  [(set (match_dup 2)
2123 
        (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2124 
   (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2125 
                                          (match_dup 2)))
2126 
              (clobber (scratch:CC))])
2127 
   (set (match_dup 4) (clz:GPR (match_dup 3)))
2128 
   (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2129 
        (minus:GPR (match_dup 5) (match_dup 4)))]
2130 
  ""
2131 
  {
2132 
     operands[2] = gen_reg_rtx (mode);
2133 
     operands[3] = gen_reg_rtx (mode);
2134 
     operands[4] = gen_reg_rtx (mode);
2135 
     operands[5] = GEN_INT (GET_MODE_BITSIZE (mode));
2136 
  })
2137 
 
2138 
(define_expand "popcount2"
2139 
  [(set (match_dup 2)
2140 
        (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2141 
                     UNSPEC_POPCNTB))
2142 
   (set (match_dup 3)
2143 
        (mult:GPR (match_dup 2) (match_dup 4)))
2144 
   (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2145 
        (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
2146 
  "TARGET_POPCNTB"
2147 
  {
2148 
    operands[2] = gen_reg_rtx (mode);
2149 
    operands[3] = gen_reg_rtx (mode);
2150 
    operands[4] = force_reg (mode,
2151 
                             mode == SImode
2152 
                             ? GEN_INT (0x01010101)
2153 
                             : GEN_INT ((HOST_WIDE_INT)
2154 
                                        0x01010101 << 32 | 0x01010101));
2155 
    operands[5] = GEN_INT (GET_MODE_BITSIZE (mode) - 8);
2156 
  })
2157 
 
2158 
(define_insn "popcntb2"
2159 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2160 
        (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2161 
                     UNSPEC_POPCNTB))]
2162 
  "TARGET_POPCNTB"
2163 
  "popcntb %0,%1")
2164 
 
2165 
(define_expand "mulsi3"
2166 
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2167 
   (use (match_operand:SI 1 "gpc_reg_operand" ""))
2168 
   (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2169 
  ""
2170 
  "
2171 
{
2172 
  if (TARGET_POWER)
2173 
    emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2174 
  else
2175 
    emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2176 
  DONE;
2177 
}")
2178 
 
2179 
(define_insn "mulsi3_mq"
2180 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2181 
        (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2182 
                 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2183 
   (clobber (match_scratch:SI 3 "=q,q"))]
2184 
  "TARGET_POWER"
2185 
  "@
2186 
   {muls|mullw} %0,%1,%2
2187 
   {muli|mulli} %0,%1,%2"
2188 
   [(set (attr "type")
2189 
      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2190 
                (const_string "imul3")
2191 
             (match_operand:SI 2 "short_cint_operand" "")
2192 
                (const_string "imul2")]
2193 
        (const_string "imul")))])
2194 
 
2195 
(define_insn "mulsi3_no_mq"
2196 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2197 
        (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2198 
                 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2199 
  "! TARGET_POWER"
2200 
  "@
2201 
   {muls|mullw} %0,%1,%2
2202 
   {muli|mulli} %0,%1,%2"
2203 
   [(set (attr "type")
2204 
      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2205 
                (const_string "imul3")
2206 
             (match_operand:SI 2 "short_cint_operand" "")
2207 
                (const_string "imul2")]
2208 
        (const_string "imul")))])
2209 
 
2210 
(define_insn "*mulsi3_mq_internal1"
2211 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2212 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2213 
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2214 
                    (const_int 0)))
2215 
   (clobber (match_scratch:SI 3 "=r,r"))
2216 
   (clobber (match_scratch:SI 4 "=q,q"))]
2217 
  "TARGET_POWER"
2218 
  "@
2219 
   {muls.|mullw.} %3,%1,%2
2220 
   #"
2221 
  [(set_attr "type" "imul_compare")
2222 
   (set_attr "length" "4,8")])
2223 
 
2224 
(define_split
2225 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2226 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2227 
                             (match_operand:SI 2 "gpc_reg_operand" ""))
2228 
                    (const_int 0)))
2229 
   (clobber (match_scratch:SI 3 ""))
2230 
   (clobber (match_scratch:SI 4 ""))]
2231 
  "TARGET_POWER && reload_completed"
2232 
  [(parallel [(set (match_dup 3)
2233 
        (mult:SI (match_dup 1) (match_dup 2)))
2234 
   (clobber (match_dup 4))])
2235 
   (set (match_dup 0)
2236 
        (compare:CC (match_dup 3)
2237 
                    (const_int 0)))]
2238 
  "")
2239 
 
2240 
(define_insn "*mulsi3_no_mq_internal1"
2241 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2242 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2243 
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2244 
                    (const_int 0)))
2245 
   (clobber (match_scratch:SI 3 "=r,r"))]
2246 
  "! TARGET_POWER"
2247 
  "@
2248 
   {muls.|mullw.} %3,%1,%2
2249 
   #"
2250 
  [(set_attr "type" "imul_compare")
2251 
   (set_attr "length" "4,8")])
2252 
 
2253 
(define_split
2254 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2255 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2256 
                             (match_operand:SI 2 "gpc_reg_operand" ""))
2257 
                    (const_int 0)))
2258 
   (clobber (match_scratch:SI 3 ""))]
2259 
  "! TARGET_POWER && reload_completed"
2260 
  [(set (match_dup 3)
2261 
        (mult:SI (match_dup 1) (match_dup 2)))
2262 
   (set (match_dup 0)
2263 
        (compare:CC (match_dup 3)
2264 
                    (const_int 0)))]
2265 
  "")
2266 
 
2267 
(define_insn "*mulsi3_mq_internal2"
2268 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2269 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2270 
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2271 
                    (const_int 0)))
2272 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2273 
        (mult:SI (match_dup 1) (match_dup 2)))
2274 
   (clobber (match_scratch:SI 4 "=q,q"))]
2275 
  "TARGET_POWER"
2276 
  "@
2277 
   {muls.|mullw.} %0,%1,%2
2278 
   #"
2279 
  [(set_attr "type" "imul_compare")
2280 
   (set_attr "length" "4,8")])
2281 
 
2282 
(define_split
2283 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2284 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2285 
                             (match_operand:SI 2 "gpc_reg_operand" ""))
2286 
                    (const_int 0)))
2287 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
2288 
        (mult:SI (match_dup 1) (match_dup 2)))
2289 
   (clobber (match_scratch:SI 4 ""))]
2290 
  "TARGET_POWER && reload_completed"
2291 
  [(parallel [(set (match_dup 0)
2292 
        (mult:SI (match_dup 1) (match_dup 2)))
2293 
   (clobber (match_dup 4))])
2294 
   (set (match_dup 3)
2295 
        (compare:CC (match_dup 0)
2296 
                    (const_int 0)))]
2297 
  "")
2298 
 
2299 
(define_insn "*mulsi3_no_mq_internal2"
2300 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2301 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2302 
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2303 
                    (const_int 0)))
2304 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2305 
        (mult:SI (match_dup 1) (match_dup 2)))]
2306 
  "! TARGET_POWER"
2307 
  "@
2308 
   {muls.|mullw.} %0,%1,%2
2309 
   #"
2310 
  [(set_attr "type" "imul_compare")
2311 
   (set_attr "length" "4,8")])
2312 
 
2313 
(define_split
2314 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2315 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2316 
                             (match_operand:SI 2 "gpc_reg_operand" ""))
2317 
                    (const_int 0)))
2318 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
2319 
        (mult:SI (match_dup 1) (match_dup 2)))]
2320 
  "! TARGET_POWER && reload_completed"
2321 
  [(set (match_dup 0)
2322 
        (mult:SI (match_dup 1) (match_dup 2)))
2323 
   (set (match_dup 3)
2324 
        (compare:CC (match_dup 0)
2325 
                    (const_int 0)))]
2326 
  "")
2327 
 
2328 
;; Operand 1 is divided by operand 2; quotient goes to operand
2329 
;; 0 and remainder to operand 3.
2330 
;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2331 
 
2332 
(define_expand "divmodsi4"
2333 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2334 
                   (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2335 
                           (match_operand:SI 2 "gpc_reg_operand" "")))
2336 
              (set (match_operand:SI 3 "register_operand" "")
2337 
                   (mod:SI (match_dup 1) (match_dup 2)))])]
2338 
  "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2339 
  "
2340 
{
2341 
  if (! TARGET_POWER && ! TARGET_POWERPC)
2342 
    {
2343 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2344 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2345 
      emit_insn (gen_divss_call ());
2346 
      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2347 
      emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2348 
      DONE;
2349 
    }
2350 
}")
2351 
 
2352 
(define_insn "*divmodsi4_internal"
2353 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2354 
        (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2355 
                (match_operand:SI 2 "gpc_reg_operand" "r")))
2356 
   (set (match_operand:SI 3 "register_operand" "=q")
2357 
        (mod:SI (match_dup 1) (match_dup 2)))]
2358 
  "TARGET_POWER"
2359 
  "divs %0,%1,%2"
2360 
  [(set_attr "type" "idiv")])
2361 
 
2362 
(define_expand "udiv3"
2363 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2364 
        (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2365 
                  (match_operand:GPR 2 "gpc_reg_operand" "")))]
2366 
  "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2367 
  "
2368 
{
2369 
  if (! TARGET_POWER && ! TARGET_POWERPC)
2370 
    {
2371 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2372 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2373 
      emit_insn (gen_quous_call ());
2374 
      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2375 
      DONE;
2376 
    }
2377 
  else if (TARGET_POWER)
2378 
    {
2379 
      emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2380 
      DONE;
2381 
    }
2382 
}")
2383 
 
2384 
(define_insn "udivsi3_mq"
2385 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2386 
        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2387 
                 (match_operand:SI 2 "gpc_reg_operand" "r")))
2388 
   (clobber (match_scratch:SI 3 "=q"))]
2389 
  "TARGET_POWERPC && TARGET_POWER"
2390 
  "divwu %0,%1,%2"
2391 
  [(set_attr "type" "idiv")])
2392 
 
2393 
(define_insn "*udivsi3_no_mq"
2394 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2395 
        (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2396 
                  (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2397 
  "TARGET_POWERPC && ! TARGET_POWER"
2398 
  "divu %0,%1,%2"
2399 
  [(set_attr "type" "idiv")])
2400 
 
2401 
;; For powers of two we can do srai/aze for divide and then adjust for
2402 
;; modulus.  If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2403 
;; used; for PowerPC, force operands into register and do a normal divide;
2404 
;; for AIX common-mode, use quoss call on register operands.
2405 
(define_expand "div3"
2406 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2407 
        (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2408 
                 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2409 
  ""
2410 
  "
2411 
{
2412 
  if (GET_CODE (operands[2]) == CONST_INT
2413 
      && INTVAL (operands[2]) > 0
2414 
      && exact_log2 (INTVAL (operands[2])) >= 0)
2415 
    ;
2416 
  else if (TARGET_POWERPC)
2417 
    {
2418 
      operands[2] = force_reg (mode, operands[2]);
2419 
      if (TARGET_POWER)
2420 
        {
2421 
          emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2422 
          DONE;
2423 
        }
2424 
    }
2425 
  else if (TARGET_POWER)
2426 
    FAIL;
2427 
  else
2428 
    {
2429 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2430 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2431 
      emit_insn (gen_quoss_call ());
2432 
      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2433 
      DONE;
2434 
    }
2435 
}")
2436 
 
2437 
(define_insn "divsi3_mq"
2438 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2439 
        (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2440 
                (match_operand:SI 2 "gpc_reg_operand" "r")))
2441 
   (clobber (match_scratch:SI 3 "=q"))]
2442 
  "TARGET_POWERPC && TARGET_POWER"
2443 
  "divw %0,%1,%2"
2444 
  [(set_attr "type" "idiv")])
2445 
 
2446 
(define_insn "*div3_no_mq"
2447 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2448 
        (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2449 
                 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2450 
  "TARGET_POWERPC && ! TARGET_POWER"
2451 
  "div %0,%1,%2"
2452 
  [(set_attr "type" "idiv")])
2453 
 
2454 
(define_expand "mod3"
2455 
  [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2456 
   (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2457 
   (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2458 
  ""
2459 
  "
2460 
{
2461 
  int i;
2462 
  rtx temp1;
2463 
  rtx temp2;
2464 
 
2465 
  if (GET_CODE (operands[2]) != CONST_INT
2466 
      || INTVAL (operands[2]) <= 0
2467 
      || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2468 
    FAIL;
2469 
 
2470 
  temp1 = gen_reg_rtx (mode);
2471 
  temp2 = gen_reg_rtx (mode);
2472 
 
2473 
  emit_insn (gen_div3 (temp1, operands[1], operands[2]));
2474 
  emit_insn (gen_ashl3 (temp2, temp1, GEN_INT (i)));
2475 
  emit_insn (gen_sub3 (operands[0], operands[1], temp2));
2476 
  DONE;
2477 
}")
2478 
 
2479 
(define_insn ""
2480 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2481 
        (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2482 
                 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2483 
  ""
2484 
  "{srai|srai} %0,%1,%p2\;{aze|addze} %0,%0"
2485 
  [(set_attr "type" "two")
2486 
   (set_attr "length" "8")])
2487 
 
2488 
(define_insn ""
2489 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2490 
        (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2491 
                           (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2492 
                    (const_int 0)))
2493 
   (clobber (match_scratch:P 3 "=r,r"))]
2494 
  ""
2495 
  "@
2496 
   {srai|srai} %3,%1,%p2\;{aze.|addze.} %3,%3
2497 
   #"
2498 
  [(set_attr "type" "compare")
2499 
   (set_attr "length" "8,12")])
2500 
 
2501 
(define_split
2502 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2503 
        (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2504 
                             (match_operand:GPR 2 "exact_log2_cint_operand"
2505 
                              ""))
2506 
                    (const_int 0)))
2507 
   (clobber (match_scratch:GPR 3 ""))]
2508 
  "reload_completed"
2509 
  [(set (match_dup 3)
2510 
        (div: (match_dup 1) (match_dup 2)))
2511 
   (set (match_dup 0)
2512 
        (compare:CC (match_dup 3)
2513 
                    (const_int 0)))]
2514 
  "")
2515 
 
2516 
(define_insn ""
2517 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2518 
        (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2519 
                           (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2520 
                    (const_int 0)))
2521 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2522 
        (div:P (match_dup 1) (match_dup 2)))]
2523 
  ""
2524 
  "@
2525 
   {srai|srai} %0,%1,%p2\;{aze.|addze.} %0,%0
2526 
   #"
2527 
  [(set_attr "type" "compare")
2528 
   (set_attr "length" "8,12")])
2529 
 
2530 
(define_split
2531 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2532 
        (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2533 
                             (match_operand:GPR 2 "exact_log2_cint_operand"
2534 
                              ""))
2535 
                    (const_int 0)))
2536 
   (set (match_operand:GPR 0 "gpc_reg_operand" "")
2537 
        (div:GPR (match_dup 1) (match_dup 2)))]
2538 
  "reload_completed"
2539 
  [(set (match_dup 0)
2540 
        (div: (match_dup 1) (match_dup 2)))
2541 
   (set (match_dup 3)
2542 
        (compare:CC (match_dup 0)
2543 
                    (const_int 0)))]
2544 
  "")
2545 
 
2546 
(define_insn ""
2547 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2548 
        (udiv:SI
2549 
         (plus:DI (ashift:DI
2550 
                   (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2551 
                   (const_int 32))
2552 
                  (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2553 
         (match_operand:SI 3 "gpc_reg_operand" "r")))
2554 
   (set (match_operand:SI 2 "register_operand" "=*q")
2555 
        (umod:SI
2556 
         (plus:DI (ashift:DI
2557 
                   (zero_extend:DI (match_dup 1)) (const_int 32))
2558 
                  (zero_extend:DI (match_dup 4)))
2559 
         (match_dup 3)))]
2560 
  "TARGET_POWER"
2561 
  "div %0,%1,%3"
2562 
  [(set_attr "type" "idiv")])
2563 
 
2564 
;; To do unsigned divide we handle the cases of the divisor looking like a
2565 
;; negative number.  If it is a constant that is less than 2**31, we don't
2566 
;; have to worry about the branches.  So make a few subroutines here.
2567 
;;
2568 
;; First comes the normal case.
2569 
(define_expand "udivmodsi4_normal"
2570 
  [(set (match_dup 4) (const_int 0))
2571 
   (parallel [(set (match_operand:SI 0 "" "")
2572 
                   (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2573 
                                                (const_int 32))
2574 
                                     (zero_extend:DI (match_operand:SI 1 "" "")))
2575 
                            (match_operand:SI 2 "" "")))
2576 
              (set (match_operand:SI 3 "" "")
2577 
                   (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2578 
                                                (const_int 32))
2579 
                                     (zero_extend:DI (match_dup 1)))
2580 
                            (match_dup 2)))])]
2581 
  "TARGET_POWER"
2582 
  "
2583 
{ operands[4] = gen_reg_rtx (SImode); }")
2584 
 
2585 
;; This handles the branches.
2586 
(define_expand "udivmodsi4_tests"
2587 
  [(set (match_operand:SI 0 "" "") (const_int 0))
2588 
   (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2589 
   (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2590 
   (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2591 
                           (label_ref (match_operand:SI 4 "" "")) (pc)))
2592 
   (set (match_dup 0) (const_int 1))
2593 
   (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2594 
   (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2595 
   (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2596 
                           (label_ref (match_dup 4)) (pc)))]
2597 
  "TARGET_POWER"
2598 
  "
2599 
{ operands[5] = gen_reg_rtx (CCUNSmode);
2600 
  operands[6] = gen_reg_rtx (CCmode);
2601 
}")
2602 
 
2603 
(define_expand "udivmodsi4"
2604 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2605 
                   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2606 
                            (match_operand:SI 2 "reg_or_cint_operand" "")))
2607 
              (set (match_operand:SI 3 "gpc_reg_operand" "")
2608 
                   (umod:SI (match_dup 1) (match_dup 2)))])]
2609 
  ""
2610 
  "
2611 
{
2612 
  rtx label = 0;
2613 
 
2614 
  if (! TARGET_POWER)
2615 
    {
2616 
      if (! TARGET_POWERPC)
2617 
        {
2618 
          emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2619 
          emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2620 
          emit_insn (gen_divus_call ());
2621 
          emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2622 
          emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2623 
          DONE;
2624 
        }
2625 
      else
2626 
        FAIL;
2627 
    }
2628 
 
2629 
  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2630 
    {
2631 
      operands[2] = force_reg (SImode, operands[2]);
2632 
      label = gen_label_rtx ();
2633 
      emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2634 
                                  operands[3], label));
2635 
    }
2636 
  else
2637 
    operands[2] = force_reg (SImode, operands[2]);
2638 
 
2639 
  emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2640 
                               operands[3]));
2641 
  if (label)
2642 
    emit_label (label);
2643 
 
2644 
  DONE;
2645 
}")
2646 
 
2647 
;; AIX architecture-independent common-mode multiply (DImode),
2648 
;; divide/modulus, and quotient subroutine calls.  Input operands in R3 and
2649 
;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2650 
;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2651 
;; assumed unused if generating common-mode, so ignore.
2652 
(define_insn "mulh_call"
2653 
  [(set (reg:SI 3)
2654 
        (truncate:SI
2655 
         (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2656 
                               (sign_extend:DI (reg:SI 4)))
2657 
                      (const_int 32))))
2658 
   (clobber (match_scratch:SI 0 "=l"))]
2659 
  "! TARGET_POWER && ! TARGET_POWERPC"
2660 
  "bla __mulh"
2661 
  [(set_attr "type" "imul")])
2662 
 
2663 
(define_insn "mull_call"
2664 
  [(set (reg:DI 3)
2665 
        (mult:DI (sign_extend:DI (reg:SI 3))
2666 
                 (sign_extend:DI (reg:SI 4))))
2667 
   (clobber (match_scratch:SI 0 "=l"))
2668 
   (clobber (reg:SI 0))]
2669 
  "! TARGET_POWER && ! TARGET_POWERPC"
2670 
  "bla __mull"
2671 
  [(set_attr "type" "imul")])
2672 
 
2673 
(define_insn "divss_call"
2674 
  [(set (reg:SI 3)
2675 
        (div:SI (reg:SI 3) (reg:SI 4)))
2676 
   (set (reg:SI 4)
2677 
        (mod:SI (reg:SI 3) (reg:SI 4)))
2678 
   (clobber (match_scratch:SI 0 "=l"))
2679 
   (clobber (reg:SI 0))]
2680 
  "! TARGET_POWER && ! TARGET_POWERPC"
2681 
  "bla __divss"
2682 
  [(set_attr "type" "idiv")])
2683 
 
2684 
(define_insn "divus_call"
2685 
  [(set (reg:SI 3)
2686 
        (udiv:SI (reg:SI 3) (reg:SI 4)))
2687 
   (set (reg:SI 4)
2688 
        (umod:SI (reg:SI 3) (reg:SI 4)))
2689 
   (clobber (match_scratch:SI 0 "=l"))
2690 
   (clobber (reg:SI 0))
2691 
   (clobber (match_scratch:CC 1 "=x"))
2692 
   (clobber (reg:CC 69))]
2693 
  "! TARGET_POWER && ! TARGET_POWERPC"
2694 
  "bla __divus"
2695 
  [(set_attr "type" "idiv")])
2696 
 
2697 
(define_insn "quoss_call"
2698 
  [(set (reg:SI 3)
2699 
        (div:SI (reg:SI 3) (reg:SI 4)))
2700 
   (clobber (match_scratch:SI 0 "=l"))]
2701 
  "! TARGET_POWER && ! TARGET_POWERPC"
2702 
  "bla __quoss"
2703 
  [(set_attr "type" "idiv")])
2704 
 
2705 
(define_insn "quous_call"
2706 
  [(set (reg:SI 3)
2707 
        (udiv:SI (reg:SI 3) (reg:SI 4)))
2708 
   (clobber (match_scratch:SI 0 "=l"))
2709 
   (clobber (reg:SI 0))
2710 
   (clobber (match_scratch:CC 1 "=x"))
2711 
   (clobber (reg:CC 69))]
2712 
  "! TARGET_POWER && ! TARGET_POWERPC"
2713 
  "bla __quous"
2714 
  [(set_attr "type" "idiv")])
2715 
 
2716 
;; Logical instructions
2717 
;; The logical instructions are mostly combined by using match_operator,
2718 
;; but the plain AND insns are somewhat different because there is no
2719 
;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2720 
;; those rotate-and-mask operations.  Thus, the AND insns come first.
2721 
 
2722 
(define_insn "andsi3"
2723 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2724 
        (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2725 
                (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2726 
   (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2727 
  ""
2728 
  "@
2729 
   and %0,%1,%2
2730 
   {rlinm|rlwinm} %0,%1,0,%m2,%M2
2731 
   {andil.|andi.} %0,%1,%b2
2732 
   {andiu.|andis.} %0,%1,%u2"
2733 
  [(set_attr "type" "*,*,compare,compare")])
2734 
 
2735 
;; Note to set cr's other than cr0 we do the and immediate and then
2736 
;; the test again -- this avoids a mfcr which on the higher end
2737 
;; machines causes an execution serialization
2738 
 
2739 
(define_insn "*andsi3_internal2"
2740 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2741 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2742 
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2743 
                    (const_int 0)))
2744 
   (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2745 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2746 
  "TARGET_32BIT"
2747 
  "@
2748 
   and. %3,%1,%2
2749 
   {andil.|andi.} %3,%1,%b2
2750 
   {andiu.|andis.} %3,%1,%u2
2751 
   {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2752 
   #
2753 
   #
2754 
   #
2755 
   #"
2756 
  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2757 
   (set_attr "length" "4,4,4,4,8,8,8,8")])
2758 
 
2759 
(define_insn "*andsi3_internal3"
2760 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2761 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2762 
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2763 
                    (const_int 0)))
2764 
   (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2765 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2766 
  "TARGET_64BIT"
2767 
  "@
2768 
   #
2769 
   {andil.|andi.} %3,%1,%b2
2770 
   {andiu.|andis.} %3,%1,%u2
2771 
   {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2772 
   #
2773 
   #
2774 
   #
2775 
   #"
2776 
  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2777 
   (set_attr "length" "8,4,4,4,8,8,8,8")])
2778 
 
2779 
(define_split
2780 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2781 
        (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2782 
                             (match_operand:GPR 2 "and_operand" ""))
2783 
                    (const_int 0)))
2784 
   (clobber (match_scratch:GPR 3 ""))
2785 
   (clobber (match_scratch:CC 4 ""))]
2786 
  "reload_completed"
2787 
  [(parallel [(set (match_dup 3)
2788 
                   (and: (match_dup 1)
2789 
                               (match_dup 2)))
2790 
              (clobber (match_dup 4))])
2791 
   (set (match_dup 0)
2792 
        (compare:CC (match_dup 3)
2793 
                    (const_int 0)))]
2794 
  "")
2795 
 
2796 
;; We don't have a 32 bit "and. rt,ra,rb" for ppc64.  cr is set from the
2797 
;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2798 
 
2799 
(define_split
2800 
  [(set (match_operand:CC 0 "cc_reg_operand" "")
2801 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2802 
                            (match_operand:SI 2 "gpc_reg_operand" ""))
2803 
                    (const_int 0)))
2804 
   (clobber (match_scratch:SI 3 ""))
2805 
   (clobber (match_scratch:CC 4 ""))]
2806 
  "TARGET_POWERPC64 && reload_completed"
2807 
  [(parallel [(set (match_dup 3)
2808 
                   (and:SI (match_dup 1)
2809 
                           (match_dup 2)))
2810 
              (clobber (match_dup 4))])
2811 
   (set (match_dup 0)
2812 
        (compare:CC (match_dup 3)
2813 
                    (const_int 0)))]
2814 
  "")
2815 
 
2816 
(define_insn "*andsi3_internal4"
2817 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2818 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2819 
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2820 
                    (const_int 0)))
2821 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2822 
        (and:SI (match_dup 1)
2823 
                (match_dup 2)))
2824 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2825 
  "TARGET_32BIT"
2826 
  "@
2827 
   and. %0,%1,%2
2828 
   {andil.|andi.} %0,%1,%b2
2829 
   {andiu.|andis.} %0,%1,%u2
2830 
   {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2831 
   #
2832 
   #
2833 
   #
2834 
   #"
2835 
  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2836 
   (set_attr "length" "4,4,4,4,8,8,8,8")])
2837 
 
2838 
(define_insn "*andsi3_internal5"
2839 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2840 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2841 
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2842 
                    (const_int 0)))
2843 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2844 
        (and:SI (match_dup 1)
2845 
                (match_dup 2)))
2846 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2847 
  "TARGET_64BIT"
2848 
  "@
2849 
   #
2850 
   {andil.|andi.} %0,%1,%b2
2851 
   {andiu.|andis.} %0,%1,%u2
2852 
   {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2853 
   #
2854 
   #
2855 
   #
2856 
   #"
2857 
  [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2858 
   (set_attr "length" "8,4,4,4,8,8,8,8")])
2859 
 
2860 
(define_split
2861 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2862 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2863 
                            (match_operand:SI 2 "and_operand" ""))
2864 
                    (const_int 0)))
2865 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
2866 
        (and:SI (match_dup 1)
2867 
                (match_dup 2)))
2868 
   (clobber (match_scratch:CC 4 ""))]
2869 
  "reload_completed"
2870 
  [(parallel [(set (match_dup 0)
2871 
                   (and:SI (match_dup 1)
2872 
                           (match_dup 2)))
2873 
              (clobber (match_dup 4))])
2874 
   (set (match_dup 3)
2875 
        (compare:CC (match_dup 0)
2876 
                    (const_int 0)))]
2877 
  "")
2878 
 
2879 
(define_split
2880 
  [(set (match_operand:CC 3 "cc_reg_operand" "")
2881 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2882 
                            (match_operand:SI 2 "gpc_reg_operand" ""))
2883 
                    (const_int 0)))
2884 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
2885 
        (and:SI (match_dup 1)
2886 
                (match_dup 2)))
2887 
   (clobber (match_scratch:CC 4 ""))]
2888 
  "TARGET_POWERPC64 && reload_completed"
2889 
  [(parallel [(set (match_dup 0)
2890 
                   (and:SI (match_dup 1)
2891 
                           (match_dup 2)))
2892 
              (clobber (match_dup 4))])
2893 
   (set (match_dup 3)
2894 
        (compare:CC (match_dup 0)
2895 
                    (const_int 0)))]
2896 
  "")
2897 
 
2898 
;; Handle the PowerPC64 rlwinm corner case
2899 
 
2900 
(define_insn_and_split "*andsi3_internal6"
2901 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2902 
        (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2903 
                (match_operand:SI 2 "mask_operand_wrap" "i")))]
2904 
  "TARGET_POWERPC64"
2905 
  "#"
2906 
  "TARGET_POWERPC64"
2907 
  [(set (match_dup 0)
2908 
        (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2909 
                (match_dup 4)))
2910 
   (set (match_dup 0)
2911 
        (rotate:SI (match_dup 0) (match_dup 5)))]
2912 
  "
2913 
{
2914 
  int mb = extract_MB (operands[2]);
2915 
  int me = extract_ME (operands[2]);
2916 
  operands[3] = GEN_INT (me + 1);
2917 
  operands[5] = GEN_INT (32 - (me + 1));
2918 
  operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2919 
}"
2920 
  [(set_attr "length" "8")])
2921 
 
2922 
(define_expand "iorsi3"
2923 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
2924 
        (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2925 
                (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2926 
  ""
2927 
  "
2928 
{
2929 
  if (GET_CODE (operands[2]) == CONST_INT
2930 
      && ! logical_operand (operands[2], SImode))
2931 
    {
2932 
      HOST_WIDE_INT value = INTVAL (operands[2]);
2933 
      rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2934 
                 ? operands[0] : gen_reg_rtx (SImode));
2935 
 
2936 
      emit_insn (gen_iorsi3 (tmp, operands[1],
2937 
                             GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2938 
      emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2939 
      DONE;
2940 
    }
2941 
}")
2942 
 
2943 
(define_expand "xorsi3"
2944 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
2945 
        (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2946 
                (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2947 
  ""
2948 
  "
2949 
{
2950 
  if (GET_CODE (operands[2]) == CONST_INT
2951 
      && ! logical_operand (operands[2], SImode))
2952 
    {
2953 
      HOST_WIDE_INT value = INTVAL (operands[2]);
2954 
      rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2955 
                 ? operands[0] : gen_reg_rtx (SImode));
2956 
 
2957 
      emit_insn (gen_xorsi3 (tmp, operands[1],
2958 
                             GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2959 
      emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2960 
      DONE;
2961 
    }
2962 
}")
2963 
 
2964 
(define_insn "*boolsi3_internal1"
2965 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2966 
        (match_operator:SI 3 "boolean_or_operator"
2967 
         [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2968 
          (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2969 
  ""
2970 
  "@
2971 
   %q3 %0,%1,%2
2972 
   {%q3il|%q3i} %0,%1,%b2
2973 
   {%q3iu|%q3is} %0,%1,%u2")
2974 
 
2975 
(define_insn "*boolsi3_internal2"
2976 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2977 
        (compare:CC (match_operator:SI 4 "boolean_or_operator"
2978 
         [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2979 
          (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2980 
         (const_int 0)))
2981 
   (clobber (match_scratch:SI 3 "=r,r"))]
2982 
  "TARGET_32BIT"
2983 
  "@
2984 
   %q4. %3,%1,%2
2985 
   #"
2986 
  [(set_attr "type" "compare")
2987 
   (set_attr "length" "4,8")])
2988 
 
2989 
(define_split
2990 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2991 
        (compare:CC (match_operator:SI 4 "boolean_operator"
2992 
         [(match_operand:SI 1 "gpc_reg_operand" "")
2993 
          (match_operand:SI 2 "gpc_reg_operand" "")])
2994 
         (const_int 0)))
2995 
   (clobber (match_scratch:SI 3 ""))]
2996 
  "TARGET_32BIT && reload_completed"
2997 
  [(set (match_dup 3) (match_dup 4))
2998 
   (set (match_dup 0)
2999 
        (compare:CC (match_dup 3)
3000 
                    (const_int 0)))]
3001 
  "")
3002 
 
3003 
(define_insn "*boolsi3_internal3"
3004 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3005 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3006 
         [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3007 
          (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3008 
         (const_int 0)))
3009 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3010 
        (match_dup 4))]
3011 
  "TARGET_32BIT"
3012 
  "@
3013 
   %q4. %0,%1,%2
3014 
   #"
3015 
  [(set_attr "type" "compare")
3016 
   (set_attr "length" "4,8")])
3017 
 
3018 
(define_split
3019 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3020 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3021 
         [(match_operand:SI 1 "gpc_reg_operand" "")
3022 
          (match_operand:SI 2 "gpc_reg_operand" "")])
3023 
         (const_int 0)))
3024 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3025 
        (match_dup 4))]
3026 
  "TARGET_32BIT && reload_completed"
3027 
  [(set (match_dup 0) (match_dup 4))
3028 
   (set (match_dup 3)
3029 
        (compare:CC (match_dup 0)
3030 
                    (const_int 0)))]
3031 
  "")
3032 
 
3033 
;; Split a logical operation that we can't do in one insn into two insns,
3034 
;; each of which does one 16-bit part.  This is used by combine.
3035 
 
3036 
(define_split
3037 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
3038 
        (match_operator:SI 3 "boolean_or_operator"
3039 
         [(match_operand:SI 1 "gpc_reg_operand" "")
3040 
          (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3041 
  ""
3042 
  [(set (match_dup 0) (match_dup 4))
3043 
   (set (match_dup 0) (match_dup 5))]
3044 
"
3045 
{
3046 
  rtx i;
3047 
  i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3048 
  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3049 
                                operands[1], i);
3050 
  i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3051 
  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3052 
                                operands[0], i);
3053 
}")
3054 
 
3055 
(define_insn "*boolcsi3_internal1"
3056 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3057 
        (match_operator:SI 3 "boolean_operator"
3058 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3059 
          (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3060 
  ""
3061 
  "%q3 %0,%2,%1")
3062 
 
3063 
(define_insn "*boolcsi3_internal2"
3064 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3065 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3066 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3067 
          (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3068 
         (const_int 0)))
3069 
   (clobber (match_scratch:SI 3 "=r,r"))]
3070 
  "TARGET_32BIT"
3071 
  "@
3072 
   %q4. %3,%2,%1
3073 
   #"
3074 
  [(set_attr "type" "compare")
3075 
   (set_attr "length" "4,8")])
3076 
 
3077 
(define_split
3078 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3079 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3080 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3081 
          (match_operand:SI 2 "gpc_reg_operand" "")])
3082 
         (const_int 0)))
3083 
   (clobber (match_scratch:SI 3 ""))]
3084 
  "TARGET_32BIT && reload_completed"
3085 
  [(set (match_dup 3) (match_dup 4))
3086 
   (set (match_dup 0)
3087 
        (compare:CC (match_dup 3)
3088 
                    (const_int 0)))]
3089 
  "")
3090 
 
3091 
(define_insn "*boolcsi3_internal3"
3092 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3093 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3094 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3095 
          (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3096 
         (const_int 0)))
3097 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3098 
        (match_dup 4))]
3099 
  "TARGET_32BIT"
3100 
  "@
3101 
   %q4. %0,%2,%1
3102 
   #"
3103 
  [(set_attr "type" "compare")
3104 
   (set_attr "length" "4,8")])
3105 
 
3106 
(define_split
3107 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3108 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3109 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3110 
          (match_operand:SI 2 "gpc_reg_operand" "")])
3111 
         (const_int 0)))
3112 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3113 
        (match_dup 4))]
3114 
  "TARGET_32BIT && reload_completed"
3115 
  [(set (match_dup 0) (match_dup 4))
3116 
   (set (match_dup 3)
3117 
        (compare:CC (match_dup 0)
3118 
                    (const_int 0)))]
3119 
  "")
3120 
 
3121 
(define_insn "*boolccsi3_internal1"
3122 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3123 
        (match_operator:SI 3 "boolean_operator"
3124 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3125 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3126 
  ""
3127 
  "%q3 %0,%1,%2")
3128 
 
3129 
(define_insn "*boolccsi3_internal2"
3130 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3131 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3132 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3133 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3134 
         (const_int 0)))
3135 
   (clobber (match_scratch:SI 3 "=r,r"))]
3136 
  "TARGET_32BIT"
3137 
  "@
3138 
   %q4. %3,%1,%2
3139 
   #"
3140 
  [(set_attr "type" "compare")
3141 
   (set_attr "length" "4,8")])
3142 
 
3143 
(define_split
3144 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3145 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3146 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3147 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3148 
         (const_int 0)))
3149 
   (clobber (match_scratch:SI 3 ""))]
3150 
  "TARGET_32BIT && reload_completed"
3151 
  [(set (match_dup 3) (match_dup 4))
3152 
   (set (match_dup 0)
3153 
        (compare:CC (match_dup 3)
3154 
                    (const_int 0)))]
3155 
  "")
3156 
 
3157 
(define_insn "*boolccsi3_internal3"
3158 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3159 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3160 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3161 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3162 
         (const_int 0)))
3163 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3164 
        (match_dup 4))]
3165 
  "TARGET_32BIT"
3166 
  "@
3167 
   %q4. %0,%1,%2
3168 
   #"
3169 
  [(set_attr "type" "compare")
3170 
   (set_attr "length" "4,8")])
3171 
 
3172 
(define_split
3173 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3174 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3175 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3176 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3177 
         (const_int 0)))
3178 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3179 
        (match_dup 4))]
3180 
  "TARGET_32BIT && reload_completed"
3181 
  [(set (match_dup 0) (match_dup 4))
3182 
   (set (match_dup 3)
3183 
        (compare:CC (match_dup 0)
3184 
                    (const_int 0)))]
3185 
  "")
3186 
 
3187 
;; maskir insn.  We need four forms because things might be in arbitrary
3188 
;; orders.  Don't define forms that only set CR fields because these
3189 
;; would modify an input register.
3190 
 
3191 
(define_insn "*maskir_internal1"
3192 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3193 
        (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3194 
                        (match_operand:SI 1 "gpc_reg_operand" "0"))
3195 
                (and:SI (match_dup 2)
3196 
                        (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3197 
  "TARGET_POWER"
3198 
  "maskir %0,%3,%2")
3199 
 
3200 
(define_insn "*maskir_internal2"
3201 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3202 
        (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3203 
                        (match_operand:SI 1 "gpc_reg_operand" "0"))
3204 
                (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3205 
                        (match_dup 2))))]
3206 
  "TARGET_POWER"
3207 
  "maskir %0,%3,%2")
3208 
 
3209 
(define_insn "*maskir_internal3"
3210 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3211 
        (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3212 
                        (match_operand:SI 3 "gpc_reg_operand" "r"))
3213 
                (and:SI (not:SI (match_dup 2))
3214 
                        (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3215 
  "TARGET_POWER"
3216 
  "maskir %0,%3,%2")
3217 
 
3218 
(define_insn "*maskir_internal4"
3219 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3220 
        (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3221 
                        (match_operand:SI 2 "gpc_reg_operand" "r"))
3222 
                (and:SI (not:SI (match_dup 2))
3223 
                        (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3224 
  "TARGET_POWER"
3225 
  "maskir %0,%3,%2")
3226 
 
3227 
(define_insn "*maskir_internal5"
3228 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3229 
        (compare:CC
3230 
         (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3231 
                         (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3232 
                 (and:SI (match_dup 2)
3233 
                         (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3234 
         (const_int 0)))
3235 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3236 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3237 
                (and:SI (match_dup 2) (match_dup 3))))]
3238 
  "TARGET_POWER"
3239 
  "@
3240 
   maskir. %0,%3,%2
3241 
   #"
3242 
  [(set_attr "type" "compare")
3243 
   (set_attr "length" "4,8")])
3244 
 
3245 
(define_split
3246 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3247 
        (compare:CC
3248 
         (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3249 
                         (match_operand:SI 1 "gpc_reg_operand" ""))
3250 
                 (and:SI (match_dup 2)
3251 
                         (match_operand:SI 3 "gpc_reg_operand" "")))
3252 
         (const_int 0)))
3253 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3254 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3255 
                (and:SI (match_dup 2) (match_dup 3))))]
3256 
  "TARGET_POWER && reload_completed"
3257 
  [(set (match_dup 0)
3258 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3259 
                (and:SI (match_dup 2) (match_dup 3))))
3260 
   (set (match_dup 4)
3261 
        (compare:CC (match_dup 0)
3262 
                    (const_int 0)))]
3263 
  "")
3264 
 
3265 
(define_insn "*maskir_internal6"
3266 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3267 
        (compare:CC
3268 
         (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3269 
                         (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3270 
                 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3271 
                         (match_dup 2)))
3272 
         (const_int 0)))
3273 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3274 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3275 
                (and:SI (match_dup 3) (match_dup 2))))]
3276 
  "TARGET_POWER"
3277 
  "@
3278 
   maskir. %0,%3,%2
3279 
   #"
3280 
  [(set_attr "type" "compare")
3281 
   (set_attr "length" "4,8")])
3282 
 
3283 
(define_split
3284 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3285 
        (compare:CC
3286 
         (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3287 
                         (match_operand:SI 1 "gpc_reg_operand" ""))
3288 
                 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3289 
                         (match_dup 2)))
3290 
         (const_int 0)))
3291 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3292 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3293 
                (and:SI (match_dup 3) (match_dup 2))))]
3294 
  "TARGET_POWER && reload_completed"
3295 
  [(set (match_dup 0)
3296 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3297 
                (and:SI (match_dup 3) (match_dup 2))))
3298 
   (set (match_dup 4)
3299 
        (compare:CC (match_dup 0)
3300 
                    (const_int 0)))]
3301 
  "")
3302 
 
3303 
(define_insn "*maskir_internal7"
3304 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3305 
        (compare:CC
3306 
         (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3307 
                         (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3308 
                 (and:SI (not:SI (match_dup 2))
3309 
                         (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3310 
         (const_int 0)))
3311 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3312 
        (ior:SI (and:SI (match_dup 2) (match_dup 3))
3313 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3314 
  "TARGET_POWER"
3315 
  "@
3316 
   maskir. %0,%3,%2
3317 
   #"
3318 
  [(set_attr "type" "compare")
3319 
   (set_attr "length" "4,8")])
3320 
 
3321 
(define_split
3322 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3323 
        (compare:CC
3324 
         (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3325 
                         (match_operand:SI 3 "gpc_reg_operand" ""))
3326 
                 (and:SI (not:SI (match_dup 2))
3327 
                         (match_operand:SI 1 "gpc_reg_operand" "")))
3328 
         (const_int 0)))
3329 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3330 
        (ior:SI (and:SI (match_dup 2) (match_dup 3))
3331 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3332 
  "TARGET_POWER && reload_completed"
3333 
  [(set (match_dup 0)
3334 
        (ior:SI (and:SI (match_dup 2) (match_dup 3))
3335 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3336 
   (set (match_dup 4)
3337 
        (compare:CC (match_dup 0)
3338 
                    (const_int 0)))]
3339 
  "")
3340 
 
3341 
(define_insn "*maskir_internal8"
3342 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3343 
        (compare:CC
3344 
         (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3345 
                         (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3346 
                 (and:SI (not:SI (match_dup 2))
3347 
                         (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3348 
         (const_int 0)))
3349 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3350 
        (ior:SI (and:SI (match_dup 3) (match_dup 2))
3351 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3352 
  "TARGET_POWER"
3353 
  "@
3354 
   maskir. %0,%3,%2
3355 
   #"
3356 
  [(set_attr "type" "compare")
3357 
   (set_attr "length" "4,8")])
3358 
 
3359 
(define_split
3360 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3361 
        (compare:CC
3362 
         (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3363 
                         (match_operand:SI 2 "gpc_reg_operand" ""))
3364 
                 (and:SI (not:SI (match_dup 2))
3365 
                         (match_operand:SI 1 "gpc_reg_operand" "")))
3366 
         (const_int 0)))
3367 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3368 
        (ior:SI (and:SI (match_dup 3) (match_dup 2))
3369 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3370 
  "TARGET_POWER && reload_completed"
3371 
  [(set (match_dup 0)
3372 
        (ior:SI (and:SI (match_dup 3) (match_dup 2))
3373 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3374 
   (set (match_dup 4)
3375 
        (compare:CC (match_dup 0)
3376 
                    (const_int 0)))]
3377 
  "")
3378 
 
3379 
;; Rotate and shift insns, in all their variants.  These support shifts,
3380 
;; field inserts and extracts, and various combinations thereof.
3381 
(define_expand "insv"
3382 
  [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3383 
                       (match_operand:SI 1 "const_int_operand" "")
3384 
                       (match_operand:SI 2 "const_int_operand" ""))
3385 
        (match_operand 3 "gpc_reg_operand" ""))]
3386 
  ""
3387 
  "
3388 
{
3389 
  /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3390 
     the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3391 
     compiler if the address of the structure is taken later.  Likewise, do
3392 
     not handle invalid E500 subregs.  */
3393 
  if (GET_CODE (operands[0]) == SUBREG
3394 
      && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3395 
          || ((TARGET_E500_DOUBLE || TARGET_SPE)
3396 
              && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3397 
    FAIL;
3398 
 
3399 
  if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3400 
    emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3401 
  else
3402 
    emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3403 
  DONE;
3404 
}")
3405 
 
3406 
(define_insn "insvsi"
3407 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3408 
                         (match_operand:SI 1 "const_int_operand" "i")
3409 
                         (match_operand:SI 2 "const_int_operand" "i"))
3410 
        (match_operand:SI 3 "gpc_reg_operand" "r"))]
3411 
  ""
3412 
  "*
3413 
{
3414 
  int start = INTVAL (operands[2]) & 31;
3415 
  int size = INTVAL (operands[1]) & 31;
3416 
 
3417 
  operands[4] = GEN_INT (32 - start - size);
3418 
  operands[1] = GEN_INT (start + size - 1);
3419 
  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3420 
}"
3421 
  [(set_attr "type" "insert_word")])
3422 
 
3423 
(define_insn "*insvsi_internal1"
3424 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3425 
                         (match_operand:SI 1 "const_int_operand" "i")
3426 
                         (match_operand:SI 2 "const_int_operand" "i"))
3427 
        (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3428 
                   (match_operand:SI 4 "const_int_operand" "i")))]
3429 
  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3430 
  "*
3431 
{
3432 
  int shift = INTVAL (operands[4]) & 31;
3433 
  int start = INTVAL (operands[2]) & 31;
3434 
  int size = INTVAL (operands[1]) & 31;
3435 
 
3436 
  operands[4] = GEN_INT (shift - start - size);
3437 
  operands[1] = GEN_INT (start + size - 1);
3438 
  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3439 
}"
3440 
  [(set_attr "type" "insert_word")])
3441 
 
3442 
(define_insn "*insvsi_internal2"
3443 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3444 
                         (match_operand:SI 1 "const_int_operand" "i")
3445 
                         (match_operand:SI 2 "const_int_operand" "i"))
3446 
        (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3447 
                     (match_operand:SI 4 "const_int_operand" "i")))]
3448 
  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3449 
  "*
3450 
{
3451 
  int shift = INTVAL (operands[4]) & 31;
3452 
  int start = INTVAL (operands[2]) & 31;
3453 
  int size = INTVAL (operands[1]) & 31;
3454 
 
3455 
  operands[4] = GEN_INT (32 - shift - start - size);
3456 
  operands[1] = GEN_INT (start + size - 1);
3457 
  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3458 
}"
3459 
  [(set_attr "type" "insert_word")])
3460 
 
3461 
(define_insn "*insvsi_internal3"
3462 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3463 
                         (match_operand:SI 1 "const_int_operand" "i")
3464 
                         (match_operand:SI 2 "const_int_operand" "i"))
3465 
        (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3466 
                     (match_operand:SI 4 "const_int_operand" "i")))]
3467 
  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3468 
  "*
3469 
{
3470 
  int shift = INTVAL (operands[4]) & 31;
3471 
  int start = INTVAL (operands[2]) & 31;
3472 
  int size = INTVAL (operands[1]) & 31;
3473 
 
3474 
  operands[4] = GEN_INT (32 - shift - start - size);
3475 
  operands[1] = GEN_INT (start + size - 1);
3476 
  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3477 
}"
3478 
  [(set_attr "type" "insert_word")])
3479 
 
3480 
(define_insn "*insvsi_internal4"
3481 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3482 
                         (match_operand:SI 1 "const_int_operand" "i")
3483 
                         (match_operand:SI 2 "const_int_operand" "i"))
3484 
        (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3485 
                         (match_operand:SI 4 "const_int_operand" "i")
3486 
                         (match_operand:SI 5 "const_int_operand" "i")))]
3487 
  "INTVAL (operands[4]) >= INTVAL (operands[1])"
3488 
  "*
3489 
{
3490 
  int extract_start = INTVAL (operands[5]) & 31;
3491 
  int extract_size = INTVAL (operands[4]) & 31;
3492 
  int insert_start = INTVAL (operands[2]) & 31;
3493 
  int insert_size = INTVAL (operands[1]) & 31;
3494 
 
3495 
/* Align extract field with insert field */
3496 
  operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3497 
  operands[1] = GEN_INT (insert_start + insert_size - 1);
3498 
  return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3499 
}"
3500 
  [(set_attr "type" "insert_word")])
3501 
 
3502 
;; combine patterns for rlwimi
3503 
(define_insn "*insvsi_internal5"
3504 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3505 
        (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3506 
                        (match_operand:SI 1 "mask_operand" "i"))
3507 
                (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3508 
                                     (match_operand:SI 2 "const_int_operand" "i"))
3509 
                        (match_operand:SI 5 "mask_operand" "i"))))]
3510 
  "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3511 
  "*
3512 
{
3513 
 int me = extract_ME(operands[5]);
3514 
 int mb = extract_MB(operands[5]);
3515 
 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3516 
 operands[2] = GEN_INT(mb);
3517 
 operands[1] = GEN_INT(me);
3518 
 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3519 
}"
3520 
  [(set_attr "type" "insert_word")])
3521 
 
3522 
(define_insn "*insvsi_internal6"
3523 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3524 
        (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3525 
                                     (match_operand:SI 2 "const_int_operand" "i"))
3526 
                        (match_operand:SI 5 "mask_operand" "i"))
3527 
                (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3528 
                        (match_operand:SI 1 "mask_operand" "i"))))]
3529 
  "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3530 
  "*
3531 
{
3532 
 int me = extract_ME(operands[5]);
3533 
 int mb = extract_MB(operands[5]);
3534 
 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3535 
 operands[2] = GEN_INT(mb);
3536 
 operands[1] = GEN_INT(me);
3537 
 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3538 
}"
3539 
  [(set_attr "type" "insert_word")])
3540 
 
3541 
(define_insn "insvdi"
3542 
  [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3543 
                         (match_operand:SI 1 "const_int_operand" "i")
3544 
                         (match_operand:SI 2 "const_int_operand" "i"))
3545 
        (match_operand:DI 3 "gpc_reg_operand" "r"))]
3546 
  "TARGET_POWERPC64"
3547 
  "*
3548 
{
3549 
  int start = INTVAL (operands[2]) & 63;
3550 
  int size = INTVAL (operands[1]) & 63;
3551 
 
3552 
  operands[1] = GEN_INT (64 - start - size);
3553 
  return \"rldimi %0,%3,%H1,%H2\";
3554 
}")
3555 
 
3556 
(define_insn "*insvdi_internal2"
3557 
  [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3558 
                         (match_operand:SI 1 "const_int_operand" "i")
3559 
                         (match_operand:SI 2 "const_int_operand" "i"))
3560 
        (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3561 
                     (match_operand:SI 4 "const_int_operand" "i")))]
3562 
  "TARGET_POWERPC64
3563 
   && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3564 
  "*
3565 
{
3566 
  int shift = INTVAL (operands[4]) & 63;
3567 
  int start = (INTVAL (operands[2]) & 63) - 32;
3568 
  int size = INTVAL (operands[1]) & 63;
3569 
 
3570 
  operands[4] = GEN_INT (64 - shift - start - size);
3571 
  operands[2] = GEN_INT (start);
3572 
  operands[1] = GEN_INT (start + size - 1);
3573 
  return \"rlwimi %0,%3,%h4,%h2,%h1\";
3574 
}")
3575 
 
3576 
(define_insn "*insvdi_internal3"
3577 
  [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3578 
                         (match_operand:SI 1 "const_int_operand" "i")
3579 
                         (match_operand:SI 2 "const_int_operand" "i"))
3580 
        (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3581 
                     (match_operand:SI 4 "const_int_operand" "i")))]
3582 
  "TARGET_POWERPC64
3583 
   && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3584 
  "*
3585 
{
3586 
  int shift = INTVAL (operands[4]) & 63;
3587 
  int start = (INTVAL (operands[2]) & 63) - 32;
3588 
  int size = INTVAL (operands[1]) & 63;
3589 
 
3590 
  operands[4] = GEN_INT (64 - shift - start - size);
3591 
  operands[2] = GEN_INT (start);
3592 
  operands[1] = GEN_INT (start + size - 1);
3593 
  return \"rlwimi %0,%3,%h4,%h2,%h1\";
3594 
}")
3595 
 
3596 
(define_expand "extzv"
3597 
  [(set (match_operand 0 "gpc_reg_operand" "")
3598 
        (zero_extract (match_operand 1 "gpc_reg_operand" "")
3599 
                       (match_operand:SI 2 "const_int_operand" "")
3600 
                       (match_operand:SI 3 "const_int_operand" "")))]
3601 
  ""
3602 
  "
3603 
{
3604 
  /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3605 
     the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3606 
     compiler if the address of the structure is taken later.  */
3607 
  if (GET_CODE (operands[0]) == SUBREG
3608 
      && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3609 
    FAIL;
3610 
 
3611 
  if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3612 
    emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3613 
  else
3614 
    emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3615 
  DONE;
3616 
}")
3617 
 
3618 
(define_insn "extzvsi"
3619 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3620 
        (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3621 
                         (match_operand:SI 2 "const_int_operand" "i")
3622 
                         (match_operand:SI 3 "const_int_operand" "i")))]
3623 
  ""
3624 
  "*
3625 
{
3626 
  int start = INTVAL (operands[3]) & 31;
3627 
  int size = INTVAL (operands[2]) & 31;
3628 
 
3629 
  if (start + size >= 32)
3630 
    operands[3] = const0_rtx;
3631 
  else
3632 
    operands[3] = GEN_INT (start + size);
3633 
  return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3634 
}")
3635 
 
3636 
(define_insn "*extzvsi_internal1"
3637 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3638 
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3639 
                         (match_operand:SI 2 "const_int_operand" "i,i")
3640 
                         (match_operand:SI 3 "const_int_operand" "i,i"))
3641 
                    (const_int 0)))
3642 
   (clobber (match_scratch:SI 4 "=r,r"))]
3643 
  ""
3644 
  "*
3645 
{
3646 
  int start = INTVAL (operands[3]) & 31;
3647 
  int size = INTVAL (operands[2]) & 31;
3648 
 
3649 
  /* Force split for non-cc0 compare.  */
3650 
  if (which_alternative == 1)
3651 
     return \"#\";
3652 
 
3653 
  /* If the bit-field being tested fits in the upper or lower half of a
3654 
     word, it is possible to use andiu. or andil. to test it.  This is
3655 
     useful because the condition register set-use delay is smaller for
3656 
     andi[ul]. than for rlinm.  This doesn't work when the starting bit
3657 
     position is 0 because the LT and GT bits may be set wrong.  */
3658 
 
3659 
  if ((start > 0 && start + size <= 16) || start >= 16)
3660 
    {
3661 
      operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3662 
                              - (1 << (16 - (start & 15) - size))));
3663 
      if (start < 16)
3664 
        return \"{andiu.|andis.} %4,%1,%3\";
3665 
      else
3666 
        return \"{andil.|andi.} %4,%1,%3\";
3667 
    }
3668 
 
3669 
  if (start + size >= 32)
3670 
    operands[3] = const0_rtx;
3671 
  else
3672 
    operands[3] = GEN_INT (start + size);
3673 
  return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3674 
}"
3675 
  [(set_attr "type" "compare")
3676 
   (set_attr "length" "4,8")])
3677 
 
3678 
(define_split
3679 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3680 
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3681 
                         (match_operand:SI 2 "const_int_operand" "")
3682 
                         (match_operand:SI 3 "const_int_operand" ""))
3683 
                    (const_int 0)))
3684 
   (clobber (match_scratch:SI 4 ""))]
3685 
  "reload_completed"
3686 
  [(set (match_dup 4)
3687 
        (zero_extract:SI (match_dup 1) (match_dup 2)
3688 
                         (match_dup 3)))
3689 
   (set (match_dup 0)
3690 
        (compare:CC (match_dup 4)
3691 
                    (const_int 0)))]
3692 
  "")
3693 
 
3694 
(define_insn "*extzvsi_internal2"
3695 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3696 
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3697 
                         (match_operand:SI 2 "const_int_operand" "i,i")
3698 
                         (match_operand:SI 3 "const_int_operand" "i,i"))
3699 
                    (const_int 0)))
3700 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3701 
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3702 
  ""
3703 
  "*
3704 
{
3705 
  int start = INTVAL (operands[3]) & 31;
3706 
  int size = INTVAL (operands[2]) & 31;
3707 
 
3708 
  /* Force split for non-cc0 compare.  */
3709 
  if (which_alternative == 1)
3710 
     return \"#\";
3711 
 
3712 
  /* Since we are using the output value, we can't ignore any need for
3713 
     a shift.  The bit-field must end at the LSB.  */
3714 
  if (start >= 16 && start + size == 32)
3715 
    {
3716 
      operands[3] = GEN_INT ((1 << size) - 1);
3717 
      return \"{andil.|andi.} %0,%1,%3\";
3718 
    }
3719 
 
3720 
  if (start + size >= 32)
3721 
    operands[3] = const0_rtx;
3722 
  else
3723 
    operands[3] = GEN_INT (start + size);
3724 
  return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3725 
}"
3726 
  [(set_attr "type" "compare")
3727 
   (set_attr "length" "4,8")])
3728 
 
3729 
(define_split
3730 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3731 
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3732 
                         (match_operand:SI 2 "const_int_operand" "")
3733 
                         (match_operand:SI 3 "const_int_operand" ""))
3734 
                    (const_int 0)))
3735 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3736 
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3737 
  "reload_completed"
3738 
  [(set (match_dup 0)
3739 
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3740 
   (set (match_dup 4)
3741 
        (compare:CC (match_dup 0)
3742 
                    (const_int 0)))]
3743 
  "")
3744 
 
3745 
(define_insn "extzvdi"
3746 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3747 
        (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3748 
                         (match_operand:SI 2 "const_int_operand" "i")
3749 
                         (match_operand:SI 3 "const_int_operand" "i")))]
3750 
  "TARGET_POWERPC64"
3751 
  "*
3752 
{
3753 
  int start = INTVAL (operands[3]) & 63;
3754 
  int size = INTVAL (operands[2]) & 63;
3755 
 
3756 
  if (start + size >= 64)
3757 
    operands[3] = const0_rtx;
3758 
  else
3759 
    operands[3] = GEN_INT (start + size);
3760 
  operands[2] = GEN_INT (64 - size);
3761 
  return \"rldicl %0,%1,%3,%2\";
3762 
}")
3763 
 
3764 
(define_insn "*extzvdi_internal1"
3765 
  [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3766 
        (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3767 
                         (match_operand:SI 2 "const_int_operand" "i")
3768 
                         (match_operand:SI 3 "const_int_operand" "i"))
3769 
                    (const_int 0)))
3770 
   (clobber (match_scratch:DI 4 "=r"))]
3771 
  "TARGET_64BIT"
3772 
  "*
3773 
{
3774 
  int start = INTVAL (operands[3]) & 63;
3775 
  int size = INTVAL (operands[2]) & 63;
3776 
 
3777 
  if (start + size >= 64)
3778 
    operands[3] = const0_rtx;
3779 
  else
3780 
    operands[3] = GEN_INT (start + size);
3781 
  operands[2] = GEN_INT (64 - size);
3782 
  return \"rldicl. %4,%1,%3,%2\";
3783 
}"
3784 
  [(set_attr "type" "compare")])
3785 
 
3786 
(define_insn "*extzvdi_internal2"
3787 
  [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3788 
        (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3789 
                         (match_operand:SI 2 "const_int_operand" "i")
3790 
                         (match_operand:SI 3 "const_int_operand" "i"))
3791 
                    (const_int 0)))
3792 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3793 
        (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3794 
  "TARGET_64BIT"
3795 
  "*
3796 
{
3797 
  int start = INTVAL (operands[3]) & 63;
3798 
  int size = INTVAL (operands[2]) & 63;
3799 
 
3800 
  if (start + size >= 64)
3801 
    operands[3] = const0_rtx;
3802 
  else
3803 
    operands[3] = GEN_INT (start + size);
3804 
  operands[2] = GEN_INT (64 - size);
3805 
  return \"rldicl. %0,%1,%3,%2\";
3806 
}"
3807 
  [(set_attr "type" "compare")])
3808 
 
3809 
(define_insn "rotlsi3"
3810 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3811 
        (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3812 
                   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3813 
  ""
3814 
  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3815 
 
3816 
(define_insn "*rotlsi3_internal2"
3817 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3818 
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3819 
                               (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3820 
                    (const_int 0)))
3821 
   (clobber (match_scratch:SI 3 "=r,r"))]
3822 
  ""
3823 
  "@
3824 
   {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3825 
   #"
3826 
  [(set_attr "type" "delayed_compare")
3827 
   (set_attr "length" "4,8")])
3828 
 
3829 
(define_split
3830 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3831 
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3832 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
3833 
                    (const_int 0)))
3834 
   (clobber (match_scratch:SI 3 ""))]
3835 
  "reload_completed"
3836 
  [(set (match_dup 3)
3837 
        (rotate:SI (match_dup 1) (match_dup 2)))
3838 
   (set (match_dup 0)
3839 
        (compare:CC (match_dup 3)
3840 
                    (const_int 0)))]
3841 
  "")
3842 
 
3843 
(define_insn "*rotlsi3_internal3"
3844 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3845 
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3846 
                               (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3847 
                    (const_int 0)))
3848 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3849 
        (rotate:SI (match_dup 1) (match_dup 2)))]
3850 
  ""
3851 
  "@
3852 
   {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3853 
   #"
3854 
  [(set_attr "type" "delayed_compare")
3855 
   (set_attr "length" "4,8")])
3856 
 
3857 
(define_split
3858 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3859 
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3860 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
3861 
                    (const_int 0)))
3862 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3863 
        (rotate:SI (match_dup 1) (match_dup 2)))]
3864 
  "reload_completed"
3865 
  [(set (match_dup 0)
3866 
        (rotate:SI (match_dup 1) (match_dup 2)))
3867 
   (set (match_dup 3)
3868 
        (compare:CC (match_dup 0)
3869 
                    (const_int 0)))]
3870 
  "")
3871 
 
3872 
(define_insn "*rotlsi3_internal4"
3873 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3874 
        (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3875 
                           (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3876 
                (match_operand:SI 3 "mask_operand" "n")))]
3877 
  ""
3878 
  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3879 
 
3880 
(define_insn "*rotlsi3_internal5"
3881 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3882 
        (compare:CC (and:SI
3883 
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3884 
                                (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3885 
                     (match_operand:SI 3 "mask_operand" "n,n"))
3886 
                    (const_int 0)))
3887 
   (clobber (match_scratch:SI 4 "=r,r"))]
3888 
  ""
3889 
  "@
3890 
   {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3891 
   #"
3892 
  [(set_attr "type" "delayed_compare")
3893 
   (set_attr "length" "4,8")])
3894 
 
3895 
(define_split
3896 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3897 
        (compare:CC (and:SI
3898 
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3899 
                                (match_operand:SI 2 "reg_or_cint_operand" ""))
3900 
                     (match_operand:SI 3 "mask_operand" ""))
3901 
                    (const_int 0)))
3902 
   (clobber (match_scratch:SI 4 ""))]
3903 
  "reload_completed"
3904 
  [(set (match_dup 4)
3905 
        (and:SI (rotate:SI (match_dup 1)
3906 
                                (match_dup 2))
3907 
                     (match_dup 3)))
3908 
   (set (match_dup 0)
3909 
        (compare:CC (match_dup 4)
3910 
                    (const_int 0)))]
3911 
  "")
3912 
 
3913 
(define_insn "*rotlsi3_internal6"
3914 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3915 
        (compare:CC (and:SI
3916 
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3917 
                                (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3918 
                     (match_operand:SI 3 "mask_operand" "n,n"))
3919 
                    (const_int 0)))
3920 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3921 
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3922 
  ""
3923 
  "@
3924 
   {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3925 
   #"
3926 
  [(set_attr "type" "delayed_compare")
3927 
   (set_attr "length" "4,8")])
3928 
 
3929 
(define_split
3930 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3931 
        (compare:CC (and:SI
3932 
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3933 
                                (match_operand:SI 2 "reg_or_cint_operand" ""))
3934 
                     (match_operand:SI 3 "mask_operand" ""))
3935 
                    (const_int 0)))
3936 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3937 
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3938 
  "reload_completed"
3939 
  [(set (match_dup 0)
3940 
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3941 
   (set (match_dup 4)
3942 
        (compare:CC (match_dup 0)
3943 
                    (const_int 0)))]
3944 
  "")
3945 
 
3946 
(define_insn "*rotlsi3_internal7"
3947 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3948 
        (zero_extend:SI
3949 
         (subreg:QI
3950 
          (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3951 
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3952 
  ""
3953 
  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3954 
 
3955 
(define_insn "*rotlsi3_internal8"
3956 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3957 
        (compare:CC (zero_extend:SI
3958 
                     (subreg:QI
3959 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3960 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3961 
                    (const_int 0)))
3962 
   (clobber (match_scratch:SI 3 "=r,r"))]
3963 
  ""
3964 
  "@
3965 
   {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3966 
   #"
3967 
  [(set_attr "type" "delayed_compare")
3968 
   (set_attr "length" "4,8")])
3969 
 
3970 
(define_split
3971 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3972 
        (compare:CC (zero_extend:SI
3973 
                     (subreg:QI
3974 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3975 
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3976 
                    (const_int 0)))
3977 
   (clobber (match_scratch:SI 3 ""))]
3978 
  "reload_completed"
3979 
  [(set (match_dup 3)
3980 
        (zero_extend:SI (subreg:QI
3981 
                      (rotate:SI (match_dup 1)
3982 
                                 (match_dup 2)) 0)))
3983 
   (set (match_dup 0)
3984 
        (compare:CC (match_dup 3)
3985 
                    (const_int 0)))]
3986 
  "")
3987 
 
3988 
(define_insn "*rotlsi3_internal9"
3989 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3990 
        (compare:CC (zero_extend:SI
3991 
                     (subreg:QI
3992 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3993 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3994 
                    (const_int 0)))
3995 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3996 
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3997 
  ""
3998 
  "@
3999 
   {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
4000 
   #"
4001 
  [(set_attr "type" "delayed_compare")
4002 
   (set_attr "length" "4,8")])
4003 
 
4004 
(define_split
4005 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4006 
        (compare:CC (zero_extend:SI
4007 
                     (subreg:QI
4008 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4009 
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4010 
                    (const_int 0)))
4011 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4012 
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4013 
  "reload_completed"
4014 
  [(set (match_dup 0)
4015 
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4016 
   (set (match_dup 3)
4017 
        (compare:CC (match_dup 0)
4018 
                    (const_int 0)))]
4019 
  "")
4020 
 
4021 
(define_insn "*rotlsi3_internal10"
4022 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4023 
        (zero_extend:SI
4024 
         (subreg:HI
4025 
          (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4026 
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4027 
  ""
4028 
  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
4029 
 
4030 
(define_insn "*rotlsi3_internal11"
4031 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4032 
        (compare:CC (zero_extend:SI
4033 
                     (subreg:HI
4034 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4035 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4036 
                    (const_int 0)))
4037 
   (clobber (match_scratch:SI 3 "=r,r"))]
4038 
  ""
4039 
  "@
4040 
   {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
4041 
   #"
4042 
  [(set_attr "type" "delayed_compare")
4043 
   (set_attr "length" "4,8")])
4044 
 
4045 
(define_split
4046 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4047 
        (compare:CC (zero_extend:SI
4048 
                     (subreg:HI
4049 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4050 
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4051 
                    (const_int 0)))
4052 
   (clobber (match_scratch:SI 3 ""))]
4053 
  "reload_completed"
4054 
  [(set (match_dup 3)
4055 
        (zero_extend:SI (subreg:HI
4056 
                      (rotate:SI (match_dup 1)
4057 
                                 (match_dup 2)) 0)))
4058 
   (set (match_dup 0)
4059 
        (compare:CC (match_dup 3)
4060 
                    (const_int 0)))]
4061 
  "")
4062 
 
4063 
(define_insn "*rotlsi3_internal12"
4064 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4065 
        (compare:CC (zero_extend:SI
4066 
                     (subreg:HI
4067 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4068 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4069 
                    (const_int 0)))
4070 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4071 
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4072 
  ""
4073 
  "@
4074 
   {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
4075 
   #"
4076 
  [(set_attr "type" "delayed_compare")
4077 
   (set_attr "length" "4,8")])
4078 
 
4079 
(define_split
4080 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4081 
        (compare:CC (zero_extend:SI
4082 
                     (subreg:HI
4083 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4084 
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4085 
                    (const_int 0)))
4086 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4087 
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4088 
  "reload_completed"
4089 
  [(set (match_dup 0)
4090 
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4091 
   (set (match_dup 3)
4092 
        (compare:CC (match_dup 0)
4093 
                    (const_int 0)))]
4094 
  "")
4095 
 
4096 
;; Note that we use "sle." instead of "sl." so that we can set
4097 
;; SHIFT_COUNT_TRUNCATED.
4098 
 
4099 
(define_expand "ashlsi3"
4100 
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4101 
   (use (match_operand:SI 1 "gpc_reg_operand" ""))
4102 
   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4103 
  ""
4104 
  "
4105 
{
4106 
  if (TARGET_POWER)
4107 
    emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4108 
  else
4109 
    emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4110 
  DONE;
4111 
}")
4112 
 
4113 
(define_insn "ashlsi3_power"
4114 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4115 
        (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4116 
                   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4117 
   (clobber (match_scratch:SI 3 "=q,X"))]
4118 
  "TARGET_POWER"
4119 
  "@
4120 
   sle %0,%1,%2
4121 
   {sli|slwi} %0,%1,%h2")
4122 
 
4123 
(define_insn "ashlsi3_no_power"
4124 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4125 
        (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4126 
                   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4127 
  "! TARGET_POWER"
4128 
  "{sl|slw}%I2 %0,%1,%h2")
4129 
 
4130 
(define_insn ""
4131 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4132 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4133 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4134 
                    (const_int 0)))
4135 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))
4136 
   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4137 
  "TARGET_POWER"
4138 
  "@
4139 
   sle. %3,%1,%2
4140 
   {sli.|slwi.} %3,%1,%h2
4141 
   #
4142 
   #"
4143 
  [(set_attr "type" "delayed_compare")
4144 
   (set_attr "length" "4,4,8,8")])
4145 
 
4146 
(define_split
4147 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4148 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4149 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4150 
                    (const_int 0)))
4151 
   (clobber (match_scratch:SI 3 ""))
4152 
   (clobber (match_scratch:SI 4 ""))]
4153 
  "TARGET_POWER && reload_completed"
4154 
  [(parallel [(set (match_dup 3)
4155 
        (ashift:SI (match_dup 1) (match_dup 2)))
4156 
   (clobber (match_dup 4))])
4157 
   (set (match_dup 0)
4158 
        (compare:CC (match_dup 3)
4159 
                    (const_int 0)))]
4160 
  "")
4161 
 
4162 
(define_insn ""
4163 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4164 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4165 
                               (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4166 
                    (const_int 0)))
4167 
   (clobber (match_scratch:SI 3 "=r,r"))]
4168 
  "! TARGET_POWER && TARGET_32BIT"
4169 
  "@
4170 
   {sl|slw}%I2. %3,%1,%h2
4171 
   #"
4172 
  [(set_attr "type" "delayed_compare")
4173 
   (set_attr "length" "4,8")])
4174 
 
4175 
(define_split
4176 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4177 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4178 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4179 
                    (const_int 0)))
4180 
   (clobber (match_scratch:SI 3 ""))]
4181 
  "! TARGET_POWER && TARGET_32BIT && reload_completed"
4182 
  [(set (match_dup 3)
4183 
        (ashift:SI (match_dup 1) (match_dup 2)))
4184 
   (set (match_dup 0)
4185 
        (compare:CC (match_dup 3)
4186 
                    (const_int 0)))]
4187 
  "")
4188 
 
4189 
(define_insn ""
4190 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4191 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4192 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4193 
                    (const_int 0)))
4194 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4195 
        (ashift:SI (match_dup 1) (match_dup 2)))
4196 
   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4197 
  "TARGET_POWER"
4198 
  "@
4199 
   sle. %0,%1,%2
4200 
   {sli.|slwi.} %0,%1,%h2
4201 
   #
4202 
   #"
4203 
  [(set_attr "type" "delayed_compare")
4204 
   (set_attr "length" "4,4,8,8")])
4205 
 
4206 
(define_split
4207 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4208 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4209 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4210 
                    (const_int 0)))
4211 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4212 
        (ashift:SI (match_dup 1) (match_dup 2)))
4213 
   (clobber (match_scratch:SI 4 ""))]
4214 
  "TARGET_POWER && reload_completed"
4215 
  [(parallel [(set (match_dup 0)
4216 
        (ashift:SI (match_dup 1) (match_dup 2)))
4217 
   (clobber (match_dup 4))])
4218 
   (set (match_dup 3)
4219 
        (compare:CC (match_dup 0)
4220 
                    (const_int 0)))]
4221 
  "")
4222 
 
4223 
(define_insn ""
4224 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4225 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4226 
                               (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4227 
                    (const_int 0)))
4228 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4229 
        (ashift:SI (match_dup 1) (match_dup 2)))]
4230 
  "! TARGET_POWER && TARGET_32BIT"
4231 
  "@
4232 
   {sl|slw}%I2. %0,%1,%h2
4233 
   #"
4234 
  [(set_attr "type" "delayed_compare")
4235 
   (set_attr "length" "4,8")])
4236 
 
4237 
(define_split
4238 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4239 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4240 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4241 
                    (const_int 0)))
4242 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4243 
        (ashift:SI (match_dup 1) (match_dup 2)))]
4244 
  "! TARGET_POWER && TARGET_32BIT && reload_completed"
4245 
  [(set (match_dup 0)
4246 
        (ashift:SI (match_dup 1) (match_dup 2)))
4247 
   (set (match_dup 3)
4248 
        (compare:CC (match_dup 0)
4249 
                    (const_int 0)))]
4250 
  "")
4251 
 
4252 
(define_insn "rlwinm"
4253 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4254 
        (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4255 
                           (match_operand:SI 2 "const_int_operand" "i"))
4256 
                (match_operand:SI 3 "mask_operand" "n")))]
4257 
  "includes_lshift_p (operands[2], operands[3])"
4258 
  "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4259 
 
4260 
(define_insn ""
4261 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4262 
        (compare:CC
4263 
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4264 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
4265 
                 (match_operand:SI 3 "mask_operand" "n,n"))
4266 
         (const_int 0)))
4267 
   (clobber (match_scratch:SI 4 "=r,r"))]
4268 
  "includes_lshift_p (operands[2], operands[3])"
4269 
  "@
4270 
   {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4271 
   #"
4272 
  [(set_attr "type" "delayed_compare")
4273 
   (set_attr "length" "4,8")])
4274 
 
4275 
(define_split
4276 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4277 
        (compare:CC
4278 
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4279 
                            (match_operand:SI 2 "const_int_operand" ""))
4280 
                 (match_operand:SI 3 "mask_operand" ""))
4281 
         (const_int 0)))
4282 
   (clobber (match_scratch:SI 4 ""))]
4283 
  "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4284 
  [(set (match_dup 4)
4285 
        (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4286 
                 (match_dup 3)))
4287 
   (set (match_dup 0)
4288 
        (compare:CC (match_dup 4)
4289 
                    (const_int 0)))]
4290 
  "")
4291 
 
4292 
(define_insn ""
4293 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4294 
        (compare:CC
4295 
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4296 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
4297 
                 (match_operand:SI 3 "mask_operand" "n,n"))
4298 
         (const_int 0)))
4299 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4300 
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4301 
  "includes_lshift_p (operands[2], operands[3])"
4302 
  "@
4303 
   {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4304 
   #"
4305 
  [(set_attr "type" "delayed_compare")
4306 
   (set_attr "length" "4,8")])
4307 
 
4308 
(define_split
4309 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4310 
        (compare:CC
4311 
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4312 
                            (match_operand:SI 2 "const_int_operand" ""))
4313 
                 (match_operand:SI 3 "mask_operand" ""))
4314 
         (const_int 0)))
4315 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4316 
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4317 
  "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4318 
  [(set (match_dup 0)
4319 
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4320 
   (set (match_dup 4)
4321 
        (compare:CC (match_dup 0)
4322 
                    (const_int 0)))]
4323 
  "")
4324 
 
4325 
;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4326 
;; "sli x,x,0".
4327 
(define_expand "lshrsi3"
4328 
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4329 
   (use (match_operand:SI 1 "gpc_reg_operand" ""))
4330 
   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4331 
  ""
4332 
  "
4333 
{
4334 
  if (TARGET_POWER)
4335 
    emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4336 
  else
4337 
    emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4338 
  DONE;
4339 
}")
4340 
 
4341 
(define_insn "lshrsi3_power"
4342 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4343 
        (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4344 
                     (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4345 
   (clobber (match_scratch:SI 3 "=q,X,X"))]
4346 
  "TARGET_POWER"
4347 
  "@
4348 
  sre %0,%1,%2
4349 
  mr %0,%1
4350 
  {s%A2i|s%A2wi} %0,%1,%h2")
4351 
 
4352 
(define_insn "lshrsi3_no_power"
4353 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4354 
        (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4355 
                     (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4356 
  "! TARGET_POWER"
4357 
  "@
4358 
  mr %0,%1
4359 
  {sr|srw}%I2 %0,%1,%h2")
4360 
 
4361 
(define_insn ""
4362 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4363 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4364 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4365 
                    (const_int 0)))
4366 
   (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4367 
   (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4368 
  "TARGET_POWER"
4369 
  "@
4370 
  sre. %3,%1,%2
4371 
  mr. %1,%1
4372 
  {s%A2i.|s%A2wi.} %3,%1,%h2
4373 
  #
4374 
  #
4375 
  #"
4376 
  [(set_attr "type" "delayed_compare")
4377 
   (set_attr "length" "4,4,4,8,8,8")])
4378 
 
4379 
(define_split
4380 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4381 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4382 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
4383 
                    (const_int 0)))
4384 
   (clobber (match_scratch:SI 3 ""))
4385 
   (clobber (match_scratch:SI 4 ""))]
4386 
  "TARGET_POWER && reload_completed"
4387 
  [(parallel [(set (match_dup 3)
4388 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
4389 
   (clobber (match_dup 4))])
4390 
   (set (match_dup 0)
4391 
        (compare:CC (match_dup 3)
4392 
                    (const_int 0)))]
4393 
  "")
4394 
 
4395 
(define_insn ""
4396 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4397 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4398 
                                 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4399 
                    (const_int 0)))
4400 
   (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4401 
  "! TARGET_POWER && TARGET_32BIT"
4402 
  "@
4403 
   mr. %1,%1
4404 
   {sr|srw}%I2. %3,%1,%h2
4405 
   #
4406 
   #"
4407 
  [(set_attr "type" "delayed_compare")
4408 
   (set_attr "length" "4,4,8,8")])
4409 
 
4410 
(define_split
4411 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4412 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4413 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
4414 
                    (const_int 0)))
4415 
   (clobber (match_scratch:SI 3 ""))]
4416 
  "! TARGET_POWER && TARGET_32BIT && reload_completed"
4417 
  [(set (match_dup 3)
4418 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
4419 
   (set (match_dup 0)
4420 
        (compare:CC (match_dup 3)
4421 
                    (const_int 0)))]
4422 
  "")
4423 
 
4424 
(define_insn ""
4425 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4426 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4427 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4428 
                    (const_int 0)))
4429 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4430 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
4431 
   (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4432 
  "TARGET_POWER"
4433 
  "@
4434 
  sre. %0,%1,%2
4435 
  mr. %0,%1
4436 
  {s%A2i.|s%A2wi.} %0,%1,%h2
4437 
  #
4438 
  #
4439 
  #"
4440 
  [(set_attr "type" "delayed_compare")
4441 
   (set_attr "length" "4,4,4,8,8,8")])
4442 
 
4443 
(define_split
4444 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4445 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4446 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
4447 
                    (const_int 0)))
4448 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4449 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
4450 
   (clobber (match_scratch:SI 4 ""))]
4451 
  "TARGET_POWER && reload_completed"
4452 
  [(parallel [(set (match_dup 0)
4453 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
4454 
   (clobber (match_dup 4))])
4455 
   (set (match_dup 3)
4456 
        (compare:CC (match_dup 0)
4457 
                    (const_int 0)))]
4458 
  "")
4459 
 
4460 
(define_insn ""
4461 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4462 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4463 
                                 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4464 
                    (const_int 0)))
4465 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4466 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4467 
  "! TARGET_POWER && TARGET_32BIT"
4468 
  "@
4469 
   mr. %0,%1
4470 
   {sr|srw}%I2. %0,%1,%h2
4471 
   #
4472 
   #"
4473 
  [(set_attr "type" "delayed_compare")
4474 
   (set_attr "length" "4,4,8,8")])
4475 
 
4476 
(define_split
4477 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4478 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4479 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
4480 
                    (const_int 0)))
4481 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4482 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4483 
  "! TARGET_POWER && TARGET_32BIT && reload_completed"
4484 
  [(set (match_dup 0)
4485 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
4486 
   (set (match_dup 3)
4487 
        (compare:CC (match_dup 0)
4488 
                    (const_int 0)))]
4489 
  "")
4490 
 
4491 
(define_insn ""
4492 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4493 
        (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4494 
                             (match_operand:SI 2 "const_int_operand" "i"))
4495 
                (match_operand:SI 3 "mask_operand" "n")))]
4496 
  "includes_rshift_p (operands[2], operands[3])"
4497 
  "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4498 
 
4499 
(define_insn ""
4500 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4501 
        (compare:CC
4502 
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4503 
                              (match_operand:SI 2 "const_int_operand" "i,i"))
4504 
                 (match_operand:SI 3 "mask_operand" "n,n"))
4505 
         (const_int 0)))
4506 
   (clobber (match_scratch:SI 4 "=r,r"))]
4507 
  "includes_rshift_p (operands[2], operands[3])"
4508 
  "@
4509 
   {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4510 
   #"
4511 
  [(set_attr "type" "delayed_compare")
4512 
   (set_attr "length" "4,8")])
4513 
 
4514 
(define_split
4515 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4516 
        (compare:CC
4517 
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4518 
                              (match_operand:SI 2 "const_int_operand" ""))
4519 
                 (match_operand:SI 3 "mask_operand" ""))
4520 
         (const_int 0)))
4521 
   (clobber (match_scratch:SI 4 ""))]
4522 
  "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4523 
  [(set (match_dup 4)
4524 
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4525 
                 (match_dup 3)))
4526 
   (set (match_dup 0)
4527 
        (compare:CC (match_dup 4)
4528 
                    (const_int 0)))]
4529 
  "")
4530 
 
4531 
(define_insn ""
4532 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4533 
        (compare:CC
4534 
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4535 
                              (match_operand:SI 2 "const_int_operand" "i,i"))
4536 
                 (match_operand:SI 3 "mask_operand" "n,n"))
4537 
         (const_int 0)))
4538 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4539 
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4540 
  "includes_rshift_p (operands[2], operands[3])"
4541 
  "@
4542 
   {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4543 
   #"
4544 
  [(set_attr "type" "delayed_compare")
4545 
   (set_attr "length" "4,8")])
4546 
 
4547 
(define_split
4548 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4549 
        (compare:CC
4550 
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4551 
                              (match_operand:SI 2 "const_int_operand" ""))
4552 
                 (match_operand:SI 3 "mask_operand" ""))
4553 
         (const_int 0)))
4554 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4555 
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4556 
  "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4557 
  [(set (match_dup 0)
4558 
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4559 
   (set (match_dup 4)
4560 
        (compare:CC (match_dup 0)
4561 
                    (const_int 0)))]
4562 
  "")
4563 
 
4564 
(define_insn ""
4565 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4566 
        (zero_extend:SI
4567 
         (subreg:QI
4568 
          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4569 
                       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4570 
  "includes_rshift_p (operands[2], GEN_INT (255))"
4571 
  "{rlinm|rlwinm} %0,%1,%s2,0xff")
4572 
 
4573 
(define_insn ""
4574 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4575 
        (compare:CC
4576 
         (zero_extend:SI
4577 
          (subreg:QI
4578 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4579 
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4580 
         (const_int 0)))
4581 
   (clobber (match_scratch:SI 3 "=r,r"))]
4582 
  "includes_rshift_p (operands[2], GEN_INT (255))"
4583 
  "@
4584 
   {rlinm.|rlwinm.} %3,%1,%s2,0xff
4585 
   #"
4586 
  [(set_attr "type" "delayed_compare")
4587 
   (set_attr "length" "4,8")])
4588 
 
4589 
(define_split
4590 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4591 
        (compare:CC
4592 
         (zero_extend:SI
4593 
          (subreg:QI
4594 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4595 
                        (match_operand:SI 2 "const_int_operand" "")) 0))
4596 
         (const_int 0)))
4597 
   (clobber (match_scratch:SI 3 ""))]
4598 
  "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4599 
  [(set (match_dup 3)
4600 
        (zero_extend:SI (subreg:QI
4601 
           (lshiftrt:SI (match_dup 1)
4602 
                        (match_dup 2)) 0)))
4603 
   (set (match_dup 0)
4604 
        (compare:CC (match_dup 3)
4605 
                    (const_int 0)))]
4606 
  "")
4607 
 
4608 
(define_insn ""
4609 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4610 
        (compare:CC
4611 
         (zero_extend:SI
4612 
          (subreg:QI
4613 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4614 
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4615 
         (const_int 0)))
4616 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4617 
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4618 
  "includes_rshift_p (operands[2], GEN_INT (255))"
4619 
  "@
4620 
   {rlinm.|rlwinm.} %0,%1,%s2,0xff
4621 
   #"
4622 
  [(set_attr "type" "delayed_compare")
4623 
   (set_attr "length" "4,8")])
4624 
 
4625 
(define_split
4626 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4627 
        (compare:CC
4628 
         (zero_extend:SI
4629 
          (subreg:QI
4630 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4631 
                        (match_operand:SI 2 "const_int_operand" "")) 0))
4632 
         (const_int 0)))
4633 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4634 
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4635 
  "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4636 
  [(set (match_dup 0)
4637 
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4638 
   (set (match_dup 3)
4639 
        (compare:CC (match_dup 0)
4640 
                    (const_int 0)))]
4641 
  "")
4642 
 
4643 
(define_insn ""
4644 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4645 
        (zero_extend:SI
4646 
         (subreg:HI
4647 
          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4648 
                       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4649 
  "includes_rshift_p (operands[2], GEN_INT (65535))"
4650 
  "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4651 
 
4652 
(define_insn ""
4653 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4654 
        (compare:CC
4655 
         (zero_extend:SI
4656 
          (subreg:HI
4657 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4658 
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4659 
         (const_int 0)))
4660 
   (clobber (match_scratch:SI 3 "=r,r"))]
4661 
  "includes_rshift_p (operands[2], GEN_INT (65535))"
4662 
  "@
4663 
   {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4664 
   #"
4665 
  [(set_attr "type" "delayed_compare")
4666 
   (set_attr "length" "4,8")])
4667 
 
4668 
(define_split
4669 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4670 
        (compare:CC
4671 
         (zero_extend:SI
4672 
          (subreg:HI
4673 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4674 
                        (match_operand:SI 2 "const_int_operand" "")) 0))
4675 
         (const_int 0)))
4676 
   (clobber (match_scratch:SI 3 ""))]
4677 
  "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4678 
  [(set (match_dup 3)
4679 
        (zero_extend:SI (subreg:HI
4680 
           (lshiftrt:SI (match_dup 1)
4681 
                        (match_dup 2)) 0)))
4682 
   (set (match_dup 0)
4683 
        (compare:CC (match_dup 3)
4684 
                    (const_int 0)))]
4685 
  "")
4686 
 
4687 
(define_insn ""
4688 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4689 
        (compare:CC
4690 
         (zero_extend:SI
4691 
          (subreg:HI
4692 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4693 
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4694 
         (const_int 0)))
4695 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4696 
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4697 
  "includes_rshift_p (operands[2], GEN_INT (65535))"
4698 
  "@
4699 
   {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4700 
   #"
4701 
  [(set_attr "type" "delayed_compare")
4702 
   (set_attr "length" "4,8")])
4703 
 
4704 
(define_split
4705 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4706 
        (compare:CC
4707 
         (zero_extend:SI
4708 
          (subreg:HI
4709 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4710 
                        (match_operand:SI 2 "const_int_operand" "")) 0))
4711 
         (const_int 0)))
4712 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4713 
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4714 
  "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4715 
  [(set (match_dup 0)
4716 
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4717 
   (set (match_dup 3)
4718 
        (compare:CC (match_dup 0)
4719 
                    (const_int 0)))]
4720 
  "")
4721 
 
4722 
(define_insn ""
4723 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4724 
                         (const_int 1)
4725 
                         (match_operand:SI 1 "gpc_reg_operand" "r"))
4726 
        (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4727 
                     (const_int 31)))]
4728 
  "TARGET_POWER"
4729 
  "rrib %0,%1,%2")
4730 
 
4731 
(define_insn ""
4732 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4733 
                         (const_int 1)
4734 
                         (match_operand:SI 1 "gpc_reg_operand" "r"))
4735 
        (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4736 
                     (const_int 31)))]
4737 
  "TARGET_POWER"
4738 
  "rrib %0,%1,%2")
4739 
 
4740 
(define_insn ""
4741 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4742 
                         (const_int 1)
4743 
                         (match_operand:SI 1 "gpc_reg_operand" "r"))
4744 
        (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4745 
                         (const_int 1)
4746 
                         (const_int 0)))]
4747 
  "TARGET_POWER"
4748 
  "rrib %0,%1,%2")
4749 
 
4750 
(define_expand "ashrsi3"
4751 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
4752 
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4753 
                     (match_operand:SI 2 "reg_or_cint_operand" "")))]
4754 
  ""
4755 
  "
4756 
{
4757 
  if (TARGET_POWER)
4758 
    emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4759 
  else
4760 
    emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4761 
  DONE;
4762 
}")
4763 
 
4764 
(define_insn "ashrsi3_power"
4765 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4766 
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4767 
                     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4768 
   (clobber (match_scratch:SI 3 "=q,X"))]
4769 
  "TARGET_POWER"
4770 
  "@
4771 
   srea %0,%1,%2
4772 
   {srai|srawi} %0,%1,%h2")
4773 
 
4774 
(define_insn "ashrsi3_no_power"
4775 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4776 
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4777 
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4778 
  "! TARGET_POWER"
4779 
  "{sra|sraw}%I2 %0,%1,%h2")
4780 
 
4781 
(define_insn ""
4782 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4783 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4784 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4785 
                    (const_int 0)))
4786 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))
4787 
   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4788 
  "TARGET_POWER"
4789 
  "@
4790 
   srea. %3,%1,%2
4791 
   {srai.|srawi.} %3,%1,%h2
4792 
   #
4793 
   #"
4794 
  [(set_attr "type" "delayed_compare")
4795 
   (set_attr "length" "4,4,8,8")])
4796 
 
4797 
(define_split
4798 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4799 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4800 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
4801 
                    (const_int 0)))
4802 
   (clobber (match_scratch:SI 3 ""))
4803 
   (clobber (match_scratch:SI 4 ""))]
4804 
  "TARGET_POWER && reload_completed"
4805 
  [(parallel [(set (match_dup 3)
4806 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
4807 
   (clobber (match_dup 4))])
4808 
   (set (match_dup 0)
4809 
        (compare:CC (match_dup 3)
4810 
                    (const_int 0)))]
4811 
  "")
4812 
 
4813 
(define_insn ""
4814 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4815 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4816 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4817 
                    (const_int 0)))
4818 
   (clobber (match_scratch:SI 3 "=r,r"))]
4819 
  "! TARGET_POWER"
4820 
  "@
4821 
   {sra|sraw}%I2. %3,%1,%h2
4822 
   #"
4823 
  [(set_attr "type" "delayed_compare")
4824 
   (set_attr "length" "4,8")])
4825 
 
4826 
(define_split
4827 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4828 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4829 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
4830 
                    (const_int 0)))
4831 
   (clobber (match_scratch:SI 3 ""))]
4832 
  "! TARGET_POWER && reload_completed"
4833 
  [(set (match_dup 3)
4834 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
4835 
   (set (match_dup 0)
4836 
        (compare:CC (match_dup 3)
4837 
                    (const_int 0)))]
4838 
  "")
4839 
 
4840 
(define_insn ""
4841 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4842 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4843 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4844 
                    (const_int 0)))
4845 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4846 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
4847 
   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4848 
  "TARGET_POWER"
4849 
  "@
4850 
   srea. %0,%1,%2
4851 
   {srai.|srawi.} %0,%1,%h2
4852 
   #
4853 
   #"
4854 
  [(set_attr "type" "delayed_compare")
4855 
   (set_attr "length" "4,4,8,8")])
4856 
 
4857 
(define_split
4858 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4859 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4860 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
4861 
                    (const_int 0)))
4862 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4863 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
4864 
   (clobber (match_scratch:SI 4 ""))]
4865 
  "TARGET_POWER && reload_completed"
4866 
  [(parallel [(set (match_dup 0)
4867 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
4868 
   (clobber (match_dup 4))])
4869 
   (set (match_dup 3)
4870 
        (compare:CC (match_dup 0)
4871 
                    (const_int 0)))]
4872 
  "")
4873 
 
4874 
(define_insn ""
4875 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4876 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4877 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4878 
                    (const_int 0)))
4879 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4880 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4881 
  "! TARGET_POWER"
4882 
  "@
4883 
   {sra|sraw}%I2. %0,%1,%h2
4884 
   #"
4885 
  [(set_attr "type" "delayed_compare")
4886 
   (set_attr "length" "4,8")])
4887 
 
4888 
(define_split
4889 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4890 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4891 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
4892 
                    (const_int 0)))
4893 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4894 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4895 
  "! TARGET_POWER && reload_completed"
4896 
  [(set (match_dup 0)
4897 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
4898 
   (set (match_dup 3)
4899 
        (compare:CC (match_dup 0)
4900 
                    (const_int 0)))]
4901 
  "")
4902 
 
4903 
;; Floating-point insns, excluding normal data motion.
4904 
;;
4905 
;; PowerPC has a full set of single-precision floating point instructions.
4906 
;;
4907 
;; For the POWER architecture, we pretend that we have both SFmode and
4908 
;; DFmode insns, while, in fact, all fp insns are actually done in double.
4909 
;; The only conversions we will do will be when storing to memory.  In that
4910 
;; case, we will use the "frsp" instruction before storing.
4911 
;;
4912 
;; Note that when we store into a single-precision memory location, we need to
4913 
;; use the frsp insn first.  If the register being stored isn't dead, we
4914 
;; need a scratch register for the frsp.  But this is difficult when the store
4915 
;; is done by reload.  It is not incorrect to do the frsp on the register in
4916 
;; this case, we just lose precision that we would have otherwise gotten but
4917 
;; is not guaranteed.  Perhaps this should be tightened up at some point.
4918 
 
4919 
(define_expand "extendsfdf2"
4920 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
4921 
        (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4922 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4923 
  "")
4924 
 
4925 
(define_insn_and_split "*extendsfdf2_fpr"
4926 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4927 
        (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4928 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
4929 
  "@
4930 
   #
4931 
   fmr %0,%1
4932 
   lfs%U1%X1 %0,%1"
4933 
  "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4934 
  [(const_int 0)]
4935 
{
4936 
  emit_note (NOTE_INSN_DELETED);
4937 
  DONE;
4938 
}
4939 
  [(set_attr "type" "fp,fp,fpload")])
4940 
 
4941 
(define_expand "truncdfsf2"
4942 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
4943 
        (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4944 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4945 
  "")
4946 
 
4947 
(define_insn "*truncdfsf2_fpr"
4948 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4949 
        (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4950 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
4951 
  "frsp %0,%1"
4952 
  [(set_attr "type" "fp")])
4953 
 
4954 
(define_insn "aux_truncdfsf2"
4955 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4956 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4957 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4958 
  "frsp %0,%1"
4959 
  [(set_attr "type" "fp")])
4960 
 
4961 
(define_expand "negsf2"
4962 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
4963 
        (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4964 
  "TARGET_HARD_FLOAT"
4965 
  "")
4966 
 
4967 
(define_insn "*negsf2"
4968 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4969 
        (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4970 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
4971 
  "fneg %0,%1"
4972 
  [(set_attr "type" "fp")])
4973 
 
4974 
(define_expand "abssf2"
4975 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
4976 
        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4977 
  "TARGET_HARD_FLOAT"
4978 
  "")
4979 
 
4980 
(define_insn "*abssf2"
4981 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4982 
        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4983 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
4984 
  "fabs %0,%1"
4985 
  [(set_attr "type" "fp")])
4986 
 
4987 
(define_insn ""
4988 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4989 
        (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4990 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
4991 
  "fnabs %0,%1"
4992 
  [(set_attr "type" "fp")])
4993 
 
4994 
(define_expand "addsf3"
4995 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
4996 
        (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4997 
                 (match_operand:SF 2 "gpc_reg_operand" "")))]
4998 
  "TARGET_HARD_FLOAT"
4999 
  "")
5000 
 
5001 
(define_insn ""
5002 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5003 
        (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5004 
                 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5005 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5006 
  "fadds %0,%1,%2"
5007 
  [(set_attr "type" "fp")])
5008 
 
5009 
(define_insn ""
5010 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5011 
        (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5012 
                 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5013 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5014 
  "{fa|fadd} %0,%1,%2"
5015 
  [(set_attr "type" "fp")])
5016 
 
5017 
(define_expand "subsf3"
5018 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5019 
        (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5020 
                  (match_operand:SF 2 "gpc_reg_operand" "")))]
5021 
  "TARGET_HARD_FLOAT"
5022 
  "")
5023 
 
5024 
(define_insn ""
5025 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5026 
        (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5027 
                  (match_operand:SF 2 "gpc_reg_operand" "f")))]
5028 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5029 
  "fsubs %0,%1,%2"
5030 
  [(set_attr "type" "fp")])
5031 
 
5032 
(define_insn ""
5033 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5034 
        (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5035 
                  (match_operand:SF 2 "gpc_reg_operand" "f")))]
5036 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5037 
  "{fs|fsub} %0,%1,%2"
5038 
  [(set_attr "type" "fp")])
5039 
 
5040 
(define_expand "mulsf3"
5041 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5042 
        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5043 
                 (match_operand:SF 2 "gpc_reg_operand" "")))]
5044 
  "TARGET_HARD_FLOAT"
5045 
  "")
5046 
 
5047 
(define_insn ""
5048 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5049 
        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5050 
                 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5051 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5052 
  "fmuls %0,%1,%2"
5053 
  [(set_attr "type" "fp")])
5054 
 
5055 
(define_insn ""
5056 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5057 
        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5058 
                 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5059 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5060 
  "{fm|fmul} %0,%1,%2"
5061 
  [(set_attr "type" "dmul")])
5062 
 
5063 
(define_insn "fres"
5064 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5065 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5066 
  "TARGET_PPC_GFXOPT && flag_finite_math_only"
5067 
  "fres %0,%1"
5068 
  [(set_attr "type" "fp")])
5069 
 
5070 
(define_expand "divsf3"
5071 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5072 
        (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5073 
                (match_operand:SF 2 "gpc_reg_operand" "")))]
5074 
  "TARGET_HARD_FLOAT"
5075 
{
5076 
  if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5077 
  && flag_finite_math_only && !flag_trapping_math)
5078 
    {
5079 
      rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5080 
      DONE;
5081 
    }
5082 
})
5083 
 
5084 
(define_insn ""
5085 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5086 
        (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5087 
                (match_operand:SF 2 "gpc_reg_operand" "f")))]
5088 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5089 
  "fdivs %0,%1,%2"
5090 
  [(set_attr "type" "sdiv")])
5091 
 
5092 
(define_insn ""
5093 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5094 
        (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5095 
                (match_operand:SF 2 "gpc_reg_operand" "f")))]
5096 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5097 
  "{fd|fdiv} %0,%1,%2"
5098 
  [(set_attr "type" "ddiv")])
5099 
 
5100 
(define_insn ""
5101 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5102 
        (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5103 
                          (match_operand:SF 2 "gpc_reg_operand" "f"))
5104 
                 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5105 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5106 
  "fmadds %0,%1,%2,%3"
5107 
  [(set_attr "type" "fp")])
5108 
 
5109 
(define_insn ""
5110 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5111 
        (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5112 
                          (match_operand:SF 2 "gpc_reg_operand" "f"))
5113 
                 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5114 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5115 
  "{fma|fmadd} %0,%1,%2,%3"
5116 
  [(set_attr "type" "dmul")])
5117 
 
5118 
(define_insn ""
5119 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5120 
        (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5121 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))
5122 
                  (match_operand:SF 3 "gpc_reg_operand" "f")))]
5123 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5124 
  "fmsubs %0,%1,%2,%3"
5125 
  [(set_attr "type" "fp")])
5126 
 
5127 
(define_insn ""
5128 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5129 
        (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5130 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))
5131 
                  (match_operand:SF 3 "gpc_reg_operand" "f")))]
5132 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5133 
  "{fms|fmsub} %0,%1,%2,%3"
5134 
  [(set_attr "type" "dmul")])
5135 
 
5136 
(define_insn ""
5137 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5138 
        (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5139 
                                  (match_operand:SF 2 "gpc_reg_operand" "f"))
5140 
                         (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5141 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5142 
   && HONOR_SIGNED_ZEROS (SFmode)"
5143 
  "fnmadds %0,%1,%2,%3"
5144 
  [(set_attr "type" "fp")])
5145 
 
5146 
(define_insn ""
5147 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5148 
        (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5149 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))
5150 
                         (match_operand:SF 3 "gpc_reg_operand" "f")))]
5151 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5152 
   && ! HONOR_SIGNED_ZEROS (SFmode)"
5153 
  "fnmadds %0,%1,%2,%3"
5154 
  [(set_attr "type" "fp")])
5155 
 
5156 
(define_insn ""
5157 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5158 
        (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5159 
                                  (match_operand:SF 2 "gpc_reg_operand" "f"))
5160 
                         (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5161 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5162 
  "{fnma|fnmadd} %0,%1,%2,%3"
5163 
  [(set_attr "type" "dmul")])
5164 
 
5165 
(define_insn ""
5166 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5167 
        (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5168 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))
5169 
                         (match_operand:SF 3 "gpc_reg_operand" "f")))]
5170 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5171 
   && ! HONOR_SIGNED_ZEROS (SFmode)"
5172 
  "{fnma|fnmadd} %0,%1,%2,%3"
5173 
  [(set_attr "type" "dmul")])
5174 
 
5175 
(define_insn ""
5176 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5177 
        (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5178 
                                   (match_operand:SF 2 "gpc_reg_operand" "f"))
5179 
                          (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5180 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5181 
   && HONOR_SIGNED_ZEROS (SFmode)"
5182 
  "fnmsubs %0,%1,%2,%3"
5183 
  [(set_attr "type" "fp")])
5184 
 
5185 
(define_insn ""
5186 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5187 
        (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5188 
                  (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5189 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5190 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5191 
   && ! HONOR_SIGNED_ZEROS (SFmode)"
5192 
  "fnmsubs %0,%1,%2,%3"
5193 
  [(set_attr "type" "fp")])
5194 
 
5195 
(define_insn ""
5196 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5197 
        (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5198 
                                   (match_operand:SF 2 "gpc_reg_operand" "f"))
5199 
                          (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5200 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5201 
  "{fnms|fnmsub} %0,%1,%2,%3"
5202 
  [(set_attr "type" "dmul")])
5203 
 
5204 
(define_insn ""
5205 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5206 
        (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5207 
                  (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5208 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5209 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5210 
   && ! HONOR_SIGNED_ZEROS (SFmode)"
5211 
  "{fnms|fnmsub} %0,%1,%2,%3"
5212 
  [(set_attr "type" "dmul")])
5213 
 
5214 
(define_expand "sqrtsf2"
5215 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5216 
        (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5217 
  "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5218 
  "")
5219 
 
5220 
(define_insn ""
5221 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5222 
        (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5223 
  "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5224 
  "fsqrts %0,%1"
5225 
  [(set_attr "type" "ssqrt")])
5226 
 
5227 
(define_insn ""
5228 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5229 
        (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5230 
  "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5231 
  "fsqrt %0,%1"
5232 
  [(set_attr "type" "dsqrt")])
5233 
 
5234 
(define_expand "copysignsf3"
5235 
  [(set (match_dup 3)
5236 
        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5237 
   (set (match_dup 4)
5238 
        (neg:SF (abs:SF (match_dup 1))))
5239 
   (set (match_operand:SF 0 "gpc_reg_operand" "")
5240 
        (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5241 
                             (match_dup 5))
5242 
                         (match_dup 3)
5243 
                         (match_dup 4)))]
5244 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5245 
   && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5246 
  {
5247 
     operands[3] = gen_reg_rtx (SFmode);
5248 
     operands[4] = gen_reg_rtx (SFmode);
5249 
     operands[5] = CONST0_RTX (SFmode);
5250 
  })
5251 
 
5252 
(define_expand "copysigndf3"
5253 
  [(set (match_dup 3)
5254 
        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5255 
   (set (match_dup 4)
5256 
        (neg:DF (abs:DF (match_dup 1))))
5257 
   (set (match_operand:DF 0 "gpc_reg_operand" "")
5258 
        (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5259 
                             (match_dup 5))
5260 
                         (match_dup 3)
5261 
                         (match_dup 4)))]
5262 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5263 
   && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5264 
  {
5265 
     operands[3] = gen_reg_rtx (DFmode);
5266 
     operands[4] = gen_reg_rtx (DFmode);
5267 
     operands[5] = CONST0_RTX (DFmode);
5268 
  })
5269 
 
5270 
;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5271 
;; fsel instruction and some auxiliary computations.  Then we just have a
5272 
;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5273 
;; combine.
5274 
(define_expand "smaxsf3"
5275 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5276 
        (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5277 
                             (match_operand:SF 2 "gpc_reg_operand" ""))
5278 
                         (match_dup 1)
5279 
                         (match_dup 2)))]
5280 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5281 
  "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5282 
 
5283 
(define_expand "sminsf3"
5284 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5285 
        (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5286 
                             (match_operand:SF 2 "gpc_reg_operand" ""))
5287 
                         (match_dup 2)
5288 
                         (match_dup 1)))]
5289 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5290 
  "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5291 
 
5292 
(define_split
5293 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5294 
        (match_operator:SF 3 "min_max_operator"
5295 
         [(match_operand:SF 1 "gpc_reg_operand" "")
5296 
          (match_operand:SF 2 "gpc_reg_operand" "")]))]
5297 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5298 
  [(const_int 0)]
5299 
  "
5300 
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5301 
                      operands[1], operands[2]);
5302 
  DONE;
5303 
}")
5304 
 
5305 
(define_expand "movsicc"
5306 
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
5307 
         (if_then_else:SI (match_operand 1 "comparison_operator" "")
5308 
                          (match_operand:SI 2 "gpc_reg_operand" "")
5309 
                          (match_operand:SI 3 "gpc_reg_operand" "")))]
5310 
  "TARGET_ISEL"
5311 
  "
5312 
{
5313 
  if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5314 
    DONE;
5315 
  else
5316 
    FAIL;
5317 
}")
5318 
 
5319 
;; We use the BASE_REGS for the isel input operands because, if rA is
5320 
;; 0, the value of 0 is placed in rD upon truth.  Similarly for rB
5321 
;; because we may switch the operands and rB may end up being rA.
5322 
;;
5323 
;; We need 2 patterns: an unsigned and a signed pattern.  We could
5324 
;; leave out the mode in operand 4 and use one pattern, but reload can
5325 
;; change the mode underneath our feet and then gets confused trying
5326 
;; to reload the value.
5327 
(define_insn "isel_signed"
5328 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5329 
        (if_then_else:SI
5330 
         (match_operator 1 "comparison_operator"
5331 
                         [(match_operand:CC 4 "cc_reg_operand" "y")
5332 
                          (const_int 0)])
5333 
         (match_operand:SI 2 "gpc_reg_operand" "b")
5334 
         (match_operand:SI 3 "gpc_reg_operand" "b")))]
5335 
  "TARGET_ISEL"
5336 
  "*
5337 
{ return output_isel (operands); }"
5338 
  [(set_attr "length" "4")])
5339 
 
5340 
(define_insn "isel_unsigned"
5341 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5342 
        (if_then_else:SI
5343 
         (match_operator 1 "comparison_operator"
5344 
                         [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5345 
                          (const_int 0)])
5346 
         (match_operand:SI 2 "gpc_reg_operand" "b")
5347 
         (match_operand:SI 3 "gpc_reg_operand" "b")))]
5348 
  "TARGET_ISEL"
5349 
  "*
5350 
{ return output_isel (operands); }"
5351 
  [(set_attr "length" "4")])
5352 
 
5353 
(define_expand "movsfcc"
5354 
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
5355 
         (if_then_else:SF (match_operand 1 "comparison_operator" "")
5356 
                          (match_operand:SF 2 "gpc_reg_operand" "")
5357 
                          (match_operand:SF 3 "gpc_reg_operand" "")))]
5358 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5359 
  "
5360 
{
5361 
  if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5362 
    DONE;
5363 
  else
5364 
    FAIL;
5365 
}")
5366 
 
5367 
(define_insn "*fselsfsf4"
5368 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5369 
        (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5370 
                             (match_operand:SF 4 "zero_fp_constant" "F"))
5371 
                         (match_operand:SF 2 "gpc_reg_operand" "f")
5372 
                         (match_operand:SF 3 "gpc_reg_operand" "f")))]
5373 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5374 
  "fsel %0,%1,%2,%3"
5375 
  [(set_attr "type" "fp")])
5376 
 
5377 
(define_insn "*fseldfsf4"
5378 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5379 
        (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5380 
                             (match_operand:DF 4 "zero_fp_constant" "F"))
5381 
                         (match_operand:SF 2 "gpc_reg_operand" "f")
5382 
                         (match_operand:SF 3 "gpc_reg_operand" "f")))]
5383 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5384 
  "fsel %0,%1,%2,%3"
5385 
  [(set_attr "type" "fp")])
5386 
 
5387 
(define_expand "negdf2"
5388 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5389 
        (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5390 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5391 
  "")
5392 
 
5393 
(define_insn "*negdf2_fpr"
5394 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5395 
        (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5396 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
5397 
  "fneg %0,%1"
5398 
  [(set_attr "type" "fp")])
5399 
 
5400 
(define_expand "absdf2"
5401 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5402 
        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5403 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5404 
  "")
5405 
 
5406 
(define_insn "*absdf2_fpr"
5407 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5408 
        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5409 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
5410 
  "fabs %0,%1"
5411 
  [(set_attr "type" "fp")])
5412 
 
5413 
(define_insn "*nabsdf2_fpr"
5414 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5415 
        (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5416 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
5417 
  "fnabs %0,%1"
5418 
  [(set_attr "type" "fp")])
5419 
 
5420 
(define_expand "adddf3"
5421 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5422 
        (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5423 
                 (match_operand:DF 2 "gpc_reg_operand" "")))]
5424 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5425 
  "")
5426 
 
5427 
(define_insn "*adddf3_fpr"
5428 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5429 
        (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5430 
                 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5431 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
5432 
  "{fa|fadd} %0,%1,%2"
5433 
  [(set_attr "type" "fp")])
5434 
 
5435 
(define_expand "subdf3"
5436 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5437 
        (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5438 
                  (match_operand:DF 2 "gpc_reg_operand" "")))]
5439 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5440 
  "")
5441 
 
5442 
(define_insn "*subdf3_fpr"
5443 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5444 
        (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5445 
                  (match_operand:DF 2 "gpc_reg_operand" "f")))]
5446 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
5447 
  "{fs|fsub} %0,%1,%2"
5448 
  [(set_attr "type" "fp")])
5449 
 
5450 
(define_expand "muldf3"
5451 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5452 
        (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5453 
                 (match_operand:DF 2 "gpc_reg_operand" "")))]
5454 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5455 
  "")
5456 
 
5457 
(define_insn "*muldf3_fpr"
5458 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5459 
        (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5460 
                 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5461 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
5462 
  "{fm|fmul} %0,%1,%2"
5463 
  [(set_attr "type" "dmul")])
5464 
 
5465 
(define_insn "fred"
5466 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5467 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5468 
  "TARGET_POPCNTB && flag_finite_math_only"
5469 
  "fre %0,%1"
5470 
  [(set_attr "type" "fp")])
5471 
 
5472 
(define_expand "divdf3"
5473 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5474 
        (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5475 
                (match_operand:DF 2 "gpc_reg_operand" "")))]
5476 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5477 
{
5478 
  if (swdiv && !optimize_size && TARGET_POPCNTB
5479 
  && flag_finite_math_only && !flag_trapping_math)
5480 
    {
5481 
      rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5482 
      DONE;
5483 
    }
5484 
})
5485 
 
5486 
(define_insn "*divdf3_fpr"
5487 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5488 
        (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5489 
                (match_operand:DF 2 "gpc_reg_operand" "f")))]
5490 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
5491 
  "{fd|fdiv} %0,%1,%2"
5492 
  [(set_attr "type" "ddiv")])
5493 
 
5494 
(define_insn ""
5495 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5496 
        (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5497 
                          (match_operand:DF 2 "gpc_reg_operand" "f"))
5498 
                 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5499 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5500 
  "{fma|fmadd} %0,%1,%2,%3"
5501 
  [(set_attr "type" "dmul")])
5502 
 
5503 
(define_insn ""
5504 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5505 
        (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5506 
                           (match_operand:DF 2 "gpc_reg_operand" "f"))
5507 
                  (match_operand:DF 3 "gpc_reg_operand" "f")))]
5508 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5509 
  "{fms|fmsub} %0,%1,%2,%3"
5510 
  [(set_attr "type" "dmul")])
5511 
 
5512 
(define_insn ""
5513 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5514 
        (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5515 
                                  (match_operand:DF 2 "gpc_reg_operand" "f"))
5516 
                         (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5517 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5518 
   && HONOR_SIGNED_ZEROS (DFmode)"
5519 
  "{fnma|fnmadd} %0,%1,%2,%3"
5520 
  [(set_attr "type" "dmul")])
5521 
 
5522 
(define_insn ""
5523 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5524 
        (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5525 
                           (match_operand:DF 2 "gpc_reg_operand" "f"))
5526 
                  (match_operand:DF 3 "gpc_reg_operand" "f")))]
5527 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5528 
   && ! HONOR_SIGNED_ZEROS (DFmode)"
5529 
  "{fnma|fnmadd} %0,%1,%2,%3"
5530 
  [(set_attr "type" "dmul")])
5531 
 
5532 
(define_insn ""
5533 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5534 
        (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5535 
                                   (match_operand:DF 2 "gpc_reg_operand" "f"))
5536 
                          (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5537 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5538 
   && HONOR_SIGNED_ZEROS (DFmode)"
5539 
  "{fnms|fnmsub} %0,%1,%2,%3"
5540 
  [(set_attr "type" "dmul")])
5541 
 
5542 
(define_insn ""
5543 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5544 
        (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5545 
                  (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5546 
                           (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5547 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5548 
   && ! HONOR_SIGNED_ZEROS (DFmode)"
5549 
  "{fnms|fnmsub} %0,%1,%2,%3"
5550 
  [(set_attr "type" "dmul")])
5551 
 
5552 
(define_insn "sqrtdf2"
5553 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5554 
        (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5555 
  "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5556 
  "fsqrt %0,%1"
5557 
  [(set_attr "type" "dsqrt")])
5558 
 
5559 
;; The conditional move instructions allow us to perform max and min
5560 
;; operations even when
5561 
 
5562 
(define_expand "smaxdf3"
5563 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5564 
        (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5565 
                             (match_operand:DF 2 "gpc_reg_operand" ""))
5566 
                         (match_dup 1)
5567 
                         (match_dup 2)))]
5568 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5569 
  "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5570 
 
5571 
(define_expand "smindf3"
5572 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5573 
        (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5574 
                             (match_operand:DF 2 "gpc_reg_operand" ""))
5575 
                         (match_dup 2)
5576 
                         (match_dup 1)))]
5577 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5578 
  "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5579 
 
5580 
(define_split
5581 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5582 
        (match_operator:DF 3 "min_max_operator"
5583 
         [(match_operand:DF 1 "gpc_reg_operand" "")
5584 
          (match_operand:DF 2 "gpc_reg_operand" "")]))]
5585 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5586 
  [(const_int 0)]
5587 
  "
5588 
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5589 
                      operands[1], operands[2]);
5590 
  DONE;
5591 
}")
5592 
 
5593 
(define_expand "movdfcc"
5594 
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
5595 
         (if_then_else:DF (match_operand 1 "comparison_operator" "")
5596 
                          (match_operand:DF 2 "gpc_reg_operand" "")
5597 
                          (match_operand:DF 3 "gpc_reg_operand" "")))]
5598 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5599 
  "
5600 
{
5601 
  if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5602 
    DONE;
5603 
  else
5604 
    FAIL;
5605 
}")
5606 
 
5607 
(define_insn "*fseldfdf4"
5608 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5609 
        (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5610 
                             (match_operand:DF 4 "zero_fp_constant" "F"))
5611 
                         (match_operand:DF 2 "gpc_reg_operand" "f")
5612 
                         (match_operand:DF 3 "gpc_reg_operand" "f")))]
5613 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5614 
  "fsel %0,%1,%2,%3"
5615 
  [(set_attr "type" "fp")])
5616 
 
5617 
(define_insn "*fselsfdf4"
5618 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5619 
        (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5620 
                             (match_operand:SF 4 "zero_fp_constant" "F"))
5621 
                         (match_operand:DF 2 "gpc_reg_operand" "f")
5622 
                         (match_operand:DF 3 "gpc_reg_operand" "f")))]
5623 
  "TARGET_PPC_GFXOPT"
5624 
  "fsel %0,%1,%2,%3"
5625 
  [(set_attr "type" "fp")])
5626 
 
5627 
;; Conversions to and from floating-point.
5628 
 
5629 
(define_expand "fixuns_truncsfsi2"
5630 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
5631 
        (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5632 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
5633 
  "")
5634 
 
5635 
(define_expand "fix_truncsfsi2"
5636 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
5637 
        (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5638 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
5639 
  "")
5640 
 
5641 
; For each of these conversions, there is a define_expand, a define_insn
5642 
; with a '#' template, and a define_split (with C code).  The idea is
5643 
; to allow constant folding with the template of the define_insn,
5644 
; then to have the insns split later (between sched1 and final).
5645 
 
5646 
(define_expand "floatsidf2"
5647 
  [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5648 
                   (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5649 
              (use (match_dup 2))
5650 
              (use (match_dup 3))
5651 
              (clobber (match_dup 4))
5652 
              (clobber (match_dup 5))
5653 
              (clobber (match_dup 6))])]
5654 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
5655 
  "
5656 
{
5657 
  if (TARGET_E500_DOUBLE)
5658 
    {
5659 
      emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5660 
      DONE;
5661 
    }
5662 
  if (TARGET_POWERPC64)
5663 
    {
5664 
      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5665 
      rtx t1 = gen_reg_rtx (DImode);
5666 
      rtx t2 = gen_reg_rtx (DImode);
5667 
      emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5668 
      DONE;
5669 
    }
5670 
 
5671 
  operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5672 
  operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5673 
  operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5674 
  operands[5] = gen_reg_rtx (DFmode);
5675 
  operands[6] = gen_reg_rtx (SImode);
5676 
}")
5677 
 
5678 
(define_insn_and_split "*floatsidf2_internal"
5679 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5680 
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5681 
   (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5682 
   (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5683 
   (clobber (match_operand:DF 4 "memory_operand" "=o"))
5684 
   (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5685 
   (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5686 
  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5687 
  "#"
5688 
  "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5689 
  [(pc)]
5690 
  "
5691 
{
5692 
  rtx lowword, highword;
5693 
  gcc_assert (MEM_P (operands[4]));
5694 
  highword = adjust_address (operands[4], SImode, 0);
5695 
  lowword = adjust_address (operands[4], SImode, 4);
5696 
  if (! WORDS_BIG_ENDIAN)
5697 
    {
5698 
      rtx tmp;
5699 
      tmp = highword; highword = lowword; lowword = tmp;
5700 
    }
5701 
 
5702 
  emit_insn (gen_xorsi3 (operands[6], operands[1],
5703 
                         GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5704 
  emit_move_insn (lowword, operands[6]);
5705 
  emit_move_insn (highword, operands[2]);
5706 
  emit_move_insn (operands[5], operands[4]);
5707 
  emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5708 
  DONE;
5709 
}"
5710 
  [(set_attr "length" "24")])
5711 
 
5712 
(define_expand "floatunssisf2"
5713 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5714 
        (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5715 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
5716 
  "")
5717 
 
5718 
(define_expand "floatunssidf2"
5719 
  [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5720 
                   (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5721 
              (use (match_dup 2))
5722 
              (use (match_dup 3))
5723 
              (clobber (match_dup 4))
5724 
              (clobber (match_dup 5))])]
5725 
  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5726 
  "
5727 
{
5728 
  if (TARGET_E500_DOUBLE)
5729 
    {
5730 
      emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5731 
      DONE;
5732 
    }
5733 
  if (TARGET_POWERPC64)
5734 
    {
5735 
      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5736 
      rtx t1 = gen_reg_rtx (DImode);
5737 
      rtx t2 = gen_reg_rtx (DImode);
5738 
      emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5739 
                                         t1, t2));
5740 
      DONE;
5741 
    }
5742 
 
5743 
  operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5744 
  operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5745 
  operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5746 
  operands[5] = gen_reg_rtx (DFmode);
5747 
}")
5748 
 
5749 
(define_insn_and_split "*floatunssidf2_internal"
5750 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5751 
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5752 
   (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5753 
   (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5754 
   (clobber (match_operand:DF 4 "memory_operand" "=o"))
5755 
   (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5756 
  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5757 
  "#"
5758 
  "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5759 
  [(pc)]
5760 
  "
5761 
{
5762 
  rtx lowword, highword;
5763 
  gcc_assert (MEM_P (operands[4]));
5764 
  highword = adjust_address (operands[4], SImode, 0);
5765 
  lowword = adjust_address (operands[4], SImode, 4);
5766 
  if (! WORDS_BIG_ENDIAN)
5767 
    {
5768 
      rtx tmp;
5769 
      tmp = highword; highword = lowword; lowword = tmp;
5770 
    }
5771 
 
5772 
  emit_move_insn (lowword, operands[1]);
5773 
  emit_move_insn (highword, operands[2]);
5774 
  emit_move_insn (operands[5], operands[4]);
5775 
  emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5776 
  DONE;
5777 
}"
5778 
  [(set_attr "length" "20")])
5779 
 
5780 
(define_expand "fix_truncdfsi2"
5781 
  [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5782 
                   (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5783 
              (clobber (match_dup 2))
5784 
              (clobber (match_dup 3))])]
5785 
  "(TARGET_POWER2 || TARGET_POWERPC)
5786 
   && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5787 
  "
5788 
{
5789 
  if (TARGET_E500_DOUBLE)
5790 
    {
5791 
     emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5792 
     DONE;
5793 
    }
5794 
  operands[2] = gen_reg_rtx (DImode);
5795 
  if (TARGET_PPC_GFXOPT)
5796 
    {
5797 
      rtx orig_dest = operands[0];
5798 
      if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5799 
        operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5800 
      emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5801 
                                                     operands[2]));
5802 
      if (operands[0] != orig_dest)
5803 
        emit_move_insn (orig_dest, operands[0]);
5804 
      DONE;
5805 
    }
5806 
  operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5807 
}")
5808 
 
5809 
(define_insn_and_split "*fix_truncdfsi2_internal"
5810 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5811 
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5812 
   (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5813 
   (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5814 
  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5815 
  "#"
5816 
  "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5817 
  [(pc)]
5818 
  "
5819 
{
5820 
  rtx lowword;
5821 
  gcc_assert (MEM_P (operands[3]));
5822 
  lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5823 
 
5824 
  emit_insn (gen_fctiwz (operands[2], operands[1]));
5825 
  emit_move_insn (operands[3], operands[2]);
5826 
  emit_move_insn (operands[0], lowword);
5827 
  DONE;
5828 
}"
5829 
  [(set_attr "length" "16")])
5830 
 
5831 
(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5832 
  [(set (match_operand:SI 0 "memory_operand" "=Z")
5833 
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5834 
   (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5835 
  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5836 
   && TARGET_PPC_GFXOPT"
5837 
  "#"
5838 
  "&& 1"
5839 
  [(pc)]
5840 
  "
5841 
{
5842 
  emit_insn (gen_fctiwz (operands[2], operands[1]));
5843 
  emit_insn (gen_stfiwx (operands[0], operands[2]));
5844 
  DONE;
5845 
}"
5846 
  [(set_attr "length" "16")])
5847 
 
5848 
; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5849 
; rather than (set (subreg:SI (reg)) (fix:SI ...))
5850 
; because the first makes it clear that operand 0 is not live
5851 
; before the instruction.
5852 
(define_insn "fctiwz"
5853 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5854 
        (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5855 
                   UNSPEC_FCTIWZ))]
5856 
  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5857 
  "{fcirz|fctiwz} %0,%1"
5858 
  [(set_attr "type" "fp")])
5859 
 
5860 
(define_insn "btruncdf2"
5861 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5862 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5863 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5864 
  "friz %0,%1"
5865 
  [(set_attr "type" "fp")])
5866 
 
5867 
(define_insn "btruncsf2"
5868 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5869 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5870 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5871 
  "friz %0,%1"
5872 
  [(set_attr "type" "fp")])
5873 
 
5874 
(define_insn "ceildf2"
5875 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5876 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5877 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5878 
  "frip %0,%1"
5879 
  [(set_attr "type" "fp")])
5880 
 
5881 
(define_insn "ceilsf2"
5882 
 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5883 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5884 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5885 
  "frip %0,%1"
5886 
  [(set_attr "type" "fp")])
5887 
 
5888 
(define_insn "floordf2"
5889 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5890 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5891 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5892 
  "frim %0,%1"
5893 
  [(set_attr "type" "fp")])
5894 
 
5895 
(define_insn "floorsf2"
5896 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5897 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5898 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5899 
  "frim %0,%1"
5900 
  [(set_attr "type" "fp")])
5901 
 
5902 
(define_insn "rounddf2"
5903 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5904 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5905 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5906 
  "frin %0,%1"
5907 
  [(set_attr "type" "fp")])
5908 
 
5909 
(define_insn "roundsf2"
5910 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5911 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5912 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5913 
  "frin %0,%1"
5914 
  [(set_attr "type" "fp")])
5915 
 
5916 
; An UNSPEC is used so we don't have to support SImode in FP registers.
5917 
(define_insn "stfiwx"
5918 
  [(set (match_operand:SI 0 "memory_operand" "=Z")
5919 
        (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5920 
                   UNSPEC_STFIWX))]
5921 
  "TARGET_PPC_GFXOPT"
5922 
  "stfiwx %1,%y0"
5923 
  [(set_attr "type" "fpstore")])
5924 
 
5925 
(define_expand "floatsisf2"
5926 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5927 
        (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5928 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
5929 
  "")
5930 
 
5931 
(define_insn "floatdidf2"
5932 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5933 
        (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5934 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5935 
  "fcfid %0,%1"
5936 
  [(set_attr "type" "fp")])
5937 
 
5938 
(define_insn_and_split "floatsidf_ppc64"
5939 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5940 
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5941 
   (clobber (match_operand:DI 2 "memory_operand" "=o"))
5942 
   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5943 
   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5944 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5945 
  "#"
5946 
  "&& 1"
5947 
  [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5948 
   (set (match_dup 2) (match_dup 3))
5949 
   (set (match_dup 4) (match_dup 2))
5950 
   (set (match_dup 0) (float:DF (match_dup 4)))]
5951 
  "")
5952 
 
5953 
(define_insn_and_split "floatunssidf_ppc64"
5954 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5955 
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5956 
   (clobber (match_operand:DI 2 "memory_operand" "=o"))
5957 
   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5958 
   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5959 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5960 
  "#"
5961 
  "&& 1"
5962 
  [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5963 
   (set (match_dup 2) (match_dup 3))
5964 
   (set (match_dup 4) (match_dup 2))
5965 
   (set (match_dup 0) (float:DF (match_dup 4)))]
5966 
  "")
5967 
 
5968 
(define_insn "fix_truncdfdi2"
5969 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5970 
        (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5971 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5972 
  "fctidz %0,%1"
5973 
  [(set_attr "type" "fp")])
5974 
 
5975 
(define_expand "floatdisf2"
5976 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5977 
        (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5978 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5979 
  "
5980 
{
5981 
  rtx val = operands[1];
5982 
  if (!flag_unsafe_math_optimizations)
5983 
    {
5984 
      rtx label = gen_label_rtx ();
5985 
      val = gen_reg_rtx (DImode);
5986 
      emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5987 
      emit_label (label);
5988 
    }
5989 
  emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5990 
  DONE;
5991 
}")
5992 
 
5993 
;; This is not IEEE compliant if rounding mode is "round to nearest".
5994 
;; If the DI->DF conversion is inexact, then it's possible to suffer
5995 
;; from double rounding.
5996 
(define_insn_and_split "floatdisf2_internal1"
5997 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5998 
        (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5999 
   (clobber (match_scratch:DF 2 "=f"))]
6000 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6001 
  "#"
6002 
  "&& reload_completed"
6003 
  [(set (match_dup 2)
6004 
        (float:DF (match_dup 1)))
6005 
   (set (match_dup 0)
6006 
        (float_truncate:SF (match_dup 2)))]
6007 
  "")
6008 
 
6009 
;; Twiddles bits to avoid double rounding.
6010 
;; Bits that might be truncated when converting to DFmode are replaced
6011 
;; by a bit that won't be lost at that stage, but is below the SFmode
6012 
;; rounding position.
6013 
(define_expand "floatdisf2_internal2"
6014 
  [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6015 
                                   (const_int 53)))
6016 
   (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6017 
                                                      (const_int 2047)))
6018 
              (clobber (scratch:CC))])
6019 
   (set (match_dup 3) (plus:DI (match_dup 3)
6020 
                               (const_int 1)))
6021 
   (set (match_dup 0) (plus:DI (match_dup 0)
6022 
                               (const_int 2047)))
6023 
   (set (match_dup 4) (compare:CCUNS (match_dup 3)
6024 
                                     (const_int 2)))
6025 
   (set (match_dup 0) (ior:DI (match_dup 0)
6026 
                              (match_dup 1)))
6027 
   (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6028 
                                         (const_int -2048)))
6029 
              (clobber (scratch:CC))])
6030 
   (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6031 
                           (label_ref (match_operand:DI 2 "" ""))
6032 
                           (pc)))
6033 
   (set (match_dup 0) (match_dup 1))]
6034 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6035 
  "
6036 
{
6037 
  operands[3] = gen_reg_rtx (DImode);
6038 
  operands[4] = gen_reg_rtx (CCUNSmode);
6039 
}")
6040 
 
6041 
;; Define the DImode operations that can be done in a small number
6042 
;; of instructions.  The & constraints are to prevent the register
6043 
;; allocator from allocating registers that overlap with the inputs
6044 
;; (for example, having an input in 7,8 and an output in 6,7).  We
6045 
;; also allow for the output being the same as one of the inputs.
6046 
 
6047 
(define_insn "*adddi3_noppc64"
6048 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6049 
        (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6050 
                 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6051 
  "! TARGET_POWERPC64"
6052 
  "*
6053 
{
6054 
  if (WORDS_BIG_ENDIAN)
6055 
    return (GET_CODE (operands[2])) != CONST_INT
6056 
            ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6057 
            : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6058 
  else
6059 
    return (GET_CODE (operands[2])) != CONST_INT
6060 
            ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6061 
            : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6062 
}"
6063 
  [(set_attr "type" "two")
6064 
   (set_attr "length" "8")])
6065 
 
6066 
(define_insn "*subdi3_noppc64"
6067 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6068 
        (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6069 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6070 
  "! TARGET_POWERPC64"
6071 
  "*
6072 
{
6073 
  if (WORDS_BIG_ENDIAN)
6074 
    return (GET_CODE (operands[1]) != CONST_INT)
6075 
            ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6076 
            : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6077 
  else
6078 
    return (GET_CODE (operands[1]) != CONST_INT)
6079 
            ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6080 
            : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6081 
}"
6082 
  [(set_attr "type" "two")
6083 
   (set_attr "length" "8")])
6084 
 
6085 
(define_insn "*negdi2_noppc64"
6086 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6087 
        (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6088 
  "! TARGET_POWERPC64"
6089 
  "*
6090 
{
6091 
  return (WORDS_BIG_ENDIAN)
6092 
    ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6093 
    : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6094 
}"
6095 
  [(set_attr "type" "two")
6096 
   (set_attr "length" "8")])
6097 
 
6098 
(define_expand "mulsidi3"
6099 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
6100 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6101 
                 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6102 
  "! TARGET_POWERPC64"
6103 
  "
6104 
{
6105 
  if (! TARGET_POWER && ! TARGET_POWERPC)
6106 
    {
6107 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6108 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6109 
      emit_insn (gen_mull_call ());
6110 
      if (WORDS_BIG_ENDIAN)
6111 
        emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6112 
      else
6113 
        {
6114 
          emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6115 
                          gen_rtx_REG (SImode, 3));
6116 
          emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6117 
                          gen_rtx_REG (SImode, 4));
6118 
        }
6119 
      DONE;
6120 
    }
6121 
  else if (TARGET_POWER)
6122 
    {
6123 
      emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6124 
      DONE;
6125 
    }
6126 
}")
6127 
 
6128 
(define_insn "mulsidi3_mq"
6129 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6130 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6131 
                 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6132 
   (clobber (match_scratch:SI 3 "=q"))]
6133 
  "TARGET_POWER"
6134 
  "mul %0,%1,%2\;mfmq %L0"
6135 
  [(set_attr "type" "imul")
6136 
   (set_attr "length" "8")])
6137 
 
6138 
(define_insn "*mulsidi3_no_mq"
6139 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6140 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6141 
                 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6142 
  "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6143 
  "*
6144 
{
6145 
  return (WORDS_BIG_ENDIAN)
6146 
    ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6147 
    : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6148 
}"
6149 
  [(set_attr "type" "imul")
6150 
   (set_attr "length" "8")])
6151 
 
6152 
(define_split
6153 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
6154 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6155 
                 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6156 
  "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6157 
  [(set (match_dup 3)
6158 
        (truncate:SI
6159 
         (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6160 
                               (sign_extend:DI (match_dup 2)))
6161 
                      (const_int 32))))
6162 
   (set (match_dup 4)
6163 
        (mult:SI (match_dup 1)
6164 
                 (match_dup 2)))]
6165 
  "
6166 
{
6167 
  int endian = (WORDS_BIG_ENDIAN == 0);
6168 
  operands[3] = operand_subword (operands[0], endian, 0, DImode);
6169 
  operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6170 
}")
6171 
 
6172 
(define_expand "umulsidi3"
6173 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
6174 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6175 
                 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6176 
  "TARGET_POWERPC && ! TARGET_POWERPC64"
6177 
  "
6178 
{
6179 
  if (TARGET_POWER)
6180 
    {
6181 
      emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6182 
      DONE;
6183 
    }
6184 
}")
6185 
 
6186 
(define_insn "umulsidi3_mq"
6187 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6188 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6189 
                 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6190 
   (clobber (match_scratch:SI 3 "=q"))]
6191 
  "TARGET_POWERPC && TARGET_POWER"
6192 
  "*
6193 
{
6194 
  return (WORDS_BIG_ENDIAN)
6195 
    ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6196 
    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6197 
}"
6198 
  [(set_attr "type" "imul")
6199 
   (set_attr "length" "8")])
6200 
 
6201 
(define_insn "*umulsidi3_no_mq"
6202 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6203 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6204 
                 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6205 
  "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6206 
  "*
6207 
{
6208 
  return (WORDS_BIG_ENDIAN)
6209 
    ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6210 
    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6211 
}"
6212 
  [(set_attr "type" "imul")
6213 
   (set_attr "length" "8")])
6214 
 
6215 
(define_split
6216 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
6217 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6218 
                 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6219 
  "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6220 
  [(set (match_dup 3)
6221 
        (truncate:SI
6222 
         (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6223 
                               (zero_extend:DI (match_dup 2)))
6224 
                      (const_int 32))))
6225 
   (set (match_dup 4)
6226 
        (mult:SI (match_dup 1)
6227 
                 (match_dup 2)))]
6228 
  "
6229 
{
6230 
  int endian = (WORDS_BIG_ENDIAN == 0);
6231 
  operands[3] = operand_subword (operands[0], endian, 0, DImode);
6232 
  operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6233 
}")
6234 
 
6235 
(define_expand "smulsi3_highpart"
6236 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
6237 
        (truncate:SI
6238 
         (lshiftrt:DI (mult:DI (sign_extend:DI
6239 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
6240 
                               (sign_extend:DI
6241 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
6242 
                      (const_int 32))))]
6243 
  ""
6244 
  "
6245 
{
6246 
  if (! TARGET_POWER && ! TARGET_POWERPC)
6247 
    {
6248 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6249 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6250 
      emit_insn (gen_mulh_call ());
6251 
      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6252 
      DONE;
6253 
    }
6254 
  else if (TARGET_POWER)
6255 
    {
6256 
      emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6257 
      DONE;
6258 
    }
6259 
}")
6260 
 
6261 
(define_insn "smulsi3_highpart_mq"
6262 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6263 
        (truncate:SI
6264 
         (lshiftrt:DI (mult:DI (sign_extend:DI
6265 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
6266 
                               (sign_extend:DI
6267 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
6268 
                      (const_int 32))))
6269 
   (clobber (match_scratch:SI 3 "=q"))]
6270 
  "TARGET_POWER"
6271 
  "mul %0,%1,%2"
6272 
  [(set_attr "type" "imul")])
6273 
 
6274 
(define_insn "*smulsi3_highpart_no_mq"
6275 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6276 
        (truncate:SI
6277 
         (lshiftrt:DI (mult:DI (sign_extend:DI
6278 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
6279 
                               (sign_extend:DI
6280 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
6281 
                      (const_int 32))))]
6282 
  "TARGET_POWERPC && ! TARGET_POWER"
6283 
  "mulhw %0,%1,%2"
6284 
  [(set_attr "type" "imul")])
6285 
 
6286 
(define_expand "umulsi3_highpart"
6287 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
6288 
        (truncate:SI
6289 
         (lshiftrt:DI (mult:DI (zero_extend:DI
6290 
                                (match_operand:SI 1 "gpc_reg_operand" ""))
6291 
                               (zero_extend:DI
6292 
                                (match_operand:SI 2 "gpc_reg_operand" "")))
6293 
                      (const_int 32))))]
6294 
  "TARGET_POWERPC"
6295 
  "
6296 
{
6297 
  if (TARGET_POWER)
6298 
    {
6299 
      emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6300 
      DONE;
6301 
    }
6302 
}")
6303 
 
6304 
(define_insn "umulsi3_highpart_mq"
6305 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6306 
        (truncate:SI
6307 
         (lshiftrt:DI (mult:DI (zero_extend:DI
6308 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
6309 
                               (zero_extend:DI
6310 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
6311 
                      (const_int 32))))
6312 
   (clobber (match_scratch:SI 3 "=q"))]
6313 
  "TARGET_POWERPC && TARGET_POWER"
6314 
  "mulhwu %0,%1,%2"
6315 
  [(set_attr "type" "imul")])
6316 
 
6317 
(define_insn "*umulsi3_highpart_no_mq"
6318 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6319 
        (truncate:SI
6320 
         (lshiftrt:DI (mult:DI (zero_extend:DI
6321 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
6322 
                               (zero_extend:DI
6323 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
6324 
                      (const_int 32))))]
6325 
  "TARGET_POWERPC && ! TARGET_POWER"
6326 
  "mulhwu %0,%1,%2"
6327 
  [(set_attr "type" "imul")])
6328 
 
6329 
;; If operands 0 and 2 are in the same register, we have a problem.  But
6330 
;; operands 0 and 1 (the usual case) can be in the same register.  That's
6331 
;; why we have the strange constraints below.
6332 
(define_insn "ashldi3_power"
6333 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6334 
        (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6335 
                   (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6336 
   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6337 
  "TARGET_POWER"
6338 
  "@
6339 
   {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6340 
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6341 
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6342 
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6343 
  [(set_attr "length" "8")])
6344 
 
6345 
(define_insn "lshrdi3_power"
6346 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6347 
        (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6348 
                     (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6349 
   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6350 
  "TARGET_POWER"
6351 
  "@
6352 
   {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6353 
   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6354 
   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6355 
   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6356 
  [(set_attr "length" "8")])
6357 
 
6358 
;; Shift by a variable amount is too complex to be worth open-coding.  We
6359 
;; just handle shifts by constants.
6360 
(define_insn "ashrdi3_power"
6361 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6362 
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6363 
                     (match_operand:SI 2 "const_int_operand" "M,i")))
6364 
   (clobber (match_scratch:SI 3 "=X,q"))]
6365 
  "TARGET_POWER"
6366 
  "@
6367 
   {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6368 
   sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6369 
  [(set_attr "length" "8")])
6370 
 
6371 
(define_insn "ashrdi3_no_power"
6372 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6373 
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6374 
                     (match_operand:SI 2 "const_int_operand" "M,i")))]
6375 
  "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6376 
  "@
6377 
   {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6378 
   {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6379 
  [(set_attr "type" "two,three")
6380 
   (set_attr "length" "8,12")])
6381 
 
6382 
(define_insn "*ashrdisi3_noppc64"
6383 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6384 
        (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6385 
                                (const_int 32)) 4))]
6386 
  "TARGET_32BIT && !TARGET_POWERPC64"
6387 
  "*
6388 
{
6389 
  if (REGNO (operands[0]) == REGNO (operands[1]))
6390 
    return \"\";
6391 
  else
6392 
    return \"mr %0,%1\";
6393 
}"
6394 
   [(set_attr "length" "4")])
6395 
 
6396 
 
6397 
;; PowerPC64 DImode operations.
6398 
 
6399 
(define_insn_and_split "absdi2"
6400 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6401 
        (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6402 
   (clobber (match_scratch:DI 2 "=&r,&r"))]
6403 
  "TARGET_POWERPC64"
6404 
  "#"
6405 
  "&& reload_completed"
6406 
  [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6407 
   (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6408 
   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6409 
  "")
6410 
 
6411 
(define_insn_and_split "*nabsdi2"
6412 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6413 
        (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6414 
   (clobber (match_scratch:DI 2 "=&r,&r"))]
6415 
  "TARGET_POWERPC64"
6416 
  "#"
6417 
  "&& reload_completed"
6418 
  [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6419 
   (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6420 
   (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6421 
  "")
6422 
 
6423 
(define_insn "muldi3"
6424 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6425 
        (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6426 
                 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6427 
  "TARGET_POWERPC64"
6428 
  "@
6429 
   mulld %0,%1,%2
6430 
   mulli %0,%1,%2"
6431 
   [(set (attr "type")
6432 
      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6433 
                (const_string "imul3")
6434 
             (match_operand:SI 2 "short_cint_operand" "")
6435 
                (const_string "imul2")]
6436 
        (const_string "lmul")))])
6437 
 
6438 
(define_insn "*muldi3_internal1"
6439 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6440 
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6441 
                             (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6442 
                    (const_int 0)))
6443 
   (clobber (match_scratch:DI 3 "=r,r"))]
6444 
  "TARGET_POWERPC64"
6445 
  "@
6446 
   mulld. %3,%1,%2
6447 
   #"
6448 
  [(set_attr "type" "lmul_compare")
6449 
   (set_attr "length" "4,8")])
6450 
 
6451 
(define_split
6452 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6453 
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6454 
                             (match_operand:DI 2 "gpc_reg_operand" ""))
6455 
                    (const_int 0)))
6456 
   (clobber (match_scratch:DI 3 ""))]
6457 
  "TARGET_POWERPC64 && reload_completed"
6458 
  [(set (match_dup 3)
6459 
        (mult:DI (match_dup 1) (match_dup 2)))
6460 
   (set (match_dup 0)
6461 
        (compare:CC (match_dup 3)
6462 
                    (const_int 0)))]
6463 
  "")
6464 
 
6465 
(define_insn "*muldi3_internal2"
6466 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6467 
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6468 
                             (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6469 
                    (const_int 0)))
6470 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6471 
        (mult:DI (match_dup 1) (match_dup 2)))]
6472 
  "TARGET_POWERPC64"
6473 
  "@
6474 
   mulld. %0,%1,%2
6475 
   #"
6476 
  [(set_attr "type" "lmul_compare")
6477 
   (set_attr "length" "4,8")])
6478 
 
6479 
(define_split
6480 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6481 
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6482 
                             (match_operand:DI 2 "gpc_reg_operand" ""))
6483 
                    (const_int 0)))
6484 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
6485 
        (mult:DI (match_dup 1) (match_dup 2)))]
6486 
  "TARGET_POWERPC64 && reload_completed"
6487 
  [(set (match_dup 0)
6488 
        (mult:DI (match_dup 1) (match_dup 2)))
6489 
   (set (match_dup 3)
6490 
        (compare:CC (match_dup 0)
6491 
                    (const_int 0)))]
6492 
  "")
6493 
 
6494 
(define_insn "smuldi3_highpart"
6495 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6496 
        (truncate:DI
6497 
         (lshiftrt:TI (mult:TI (sign_extend:TI
6498 
                                (match_operand:DI 1 "gpc_reg_operand" "%r"))
6499 
                               (sign_extend:TI
6500 
                                (match_operand:DI 2 "gpc_reg_operand" "r")))
6501 
                      (const_int 64))))]
6502 
  "TARGET_POWERPC64"
6503 
  "mulhd %0,%1,%2"
6504 
  [(set_attr "type" "lmul")])
6505 
 
6506 
(define_insn "umuldi3_highpart"
6507 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6508 
        (truncate:DI
6509 
         (lshiftrt:TI (mult:TI (zero_extend:TI
6510 
                                (match_operand:DI 1 "gpc_reg_operand" "%r"))
6511 
                               (zero_extend:TI
6512 
                                (match_operand:DI 2 "gpc_reg_operand" "r")))
6513 
                      (const_int 64))))]
6514 
  "TARGET_POWERPC64"
6515 
  "mulhdu %0,%1,%2"
6516 
  [(set_attr "type" "lmul")])
6517 
 
6518 
(define_insn "rotldi3"
6519 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6520 
        (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6521 
                   (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6522 
  "TARGET_POWERPC64"
6523 
  "rld%I2cl %0,%1,%H2,0")
6524 
 
6525 
(define_insn "*rotldi3_internal2"
6526 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6527 
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6528 
                               (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6529 
                    (const_int 0)))
6530 
   (clobber (match_scratch:DI 3 "=r,r"))]
6531 
  "TARGET_64BIT"
6532 
  "@
6533 
   rld%I2cl. %3,%1,%H2,0
6534 
   #"
6535 
  [(set_attr "type" "delayed_compare")
6536 
   (set_attr "length" "4,8")])
6537 
 
6538 
(define_split
6539 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6540 
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6541 
                               (match_operand:DI 2 "reg_or_cint_operand" ""))
6542 
                    (const_int 0)))
6543 
   (clobber (match_scratch:DI 3 ""))]
6544 
  "TARGET_POWERPC64 && reload_completed"
6545 
  [(set (match_dup 3)
6546 
        (rotate:DI (match_dup 1) (match_dup 2)))
6547 
   (set (match_dup 0)
6548 
        (compare:CC (match_dup 3)
6549 
                    (const_int 0)))]
6550 
  "")
6551 
 
6552 
(define_insn "*rotldi3_internal3"
6553 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6554 
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6555 
                               (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6556 
                    (const_int 0)))
6557 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6558 
        (rotate:DI (match_dup 1) (match_dup 2)))]
6559 
  "TARGET_64BIT"
6560 
  "@
6561 
   rld%I2cl. %0,%1,%H2,0
6562 
   #"
6563 
  [(set_attr "type" "delayed_compare")
6564 
   (set_attr "length" "4,8")])
6565 
 
6566 
(define_split
6567 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6568 
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6569 
                               (match_operand:DI 2 "reg_or_cint_operand" ""))
6570 
                    (const_int 0)))
6571 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
6572 
        (rotate:DI (match_dup 1) (match_dup 2)))]
6573 
  "TARGET_POWERPC64 && reload_completed"
6574 
  [(set (match_dup 0)
6575 
        (rotate:DI (match_dup 1) (match_dup 2)))
6576 
   (set (match_dup 3)
6577 
        (compare:CC (match_dup 0)
6578 
                    (const_int 0)))]
6579 
  "")
6580 
 
6581 
(define_insn "*rotldi3_internal4"
6582 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6583 
        (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6584 
                           (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6585 
                (match_operand:DI 3 "mask64_operand" "n")))]
6586 
  "TARGET_POWERPC64"
6587 
  "rld%I2c%B3 %0,%1,%H2,%S3")
6588 
 
6589 
(define_insn "*rotldi3_internal5"
6590 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6591 
        (compare:CC (and:DI
6592 
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6593 
                                (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6594 
                     (match_operand:DI 3 "mask64_operand" "n,n"))
6595 
                    (const_int 0)))
6596 
   (clobber (match_scratch:DI 4 "=r,r"))]
6597 
  "TARGET_64BIT"
6598 
  "@
6599 
   rld%I2c%B3. %4,%1,%H2,%S3
6600 
   #"
6601 
  [(set_attr "type" "delayed_compare")
6602 
   (set_attr "length" "4,8")])
6603 
 
6604 
(define_split
6605 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6606 
        (compare:CC (and:DI
6607 
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6608 
                                (match_operand:DI 2 "reg_or_cint_operand" ""))
6609 
                     (match_operand:DI 3 "mask64_operand" ""))
6610 
                    (const_int 0)))
6611 
   (clobber (match_scratch:DI 4 ""))]
6612 
  "TARGET_POWERPC64 && reload_completed"
6613 
  [(set (match_dup 4)
6614 
        (and:DI (rotate:DI (match_dup 1)
6615 
                                (match_dup 2))
6616 
                     (match_dup 3)))
6617 
   (set (match_dup 0)
6618 
        (compare:CC (match_dup 4)
6619 
                    (const_int 0)))]
6620 
  "")
6621 
 
6622 
(define_insn "*rotldi3_internal6"
6623 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6624 
        (compare:CC (and:DI
6625 
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6626 
                                (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6627 
                     (match_operand:DI 3 "mask64_operand" "n,n"))
6628 
                    (const_int 0)))
6629 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6630 
        (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6631 
  "TARGET_64BIT"
6632 
  "@
6633 
   rld%I2c%B3. %0,%1,%H2,%S3
6634 
   #"
6635 
  [(set_attr "type" "delayed_compare")
6636 
   (set_attr "length" "4,8")])
6637 
 
6638 
(define_split
6639 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6640 
        (compare:CC (and:DI
6641 
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6642 
                                (match_operand:DI 2 "reg_or_cint_operand" ""))
6643 
                     (match_operand:DI 3 "mask64_operand" ""))
6644 
                    (const_int 0)))
6645 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
6646 
        (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6647 
  "TARGET_POWERPC64 && reload_completed"
6648 
  [(set (match_dup 0)
6649 
        (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6650 
   (set (match_dup 4)
6651 
        (compare:CC (match_dup 0)
6652 
                    (const_int 0)))]
6653 
  "")
6654 
 
6655 
(define_insn "*rotldi3_internal7"
6656 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6657 
        (zero_extend:DI
6658 
         (subreg:QI
6659 
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6660 
                     (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6661 
  "TARGET_POWERPC64"
6662 
  "rld%I2cl %0,%1,%H2,56")
6663 
 
6664 
(define_insn "*rotldi3_internal8"
6665 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6666 
        (compare:CC (zero_extend:DI
6667 
                     (subreg:QI
6668 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6669 
                                 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6670 
                    (const_int 0)))
6671 
   (clobber (match_scratch:DI 3 "=r,r"))]
6672 
  "TARGET_64BIT"
6673 
  "@
6674 
   rld%I2cl. %3,%1,%H2,56
6675 
   #"
6676 
  [(set_attr "type" "delayed_compare")
6677 
   (set_attr "length" "4,8")])
6678 
 
6679 
(define_split
6680 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6681 
        (compare:CC (zero_extend:DI
6682 
                     (subreg:QI
6683 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6684 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6685 
                    (const_int 0)))
6686 
   (clobber (match_scratch:DI 3 ""))]
6687 
  "TARGET_POWERPC64 && reload_completed"
6688 
  [(set (match_dup 3)
6689 
        (zero_extend:DI (subreg:QI
6690 
                      (rotate:DI (match_dup 1)
6691 
                                 (match_dup 2)) 0)))
6692 
   (set (match_dup 0)
6693 
        (compare:CC (match_dup 3)
6694 
                    (const_int 0)))]
6695 
  "")
6696 
 
6697 
(define_insn "*rotldi3_internal9"
6698 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6699 
        (compare:CC (zero_extend:DI
6700 
                     (subreg:QI
6701 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6702 
                                 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6703 
                    (const_int 0)))
6704 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6705 
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6706 
  "TARGET_64BIT"
6707 
  "@
6708 
   rld%I2cl. %0,%1,%H2,56
6709 
   #"
6710 
  [(set_attr "type" "delayed_compare")
6711 
   (set_attr "length" "4,8")])
6712 
 
6713 
(define_split
6714 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6715 
        (compare:CC (zero_extend:DI
6716 
                     (subreg:QI
6717 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6718 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6719 
                    (const_int 0)))
6720 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
6721 
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6722 
  "TARGET_POWERPC64 && reload_completed"
6723 
  [(set (match_dup 0)
6724 
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6725 
   (set (match_dup 3)
6726 
        (compare:CC (match_dup 0)
6727 
                    (const_int 0)))]
6728 
  "")
6729 
 
6730 
(define_insn "*rotldi3_internal10"
6731 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6732 
        (zero_extend:DI
6733 
         (subreg:HI
6734 
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6735 
                     (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6736 
  "TARGET_POWERPC64"
6737 
  "rld%I2cl %0,%1,%H2,48")
6738 
 
6739 
(define_insn "*rotldi3_internal11"
6740 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6741 
        (compare:CC (zero_extend:DI
6742 
                     (subreg:HI
6743 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6744 
                                 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6745 
                    (const_int 0)))
6746 
   (clobber (match_scratch:DI 3 "=r,r"))]
6747 
  "TARGET_64BIT"
6748 
  "@
6749 
   rld%I2cl. %3,%1,%H2,48
6750 
   #"
6751 
  [(set_attr "type" "delayed_compare")
6752 
   (set_attr "length" "4,8")])
6753 
 
6754 
(define_split
6755 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6756 
        (compare:CC (zero_extend:DI
6757 
                     (subreg:HI
6758 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6759 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6760 
                    (const_int 0)))
6761 
   (clobber (match_scratch:DI 3 ""))]
6762 
  "TARGET_POWERPC64 && reload_completed"
6763 
  [(set (match_dup 3)
6764 
        (zero_extend:DI (subreg:HI
6765 
                      (rotate:DI (match_dup 1)
6766 
                                 (match_dup 2)) 0)))
6767 
   (set (match_dup 0)
6768 
        (compare:CC (match_dup 3)
6769 
                    (const_int 0)))]
6770 
  "")
6771 
 
6772 
(define_insn "*rotldi3_internal12"
6773 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6774 
        (compare:CC (zero_extend:DI
6775 
                     (subreg:HI
6776 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6777 
                                 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6778 
                    (const_int 0)))
6779 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6780 
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6781 
  "TARGET_64BIT"
6782 
  "@
6783 
   rld%I2cl. %0,%1,%H2,48
6784 
   #"
6785 
  [(set_attr "type" "delayed_compare")
6786 
   (set_attr "length" "4,8")])
6787 
 
6788 
(define_split
6789 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6790 
        (compare:CC (zero_extend:DI
6791 
                     (subreg:HI
6792 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6793 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6794 
                    (const_int 0)))
6795 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
6796 
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6797 
  "TARGET_POWERPC64 && reload_completed"
6798 
  [(set (match_dup 0)
6799 
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6800 
   (set (match_dup 3)
6801 
        (compare:CC (match_dup 0)
6802 
                    (const_int 0)))]
6803 
  "")
6804 
 
6805 
(define_insn "*rotldi3_internal13"
6806 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6807 
        (zero_extend:DI
6808 
         (subreg:SI
6809 
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6810 
                     (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6811 
  "TARGET_POWERPC64"
6812 
  "rld%I2cl %0,%1,%H2,32")
6813 
 
6814 
(define_insn "*rotldi3_internal14"
6815 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6816 
        (compare:CC (zero_extend:DI
6817 
                     (subreg:SI
6818 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6819 
                                 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6820 
                    (const_int 0)))
6821 
   (clobber (match_scratch:DI 3 "=r,r"))]
6822 
  "TARGET_64BIT"
6823 
  "@
6824 
   rld%I2cl. %3,%1,%H2,32
6825 
   #"
6826 
  [(set_attr "type" "delayed_compare")
6827 
   (set_attr "length" "4,8")])
6828 
 
6829 
(define_split
6830 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6831 
        (compare:CC (zero_extend:DI
6832 
                     (subreg:SI
6833 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6834 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6835 
                    (const_int 0)))
6836 
   (clobber (match_scratch:DI 3 ""))]
6837 
  "TARGET_POWERPC64 && reload_completed"
6838 
  [(set (match_dup 3)
6839 
        (zero_extend:DI (subreg:SI
6840 
                      (rotate:DI (match_dup 1)
6841 
                                 (match_dup 2)) 0)))
6842 
   (set (match_dup 0)
6843 
        (compare:CC (match_dup 3)
6844 
                    (const_int 0)))]
6845 
  "")
6846 
 
6847 
(define_insn "*rotldi3_internal15"
6848 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6849 
        (compare:CC (zero_extend:DI
6850 
                     (subreg:SI
6851 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6852 
                                 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6853 
                    (const_int 0)))
6854 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6855 
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6856 
  "TARGET_64BIT"
6857 
  "@
6858 
   rld%I2cl. %0,%1,%H2,32
6859 
   #"
6860 
  [(set_attr "type" "delayed_compare")
6861 
   (set_attr "length" "4,8")])
6862 
 
6863 
(define_split
6864 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6865 
        (compare:CC (zero_extend:DI
6866 
                     (subreg:SI
6867 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6868 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6869 
                    (const_int 0)))
6870 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
6871 
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6872 
  "TARGET_POWERPC64 && reload_completed"
6873 
  [(set (match_dup 0)
6874 
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6875 
   (set (match_dup 3)
6876 
        (compare:CC (match_dup 0)
6877 
                    (const_int 0)))]
6878 
  "")
6879 
 
6880 
(define_expand "ashldi3"
6881 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
6882 
        (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6883 
                   (match_operand:SI 2 "reg_or_cint_operand" "")))]
6884 
  "TARGET_POWERPC64 || TARGET_POWER"
6885 
  "
6886 
{
6887 
  if (TARGET_POWERPC64)
6888 
    ;
6889 
  else if (TARGET_POWER)
6890 
    {
6891 
      emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6892 
      DONE;
6893 
    }
6894 
  else
6895 
    FAIL;
6896 
}")
6897 
 
6898 
(define_insn "*ashldi3_internal1"
6899 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6900 
        (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6901 
                   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6902 
  "TARGET_POWERPC64"
6903 
  "sld%I2 %0,%1,%H2")
6904 
 
6905 
(define_insn "*ashldi3_internal2"
6906 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6907 
        (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6908 
                               (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6909 
                    (const_int 0)))
6910 
   (clobber (match_scratch:DI 3 "=r,r"))]
6911 
  "TARGET_64BIT"
6912 
  "@
6913 
   sld%I2. %3,%1,%H2
6914 
   #"
6915 
  [(set_attr "type" "delayed_compare")
6916 
   (set_attr "length" "4,8")])
6917 
 
6918 
(define_split
6919 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6920 
        (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6921 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
6922 
                    (const_int 0)))
6923 
   (clobber (match_scratch:DI 3 ""))]
6924 
  "TARGET_POWERPC64 && reload_completed"
6925 
  [(set (match_dup 3)
6926 
        (ashift:DI (match_dup 1) (match_dup 2)))
6927 
   (set (match_dup 0)
6928 
        (compare:CC (match_dup 3)
6929 
                    (const_int 0)))]
6930 
  "")
6931 
 
6932 
(define_insn "*ashldi3_internal3"
6933 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6934 
        (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6935 
                               (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6936 
                    (const_int 0)))
6937 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6938 
        (ashift:DI (match_dup 1) (match_dup 2)))]
6939 
  "TARGET_64BIT"
6940 
  "@
6941 
   sld%I2. %0,%1,%H2
6942 
   #"
6943 
  [(set_attr "type" "delayed_compare")
6944 
   (set_attr "length" "4,8")])
6945 
 
6946 
(define_split
6947 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6948 
        (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6949 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
6950 
                    (const_int 0)))
6951 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
6952 
        (ashift:DI (match_dup 1) (match_dup 2)))]
6953 
  "TARGET_POWERPC64 && reload_completed"
6954 
  [(set (match_dup 0)
6955 
        (ashift:DI (match_dup 1) (match_dup 2)))
6956 
   (set (match_dup 3)
6957 
        (compare:CC (match_dup 0)
6958 
                    (const_int 0)))]
6959 
  "")
6960 
 
6961 
(define_insn "*ashldi3_internal4"
6962 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6963 
        (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6964 
                           (match_operand:SI 2 "const_int_operand" "i"))
6965 
                (match_operand:DI 3 "const_int_operand" "n")))]
6966 
  "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6967 
  "rldic %0,%1,%H2,%W3")
6968 
 
6969 
(define_insn "ashldi3_internal5"
6970 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6971 
        (compare:CC
6972 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6973 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
6974 
                 (match_operand:DI 3 "const_int_operand" "n,n"))
6975 
         (const_int 0)))
6976 
   (clobber (match_scratch:DI 4 "=r,r"))]
6977 
  "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6978 
  "@
6979 
   rldic. %4,%1,%H2,%W3
6980 
   #"
6981 
  [(set_attr "type" "compare")
6982 
   (set_attr "length" "4,8")])
6983 
 
6984 
(define_split
6985 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6986 
        (compare:CC
6987 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6988 
                            (match_operand:SI 2 "const_int_operand" ""))
6989 
                 (match_operand:DI 3 "const_int_operand" ""))
6990 
         (const_int 0)))
6991 
   (clobber (match_scratch:DI 4 ""))]
6992 
  "TARGET_POWERPC64 && reload_completed
6993 
   && includes_rldic_lshift_p (operands[2], operands[3])"
6994 
  [(set (match_dup 4)
6995 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6996 
                (match_dup 3)))
6997 
   (set (match_dup 0)
6998 
        (compare:CC (match_dup 4)
6999 
                    (const_int 0)))]
7000 
  "")
7001 
 
7002 
(define_insn "*ashldi3_internal6"
7003 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7004 
        (compare:CC
7005 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7006 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
7007 
                    (match_operand:DI 3 "const_int_operand" "n,n"))
7008 
         (const_int 0)))
7009 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7010 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7011 
  "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7012 
  "@
7013 
   rldic. %0,%1,%H2,%W3
7014 
   #"
7015 
  [(set_attr "type" "compare")
7016 
   (set_attr "length" "4,8")])
7017 
 
7018 
(define_split
7019 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7020 
        (compare:CC
7021 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7022 
                            (match_operand:SI 2 "const_int_operand" ""))
7023 
                 (match_operand:DI 3 "const_int_operand" ""))
7024 
         (const_int 0)))
7025 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7026 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7027 
  "TARGET_POWERPC64 && reload_completed
7028 
   && includes_rldic_lshift_p (operands[2], operands[3])"
7029 
  [(set (match_dup 0)
7030 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7031 
                (match_dup 3)))
7032 
   (set (match_dup 4)
7033 
        (compare:CC (match_dup 0)
7034 
                    (const_int 0)))]
7035 
  "")
7036 
 
7037 
(define_insn "*ashldi3_internal7"
7038 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7039 
        (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7040 
                           (match_operand:SI 2 "const_int_operand" "i"))
7041 
                (match_operand:DI 3 "mask64_operand" "n")))]
7042 
  "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7043 
  "rldicr %0,%1,%H2,%S3")
7044 
 
7045 
(define_insn "ashldi3_internal8"
7046 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7047 
        (compare:CC
7048 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7049 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
7050 
                 (match_operand:DI 3 "mask64_operand" "n,n"))
7051 
         (const_int 0)))
7052 
   (clobber (match_scratch:DI 4 "=r,r"))]
7053 
  "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7054 
  "@
7055 
   rldicr. %4,%1,%H2,%S3
7056 
   #"
7057 
  [(set_attr "type" "compare")
7058 
   (set_attr "length" "4,8")])
7059 
 
7060 
(define_split
7061 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7062 
        (compare:CC
7063 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7064 
                            (match_operand:SI 2 "const_int_operand" ""))
7065 
                 (match_operand:DI 3 "mask64_operand" ""))
7066 
         (const_int 0)))
7067 
   (clobber (match_scratch:DI 4 ""))]
7068 
  "TARGET_POWERPC64 && reload_completed
7069 
   && includes_rldicr_lshift_p (operands[2], operands[3])"
7070 
  [(set (match_dup 4)
7071 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7072 
                (match_dup 3)))
7073 
   (set (match_dup 0)
7074 
        (compare:CC (match_dup 4)
7075 
                    (const_int 0)))]
7076 
  "")
7077 
 
7078 
(define_insn "*ashldi3_internal9"
7079 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7080 
        (compare:CC
7081 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7082 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
7083 
                    (match_operand:DI 3 "mask64_operand" "n,n"))
7084 
         (const_int 0)))
7085 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7086 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7087 
  "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7088 
  "@
7089 
   rldicr. %0,%1,%H2,%S3
7090 
   #"
7091 
  [(set_attr "type" "compare")
7092 
   (set_attr "length" "4,8")])
7093 
 
7094 
(define_split
7095 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7096 
        (compare:CC
7097 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7098 
                            (match_operand:SI 2 "const_int_operand" ""))
7099 
                 (match_operand:DI 3 "mask64_operand" ""))
7100 
         (const_int 0)))
7101 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7102 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7103 
  "TARGET_POWERPC64 && reload_completed
7104 
   && includes_rldicr_lshift_p (operands[2], operands[3])"
7105 
  [(set (match_dup 0)
7106 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7107 
                (match_dup 3)))
7108 
   (set (match_dup 4)
7109 
        (compare:CC (match_dup 0)
7110 
                    (const_int 0)))]
7111 
  "")
7112 
 
7113 
(define_expand "lshrdi3"
7114 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7115 
        (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7116 
                     (match_operand:SI 2 "reg_or_cint_operand" "")))]
7117 
  "TARGET_POWERPC64 || TARGET_POWER"
7118 
  "
7119 
{
7120 
  if (TARGET_POWERPC64)
7121 
    ;
7122 
  else if (TARGET_POWER)
7123 
    {
7124 
      emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7125 
      DONE;
7126 
    }
7127 
  else
7128 
    FAIL;
7129 
}")
7130 
 
7131 
(define_insn "*lshrdi3_internal1"
7132 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7133 
        (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7134 
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7135 
  "TARGET_POWERPC64"
7136 
  "srd%I2 %0,%1,%H2")
7137 
 
7138 
(define_insn "*lshrdi3_internal2"
7139 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7140 
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7141 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7142 
                    (const_int 0)))
7143 
   (clobber (match_scratch:DI 3 "=r,r"))]
7144 
  "TARGET_64BIT "
7145 
  "@
7146 
   srd%I2. %3,%1,%H2
7147 
   #"
7148 
  [(set_attr "type" "delayed_compare")
7149 
   (set_attr "length" "4,8")])
7150 
 
7151 
(define_split
7152 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7153 
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7154 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
7155 
                    (const_int 0)))
7156 
   (clobber (match_scratch:DI 3 ""))]
7157 
  "TARGET_POWERPC64 && reload_completed"
7158 
  [(set (match_dup 3)
7159 
        (lshiftrt:DI (match_dup 1) (match_dup 2)))
7160 
   (set (match_dup 0)
7161 
        (compare:CC (match_dup 3)
7162 
                    (const_int 0)))]
7163 
  "")
7164 
 
7165 
(define_insn "*lshrdi3_internal3"
7166 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7167 
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7168 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7169 
                    (const_int 0)))
7170 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7171 
        (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7172 
  "TARGET_64BIT"
7173 
  "@
7174 
   srd%I2. %0,%1,%H2
7175 
   #"
7176 
  [(set_attr "type" "delayed_compare")
7177 
   (set_attr "length" "4,8")])
7178 
 
7179 
(define_split
7180 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7181 
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7182 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
7183 
                    (const_int 0)))
7184 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7185 
        (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7186 
  "TARGET_POWERPC64 && reload_completed"
7187 
  [(set (match_dup 0)
7188 
        (lshiftrt:DI (match_dup 1) (match_dup 2)))
7189 
   (set (match_dup 3)
7190 
        (compare:CC (match_dup 0)
7191 
                    (const_int 0)))]
7192 
  "")
7193 
 
7194 
(define_expand "ashrdi3"
7195 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7196 
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7197 
                     (match_operand:SI 2 "reg_or_cint_operand" "")))]
7198 
  "WORDS_BIG_ENDIAN"
7199 
  "
7200 
{
7201 
  if (TARGET_POWERPC64)
7202 
    ;
7203 
  else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7204 
    {
7205 
      emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7206 
      DONE;
7207 
    }
7208 
  else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7209 
           && WORDS_BIG_ENDIAN)
7210 
    {
7211 
      emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7212 
      DONE;
7213 
    }
7214 
  else
7215 
    FAIL;
7216 
}")
7217 
 
7218 
(define_insn "*ashrdi3_internal1"
7219 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7220 
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7221 
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7222 
  "TARGET_POWERPC64"
7223 
  "srad%I2 %0,%1,%H2")
7224 
 
7225 
(define_insn "*ashrdi3_internal2"
7226 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7227 
        (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7228 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7229 
                    (const_int 0)))
7230 
   (clobber (match_scratch:DI 3 "=r,r"))]
7231 
  "TARGET_64BIT"
7232 
  "@
7233 
   srad%I2. %3,%1,%H2
7234 
   #"
7235 
  [(set_attr "type" "delayed_compare")
7236 
   (set_attr "length" "4,8")])
7237 
 
7238 
(define_split
7239 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7240 
        (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7241 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
7242 
                    (const_int 0)))
7243 
   (clobber (match_scratch:DI 3 ""))]
7244 
  "TARGET_POWERPC64 && reload_completed"
7245 
  [(set (match_dup 3)
7246 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))
7247 
   (set (match_dup 0)
7248 
        (compare:CC (match_dup 3)
7249 
                    (const_int 0)))]
7250 
  "")
7251 
 
7252 
(define_insn "*ashrdi3_internal3"
7253 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7254 
        (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7255 
                                 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7256 
                    (const_int 0)))
7257 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7258 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7259 
  "TARGET_64BIT"
7260 
  "@
7261 
   srad%I2. %0,%1,%H2
7262 
   #"
7263 
  [(set_attr "type" "delayed_compare")
7264 
   (set_attr "length" "4,8")])
7265 
 
7266 
(define_split
7267 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7268 
        (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7269 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
7270 
                    (const_int 0)))
7271 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7272 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7273 
  "TARGET_POWERPC64 && reload_completed"
7274 
  [(set (match_dup 0)
7275 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))
7276 
   (set (match_dup 3)
7277 
        (compare:CC (match_dup 0)
7278 
                    (const_int 0)))]
7279 
  "")
7280 
 
7281 
(define_insn "anddi3"
7282 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7283 
        (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7284 
                (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7285 
   (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7286 
  "TARGET_POWERPC64"
7287 
  "@
7288 
   and %0,%1,%2
7289 
   rldic%B2 %0,%1,0,%S2
7290 
   rlwinm %0,%1,0,%m2,%M2
7291 
   andi. %0,%1,%b2
7292 
   andis. %0,%1,%u2
7293 
   #"
7294 
  [(set_attr "type" "*,*,*,compare,compare,*")
7295 
   (set_attr "length" "4,4,4,4,4,8")])
7296 
 
7297 
(define_split
7298 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7299 
        (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7300 
                (match_operand:DI 2 "mask64_2_operand" "")))
7301 
   (clobber (match_scratch:CC 3 ""))]
7302 
  "TARGET_POWERPC64
7303 
    && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7304 
    && !mask_operand (operands[2], DImode)
7305 
    && !mask64_operand (operands[2], DImode)"
7306 
  [(set (match_dup 0)
7307 
        (and:DI (rotate:DI (match_dup 1)
7308 
                           (match_dup 4))
7309 
                (match_dup 5)))
7310 
   (set (match_dup 0)
7311 
        (and:DI (rotate:DI (match_dup 0)
7312 
                           (match_dup 6))
7313 
                (match_dup 7)))]
7314 
{
7315 
  build_mask64_2_operands (operands[2], &operands[4]);
7316 
})
7317 
 
7318 
(define_insn "*anddi3_internal2"
7319 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7320 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7321 
                            (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7322 
                    (const_int 0)))
7323 
   (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7324 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7325 
  "TARGET_64BIT"
7326 
  "@
7327 
   and. %3,%1,%2
7328 
   rldic%B2. %3,%1,0,%S2
7329 
   rlwinm. %3,%1,0,%m2,%M2
7330 
   andi. %3,%1,%b2
7331 
   andis. %3,%1,%u2
7332 
   #
7333 
   #
7334 
   #
7335 
   #
7336 
   #
7337 
   #
7338 
   #"
7339 
  [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7340 
   (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7341 
 
7342 
(define_split
7343 
  [(set (match_operand:CC 0 "cc_reg_operand" "")
7344 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7345 
                            (match_operand:DI 2 "mask64_2_operand" ""))
7346 
                    (const_int 0)))
7347 
   (clobber (match_scratch:DI 3 ""))
7348 
   (clobber (match_scratch:CC 4 ""))]
7349 
  "TARGET_64BIT && reload_completed
7350 
    && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7351 
    && !mask_operand (operands[2], DImode)
7352 
    && !mask64_operand (operands[2], DImode)"
7353 
  [(set (match_dup 3)
7354 
        (and:DI (rotate:DI (match_dup 1)
7355 
                           (match_dup 5))
7356 
                (match_dup 6)))
7357 
   (parallel [(set (match_dup 0)
7358 
                   (compare:CC (and:DI (rotate:DI (match_dup 3)
7359 
                                                  (match_dup 7))
7360 
                                       (match_dup 8))
7361 
                               (const_int 0)))
7362 
              (clobber (match_dup 3))])]
7363 
  "
7364 
{
7365 
  build_mask64_2_operands (operands[2], &operands[5]);
7366 
}")
7367 
 
7368 
(define_insn "*anddi3_internal3"
7369 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7370 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7371 
                            (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7372 
                    (const_int 0)))
7373 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7374 
        (and:DI (match_dup 1) (match_dup 2)))
7375 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7376 
  "TARGET_64BIT"
7377 
  "@
7378 
   and. %0,%1,%2
7379 
   rldic%B2. %0,%1,0,%S2
7380 
   rlwinm. %0,%1,0,%m2,%M2
7381 
   andi. %0,%1,%b2
7382 
   andis. %0,%1,%u2
7383 
   #
7384 
   #
7385 
   #
7386 
   #
7387 
   #
7388 
   #
7389 
   #"
7390 
  [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7391 
   (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7392 
 
7393 
(define_split
7394 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7395 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7396 
                            (match_operand:DI 2 "and64_2_operand" ""))
7397 
                    (const_int 0)))
7398 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7399 
        (and:DI (match_dup 1) (match_dup 2)))
7400 
   (clobber (match_scratch:CC 4 ""))]
7401 
  "TARGET_64BIT && reload_completed"
7402 
  [(parallel [(set (match_dup 0)
7403 
                    (and:DI (match_dup 1) (match_dup 2)))
7404 
               (clobber (match_dup 4))])
7405 
   (set (match_dup 3)
7406 
        (compare:CC (match_dup 0)
7407 
                    (const_int 0)))]
7408 
  "")
7409 
 
7410 
(define_split
7411 
  [(set (match_operand:CC 3 "cc_reg_operand" "")
7412 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7413 
                            (match_operand:DI 2 "mask64_2_operand" ""))
7414 
                    (const_int 0)))
7415 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7416 
        (and:DI (match_dup 1) (match_dup 2)))
7417 
   (clobber (match_scratch:CC 4 ""))]
7418 
  "TARGET_64BIT && reload_completed
7419 
    && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7420 
    && !mask_operand (operands[2], DImode)
7421 
    && !mask64_operand (operands[2], DImode)"
7422 
  [(set (match_dup 0)
7423 
        (and:DI (rotate:DI (match_dup 1)
7424 
                           (match_dup 5))
7425 
                (match_dup 6)))
7426 
   (parallel [(set (match_dup 3)
7427 
                   (compare:CC (and:DI (rotate:DI (match_dup 0)
7428 
                                                  (match_dup 7))
7429 
                                       (match_dup 8))
7430 
                               (const_int 0)))
7431 
              (set (match_dup 0)
7432 
                   (and:DI (rotate:DI (match_dup 0)
7433 
                                      (match_dup 7))
7434 
                           (match_dup 8)))])]
7435 
  "
7436 
{
7437 
  build_mask64_2_operands (operands[2], &operands[5]);
7438 
}")
7439 
 
7440 
(define_expand "iordi3"
7441 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7442 
        (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7443 
                (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7444 
  "TARGET_POWERPC64"
7445 
  "
7446 
{
7447 
  if (non_logical_cint_operand (operands[2], DImode))
7448 
    {
7449 
      HOST_WIDE_INT value;
7450 
      rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7451 
                 ? operands[0] : gen_reg_rtx (DImode));
7452 
 
7453 
      if (GET_CODE (operands[2]) == CONST_INT)
7454 
        {
7455 
          value = INTVAL (operands[2]);
7456 
          emit_insn (gen_iordi3 (tmp, operands[1],
7457 
                                 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7458 
        }
7459 
      else
7460 
        {
7461 
          value = CONST_DOUBLE_LOW (operands[2]);
7462 
          emit_insn (gen_iordi3 (tmp, operands[1],
7463 
                                 immed_double_const (value
7464 
                                                     & (~ (HOST_WIDE_INT) 0xffff),
7465 
                                                     0, DImode)));
7466 
        }
7467 
 
7468 
      emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7469 
      DONE;
7470 
    }
7471 
}")
7472 
 
7473 
(define_expand "xordi3"
7474 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7475 
        (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7476 
                (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7477 
  "TARGET_POWERPC64"
7478 
  "
7479 
{
7480 
  if (non_logical_cint_operand (operands[2], DImode))
7481 
    {
7482 
      HOST_WIDE_INT value;
7483 
      rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7484 
                 ? operands[0] : gen_reg_rtx (DImode));
7485 
 
7486 
      if (GET_CODE (operands[2]) == CONST_INT)
7487 
        {
7488 
          value = INTVAL (operands[2]);
7489 
          emit_insn (gen_xordi3 (tmp, operands[1],
7490 
                                 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7491 
        }
7492 
      else
7493 
        {
7494 
          value = CONST_DOUBLE_LOW (operands[2]);
7495 
          emit_insn (gen_xordi3 (tmp, operands[1],
7496 
                                 immed_double_const (value
7497 
                                                     & (~ (HOST_WIDE_INT) 0xffff),
7498 
                                                     0, DImode)));
7499 
        }
7500 
 
7501 
      emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7502 
      DONE;
7503 
    }
7504 
}")
7505 
 
7506 
(define_insn "*booldi3_internal1"
7507 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7508 
        (match_operator:DI 3 "boolean_or_operator"
7509 
         [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7510 
          (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7511 
  "TARGET_POWERPC64"
7512 
  "@
7513 
   %q3 %0,%1,%2
7514 
   %q3i %0,%1,%b2
7515 
   %q3is %0,%1,%u2")
7516 
 
7517 
(define_insn "*booldi3_internal2"
7518 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7519 
        (compare:CC (match_operator:DI 4 "boolean_or_operator"
7520 
         [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7521 
          (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7522 
         (const_int 0)))
7523 
   (clobber (match_scratch:DI 3 "=r,r"))]
7524 
  "TARGET_64BIT"
7525 
  "@
7526 
   %q4. %3,%1,%2
7527 
   #"
7528 
  [(set_attr "type" "compare")
7529 
   (set_attr "length" "4,8")])
7530 
 
7531 
(define_split
7532 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7533 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7534 
         [(match_operand:DI 1 "gpc_reg_operand" "")
7535 
          (match_operand:DI 2 "gpc_reg_operand" "")])
7536 
         (const_int 0)))
7537 
   (clobber (match_scratch:DI 3 ""))]
7538 
  "TARGET_POWERPC64 && reload_completed"
7539 
  [(set (match_dup 3) (match_dup 4))
7540 
   (set (match_dup 0)
7541 
        (compare:CC (match_dup 3)
7542 
                    (const_int 0)))]
7543 
  "")
7544 
 
7545 
(define_insn "*booldi3_internal3"
7546 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7547 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7548 
         [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7549 
          (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7550 
         (const_int 0)))
7551 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7552 
        (match_dup 4))]
7553 
  "TARGET_64BIT"
7554 
  "@
7555 
   %q4. %0,%1,%2
7556 
   #"
7557 
  [(set_attr "type" "compare")
7558 
   (set_attr "length" "4,8")])
7559 
 
7560 
(define_split
7561 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7562 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7563 
         [(match_operand:DI 1 "gpc_reg_operand" "")
7564 
          (match_operand:DI 2 "gpc_reg_operand" "")])
7565 
         (const_int 0)))
7566 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7567 
        (match_dup 4))]
7568 
  "TARGET_POWERPC64 && reload_completed"
7569 
  [(set (match_dup 0) (match_dup 4))
7570 
   (set (match_dup 3)
7571 
        (compare:CC (match_dup 0)
7572 
                    (const_int 0)))]
7573 
  "")
7574 
 
7575 
;; Split a logical operation that we can't do in one insn into two insns,
7576 
;; each of which does one 16-bit part.  This is used by combine.
7577 
 
7578 
(define_split
7579 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7580 
        (match_operator:DI 3 "boolean_or_operator"
7581 
         [(match_operand:DI 1 "gpc_reg_operand" "")
7582 
          (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7583 
  "TARGET_POWERPC64"
7584 
  [(set (match_dup 0) (match_dup 4))
7585 
   (set (match_dup 0) (match_dup 5))]
7586 
"
7587 
{
7588 
  rtx i3,i4;
7589 
 
7590 
  if (GET_CODE (operands[2]) == CONST_DOUBLE)
7591 
    {
7592 
      HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7593 
      i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7594 
                                        0, DImode);
7595 
      i4 = GEN_INT (value & 0xffff);
7596 
    }
7597 
  else
7598 
    {
7599 
      i3 = GEN_INT (INTVAL (operands[2])
7600 
                             & (~ (HOST_WIDE_INT) 0xffff));
7601 
      i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7602 
    }
7603 
  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7604 
                                operands[1], i3);
7605 
  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7606 
                                operands[0], i4);
7607 
}")
7608 
 
7609 
(define_insn "*boolcdi3_internal1"
7610 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7611 
        (match_operator:DI 3 "boolean_operator"
7612 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7613 
          (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7614 
  "TARGET_POWERPC64"
7615 
  "%q3 %0,%2,%1")
7616 
 
7617 
(define_insn "*boolcdi3_internal2"
7618 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7619 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7620 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7621 
          (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7622 
         (const_int 0)))
7623 
   (clobber (match_scratch:DI 3 "=r,r"))]
7624 
  "TARGET_64BIT"
7625 
  "@
7626 
   %q4. %3,%2,%1
7627 
   #"
7628 
  [(set_attr "type" "compare")
7629 
   (set_attr "length" "4,8")])
7630 
 
7631 
(define_split
7632 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7633 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7634 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7635 
          (match_operand:DI 2 "gpc_reg_operand" "")])
7636 
         (const_int 0)))
7637 
   (clobber (match_scratch:DI 3 ""))]
7638 
  "TARGET_POWERPC64 && reload_completed"
7639 
  [(set (match_dup 3) (match_dup 4))
7640 
   (set (match_dup 0)
7641 
        (compare:CC (match_dup 3)
7642 
                    (const_int 0)))]
7643 
  "")
7644 
 
7645 
(define_insn "*boolcdi3_internal3"
7646 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7647 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7648 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7649 
          (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7650 
         (const_int 0)))
7651 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7652 
        (match_dup 4))]
7653 
  "TARGET_64BIT"
7654 
  "@
7655 
   %q4. %0,%2,%1
7656 
   #"
7657 
  [(set_attr "type" "compare")
7658 
   (set_attr "length" "4,8")])
7659 
 
7660 
(define_split
7661 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7662 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7663 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7664 
          (match_operand:DI 2 "gpc_reg_operand" "")])
7665 
         (const_int 0)))
7666 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7667 
        (match_dup 4))]
7668 
  "TARGET_POWERPC64 && reload_completed"
7669 
  [(set (match_dup 0) (match_dup 4))
7670 
   (set (match_dup 3)
7671 
        (compare:CC (match_dup 0)
7672 
                    (const_int 0)))]
7673 
  "")
7674 
 
7675 
(define_insn "*boolccdi3_internal1"
7676 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7677 
        (match_operator:DI 3 "boolean_operator"
7678 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7679 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7680 
  "TARGET_POWERPC64"
7681 
  "%q3 %0,%1,%2")
7682 
 
7683 
(define_insn "*boolccdi3_internal2"
7684 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7685 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7686 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7687 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7688 
         (const_int 0)))
7689 
   (clobber (match_scratch:DI 3 "=r,r"))]
7690 
  "TARGET_64BIT"
7691 
  "@
7692 
   %q4. %3,%1,%2
7693 
   #"
7694 
  [(set_attr "type" "compare")
7695 
   (set_attr "length" "4,8")])
7696 
 
7697 
(define_split
7698 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7699 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7700 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7701 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7702 
         (const_int 0)))
7703 
   (clobber (match_scratch:DI 3 ""))]
7704 
  "TARGET_POWERPC64 && reload_completed"
7705 
  [(set (match_dup 3) (match_dup 4))
7706 
   (set (match_dup 0)
7707 
        (compare:CC (match_dup 3)
7708 
                    (const_int 0)))]
7709 
  "")
7710 
 
7711 
(define_insn "*boolccdi3_internal3"
7712 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7713 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7714 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7715 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7716 
         (const_int 0)))
7717 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7718 
        (match_dup 4))]
7719 
  "TARGET_64BIT"
7720 
  "@
7721 
   %q4. %0,%1,%2
7722 
   #"
7723 
  [(set_attr "type" "compare")
7724 
   (set_attr "length" "4,8")])
7725 
 
7726 
(define_split
7727 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7728 
        (compare:CC (match_operator:DI 4 "boolean_operator"
7729 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7730 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7731 
         (const_int 0)))
7732 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7733 
        (match_dup 4))]
7734 
  "TARGET_POWERPC64 && reload_completed"
7735 
  [(set (match_dup 0) (match_dup 4))
7736 
   (set (match_dup 3)
7737 
        (compare:CC (match_dup 0)
7738 
                    (const_int 0)))]
7739 
  "")
7740 
 
7741 
;; Now define ways of moving data around.
7742 
 
7743 
;; Set up a register with a value from the GOT table
7744 
 
7745 
(define_expand "movsi_got"
7746 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
7747 
        (unspec:SI [(match_operand:SI 1 "got_operand" "")
7748 
                    (match_dup 2)] UNSPEC_MOVSI_GOT))]
7749 
  "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7750 
  "
7751 
{
7752 
  if (GET_CODE (operands[1]) == CONST)
7753 
    {
7754 
      rtx offset = const0_rtx;
7755 
      HOST_WIDE_INT value;
7756 
 
7757 
      operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7758 
      value = INTVAL (offset);
7759 
      if (value != 0)
7760 
        {
7761 
          rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7762 
          emit_insn (gen_movsi_got (tmp, operands[1]));
7763 
          emit_insn (gen_addsi3 (operands[0], tmp, offset));
7764 
          DONE;
7765 
        }
7766 
    }
7767 
 
7768 
  operands[2] = rs6000_got_register (operands[1]);
7769 
}")
7770 
 
7771 
(define_insn "*movsi_got_internal"
7772 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7773 
        (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7774 
                    (match_operand:SI 2 "gpc_reg_operand" "b")]
7775 
                   UNSPEC_MOVSI_GOT))]
7776 
  "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7777 
  "{l|lwz} %0,%a1@got(%2)"
7778 
  [(set_attr "type" "load")])
7779 
 
7780 
;; Used by sched, shorten_branches and final when the GOT pseudo reg
7781 
;; didn't get allocated to a hard register.
7782 
(define_split
7783 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
7784 
        (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7785 
                    (match_operand:SI 2 "memory_operand" "")]
7786 
                   UNSPEC_MOVSI_GOT))]
7787 
  "DEFAULT_ABI == ABI_V4
7788 
    && flag_pic == 1
7789 
    && (reload_in_progress || reload_completed)"
7790 
  [(set (match_dup 0) (match_dup 2))
7791 
   (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7792 
                                 UNSPEC_MOVSI_GOT))]
7793 
  "")
7794 
 
7795 
;; For SI, we special-case integers that can't be loaded in one insn.  We
7796 
;; do the load 16-bits at a time.  We could do this by loading from memory,
7797 
;; and this is even supposed to be faster, but it is simpler not to get
7798 
;; integers in the TOC.
7799 
(define_insn "movsi_low"
7800 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7801 
        (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7802 
                           (match_operand 2 "" ""))))]
7803 
  "TARGET_MACHO && ! TARGET_64BIT"
7804 
  "{l|lwz} %0,lo16(%2)(%1)"
7805 
  [(set_attr "type" "load")
7806 
   (set_attr "length" "4")])
7807 
 
7808 
(define_insn "*movsi_internal1"
7809 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7810 
        (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7811 
  "gpc_reg_operand (operands[0], SImode)
7812 
   || gpc_reg_operand (operands[1], SImode)"
7813 
  "@
7814 
   mr %0,%1
7815 
   {cal|la} %0,%a1
7816 
   {l%U1%X1|lwz%U1%X1} %0,%1
7817 
   {st%U0%X0|stw%U0%X0} %1,%0
7818 
   {lil|li} %0,%1
7819 
   {liu|lis} %0,%v1
7820 
   #
7821 
   {cal|la} %0,%a1
7822 
   mf%1 %0
7823 
   mt%0 %1
7824 
   mt%0 %1
7825 
   mt%0 %1
7826 
   {cror 0,0,0|nop}"
7827 
  [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7828 
   (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7829 
 
7830 
;; Split a load of a large constant into the appropriate two-insn
7831 
;; sequence.
7832 
 
7833 
(define_split
7834 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
7835 
        (match_operand:SI 1 "const_int_operand" ""))]
7836 
  "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7837 
   && (INTVAL (operands[1]) & 0xffff) != 0"
7838 
  [(set (match_dup 0)
7839 
        (match_dup 2))
7840 
   (set (match_dup 0)
7841 
        (ior:SI (match_dup 0)
7842 
                (match_dup 3)))]
7843 
  "
7844 
{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7845 
 
7846 
  if (tem == operands[0])
7847 
    DONE;
7848 
  else
7849 
    FAIL;
7850 
}")
7851 
 
7852 
(define_insn "*mov_internal2"
7853 
  [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7854 
        (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7855 
                    (const_int 0)))
7856 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7857 
  ""
7858 
  "@
7859 
   {cmpi|cmpi} %2,%0,0
7860 
   mr. %0,%1
7861 
   #"
7862 
  [(set_attr "type" "cmp,compare,cmp")
7863 
   (set_attr "length" "4,4,8")])
7864 
 
7865 
(define_split
7866 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7867 
        (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7868 
                    (const_int 0)))
7869 
   (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7870 
  "reload_completed"
7871 
  [(set (match_dup 0) (match_dup 1))
7872 
   (set (match_dup 2)
7873 
        (compare:CC (match_dup 0)
7874 
                    (const_int 0)))]
7875 
  "")
7876 
 
7877 
(define_insn "*movhi_internal"
7878 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7879 
        (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7880 
  "gpc_reg_operand (operands[0], HImode)
7881 
   || gpc_reg_operand (operands[1], HImode)"
7882 
  "@
7883 
   mr %0,%1
7884 
   lhz%U1%X1 %0,%1
7885 
   sth%U0%X0 %1,%0
7886 
   {lil|li} %0,%w1
7887 
   mf%1 %0
7888 
   mt%0 %1
7889 
   mt%0 %1
7890 
   {cror 0,0,0|nop}"
7891 
  [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7892 
 
7893 
(define_expand "mov"
7894 
  [(set (match_operand:INT 0 "general_operand" "")
7895 
        (match_operand:INT 1 "any_operand" ""))]
7896 
  ""
7897 
  "{ rs6000_emit_move (operands[0], operands[1], mode); DONE; }")
7898 
 
7899 
(define_insn "*movqi_internal"
7900 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7901 
        (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7902 
  "gpc_reg_operand (operands[0], QImode)
7903 
   || gpc_reg_operand (operands[1], QImode)"
7904 
  "@
7905 
   mr %0,%1
7906 
   lbz%U1%X1 %0,%1
7907 
   stb%U0%X0 %1,%0
7908 
   {lil|li} %0,%1
7909 
   mf%1 %0
7910 
   mt%0 %1
7911 
   mt%0 %1
7912 
   {cror 0,0,0|nop}"
7913 
  [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7914 
 
7915 
;; Here is how to move condition codes around.  When we store CC data in
7916 
;; an integer register or memory, we store just the high-order 4 bits.
7917 
;; This lets us not shift in the most common case of CR0.
7918 
(define_expand "movcc"
7919 
  [(set (match_operand:CC 0 "nonimmediate_operand" "")
7920 
        (match_operand:CC 1 "nonimmediate_operand" ""))]
7921 
  ""
7922 
  "")
7923 
 
7924 
(define_insn "*movcc_internal1"
7925 
  [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
7926 
        (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
7927 
  "register_operand (operands[0], CCmode)
7928 
   || register_operand (operands[1], CCmode)"
7929 
  "@
7930 
   mcrf %0,%1
7931 
   mtcrf 128,%1
7932 
   {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7933 
   crxor %0,%0,%0
7934 
   mfcr %0%Q1
7935 
   mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7936 
   mr %0,%1
7937 
   {lil|li} %0,%1
7938 
   mf%1 %0
7939 
   mt%0 %1
7940 
   mt%0 %1
7941 
   {l%U1%X1|lwz%U1%X1} %0,%1
7942 
   {st%U0%U1|stw%U0%U1} %1,%0"
7943 
  [(set (attr "type")
7944 
     (cond [(eq_attr "alternative" "0,3")
7945 
                (const_string "cr_logical")
7946 
            (eq_attr "alternative" "1,2")
7947 
                (const_string "mtcr")
7948 
            (eq_attr "alternative" "6,7,9")
7949 
                (const_string "integer")
7950 
            (eq_attr "alternative" "8")
7951 
                (const_string "mfjmpr")
7952 
            (eq_attr "alternative" "10")
7953 
                (const_string "mtjmpr")
7954 
            (eq_attr "alternative" "11")
7955 
                (const_string "load")
7956 
            (eq_attr "alternative" "12")
7957 
                (const_string "store")
7958 
            (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7959 
                (const_string "mfcrf")
7960 
           ]
7961 
        (const_string "mfcr")))
7962 
   (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
7963 
 
7964 
;; For floating-point, we normally deal with the floating-point registers
7965 
;; unless -msoft-float is used.  The sole exception is that parameter passing
7966 
;; can produce floating-point values in fixed-point registers.  Unless the
7967 
;; value is a simple constant or already in memory, we deal with this by
7968 
;; allocating memory and copying the value explicitly via that memory location.
7969 
(define_expand "movsf"
7970 
  [(set (match_operand:SF 0 "nonimmediate_operand" "")
7971 
        (match_operand:SF 1 "any_operand" ""))]
7972 
  ""
7973 
  "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7974 
 
7975 
(define_split
7976 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
7977 
        (match_operand:SF 1 "const_double_operand" ""))]
7978 
  "reload_completed
7979 
   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7980 
       || (GET_CODE (operands[0]) == SUBREG
7981 
           && GET_CODE (SUBREG_REG (operands[0])) == REG
7982 
           && REGNO (SUBREG_REG (operands[0])) <= 31))"
7983 
  [(set (match_dup 2) (match_dup 3))]
7984 
  "
7985 
{
7986 
  long l;
7987 
  REAL_VALUE_TYPE rv;
7988 
 
7989 
  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7990 
  REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7991 
 
7992 
  if (! TARGET_POWERPC64)
7993 
    operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7994 
  else
7995 
    operands[2] = gen_lowpart (SImode, operands[0]);
7996 
 
7997 
  operands[3] = gen_int_mode (l, SImode);
7998 
}")
7999 
 
8000 
(define_insn "*movsf_hardfloat"
8001 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8002 
        (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8003 
  "(gpc_reg_operand (operands[0], SFmode)
8004 
   || gpc_reg_operand (operands[1], SFmode))
8005 
   && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8006 
  "@
8007 
   mr %0,%1
8008 
   {l%U1%X1|lwz%U1%X1} %0,%1
8009 
   {st%U0%X0|stw%U0%X0} %1,%0
8010 
   fmr %0,%1
8011 
   lfs%U1%X1 %0,%1
8012 
   stfs%U0%X0 %1,%0
8013 
   mt%0 %1
8014 
   mt%0 %1
8015 
   mf%1 %0
8016 
   {cror 0,0,0|nop}
8017 
   #
8018 
   #"
8019 
  [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8020 
   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8021 
 
8022 
(define_insn "*movsf_softfloat"
8023 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8024 
        (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8025 
  "(gpc_reg_operand (operands[0], SFmode)
8026 
   || gpc_reg_operand (operands[1], SFmode))
8027 
   && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8028 
  "@
8029 
   mr %0,%1
8030 
   mt%0 %1
8031 
   mt%0 %1
8032 
   mf%1 %0
8033 
   {l%U1%X1|lwz%U1%X1} %0,%1
8034 
   {st%U0%X0|stw%U0%X0} %1,%0
8035 
   {lil|li} %0,%1
8036 
   {liu|lis} %0,%v1
8037 
   {cal|la} %0,%a1
8038 
   #
8039 
   #
8040 
   {cror 0,0,0|nop}"
8041 
  [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8042 
   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8043 
 
8044 
 
8045 
(define_expand "movdf"
8046 
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
8047 
        (match_operand:DF 1 "any_operand" ""))]
8048 
  ""
8049 
  "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8050 
 
8051 
(define_split
8052 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
8053 
        (match_operand:DF 1 "const_int_operand" ""))]
8054 
  "! TARGET_POWERPC64 && reload_completed
8055 
   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8056 
       || (GET_CODE (operands[0]) == SUBREG
8057 
           && GET_CODE (SUBREG_REG (operands[0])) == REG
8058 
           && REGNO (SUBREG_REG (operands[0])) <= 31))"
8059 
  [(set (match_dup 2) (match_dup 4))
8060 
   (set (match_dup 3) (match_dup 1))]
8061 
  "
8062 
{
8063 
  int endian = (WORDS_BIG_ENDIAN == 0);
8064 
  HOST_WIDE_INT value = INTVAL (operands[1]);
8065 
 
8066 
  operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8067 
  operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8068 
#if HOST_BITS_PER_WIDE_INT == 32
8069 
  operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8070 
#else
8071 
  operands[4] = GEN_INT (value >> 32);
8072 
  operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8073 
#endif
8074 
}")
8075 
 
8076 
(define_split
8077 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
8078 
        (match_operand:DF 1 "const_double_operand" ""))]
8079 
  "! TARGET_POWERPC64 && reload_completed
8080 
   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8081 
       || (GET_CODE (operands[0]) == SUBREG
8082 
           && GET_CODE (SUBREG_REG (operands[0])) == REG
8083 
           && REGNO (SUBREG_REG (operands[0])) <= 31))"
8084 
  [(set (match_dup 2) (match_dup 4))
8085 
   (set (match_dup 3) (match_dup 5))]
8086 
  "
8087 
{
8088 
  int endian = (WORDS_BIG_ENDIAN == 0);
8089 
  long l[2];
8090 
  REAL_VALUE_TYPE rv;
8091 
 
8092 
  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8093 
  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8094 
 
8095 
  operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8096 
  operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8097 
  operands[4] = gen_int_mode (l[endian], SImode);
8098 
  operands[5] = gen_int_mode (l[1 - endian], SImode);
8099 
}")
8100 
 
8101 
(define_split
8102 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
8103 
        (match_operand:DF 1 "const_double_operand" ""))]
8104 
  "TARGET_POWERPC64 && reload_completed
8105 
   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8106 
       || (GET_CODE (operands[0]) == SUBREG
8107 
           && GET_CODE (SUBREG_REG (operands[0])) == REG
8108 
           && REGNO (SUBREG_REG (operands[0])) <= 31))"
8109 
  [(set (match_dup 2) (match_dup 3))]
8110 
  "
8111 
{
8112 
  int endian = (WORDS_BIG_ENDIAN == 0);
8113 
  long l[2];
8114 
  REAL_VALUE_TYPE rv;
8115 
#if HOST_BITS_PER_WIDE_INT >= 64
8116 
  HOST_WIDE_INT val;
8117 
#endif
8118 
 
8119 
  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8120 
  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8121 
 
8122 
  operands[2] = gen_lowpart (DImode, operands[0]);
8123 
  /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN.  */
8124 
#if HOST_BITS_PER_WIDE_INT >= 64
8125 
  val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8126 
         | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8127 
 
8128 
  operands[3] = gen_int_mode (val, DImode);
8129 
#else
8130 
  operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8131 
#endif
8132 
}")
8133 
 
8134 
;; Don't have reload use general registers to load a constant.  First,
8135 
;; it might not work if the output operand is the equivalent of
8136 
;; a non-offsettable memref, but also it is less efficient than loading
8137 
;; the constant into an FP register, since it will probably be used there.
8138 
;; The "??" is a kludge until we can figure out a more reasonable way
8139 
;; of handling these non-offsettable values.
8140 
(define_insn "*movdf_hardfloat32"
8141 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8142 
        (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8143 
  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8144 
   && (gpc_reg_operand (operands[0], DFmode)
8145 
       || gpc_reg_operand (operands[1], DFmode))"
8146 
  "*
8147 
{
8148 
  switch (which_alternative)
8149 
    {
8150 
    default:
8151 
      gcc_unreachable ();
8152 
    case 0:
8153 
      /* We normally copy the low-numbered register first.  However, if
8154 
         the first register operand 0 is the same as the second register
8155 
         of operand 1, we must copy in the opposite order.  */
8156 
      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8157 
        return \"mr %L0,%L1\;mr %0,%1\";
8158 
      else
8159 
        return \"mr %0,%1\;mr %L0,%L1\";
8160 
    case 1:
8161 
      if (rs6000_offsettable_memref_p (operands[1])
8162 
          || (GET_CODE (operands[1]) == MEM
8163 
              && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8164 
                  || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8165 
                  || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8166 
        {
8167 
          /* If the low-address word is used in the address, we must load
8168 
             it last.  Otherwise, load it first.  Note that we cannot have
8169 
             auto-increment in that case since the address register is
8170 
             known to be dead.  */
8171 
          if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8172 
                                 operands[1], 0))
8173 
            return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8174 
          else
8175 
            return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8176 
        }
8177 
      else
8178 
        {
8179 
          rtx addreg;
8180 
 
8181 
          addreg = find_addr_reg (XEXP (operands[1], 0));
8182 
          if (refers_to_regno_p (REGNO (operands[0]),
8183 
                                 REGNO (operands[0]) + 1,
8184 
                                 operands[1], 0))
8185 
            {
8186 
              output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8187 
              output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8188 
              output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8189 
              return \"{lx|lwzx} %0,%1\";
8190 
            }
8191 
          else
8192 
            {
8193 
              output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8194 
              output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8195 
              output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8196 
              output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8197 
              return \"\";
8198 
            }
8199 
        }
8200 
    case 2:
8201 
      if (rs6000_offsettable_memref_p (operands[0])
8202 
          || (GET_CODE (operands[0]) == MEM
8203 
              && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8204 
                  || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8205 
                  || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8206 
        return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8207 
      else
8208 
        {
8209 
          rtx addreg;
8210 
 
8211 
          addreg = find_addr_reg (XEXP (operands[0], 0));
8212 
          output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8213 
          output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8214 
          output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8215 
          output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8216 
          return \"\";
8217 
        }
8218 
    case 3:
8219 
      return \"fmr %0,%1\";
8220 
    case 4:
8221 
      return \"lfd%U1%X1 %0,%1\";
8222 
    case 5:
8223 
      return \"stfd%U0%X0 %1,%0\";
8224 
    case 6:
8225 
    case 7:
8226 
    case 8:
8227 
      return \"#\";
8228 
    }
8229 
}"
8230 
  [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8231 
   (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8232 
 
8233 
(define_insn "*movdf_softfloat32"
8234 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8235 
        (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8236 
  "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8237 
   && (gpc_reg_operand (operands[0], DFmode)
8238 
       || gpc_reg_operand (operands[1], DFmode))"
8239 
  "*
8240 
{
8241 
  switch (which_alternative)
8242 
    {
8243 
    default:
8244 
      gcc_unreachable ();
8245 
    case 0:
8246 
      /* We normally copy the low-numbered register first.  However, if
8247 
         the first register operand 0 is the same as the second register of
8248 
         operand 1, we must copy in the opposite order.  */
8249 
      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8250 
        return \"mr %L0,%L1\;mr %0,%1\";
8251 
      else
8252 
        return \"mr %0,%1\;mr %L0,%L1\";
8253 
    case 1:
8254 
      /* If the low-address word is used in the address, we must load
8255 
         it last.  Otherwise, load it first.  Note that we cannot have
8256 
         auto-increment in that case since the address register is
8257 
         known to be dead.  */
8258 
      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8259 
                             operands[1], 0))
8260 
        return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8261 
      else
8262 
        return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8263 
    case 2:
8264 
      return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8265 
    case 3:
8266 
    case 4:
8267 
    case 5:
8268 
      return \"#\";
8269 
    }
8270 
}"
8271 
  [(set_attr "type" "two,load,store,*,*,*")
8272 
   (set_attr "length" "8,8,8,8,12,16")])
8273 
 
8274 
; ld/std require word-aligned displacements -> 'Y' constraint.
8275 
; List Y->r and r->Y before r->r for reload.
8276 
(define_insn "*movdf_hardfloat64"
8277 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8278 
        (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8279 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8280 
   && (gpc_reg_operand (operands[0], DFmode)
8281 
       || gpc_reg_operand (operands[1], DFmode))"
8282 
  "@
8283 
   std%U0%X0 %1,%0
8284 
   ld%U1%X1 %0,%1
8285 
   mr %0,%1
8286 
   fmr %0,%1
8287 
   lfd%U1%X1 %0,%1
8288 
   stfd%U0%X0 %1,%0
8289 
   mt%0 %1
8290 
   mf%1 %0
8291 
   {cror 0,0,0|nop}
8292 
   #
8293 
   #
8294 
   #"
8295 
  [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8296 
   (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8297 
 
8298 
(define_insn "*movdf_softfloat64"
8299 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8300 
        (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8301 
  "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8302 
   && (gpc_reg_operand (operands[0], DFmode)
8303 
       || gpc_reg_operand (operands[1], DFmode))"
8304 
  "@
8305 
   ld%U1%X1 %0,%1
8306 
   std%U0%X0 %1,%0
8307 
   mr %0,%1
8308 
   mt%0 %1
8309 
   mf%1 %0
8310 
   #
8311 
   #
8312 
   #
8313 
   {cror 0,0,0|nop}"
8314 
  [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8315 
   (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8316 
 
8317 
(define_expand "movtf"
8318 
  [(set (match_operand:TF 0 "general_operand" "")
8319 
        (match_operand:TF 1 "any_operand" ""))]
8320 
  "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8321 
  "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8322 
 
8323 
; It's important to list the o->f and f->o moves before f->f because
8324 
; otherwise reload, given m->f, will try to pick f->f and reload it,
8325 
; which doesn't make progress.  Likewise r->Y must be before r->r.
8326 
(define_insn_and_split "*movtf_internal"
8327 
  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8328 
        (match_operand:TF 1 "input_operand"         "f,o,f,YGHF,r,r"))]
8329 
  "!TARGET_IEEEQUAD
8330 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8331 
   && (gpc_reg_operand (operands[0], TFmode)
8332 
       || gpc_reg_operand (operands[1], TFmode))"
8333 
  "#"
8334 
  "&& reload_completed"
8335 
  [(pc)]
8336 
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8337 
  [(set_attr "length" "8,8,8,20,20,16")])
8338 
 
8339 
(define_insn_and_split "*movtf_softfloat"
8340 
  [(set (match_operand:TF 0 "nonimmediate_operand" "=r,Y,r")
8341 
        (match_operand:TF 1 "input_operand"         "YGHF,r,r"))]
8342 
  "!TARGET_IEEEQUAD
8343 
   && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8344 
   && (gpc_reg_operand (operands[0], TFmode)
8345 
       || gpc_reg_operand (operands[1], TFmode))"
8346 
  "#"
8347 
  "&& reload_completed"
8348 
  [(pc)]
8349 
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8350 
  [(set_attr "length" "20,20,16")])
8351 
 
8352 
(define_expand "extenddftf2"
8353 
  [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8354 
                   (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8355 
              (use (match_dup 2))])]
8356 
  "!TARGET_IEEEQUAD
8357 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8358 
{
8359 
  operands[2] = CONST0_RTX (DFmode);
8360 
  /* Generate GOT reference early for SVR4 PIC.  */
8361 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
8362 
    operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8363 
})
8364 
 
8365 
(define_insn_and_split "*extenddftf2_internal"
8366 
  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8367 
       (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8368 
   (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8369 
  "!TARGET_IEEEQUAD
8370 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8371 
  "#"
8372 
  "&& reload_completed"
8373 
  [(pc)]
8374 
{
8375 
  const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8376 
  const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8377 
  emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8378 
                  operands[1]);
8379 
  emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8380 
                  operands[2]);
8381 
  DONE;
8382 
})
8383 
 
8384 
(define_expand "extendsftf2"
8385 
  [(set (match_operand:TF 0 "nonimmediate_operand" "")
8386 
        (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8387 
  "!TARGET_IEEEQUAD
8388 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8389 
{
8390 
  rtx tmp = gen_reg_rtx (DFmode);
8391 
  emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8392 
  emit_insn (gen_extenddftf2 (operands[0], tmp));
8393 
  DONE;
8394 
})
8395 
 
8396 
(define_expand "trunctfdf2"
8397 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
8398 
        (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8399 
  "!TARGET_IEEEQUAD
8400 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8401 
  "")
8402 
 
8403 
(define_insn_and_split "trunctfdf2_internal1"
8404 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8405 
        (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8406 
  "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8407 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8408 
  "@
8409 
   #
8410 
   fmr %0,%1"
8411 
  "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8412 
  [(const_int 0)]
8413 
{
8414 
  emit_note (NOTE_INSN_DELETED);
8415 
  DONE;
8416 
}
8417 
  [(set_attr "type" "fp")])
8418 
 
8419 
(define_insn "trunctfdf2_internal2"
8420 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8421 
        (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8422 
  "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8423 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8424 
  "fadd %0,%1,%L1"
8425 
  [(set_attr "type" "fp")])
8426 
 
8427 
(define_insn_and_split "trunctfsf2"
8428 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8429 
        (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8430 
   (clobber (match_scratch:DF 2 "=f"))]
8431 
  "!TARGET_IEEEQUAD
8432 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8433 
  "#"
8434 
  "&& reload_completed"
8435 
  [(set (match_dup 2)
8436 
        (float_truncate:DF (match_dup 1)))
8437 
   (set (match_dup 0)
8438 
        (float_truncate:SF (match_dup 2)))]
8439 
  "")
8440 
 
8441 
(define_expand "floatsitf2"
8442 
  [(set (match_operand:TF 0 "gpc_reg_operand" "")
8443 
        (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8444 
  "!TARGET_IEEEQUAD
8445 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8446 
{
8447 
  rtx tmp = gen_reg_rtx (DFmode);
8448 
  expand_float (tmp, operands[1], false);
8449 
  emit_insn (gen_extenddftf2 (operands[0], tmp));
8450 
  DONE;
8451 
})
8452 
 
8453 
; fadd, but rounding towards zero.
8454 
; This is probably not the optimal code sequence.
8455 
(define_insn "fix_trunc_helper"
8456 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8457 
        (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8458 
                   UNSPEC_FIX_TRUNC_TF))
8459 
   (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8460 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
8461 
  "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8462 
  [(set_attr "type" "fp")
8463 
   (set_attr "length" "20")])
8464 
 
8465 
(define_expand "fix_trunctfsi2"
8466 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8467 
                   (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8468 
              (clobber (match_dup 2))
8469 
              (clobber (match_dup 3))
8470 
              (clobber (match_dup 4))
8471 
              (clobber (match_dup 5))])]
8472 
  "!TARGET_IEEEQUAD
8473 
   && (TARGET_POWER2 || TARGET_POWERPC)
8474 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8475 
{
8476 
  operands[2] = gen_reg_rtx (DFmode);
8477 
  operands[3] = gen_reg_rtx (DFmode);
8478 
  operands[4] = gen_reg_rtx (DImode);
8479 
  operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8480 
})
8481 
 
8482 
(define_insn_and_split "*fix_trunctfsi2_internal"
8483 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8484 
        (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8485 
   (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8486 
   (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8487 
   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8488 
   (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8489 
  "!TARGET_IEEEQUAD
8490 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8491 
  "#"
8492 
  "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8493 
  [(pc)]
8494 
{
8495 
  rtx lowword;
8496 
  emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8497 
 
8498 
  gcc_assert (MEM_P (operands[5]));
8499 
  lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8500 
 
8501 
  emit_insn (gen_fctiwz (operands[4], operands[2]));
8502 
  emit_move_insn (operands[5], operands[4]);
8503 
  emit_move_insn (operands[0], lowword);
8504 
  DONE;
8505 
})
8506 
 
8507 
(define_insn "negtf2"
8508 
  [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8509 
        (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8510 
  "!TARGET_IEEEQUAD
8511 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8512 
  "*
8513 
{
8514 
  if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8515 
    return \"fneg %L0,%L1\;fneg %0,%1\";
8516 
  else
8517 
    return \"fneg %0,%1\;fneg %L0,%L1\";
8518 
}"
8519 
  [(set_attr "type" "fp")
8520 
   (set_attr "length" "8")])
8521 
 
8522 
(define_expand "abstf2"
8523 
  [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8524 
        (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8525 
  "!TARGET_IEEEQUAD
8526 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8527 
  "
8528 
{
8529 
  rtx label = gen_label_rtx ();
8530 
  emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8531 
  emit_label (label);
8532 
  DONE;
8533 
}")
8534 
 
8535 
(define_expand "abstf2_internal"
8536 
  [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8537 
        (match_operand:TF 1 "gpc_reg_operand" "f"))
8538 
   (set (match_dup 3) (match_dup 5))
8539 
   (set (match_dup 5) (abs:DF (match_dup 5)))
8540 
   (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8541 
   (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8542 
                           (label_ref (match_operand 2 "" ""))
8543 
                           (pc)))
8544 
   (set (match_dup 6) (neg:DF (match_dup 6)))]
8545 
  "!TARGET_IEEEQUAD
8546 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8547 
  "
8548 
{
8549 
  const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8550 
  const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8551 
  operands[3] = gen_reg_rtx (DFmode);
8552 
  operands[4] = gen_reg_rtx (CCFPmode);
8553 
  operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8554 
  operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8555 
}")
8556 
 
8557 
;; Next come the multi-word integer load and store and the load and store
8558 
;; multiple insns.
8559 
 
8560 
; List r->r after r->"o<>", otherwise reload will try to reload a
8561 
; non-offsettable address by using r->r which won't make progress.
8562 
(define_insn "*movdi_internal32"
8563 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8564 
        (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8565 
  "! TARGET_POWERPC64
8566 
   && (gpc_reg_operand (operands[0], DImode)
8567 
       || gpc_reg_operand (operands[1], DImode))"
8568 
  "@
8569 
   #
8570 
   #
8571 
   #
8572 
   fmr %0,%1
8573 
   lfd%U1%X1 %0,%1
8574 
   stfd%U0%X0 %1,%0
8575 
   #"
8576 
  [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8577 
 
8578 
(define_split
8579 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8580 
        (match_operand:DI 1 "const_int_operand" ""))]
8581 
  "! TARGET_POWERPC64 && reload_completed"
8582 
  [(set (match_dup 2) (match_dup 4))
8583 
   (set (match_dup 3) (match_dup 1))]
8584 
  "
8585 
{
8586 
  HOST_WIDE_INT value = INTVAL (operands[1]);
8587 
  operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8588 
                                       DImode);
8589 
  operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8590 
                                       DImode);
8591 
#if HOST_BITS_PER_WIDE_INT == 32
8592 
  operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8593 
#else
8594 
  operands[4] = GEN_INT (value >> 32);
8595 
  operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8596 
#endif
8597 
}")
8598 
 
8599 
(define_split
8600 
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
8601 
        (match_operand:DI 1 "input_operand" ""))]
8602 
  "reload_completed && !TARGET_POWERPC64
8603 
   && gpr_or_gpr_p (operands[0], operands[1])"
8604 
  [(pc)]
8605 
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8606 
 
8607 
(define_insn "*movdi_internal64"
8608 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8609 
        (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8610 
  "TARGET_POWERPC64
8611 
   && (gpc_reg_operand (operands[0], DImode)
8612 
       || gpc_reg_operand (operands[1], DImode))"
8613 
  "@
8614 
   mr %0,%1
8615 
   ld%U1%X1 %0,%1
8616 
   std%U0%X0 %1,%0
8617 
   li %0,%1
8618 
   lis %0,%v1
8619 
   #
8620 
   {cal|la} %0,%a1
8621 
   fmr %0,%1
8622 
   lfd%U1%X1 %0,%1
8623 
   stfd%U0%X0 %1,%0
8624 
   mf%1 %0
8625 
   mt%0 %1
8626 
   {cror 0,0,0|nop}"
8627 
  [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8628 
   (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8629 
 
8630 
;; immediate value valid for a single instruction hiding in a const_double
8631 
(define_insn ""
8632 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8633 
        (match_operand:DI 1 "const_double_operand" "F"))]
8634 
  "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8635 
   && GET_CODE (operands[1]) == CONST_DOUBLE
8636 
   && num_insns_constant (operands[1], DImode) == 1"
8637 
  "*
8638 
{
8639 
  return ((unsigned HOST_WIDE_INT)
8640 
          (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8641 
         ? \"li %0,%1\" : \"lis %0,%v1\";
8642 
}")
8643 
 
8644 
;; Generate all one-bits and clear left or right.
8645 
;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8646 
(define_split
8647 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8648 
        (match_operand:DI 1 "mask64_operand" ""))]
8649 
  "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8650 
  [(set (match_dup 0) (const_int -1))
8651 
   (set (match_dup 0)
8652 
        (and:DI (rotate:DI (match_dup 0)
8653 
                           (const_int 0))
8654 
                (match_dup 1)))]
8655 
  "")
8656 
 
8657 
;; Split a load of a large constant into the appropriate five-instruction
8658 
;; sequence.  Handle anything in a constant number of insns.
8659 
;; When non-easy constants can go in the TOC, this should use
8660 
;; easy_fp_constant predicate.
8661 
(define_split
8662 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8663 
        (match_operand:DI 1 "const_int_operand" ""))]
8664 
  "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8665 
  [(set (match_dup 0) (match_dup 2))
8666 
   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8667 
  "
8668 
{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8669 
 
8670 
  if (tem == operands[0])
8671 
    DONE;
8672 
  else
8673 
    FAIL;
8674 
}")
8675 
 
8676 
(define_split
8677 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8678 
        (match_operand:DI 1 "const_double_operand" ""))]
8679 
  "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8680 
  [(set (match_dup 0) (match_dup 2))
8681 
   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8682 
  "
8683 
{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8684 
 
8685 
  if (tem == operands[0])
8686 
    DONE;
8687 
  else
8688 
    FAIL;
8689 
}")
8690 
 
8691 
;; TImode is similar, except that we usually want to compute the address into
8692 
;; a register and use lsi/stsi (the exception is during reload).  MQ is also
8693 
;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8694 
 
8695 
;; We say that MQ is clobbered in the last alternative because the first
8696 
;; alternative would never get used otherwise since it would need a reload
8697 
;; while the 2nd alternative would not.  We put memory cases first so they
8698 
;; are preferred.  Otherwise, we'd try to reload the output instead of
8699 
;; giving the SCRATCH mq.
8700 
 
8701 
(define_insn "*movti_power"
8702 
  [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8703 
        (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8704 
   (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8705 
  "TARGET_POWER && ! TARGET_POWERPC64
8706 
   && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8707 
  "*
8708 
{
8709 
  switch (which_alternative)
8710 
    {
8711 
    default:
8712 
      gcc_unreachable ();
8713 
 
8714 
    case 0:
8715 
      if (TARGET_STRING)
8716 
        return \"{stsi|stswi} %1,%P0,16\";
8717 
    case 1:
8718 
    case 2:
8719 
      return \"#\";
8720 
    case 3:
8721 
      /* If the address is not used in the output, we can use lsi.  Otherwise,
8722 
         fall through to generating four loads.  */
8723 
      if (TARGET_STRING
8724 
          && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8725 
        return \"{lsi|lswi} %0,%P1,16\";
8726 
      /* ... fall through ...  */
8727 
    case 4:
8728 
    case 5:
8729 
      return \"#\";
8730 
    }
8731 
}"
8732 
  [(set_attr "type" "store,store,*,load,load,*")])
8733 
 
8734 
(define_insn "*movti_string"
8735 
  [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8736 
        (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8737 
  "! TARGET_POWER && ! TARGET_POWERPC64
8738 
   && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8739 
  "*
8740 
{
8741 
  switch (which_alternative)
8742 
    {
8743 
    default:
8744 
      gcc_unreachable ();
8745 
    case 0:
8746 
      if (TARGET_STRING)
8747 
        return \"{stsi|stswi} %1,%P0,16\";
8748 
    case 1:
8749 
    case 2:
8750 
      return \"#\";
8751 
    case 3:
8752 
      /* If the address is not used in the output, we can use lsi.  Otherwise,
8753 
         fall through to generating four loads.  */
8754 
      if (TARGET_STRING
8755 
          && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8756 
        return \"{lsi|lswi} %0,%P1,16\";
8757 
      /* ... fall through ...  */
8758 
    case 4:
8759 
    case 5:
8760 
      return \"#\";
8761 
    }
8762 
}"
8763 
  [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8764 
 
8765 
(define_insn "*movti_ppc64"
8766 
  [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8767 
        (match_operand:TI 1 "input_operand" "r,r,m"))]
8768 
  "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8769 
   || gpc_reg_operand (operands[1], TImode))"
8770 
  "#"
8771 
  [(set_attr "type" "*,load,store")])
8772 
 
8773 
(define_split
8774 
  [(set (match_operand:TI 0 "gpc_reg_operand" "")
8775 
        (match_operand:TI 1 "const_double_operand" ""))]
8776 
  "TARGET_POWERPC64"
8777 
  [(set (match_dup 2) (match_dup 4))
8778 
   (set (match_dup 3) (match_dup 5))]
8779 
  "
8780 
{
8781 
  operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8782 
                                       TImode);
8783 
  operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8784 
                                       TImode);
8785 
  if (GET_CODE (operands[1]) == CONST_DOUBLE)
8786 
    {
8787 
      operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8788 
      operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8789 
    }
8790 
  else if (GET_CODE (operands[1]) == CONST_INT)
8791 
    {
8792 
      operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8793 
      operands[5] = operands[1];
8794 
    }
8795 
  else
8796 
    FAIL;
8797 
}")
8798 
 
8799 
(define_split
8800 
  [(set (match_operand:TI 0 "nonimmediate_operand" "")
8801 
        (match_operand:TI 1 "input_operand" ""))]
8802 
  "reload_completed
8803 
   && gpr_or_gpr_p (operands[0], operands[1])"
8804 
  [(pc)]
8805 
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8806 
 
8807 
(define_expand "load_multiple"
8808 
  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8809 
                          (match_operand:SI 1 "" ""))
8810 
                     (use (match_operand:SI 2 "" ""))])]
8811 
  "TARGET_STRING && !TARGET_POWERPC64"
8812 
  "
8813 
{
8814 
  int regno;
8815 
  int count;
8816 
  rtx op1;
8817 
  int i;
8818 
 
8819 
  /* Support only loading a constant number of fixed-point registers from
8820 
     memory and only bother with this if more than two; the machine
8821 
     doesn't support more than eight.  */
8822 
  if (GET_CODE (operands[2]) != CONST_INT
8823 
      || INTVAL (operands[2]) <= 2
8824 
      || INTVAL (operands[2]) > 8
8825 
      || GET_CODE (operands[1]) != MEM
8826 
      || GET_CODE (operands[0]) != REG
8827 
      || REGNO (operands[0]) >= 32)
8828 
    FAIL;
8829 
 
8830 
  count = INTVAL (operands[2]);
8831 
  regno = REGNO (operands[0]);
8832 
 
8833 
  operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8834 
  op1 = replace_equiv_address (operands[1],
8835 
                               force_reg (SImode, XEXP (operands[1], 0)));
8836 
 
8837 
  for (i = 0; i < count; i++)
8838 
    XVECEXP (operands[3], 0, i)
8839 
      = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8840 
                     adjust_address_nv (op1, SImode, i * 4));
8841 
}")
8842 
 
8843 
(define_insn "*ldmsi8"
8844 
  [(match_parallel 0 "load_multiple_operation"
8845 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
8846 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8847 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
8848 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8849 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
8850 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8851 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
8852 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8853 
     (set (match_operand:SI 6 "gpc_reg_operand" "")
8854 
          (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8855 
     (set (match_operand:SI 7 "gpc_reg_operand" "")
8856 
          (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8857 
     (set (match_operand:SI 8 "gpc_reg_operand" "")
8858 
          (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8859 
     (set (match_operand:SI 9 "gpc_reg_operand" "")
8860 
          (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8861 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8862 
  "*
8863 
{ return rs6000_output_load_multiple (operands); }"
8864 
  [(set_attr "type" "load_ux")
8865 
   (set_attr "length" "32")])
8866 
 
8867 
(define_insn "*ldmsi7"
8868 
  [(match_parallel 0 "load_multiple_operation"
8869 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
8870 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8871 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
8872 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8873 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
8874 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8875 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
8876 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8877 
     (set (match_operand:SI 6 "gpc_reg_operand" "")
8878 
          (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8879 
     (set (match_operand:SI 7 "gpc_reg_operand" "")
8880 
          (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8881 
     (set (match_operand:SI 8 "gpc_reg_operand" "")
8882 
          (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8883 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8884 
  "*
8885 
{ return rs6000_output_load_multiple (operands); }"
8886 
  [(set_attr "type" "load_ux")
8887 
   (set_attr "length" "32")])
8888 
 
8889 
(define_insn "*ldmsi6"
8890 
  [(match_parallel 0 "load_multiple_operation"
8891 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
8892 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8893 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
8894 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8895 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
8896 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8897 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
8898 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8899 
     (set (match_operand:SI 6 "gpc_reg_operand" "")
8900 
          (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8901 
     (set (match_operand:SI 7 "gpc_reg_operand" "")
8902 
          (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8903 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8904 
  "*
8905 
{ return rs6000_output_load_multiple (operands); }"
8906 
  [(set_attr "type" "load_ux")
8907 
   (set_attr "length" "32")])
8908 
 
8909 
(define_insn "*ldmsi5"
8910 
  [(match_parallel 0 "load_multiple_operation"
8911 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
8912 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8913 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
8914 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8915 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
8916 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8917 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
8918 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8919 
     (set (match_operand:SI 6 "gpc_reg_operand" "")
8920 
          (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8921 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8922 
  "*
8923 
{ return rs6000_output_load_multiple (operands); }"
8924 
  [(set_attr "type" "load_ux")
8925 
   (set_attr "length" "32")])
8926 
 
8927 
(define_insn "*ldmsi4"
8928 
  [(match_parallel 0 "load_multiple_operation"
8929 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
8930 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8931 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
8932 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8933 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
8934 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8935 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
8936 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8937 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8938 
  "*
8939 
{ return rs6000_output_load_multiple (operands); }"
8940 
  [(set_attr "type" "load_ux")
8941 
   (set_attr "length" "32")])
8942 
 
8943 
(define_insn "*ldmsi3"
8944 
  [(match_parallel 0 "load_multiple_operation"
8945 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
8946 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8947 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
8948 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8949 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
8950 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8951 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8952 
  "*
8953 
{ return rs6000_output_load_multiple (operands); }"
8954 
  [(set_attr "type" "load_ux")
8955 
   (set_attr "length" "32")])
8956 
 
8957 
(define_expand "store_multiple"
8958 
  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8959 
                          (match_operand:SI 1 "" ""))
8960 
                     (clobber (scratch:SI))
8961 
                     (use (match_operand:SI 2 "" ""))])]
8962 
  "TARGET_STRING && !TARGET_POWERPC64"
8963 
  "
8964 
{
8965 
  int regno;
8966 
  int count;
8967 
  rtx to;
8968 
  rtx op0;
8969 
  int i;
8970 
 
8971 
  /* Support only storing a constant number of fixed-point registers to
8972 
     memory and only bother with this if more than two; the machine
8973 
     doesn't support more than eight.  */
8974 
  if (GET_CODE (operands[2]) != CONST_INT
8975 
      || INTVAL (operands[2]) <= 2
8976 
      || INTVAL (operands[2]) > 8
8977 
      || GET_CODE (operands[0]) != MEM
8978 
      || GET_CODE (operands[1]) != REG
8979 
      || REGNO (operands[1]) >= 32)
8980 
    FAIL;
8981 
 
8982 
  count = INTVAL (operands[2]);
8983 
  regno = REGNO (operands[1]);
8984 
 
8985 
  operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8986 
  to = force_reg (SImode, XEXP (operands[0], 0));
8987 
  op0 = replace_equiv_address (operands[0], to);
8988 
 
8989 
  XVECEXP (operands[3], 0, 0)
8990 
    = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8991 
  XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8992 
                                                 gen_rtx_SCRATCH (SImode));
8993 
 
8994 
  for (i = 1; i < count; i++)
8995 
    XVECEXP (operands[3], 0, i + 1)
8996 
      = gen_rtx_SET (VOIDmode,
8997 
                     adjust_address_nv (op0, SImode, i * 4),
8998 
                     gen_rtx_REG (SImode, regno + i));
8999 
}")
9000 
 
9001 
(define_insn "*stmsi8"
9002 
  [(match_parallel 0 "store_multiple_operation"
9003 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9004 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9005 
     (clobber (match_scratch:SI 3 "=X"))
9006 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9007 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9008 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9009 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9010 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9011 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
9012 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9013 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
9014 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9015 
          (match_operand:SI 8 "gpc_reg_operand" "r"))
9016 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9017 
          (match_operand:SI 9 "gpc_reg_operand" "r"))
9018 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9019 
          (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9020 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9021 
  "{stsi|stswi} %2,%1,%O0"
9022 
  [(set_attr "type" "store_ux")])
9023 
 
9024 
(define_insn "*stmsi7"
9025 
  [(match_parallel 0 "store_multiple_operation"
9026 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9027 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9028 
     (clobber (match_scratch:SI 3 "=X"))
9029 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9030 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9031 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9032 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9033 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9034 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
9035 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9036 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
9037 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9038 
          (match_operand:SI 8 "gpc_reg_operand" "r"))
9039 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9040 
          (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9041 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9042 
  "{stsi|stswi} %2,%1,%O0"
9043 
  [(set_attr "type" "store_ux")])
9044 
 
9045 
(define_insn "*stmsi6"
9046 
  [(match_parallel 0 "store_multiple_operation"
9047 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9048 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9049 
     (clobber (match_scratch:SI 3 "=X"))
9050 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9051 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9052 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9053 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9054 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9055 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
9056 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9057 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
9058 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9059 
          (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9060 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9061 
  "{stsi|stswi} %2,%1,%O0"
9062 
  [(set_attr "type" "store_ux")])
9063 
 
9064 
(define_insn "*stmsi5"
9065 
  [(match_parallel 0 "store_multiple_operation"
9066 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9067 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9068 
     (clobber (match_scratch:SI 3 "=X"))
9069 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9070 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9071 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9072 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9073 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9074 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
9075 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9076 
          (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9077 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9078 
  "{stsi|stswi} %2,%1,%O0"
9079 
  [(set_attr "type" "store_ux")])
9080 
 
9081 
(define_insn "*stmsi4"
9082 
  [(match_parallel 0 "store_multiple_operation"
9083 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9084 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9085 
     (clobber (match_scratch:SI 3 "=X"))
9086 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9087 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9088 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9089 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9090 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9091 
          (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9092 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9093 
  "{stsi|stswi} %2,%1,%O0"
9094 
  [(set_attr "type" "store_ux")])
9095 
 
9096 
(define_insn "*stmsi3"
9097 
  [(match_parallel 0 "store_multiple_operation"
9098 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9099 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9100 
     (clobber (match_scratch:SI 3 "=X"))
9101 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9102 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9103 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9104 
          (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9105 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9106 
  "{stsi|stswi} %2,%1,%O0"
9107 
  [(set_attr "type" "store_ux")])
9108 
 
9109 
(define_insn "*stmsi8_power"
9110 
  [(match_parallel 0 "store_multiple_operation"
9111 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9112 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9113 
     (clobber (match_scratch:SI 3 "=q"))
9114 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9115 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9116 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9117 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9118 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9119 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
9120 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9121 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
9122 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9123 
          (match_operand:SI 8 "gpc_reg_operand" "r"))
9124 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9125 
          (match_operand:SI 9 "gpc_reg_operand" "r"))
9126 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9127 
          (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9128 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9129 
  "{stsi|stswi} %2,%1,%O0"
9130 
  [(set_attr "type" "store_ux")])
9131 
 
9132 
(define_insn "*stmsi7_power"
9133 
  [(match_parallel 0 "store_multiple_operation"
9134 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9135 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9136 
     (clobber (match_scratch:SI 3 "=q"))
9137 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9138 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9139 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9140 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9141 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9142 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
9143 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9144 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
9145 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9146 
          (match_operand:SI 8 "gpc_reg_operand" "r"))
9147 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9148 
          (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9149 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9150 
  "{stsi|stswi} %2,%1,%O0"
9151 
  [(set_attr "type" "store_ux")])
9152 
 
9153 
(define_insn "*stmsi6_power"
9154 
  [(match_parallel 0 "store_multiple_operation"
9155 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9156 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9157 
     (clobber (match_scratch:SI 3 "=q"))
9158 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9159 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9160 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9161 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9162 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9163 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
9164 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9165 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
9166 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9167 
          (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9168 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9169 
  "{stsi|stswi} %2,%1,%O0"
9170 
  [(set_attr "type" "store_ux")])
9171 
 
9172 
(define_insn "*stmsi5_power"
9173 
  [(match_parallel 0 "store_multiple_operation"
9174 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9175 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9176 
     (clobber (match_scratch:SI 3 "=q"))
9177 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9178 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9179 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9180 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9181 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9182 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
9183 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9184 
          (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9185 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9186 
  "{stsi|stswi} %2,%1,%O0"
9187 
  [(set_attr "type" "store_ux")])
9188 
 
9189 
(define_insn "*stmsi4_power"
9190 
  [(match_parallel 0 "store_multiple_operation"
9191 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9192 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9193 
     (clobber (match_scratch:SI 3 "=q"))
9194 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9195 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9196 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9197 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
9198 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9199 
          (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9200 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9201 
  "{stsi|stswi} %2,%1,%O0"
9202 
  [(set_attr "type" "store_ux")])
9203 
 
9204 
(define_insn "*stmsi3_power"
9205 
  [(match_parallel 0 "store_multiple_operation"
9206 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9207 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
9208 
     (clobber (match_scratch:SI 3 "=q"))
9209 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9210 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
9211 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9212 
          (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9213 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9214 
  "{stsi|stswi} %2,%1,%O0"
9215 
  [(set_attr "type" "store_ux")])
9216 
 
9217 
(define_expand "setmemsi"
9218 
  [(parallel [(set (match_operand:BLK 0 "" "")
9219 
                   (match_operand 2 "const_int_operand" ""))
9220 
              (use (match_operand:SI 1 "" ""))
9221 
              (use (match_operand:SI 3 "" ""))])]
9222 
  ""
9223 
  "
9224 
{
9225 
  /* If value to set is not zero, use the library routine.  */
9226 
  if (operands[2] != const0_rtx)
9227 
    FAIL;
9228 
 
9229 
  if (expand_block_clear (operands))
9230 
    DONE;
9231 
  else
9232 
    FAIL;
9233 
}")
9234 
 
9235 
;; String/block move insn.
9236 
;; Argument 0 is the destination
9237 
;; Argument 1 is the source
9238 
;; Argument 2 is the length
9239 
;; Argument 3 is the alignment
9240 
 
9241 
(define_expand "movmemsi"
9242 
  [(parallel [(set (match_operand:BLK 0 "" "")
9243 
                   (match_operand:BLK 1 "" ""))
9244 
              (use (match_operand:SI 2 "" ""))
9245 
              (use (match_operand:SI 3 "" ""))])]
9246 
  ""
9247 
  "
9248 
{
9249 
  if (expand_block_move (operands))
9250 
    DONE;
9251 
  else
9252 
    FAIL;
9253 
}")
9254 
 
9255 
;; Move up to 32 bytes at a time.  The fixed registers are needed because the
9256 
;; register allocator doesn't have a clue about allocating 8 word registers.
9257 
;; rD/rS = r5 is preferred, efficient form.
9258 
(define_expand "movmemsi_8reg"
9259 
  [(parallel [(set (match_operand 0 "" "")
9260 
                   (match_operand 1 "" ""))
9261 
              (use (match_operand 2 "" ""))
9262 
              (use (match_operand 3 "" ""))
9263 
              (clobber (reg:SI  5))
9264 
              (clobber (reg:SI  6))
9265 
              (clobber (reg:SI  7))
9266 
              (clobber (reg:SI  8))
9267 
              (clobber (reg:SI  9))
9268 
              (clobber (reg:SI 10))
9269 
              (clobber (reg:SI 11))
9270 
              (clobber (reg:SI 12))
9271 
              (clobber (match_scratch:SI 4 ""))])]
9272 
  "TARGET_STRING"
9273 
  "")
9274 
 
9275 
(define_insn ""
9276 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9277 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9278 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9279 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9280 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9281 
   (clobber (reg:SI  6))
9282 
   (clobber (reg:SI  7))
9283 
   (clobber (reg:SI  8))
9284 
   (clobber (reg:SI  9))
9285 
   (clobber (reg:SI 10))
9286 
   (clobber (reg:SI 11))
9287 
   (clobber (reg:SI 12))
9288 
   (clobber (match_scratch:SI 5 "=q"))]
9289 
  "TARGET_STRING && TARGET_POWER
9290 
   && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9291 
       || INTVAL (operands[2]) == 0)
9292 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9293 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9294 
   && REGNO (operands[4]) == 5"
9295 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9296 
  [(set_attr "type" "store_ux")
9297 
   (set_attr "length" "8")])
9298 
 
9299 
(define_insn ""
9300 
  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9301 
        (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9302 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9303 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9304 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9305 
   (clobber (reg:SI  6))
9306 
   (clobber (reg:SI  7))
9307 
   (clobber (reg:SI  8))
9308 
   (clobber (reg:SI  9))
9309 
   (clobber (reg:SI 10))
9310 
   (clobber (reg:SI 11))
9311 
   (clobber (reg:SI 12))
9312 
   (clobber (match_scratch:SI 5 "=X"))]
9313 
  "TARGET_STRING && ! TARGET_POWER
9314 
   && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9315 
       || INTVAL (operands[2]) == 0)
9316 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9317 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9318 
   && REGNO (operands[4]) == 5"
9319 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9320 
  [(set_attr "type" "store_ux")
9321 
   (set_attr "length" "8")])
9322 
 
9323 
;; Move up to 24 bytes at a time.  The fixed registers are needed because the
9324 
;; register allocator doesn't have a clue about allocating 6 word registers.
9325 
;; rD/rS = r5 is preferred, efficient form.
9326 
(define_expand "movmemsi_6reg"
9327 
  [(parallel [(set (match_operand 0 "" "")
9328 
                   (match_operand 1 "" ""))
9329 
              (use (match_operand 2 "" ""))
9330 
              (use (match_operand 3 "" ""))
9331 
              (clobber (reg:SI  5))
9332 
              (clobber (reg:SI  6))
9333 
              (clobber (reg:SI  7))
9334 
              (clobber (reg:SI  8))
9335 
              (clobber (reg:SI  9))
9336 
              (clobber (reg:SI 10))
9337 
              (clobber (match_scratch:SI 4 ""))])]
9338 
  "TARGET_STRING"
9339 
  "")
9340 
 
9341 
(define_insn ""
9342 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9343 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9344 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9345 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9346 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9347 
   (clobber (reg:SI  6))
9348 
   (clobber (reg:SI  7))
9349 
   (clobber (reg:SI  8))
9350 
   (clobber (reg:SI  9))
9351 
   (clobber (reg:SI 10))
9352 
   (clobber (match_scratch:SI 5 "=q"))]
9353 
  "TARGET_STRING && TARGET_POWER
9354 
   && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9355 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9356 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9357 
   && REGNO (operands[4]) == 5"
9358 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9359 
  [(set_attr "type" "store_ux")
9360 
   (set_attr "length" "8")])
9361 
 
9362 
(define_insn ""
9363 
  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9364 
        (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9365 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9366 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9367 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9368 
   (clobber (reg:SI  6))
9369 
   (clobber (reg:SI  7))
9370 
   (clobber (reg:SI  8))
9371 
   (clobber (reg:SI  9))
9372 
   (clobber (reg:SI 10))
9373 
   (clobber (match_scratch:SI 5 "=X"))]
9374 
  "TARGET_STRING && ! TARGET_POWER
9375 
   && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9376 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9377 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9378 
   && REGNO (operands[4]) == 5"
9379 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9380 
  [(set_attr "type" "store_ux")
9381 
   (set_attr "length" "8")])
9382 
 
9383 
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9384 
;; problems with TImode.
9385 
;; rD/rS = r5 is preferred, efficient form.
9386 
(define_expand "movmemsi_4reg"
9387 
  [(parallel [(set (match_operand 0 "" "")
9388 
                   (match_operand 1 "" ""))
9389 
              (use (match_operand 2 "" ""))
9390 
              (use (match_operand 3 "" ""))
9391 
              (clobber (reg:SI 5))
9392 
              (clobber (reg:SI 6))
9393 
              (clobber (reg:SI 7))
9394 
              (clobber (reg:SI 8))
9395 
              (clobber (match_scratch:SI 4 ""))])]
9396 
  "TARGET_STRING"
9397 
  "")
9398 
 
9399 
(define_insn ""
9400 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9401 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9402 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9403 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9404 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9405 
   (clobber (reg:SI 6))
9406 
   (clobber (reg:SI 7))
9407 
   (clobber (reg:SI 8))
9408 
   (clobber (match_scratch:SI 5 "=q"))]
9409 
  "TARGET_STRING && TARGET_POWER
9410 
   && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9411 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9412 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9413 
   && REGNO (operands[4]) == 5"
9414 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9415 
  [(set_attr "type" "store_ux")
9416 
   (set_attr "length" "8")])
9417 
 
9418 
(define_insn ""
9419 
  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9420 
        (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9421 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9422 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9423 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9424 
   (clobber (reg:SI 6))
9425 
   (clobber (reg:SI 7))
9426 
   (clobber (reg:SI 8))
9427 
   (clobber (match_scratch:SI 5 "=X"))]
9428 
  "TARGET_STRING && ! TARGET_POWER
9429 
   && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9430 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9431 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9432 
   && REGNO (operands[4]) == 5"
9433 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9434 
  [(set_attr "type" "store_ux")
9435 
   (set_attr "length" "8")])
9436 
 
9437 
;; Move up to 8 bytes at a time.
9438 
(define_expand "movmemsi_2reg"
9439 
  [(parallel [(set (match_operand 0 "" "")
9440 
                   (match_operand 1 "" ""))
9441 
              (use (match_operand 2 "" ""))
9442 
              (use (match_operand 3 "" ""))
9443 
              (clobber (match_scratch:DI 4 ""))
9444 
              (clobber (match_scratch:SI 5 ""))])]
9445 
  "TARGET_STRING && ! TARGET_POWERPC64"
9446 
  "")
9447 
 
9448 
(define_insn ""
9449 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9450 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9451 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9452 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9453 
   (clobber (match_scratch:DI 4 "=&r"))
9454 
   (clobber (match_scratch:SI 5 "=q"))]
9455 
  "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9456 
   && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9457 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9458 
  [(set_attr "type" "store_ux")
9459 
   (set_attr "length" "8")])
9460 
 
9461 
(define_insn ""
9462 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9463 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9464 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9465 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9466 
   (clobber (match_scratch:DI 4 "=&r"))
9467 
   (clobber (match_scratch:SI 5 "=X"))]
9468 
  "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9469 
   && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9470 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9471 
  [(set_attr "type" "store_ux")
9472 
   (set_attr "length" "8")])
9473 
 
9474 
;; Move up to 4 bytes at a time.
9475 
(define_expand "movmemsi_1reg"
9476 
  [(parallel [(set (match_operand 0 "" "")
9477 
                   (match_operand 1 "" ""))
9478 
              (use (match_operand 2 "" ""))
9479 
              (use (match_operand 3 "" ""))
9480 
              (clobber (match_scratch:SI 4 ""))
9481 
              (clobber (match_scratch:SI 5 ""))])]
9482 
  "TARGET_STRING"
9483 
  "")
9484 
 
9485 
(define_insn ""
9486 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9487 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9488 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9489 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9490 
   (clobber (match_scratch:SI 4 "=&r"))
9491 
   (clobber (match_scratch:SI 5 "=q"))]
9492 
  "TARGET_STRING && TARGET_POWER
9493 
   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9494 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9495 
  [(set_attr "type" "store_ux")
9496 
   (set_attr "length" "8")])
9497 
 
9498 
(define_insn ""
9499 
  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9500 
        (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9501 
   (use (match_operand:SI 2 "immediate_operand" "i"))
9502 
   (use (match_operand:SI 3 "immediate_operand" "i"))
9503 
   (clobber (match_scratch:SI 4 "=&r"))
9504 
   (clobber (match_scratch:SI 5 "=X"))]
9505 
  "TARGET_STRING && ! TARGET_POWER
9506 
   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9507 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9508 
  [(set_attr "type" "store_ux")
9509 
   (set_attr "length" "8")])
9510 
 
9511 
;; Define insns that do load or store with update.  Some of these we can
9512 
;; get by using pre-decrement or pre-increment, but the hardware can also
9513 
;; do cases where the increment is not the size of the object.
9514 
;;
9515 
;; In all these cases, we use operands 0 and 1 for the register being
9516 
;; incremented because those are the operands that local-alloc will
9517 
;; tie and these are the pair most likely to be tieable (and the ones
9518 
;; that will benefit the most).
9519 
 
9520 
(define_insn "*movdi_update1"
9521 
  [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9522 
        (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9523 
                         (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9524 
   (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9525 
        (plus:DI (match_dup 1) (match_dup 2)))]
9526 
  "TARGET_POWERPC64 && TARGET_UPDATE"
9527 
  "@
9528 
   ldux %3,%0,%2
9529 
   ldu %3,%2(%0)"
9530 
  [(set_attr "type" "load_ux,load_u")])
9531 
 
9532 
(define_insn "movdi__update"
9533 
  [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9534 
                         (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9535 
        (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9536 
   (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9537 
        (plus:P (match_dup 1) (match_dup 2)))]
9538 
  "TARGET_POWERPC64 && TARGET_UPDATE"
9539 
  "@
9540 
   stdux %3,%0,%2
9541 
   stdu %3,%2(%0)"
9542 
  [(set_attr "type" "store_ux,store_u")])
9543 
 
9544 
(define_insn "*movsi_update1"
9545 
  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9546 
        (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9547 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9548 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9549 
        (plus:SI (match_dup 1) (match_dup 2)))]
9550 
  "TARGET_UPDATE"
9551 
  "@
9552 
   {lux|lwzux} %3,%0,%2
9553 
   {lu|lwzu} %3,%2(%0)"
9554 
  [(set_attr "type" "load_ux,load_u")])
9555 
 
9556 
(define_insn "*movsi_update2"
9557 
  [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9558 
        (sign_extend:DI
9559 
         (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9560 
                          (match_operand:DI 2 "gpc_reg_operand" "r")))))
9561 
   (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9562 
        (plus:DI (match_dup 1) (match_dup 2)))]
9563 
  "TARGET_POWERPC64"
9564 
  "lwaux %3,%0,%2"
9565 
  [(set_attr "type" "load_ext_ux")])
9566 
 
9567 
(define_insn "movsi_update"
9568 
  [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9569 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9570 
        (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9571 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9572 
        (plus:SI (match_dup 1) (match_dup 2)))]
9573 
  "TARGET_UPDATE"
9574 
  "@
9575 
   {stux|stwux} %3,%0,%2
9576 
   {stu|stwu} %3,%2(%0)"
9577 
  [(set_attr "type" "store_ux,store_u")])
9578 
 
9579 
(define_insn "*movhi_update1"
9580 
  [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9581 
        (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9582 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9583 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9584 
        (plus:SI (match_dup 1) (match_dup 2)))]
9585 
  "TARGET_UPDATE"
9586 
  "@
9587 
   lhzux %3,%0,%2
9588 
   lhzu %3,%2(%0)"
9589 
  [(set_attr "type" "load_ux,load_u")])
9590 
 
9591 
(define_insn "*movhi_update2"
9592 
  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9593 
        (zero_extend:SI
9594 
         (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9595 
                          (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9596 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9597 
        (plus:SI (match_dup 1) (match_dup 2)))]
9598 
  "TARGET_UPDATE"
9599 
  "@
9600 
   lhzux %3,%0,%2
9601 
   lhzu %3,%2(%0)"
9602 
  [(set_attr "type" "load_ux,load_u")])
9603 
 
9604 
(define_insn "*movhi_update3"
9605 
  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9606 
        (sign_extend:SI
9607 
         (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9608 
                          (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9609 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9610 
        (plus:SI (match_dup 1) (match_dup 2)))]
9611 
  "TARGET_UPDATE"
9612 
  "@
9613 
   lhaux %3,%0,%2
9614 
   lhau %3,%2(%0)"
9615 
  [(set_attr "type" "load_ext_ux,load_ext_u")])
9616 
 
9617 
(define_insn "*movhi_update4"
9618 
  [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9619 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9620 
        (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9621 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9622 
        (plus:SI (match_dup 1) (match_dup 2)))]
9623 
  "TARGET_UPDATE"
9624 
  "@
9625 
   sthux %3,%0,%2
9626 
   sthu %3,%2(%0)"
9627 
  [(set_attr "type" "store_ux,store_u")])
9628 
 
9629 
(define_insn "*movqi_update1"
9630 
  [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9631 
        (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9632 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9633 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9634 
        (plus:SI (match_dup 1) (match_dup 2)))]
9635 
  "TARGET_UPDATE"
9636 
  "@
9637 
   lbzux %3,%0,%2
9638 
   lbzu %3,%2(%0)"
9639 
  [(set_attr "type" "load_ux,load_u")])
9640 
 
9641 
(define_insn "*movqi_update2"
9642 
  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9643 
        (zero_extend:SI
9644 
         (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9645 
                          (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9646 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9647 
        (plus:SI (match_dup 1) (match_dup 2)))]
9648 
  "TARGET_UPDATE"
9649 
  "@
9650 
   lbzux %3,%0,%2
9651 
   lbzu %3,%2(%0)"
9652 
  [(set_attr "type" "load_ux,load_u")])
9653 
 
9654 
(define_insn "*movqi_update3"
9655 
  [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9656 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9657 
        (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9658 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9659 
        (plus:SI (match_dup 1) (match_dup 2)))]
9660 
  "TARGET_UPDATE"
9661 
  "@
9662 
   stbux %3,%0,%2
9663 
   stbu %3,%2(%0)"
9664 
  [(set_attr "type" "store_ux,store_u")])
9665 
 
9666 
(define_insn "*movsf_update1"
9667 
  [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9668 
        (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9669 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9670 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9671 
        (plus:SI (match_dup 1) (match_dup 2)))]
9672 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9673 
  "@
9674 
   lfsux %3,%0,%2
9675 
   lfsu %3,%2(%0)"
9676 
  [(set_attr "type" "fpload_ux,fpload_u")])
9677 
 
9678 
(define_insn "*movsf_update2"
9679 
  [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9680 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9681 
        (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9682 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9683 
        (plus:SI (match_dup 1) (match_dup 2)))]
9684 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9685 
  "@
9686 
   stfsux %3,%0,%2
9687 
   stfsu %3,%2(%0)"
9688 
  [(set_attr "type" "fpstore_ux,fpstore_u")])
9689 
 
9690 
(define_insn "*movsf_update3"
9691 
  [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9692 
        (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9693 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9694 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9695 
        (plus:SI (match_dup 1) (match_dup 2)))]
9696 
  "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9697 
  "@
9698 
   {lux|lwzux} %3,%0,%2
9699 
   {lu|lwzu} %3,%2(%0)"
9700 
  [(set_attr "type" "load_ux,load_u")])
9701 
 
9702 
(define_insn "*movsf_update4"
9703 
  [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9704 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9705 
        (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9706 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9707 
        (plus:SI (match_dup 1) (match_dup 2)))]
9708 
  "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9709 
  "@
9710 
   {stux|stwux} %3,%0,%2
9711 
   {stu|stwu} %3,%2(%0)"
9712 
  [(set_attr "type" "store_ux,store_u")])
9713 
 
9714 
(define_insn "*movdf_update1"
9715 
  [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9716 
        (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9717 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9718 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9719 
        (plus:SI (match_dup 1) (match_dup 2)))]
9720 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9721 
  "@
9722 
   lfdux %3,%0,%2
9723 
   lfdu %3,%2(%0)"
9724 
  [(set_attr "type" "fpload_ux,fpload_u")])
9725 
 
9726 
(define_insn "*movdf_update2"
9727 
  [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9728 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9729 
        (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9730 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9731 
        (plus:SI (match_dup 1) (match_dup 2)))]
9732 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9733 
  "@
9734 
   stfdux %3,%0,%2
9735 
   stfdu %3,%2(%0)"
9736 
  [(set_attr "type" "fpstore_ux,fpstore_u")])
9737 
 
9738 
;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9739 
 
9740 
(define_insn "*lfq_power2"
9741 
  [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9742 
        (match_operand:V2DF 1 "memory_operand" ""))]
9743 
  "TARGET_POWER2
9744 
   && TARGET_HARD_FLOAT && TARGET_FPRS"
9745 
  "lfq%U1%X1 %0,%1")
9746 
 
9747 
(define_peephole2
9748 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
9749 
        (match_operand:DF 1 "memory_operand" ""))
9750 
   (set (match_operand:DF 2 "gpc_reg_operand" "")
9751 
        (match_operand:DF 3 "memory_operand" ""))]
9752 
  "TARGET_POWER2
9753 
   && TARGET_HARD_FLOAT && TARGET_FPRS
9754 
   && registers_ok_for_quad_peep (operands[0], operands[2])
9755 
   && mems_ok_for_quad_peep (operands[1], operands[3])"
9756 
  [(set (match_dup 0)
9757 
        (match_dup 1))]
9758 
  "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9759 
   operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9760 
 
9761 
(define_insn "*stfq_power2"
9762 
  [(set (match_operand:V2DF 0 "memory_operand" "")
9763 
        (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9764 
  "TARGET_POWER2
9765 
   && TARGET_HARD_FLOAT && TARGET_FPRS"
9766 
  "stfq%U0%X0 %1,%0")
9767 
 
9768 
 
9769 
(define_peephole2
9770 
  [(set (match_operand:DF 0 "memory_operand" "")
9771 
        (match_operand:DF 1 "gpc_reg_operand" ""))
9772 
   (set (match_operand:DF 2 "memory_operand" "")
9773 
        (match_operand:DF 3 "gpc_reg_operand" ""))]
9774 
  "TARGET_POWER2
9775 
   && TARGET_HARD_FLOAT && TARGET_FPRS
9776 
   && registers_ok_for_quad_peep (operands[1], operands[3])
9777 
   && mems_ok_for_quad_peep (operands[0], operands[2])"
9778 
  [(set (match_dup 0)
9779 
        (match_dup 1))]
9780 
  "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9781 
   operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9782 
 
9783 
;; After inserting conditional returns we can sometimes have
9784 
;; unnecessary register moves.  Unfortunately we cannot have a
9785 
;; modeless peephole here, because some single SImode sets have early
9786 
;; clobber outputs.  Although those sets expand to multi-ppc-insn
9787 
;; sequences, using get_attr_length here will smash the operands
9788 
;; array.  Neither is there an early_cobbler_p predicate.
9789 
;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9790 
(define_peephole2
9791 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
9792 
        (match_operand:DF 1 "any_operand" ""))
9793 
   (set (match_operand:DF 2 "gpc_reg_operand" "")
9794 
        (match_dup 0))]
9795 
  "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9796 
   && peep2_reg_dead_p (2, operands[0])"
9797 
  [(set (match_dup 2) (match_dup 1))])
9798 
 
9799 
(define_peephole2
9800 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
9801 
        (match_operand:SF 1 "any_operand" ""))
9802 
   (set (match_operand:SF 2 "gpc_reg_operand" "")
9803 
        (match_dup 0))]
9804 
  "peep2_reg_dead_p (2, operands[0])"
9805 
  [(set (match_dup 2) (match_dup 1))])
9806 
 
9807 
 
9808 
;; TLS support.
9809 
 
9810 
;; "b" output constraint here and on tls_ld to support tls linker optimization.
9811 
(define_insn "tls_gd_32"
9812 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9813 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9814 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9815 
                   UNSPEC_TLSGD))]
9816 
  "HAVE_AS_TLS && !TARGET_64BIT"
9817 
  "addi %0,%1,%2@got@tlsgd")
9818 
 
9819 
(define_insn "tls_gd_64"
9820 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9821 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9822 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9823 
                   UNSPEC_TLSGD))]
9824 
  "HAVE_AS_TLS && TARGET_64BIT"
9825 
  "addi %0,%1,%2@got@tlsgd")
9826 
 
9827 
(define_insn "tls_ld_32"
9828 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9829 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9830 
                   UNSPEC_TLSLD))]
9831 
  "HAVE_AS_TLS && !TARGET_64BIT"
9832 
  "addi %0,%1,%&@got@tlsld")
9833 
 
9834 
(define_insn "tls_ld_64"
9835 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9836 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9837 
                   UNSPEC_TLSLD))]
9838 
  "HAVE_AS_TLS && TARGET_64BIT"
9839 
  "addi %0,%1,%&@got@tlsld")
9840 
 
9841 
(define_insn "tls_dtprel_32"
9842 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9843 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9844 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9845 
                   UNSPEC_TLSDTPREL))]
9846 
  "HAVE_AS_TLS && !TARGET_64BIT"
9847 
  "addi %0,%1,%2@dtprel")
9848 
 
9849 
(define_insn "tls_dtprel_64"
9850 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9851 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9852 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9853 
                   UNSPEC_TLSDTPREL))]
9854 
  "HAVE_AS_TLS && TARGET_64BIT"
9855 
  "addi %0,%1,%2@dtprel")
9856 
 
9857 
(define_insn "tls_dtprel_ha_32"
9858 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9859 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9860 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9861 
                   UNSPEC_TLSDTPRELHA))]
9862 
  "HAVE_AS_TLS && !TARGET_64BIT"
9863 
  "addis %0,%1,%2@dtprel@ha")
9864 
 
9865 
(define_insn "tls_dtprel_ha_64"
9866 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9867 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9868 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9869 
                   UNSPEC_TLSDTPRELHA))]
9870 
  "HAVE_AS_TLS && TARGET_64BIT"
9871 
  "addis %0,%1,%2@dtprel@ha")
9872 
 
9873 
(define_insn "tls_dtprel_lo_32"
9874 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9875 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9876 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9877 
                   UNSPEC_TLSDTPRELLO))]
9878 
  "HAVE_AS_TLS && !TARGET_64BIT"
9879 
  "addi %0,%1,%2@dtprel@l")
9880 
 
9881 
(define_insn "tls_dtprel_lo_64"
9882 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9883 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9884 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9885 
                   UNSPEC_TLSDTPRELLO))]
9886 
  "HAVE_AS_TLS && TARGET_64BIT"
9887 
  "addi %0,%1,%2@dtprel@l")
9888 
 
9889 
(define_insn "tls_got_dtprel_32"
9890 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9891 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9892 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9893 
                   UNSPEC_TLSGOTDTPREL))]
9894 
  "HAVE_AS_TLS && !TARGET_64BIT"
9895 
  "lwz %0,%2@got@dtprel(%1)")
9896 
 
9897 
(define_insn "tls_got_dtprel_64"
9898 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9899 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9900 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9901 
                   UNSPEC_TLSGOTDTPREL))]
9902 
  "HAVE_AS_TLS && TARGET_64BIT"
9903 
  "ld %0,%2@got@dtprel(%1)")
9904 
 
9905 
(define_insn "tls_tprel_32"
9906 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9907 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9908 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9909 
                   UNSPEC_TLSTPREL))]
9910 
  "HAVE_AS_TLS && !TARGET_64BIT"
9911 
  "addi %0,%1,%2@tprel")
9912 
 
9913 
(define_insn "tls_tprel_64"
9914 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9915 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9916 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9917 
                   UNSPEC_TLSTPREL))]
9918 
  "HAVE_AS_TLS && TARGET_64BIT"
9919 
  "addi %0,%1,%2@tprel")
9920 
 
9921 
(define_insn "tls_tprel_ha_32"
9922 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9923 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9924 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9925 
                   UNSPEC_TLSTPRELHA))]
9926 
  "HAVE_AS_TLS && !TARGET_64BIT"
9927 
  "addis %0,%1,%2@tprel@ha")
9928 
 
9929 
(define_insn "tls_tprel_ha_64"
9930 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9931 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9932 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9933 
                   UNSPEC_TLSTPRELHA))]
9934 
  "HAVE_AS_TLS && TARGET_64BIT"
9935 
  "addis %0,%1,%2@tprel@ha")
9936 
 
9937 
(define_insn "tls_tprel_lo_32"
9938 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9939 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9940 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9941 
                   UNSPEC_TLSTPRELLO))]
9942 
  "HAVE_AS_TLS && !TARGET_64BIT"
9943 
  "addi %0,%1,%2@tprel@l")
9944 
 
9945 
(define_insn "tls_tprel_lo_64"
9946 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9947 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9948 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9949 
                   UNSPEC_TLSTPRELLO))]
9950 
  "HAVE_AS_TLS && TARGET_64BIT"
9951 
  "addi %0,%1,%2@tprel@l")
9952 
 
9953 
;; "b" output constraint here and on tls_tls input to support linker tls
9954 
;; optimization.  The linker may edit the instructions emitted by a
9955 
;; tls_got_tprel/tls_tls pair to addis,addi.
9956 
(define_insn "tls_got_tprel_32"
9957 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9958 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9959 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9960 
                   UNSPEC_TLSGOTTPREL))]
9961 
  "HAVE_AS_TLS && !TARGET_64BIT"
9962 
  "lwz %0,%2@got@tprel(%1)")
9963 
 
9964 
(define_insn "tls_got_tprel_64"
9965 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9966 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9967 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9968 
                   UNSPEC_TLSGOTTPREL))]
9969 
  "HAVE_AS_TLS && TARGET_64BIT"
9970 
  "ld %0,%2@got@tprel(%1)")
9971 
 
9972 
(define_insn "tls_tls_32"
9973 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9974 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9975 
                    (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9976 
                   UNSPEC_TLSTLS))]
9977 
  "HAVE_AS_TLS && !TARGET_64BIT"
9978 
  "add %0,%1,%2@tls")
9979 
 
9980 
(define_insn "tls_tls_64"
9981 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9982 
        (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9983 
                    (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9984 
                   UNSPEC_TLSTLS))]
9985 
  "HAVE_AS_TLS && TARGET_64BIT"
9986 
  "add %0,%1,%2@tls")
9987 
 
9988 
;; Next come insns related to the calling sequence.
9989 
;;
9990 
;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9991 
;; We move the back-chain and decrement the stack pointer.
9992 
 
9993 
(define_expand "allocate_stack"
9994 
  [(set (match_operand 0 "gpc_reg_operand" "=r")
9995 
        (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9996 
   (set (reg 1)
9997 
        (minus (reg 1) (match_dup 1)))]
9998 
  ""
9999 
  "
10000 
{ rtx chain = gen_reg_rtx (Pmode);
10001 
  rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10002 
  rtx neg_op0;
10003 
 
10004 
  emit_move_insn (chain, stack_bot);
10005 
 
10006 
  /* Check stack bounds if necessary.  */
10007 
  if (current_function_limit_stack)
10008 
    {
10009 
      rtx available;
10010 
      available = expand_binop (Pmode, sub_optab,
10011 
                                stack_pointer_rtx, stack_limit_rtx,
10012 
                                NULL_RTX, 1, OPTAB_WIDEN);
10013 
      emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10014 
    }
10015 
 
10016 
  if (GET_CODE (operands[1]) != CONST_INT
10017 
      || INTVAL (operands[1]) < -32767
10018 
      || INTVAL (operands[1]) > 32768)
10019 
    {
10020 
      neg_op0 = gen_reg_rtx (Pmode);
10021 
      if (TARGET_32BIT)
10022 
        emit_insn (gen_negsi2 (neg_op0, operands[1]));
10023 
      else
10024 
        emit_insn (gen_negdi2 (neg_op0, operands[1]));
10025 
    }
10026 
  else
10027 
    neg_op0 = GEN_INT (- INTVAL (operands[1]));
10028 
 
10029 
  if (TARGET_UPDATE)
10030 
    emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10031 
                (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10032 
 
10033 
  else
10034 
    {
10035 
      emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10036 
                 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10037 
      emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10038 
    }
10039 
 
10040 
  emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10041 
  DONE;
10042 
}")
10043 
 
10044 
;; These patterns say how to save and restore the stack pointer.  We need not
10045 
;; save the stack pointer at function level since we are careful to
10046 
;; preserve the backchain.  At block level, we have to restore the backchain
10047 
;; when we restore the stack pointer.
10048 
;;
10049 
;; For nonlocal gotos, we must save both the stack pointer and its
10050 
;; backchain and restore both.  Note that in the nonlocal case, the
10051 
;; save area is a memory location.
10052 
 
10053 
(define_expand "save_stack_function"
10054 
  [(match_operand 0 "any_operand" "")
10055 
   (match_operand 1 "any_operand" "")]
10056 
  ""
10057 
  "DONE;")
10058 
 
10059 
(define_expand "restore_stack_function"
10060 
  [(match_operand 0 "any_operand" "")
10061 
   (match_operand 1 "any_operand" "")]
10062 
  ""
10063 
  "DONE;")
10064 
 
10065 
;; Adjust stack pointer (op0) to a new value (op1).
10066 
;; First copy old stack backchain to new location, and ensure that the
10067 
;; scheduler won't reorder the sp assignment before the backchain write.
10068 
(define_expand "restore_stack_block"
10069 
  [(set (match_dup 2) (match_dup 3))
10070 
   (set (match_dup 4) (match_dup 2))
10071 
   (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10072 
   (set (match_operand 0 "register_operand" "")
10073 
        (match_operand 1 "register_operand" ""))]
10074 
  ""
10075 
  "
10076 
{
10077 
  operands[2] = gen_reg_rtx (Pmode);
10078 
  operands[3] = gen_frame_mem (Pmode, operands[0]);
10079 
  operands[4] = gen_frame_mem (Pmode, operands[1]);
10080 
  operands[5] = gen_frame_mem (BLKmode, operands[0]);
10081 
}")
10082 
 
10083 
(define_expand "save_stack_nonlocal"
10084 
  [(set (match_dup 3) (match_dup 4))
10085 
   (set (match_operand 0 "memory_operand" "") (match_dup 3))
10086 
   (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10087 
  ""
10088 
  "
10089 
{
10090 
  int units_per_word = (TARGET_32BIT) ? 4 : 8;
10091 
 
10092 
  /* Copy the backchain to the first word, sp to the second.  */
10093 
  operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10094 
  operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10095 
  operands[3] = gen_reg_rtx (Pmode);
10096 
  operands[4] = gen_frame_mem (Pmode, operands[1]);
10097 
}")
10098 
 
10099 
(define_expand "restore_stack_nonlocal"
10100 
  [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10101 
   (set (match_dup 3) (match_dup 4))
10102 
   (set (match_dup 5) (match_dup 2))
10103 
   (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10104 
   (set (match_operand 0 "register_operand" "") (match_dup 3))]
10105 
  ""
10106 
  "
10107 
{
10108 
  int units_per_word = (TARGET_32BIT) ? 4 : 8;
10109 
 
10110 
  /* Restore the backchain from the first word, sp from the second.  */
10111 
  operands[2] = gen_reg_rtx (Pmode);
10112 
  operands[3] = gen_reg_rtx (Pmode);
10113 
  operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10114 
  operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10115 
  operands[5] = gen_frame_mem (Pmode, operands[3]);
10116 
  operands[6] = gen_frame_mem (BLKmode, operands[0]);
10117 
}")
10118 
 
10119 
;; TOC register handling.
10120 
 
10121 
;; Code to initialize the TOC register...
10122 
 
10123 
(define_insn "load_toc_aix_si"
10124 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10125 
                   (unspec:SI [(const_int 0)] UNSPEC_TOC))
10126 
              (use (reg:SI 2))])]
10127 
  "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10128 
  "*
10129 
{
10130 
  char buf[30];
10131 
  ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10132 
  operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10133 
  operands[2] = gen_rtx_REG (Pmode, 2);
10134 
  return \"{l|lwz} %0,%1(%2)\";
10135 
}"
10136 
  [(set_attr "type" "load")])
10137 
 
10138 
(define_insn "load_toc_aix_di"
10139 
  [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10140 
                   (unspec:DI [(const_int 0)] UNSPEC_TOC))
10141 
              (use (reg:DI 2))])]
10142 
  "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10143 
  "*
10144 
{
10145 
  char buf[30];
10146 
#ifdef TARGET_RELOCATABLE
10147 
  ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10148 
                               !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10149 
#else
10150 
  ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10151 
#endif
10152 
  if (TARGET_ELF)
10153 
    strcat (buf, \"@toc\");
10154 
  operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10155 
  operands[2] = gen_rtx_REG (Pmode, 2);
10156 
  return \"ld %0,%1(%2)\";
10157 
}"
10158 
  [(set_attr "type" "load")])
10159 
 
10160 
(define_insn "load_toc_v4_pic_si"
10161 
  [(set (match_operand:SI 0 "register_operand" "=l")
10162 
        (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10163 
  "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10164 
  "bl _GLOBAL_OFFSET_TABLE_@local-4"
10165 
  [(set_attr "type" "branch")
10166 
   (set_attr "length" "4")])
10167 
 
10168 
(define_insn "load_toc_v4_PIC_1"
10169 
  [(set (match_operand:SI 0 "register_operand" "=l")
10170 
        (match_operand:SI 1 "immediate_operand" "s"))
10171 
   (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10172 
  "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10173 
   && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10174 
  "bcl 20,31,%1\\n%1:"
10175 
  [(set_attr "type" "branch")
10176 
   (set_attr "length" "4")])
10177 
 
10178 
(define_insn "load_toc_v4_PIC_1b"
10179 
  [(set (match_operand:SI 0 "register_operand" "=l")
10180 
        (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10181 
                UNSPEC_TOCPTR))]
10182 
  "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10183 
  "bcl 20,31,$+8\\n\\t.long %1-$"
10184 
  [(set_attr "type" "branch")
10185 
   (set_attr "length" "8")])
10186 
 
10187 
(define_insn "load_toc_v4_PIC_2"
10188 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10189 
        (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10190 
                   (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10191 
                             (match_operand:SI 3 "immediate_operand" "s")))))]
10192 
  "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10193 
  "{l|lwz} %0,%2-%3(%1)"
10194 
  [(set_attr "type" "load")])
10195 
 
10196 
(define_insn "load_toc_v4_PIC_3b"
10197 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10198 
        (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10199 
                 (high:SI
10200 
                   (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10201 
                             (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10202 
  "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10203 
  "{cau|addis} %0,%1,%2-%3@ha")
10204 
 
10205 
(define_insn "load_toc_v4_PIC_3c"
10206 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10207 
        (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10208 
                   (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10209 
                             (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10210 
  "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10211 
  "{cal|addi} %0,%1,%2-%3@l")
10212 
 
10213 
;; If the TOC is shared over a translation unit, as happens with all
10214 
;; the kinds of PIC that we support, we need to restore the TOC
10215 
;; pointer only when jumping over units of translation.
10216 
;; On Darwin, we need to reload the picbase.
10217 
 
10218 
(define_expand "builtin_setjmp_receiver"
10219 
  [(use (label_ref (match_operand 0 "" "")))]
10220 
  "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10221 
   || (TARGET_TOC && TARGET_MINIMAL_TOC)
10222 
   || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10223 
  "
10224 
{
10225 
#if TARGET_MACHO
10226 
  if (DEFAULT_ABI == ABI_DARWIN)
10227 
    {
10228 
      const char *picbase = machopic_function_base_name ();
10229 
      rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10230 
      rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10231 
      rtx tmplabrtx;
10232 
      char tmplab[20];
10233 
 
10234 
      ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10235 
                                  CODE_LABEL_NUMBER (operands[0]));
10236 
      tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10237 
 
10238 
      emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10239 
      emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10240 
    }
10241 
  else
10242 
#endif
10243 
    rs6000_emit_load_toc_table (FALSE);
10244 
  DONE;
10245 
}")
10246 
 
10247 
;; Elf specific ways of loading addresses for non-PIC code.
10248 
;; The output of this could be r0, but we make a very strong
10249 
;; preference for a base register because it will usually
10250 
;; be needed there.
10251 
(define_insn "elf_high"
10252 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10253 
        (high:SI (match_operand 1 "" "")))]
10254 
  "TARGET_ELF && ! TARGET_64BIT"
10255 
  "{liu|lis} %0,%1@ha")
10256 
 
10257 
(define_insn "elf_low"
10258 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10259 
        (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10260 
                   (match_operand 2 "" "")))]
10261 
   "TARGET_ELF && ! TARGET_64BIT"
10262 
   "@
10263 
    {cal|la} %0,%2@l(%1)
10264 
    {ai|addic} %0,%1,%K2")
10265 
 
10266 
;; A function pointer under AIX is a pointer to a data area whose first word
10267 
;; contains the actual address of the function, whose second word contains a
10268 
;; pointer to its TOC, and whose third word contains a value to place in the
10269 
;; static chain register (r11).  Note that if we load the static chain, our
10270 
;; "trampoline" need not have any executable code.
10271 
 
10272 
(define_expand "call_indirect_aix32"
10273 
  [(set (match_dup 2)
10274 
        (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10275 
   (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10276 
        (reg:SI 2))
10277 
   (set (reg:SI 2)
10278 
        (mem:SI (plus:SI (match_dup 0)
10279 
                         (const_int 4))))
10280 
   (set (reg:SI 11)
10281 
        (mem:SI (plus:SI (match_dup 0)
10282 
                         (const_int 8))))
10283 
   (parallel [(call (mem:SI (match_dup 2))
10284 
                    (match_operand 1 "" ""))
10285 
              (use (reg:SI 2))
10286 
              (use (reg:SI 11))
10287 
              (set (reg:SI 2)
10288 
                   (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10289 
              (clobber (scratch:SI))])]
10290 
  "TARGET_32BIT"
10291 
  "
10292 
{ operands[2] = gen_reg_rtx (SImode); }")
10293 
 
10294 
(define_expand "call_indirect_aix64"
10295 
  [(set (match_dup 2)
10296 
        (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10297 
   (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10298 
        (reg:DI 2))
10299 
   (set (reg:DI 2)
10300 
        (mem:DI (plus:DI (match_dup 0)
10301 
                         (const_int 8))))
10302 
   (set (reg:DI 11)
10303 
        (mem:DI (plus:DI (match_dup 0)
10304 
                         (const_int 16))))
10305 
   (parallel [(call (mem:SI (match_dup 2))
10306 
                    (match_operand 1 "" ""))
10307 
              (use (reg:DI 2))
10308 
              (use (reg:DI 11))
10309 
              (set (reg:DI 2)
10310 
                   (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10311 
              (clobber (scratch:SI))])]
10312 
  "TARGET_64BIT"
10313 
  "
10314 
{ operands[2] = gen_reg_rtx (DImode); }")
10315 
 
10316 
(define_expand "call_value_indirect_aix32"
10317 
  [(set (match_dup 3)
10318 
        (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10319 
   (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10320 
        (reg:SI 2))
10321 
   (set (reg:SI 2)
10322 
        (mem:SI (plus:SI (match_dup 1)
10323 
                         (const_int 4))))
10324 
   (set (reg:SI 11)
10325 
        (mem:SI (plus:SI (match_dup 1)
10326 
                         (const_int 8))))
10327 
   (parallel [(set (match_operand 0 "" "")
10328 
                   (call (mem:SI (match_dup 3))
10329 
                         (match_operand 2 "" "")))
10330 
              (use (reg:SI 2))
10331 
              (use (reg:SI 11))
10332 
              (set (reg:SI 2)
10333 
                   (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10334 
              (clobber (scratch:SI))])]
10335 
  "TARGET_32BIT"
10336 
  "
10337 
{ operands[3] = gen_reg_rtx (SImode); }")
10338 
 
10339 
(define_expand "call_value_indirect_aix64"
10340 
  [(set (match_dup 3)
10341 
        (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10342 
   (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10343 
        (reg:DI 2))
10344 
   (set (reg:DI 2)
10345 
        (mem:DI (plus:DI (match_dup 1)
10346 
                         (const_int 8))))
10347 
   (set (reg:DI 11)
10348 
        (mem:DI (plus:DI (match_dup 1)
10349 
                         (const_int 16))))
10350 
   (parallel [(set (match_operand 0 "" "")
10351 
                   (call (mem:SI (match_dup 3))
10352 
                         (match_operand 2 "" "")))
10353 
              (use (reg:DI 2))
10354 
              (use (reg:DI 11))
10355 
              (set (reg:DI 2)
10356 
                   (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10357 
              (clobber (scratch:SI))])]
10358 
  "TARGET_64BIT"
10359 
  "
10360 
{ operands[3] = gen_reg_rtx (DImode); }")
10361 
 
10362 
;; Now the definitions for the call and call_value insns
10363 
(define_expand "call"
10364 
  [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10365 
                    (match_operand 1 "" ""))
10366 
              (use (match_operand 2 "" ""))
10367 
              (clobber (scratch:SI))])]
10368 
  ""
10369 
  "
10370 
{
10371 
#if TARGET_MACHO
10372 
  if (MACHOPIC_INDIRECT)
10373 
    operands[0] = machopic_indirect_call_target (operands[0]);
10374 
#endif
10375 
 
10376 
  gcc_assert (GET_CODE (operands[0]) == MEM);
10377 
  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10378 
 
10379 
  operands[0] = XEXP (operands[0], 0);
10380 
 
10381 
  if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10382 
      && flag_pic
10383 
      && GET_CODE (operands[0]) == SYMBOL_REF
10384 
      && !SYMBOL_REF_LOCAL_P (operands[0]))
10385 
    {
10386 
      rtx call;
10387 
      rtvec tmp;
10388 
 
10389 
      tmp = gen_rtvec (3,
10390 
                       gen_rtx_CALL (VOIDmode,
10391 
                                     gen_rtx_MEM (SImode, operands[0]),
10392 
                                     operands[1]),
10393 
                       gen_rtx_USE (VOIDmode, operands[2]),
10394 
                       gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10395 
      call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10396 
      use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10397 
      DONE;
10398 
    }
10399 
 
10400 
  if (GET_CODE (operands[0]) != SYMBOL_REF
10401 
      || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10402 
      || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10403 
    {
10404 
      if (INTVAL (operands[2]) & CALL_LONG)
10405 
        operands[0] = rs6000_longcall_ref (operands[0]);
10406 
 
10407 
      switch (DEFAULT_ABI)
10408 
        {
10409 
        case ABI_V4:
10410 
        case ABI_DARWIN:
10411 
          operands[0] = force_reg (Pmode, operands[0]);
10412 
          break;
10413 
 
10414 
        case ABI_AIX:
10415 
          /* AIX function pointers are really pointers to a three word
10416 
             area.  */
10417 
          emit_call_insn (TARGET_32BIT
10418 
                          ? gen_call_indirect_aix32 (force_reg (SImode,
10419 
                                                                operands[0]),
10420 
                                                     operands[1])
10421 
                          : gen_call_indirect_aix64 (force_reg (DImode,
10422 
                                                                operands[0]),
10423 
                                                     operands[1]));
10424 
          DONE;
10425 
 
10426 
        default:
10427 
          gcc_unreachable ();
10428 
        }
10429 
    }
10430 
}")
10431 
 
10432 
(define_expand "call_value"
10433 
  [(parallel [(set (match_operand 0 "" "")
10434 
                   (call (mem:SI (match_operand 1 "address_operand" ""))
10435 
                         (match_operand 2 "" "")))
10436 
              (use (match_operand 3 "" ""))
10437 
              (clobber (scratch:SI))])]
10438 
  ""
10439 
  "
10440 
{
10441 
#if TARGET_MACHO
10442 
  if (MACHOPIC_INDIRECT)
10443 
    operands[1] = machopic_indirect_call_target (operands[1]);
10444 
#endif
10445 
 
10446 
  gcc_assert (GET_CODE (operands[1]) == MEM);
10447 
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10448 
 
10449 
  operands[1] = XEXP (operands[1], 0);
10450 
 
10451 
  if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10452 
      && flag_pic
10453 
      && GET_CODE (operands[1]) == SYMBOL_REF
10454 
      && !SYMBOL_REF_LOCAL_P (operands[1]))
10455 
    {
10456 
      rtx call;
10457 
      rtvec tmp;
10458 
 
10459 
      tmp = gen_rtvec (3,
10460 
                       gen_rtx_SET (VOIDmode,
10461 
                                    operands[0],
10462 
                                    gen_rtx_CALL (VOIDmode,
10463 
                                                  gen_rtx_MEM (SImode,
10464 
                                                               operands[1]),
10465 
                                                  operands[2])),
10466 
                       gen_rtx_USE (VOIDmode, operands[3]),
10467 
                       gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10468 
      call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10469 
      use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10470 
      DONE;
10471 
    }
10472 
 
10473 
  if (GET_CODE (operands[1]) != SYMBOL_REF
10474 
      || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10475 
      || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10476 
    {
10477 
      if (INTVAL (operands[3]) & CALL_LONG)
10478 
        operands[1] = rs6000_longcall_ref (operands[1]);
10479 
 
10480 
      switch (DEFAULT_ABI)
10481 
        {
10482 
        case ABI_V4:
10483 
        case ABI_DARWIN:
10484 
          operands[1] = force_reg (Pmode, operands[1]);
10485 
          break;
10486 
 
10487 
        case ABI_AIX:
10488 
          /* AIX function pointers are really pointers to a three word
10489 
             area.  */
10490 
          emit_call_insn (TARGET_32BIT
10491 
                          ? gen_call_value_indirect_aix32 (operands[0],
10492 
                                                           force_reg (SImode,
10493 
                                                                      operands[1]),
10494 
                                                           operands[2])
10495 
                          : gen_call_value_indirect_aix64 (operands[0],
10496 
                                                           force_reg (DImode,
10497 
                                                                      operands[1]),
10498 
                                                           operands[2]));
10499 
          DONE;
10500 
 
10501 
        default:
10502 
          gcc_unreachable ();
10503 
        }
10504 
    }
10505 
}")
10506 
 
10507 
;; Call to function in current module.  No TOC pointer reload needed.
10508 
;; Operand2 is nonzero if we are using the V.4 calling sequence and
10509 
;; either the function was not prototyped, or it was prototyped as a
10510 
;; variable argument function.  It is > 0 if FP registers were passed
10511 
;; and < 0 if they were not.
10512 
 
10513 
(define_insn "*call_local32"
10514 
  [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10515 
         (match_operand 1 "" "g,g"))
10516 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
10517 
   (clobber (match_scratch:SI 3 "=l,l"))]
10518 
  "(INTVAL (operands[2]) & CALL_LONG) == 0"
10519 
  "*
10520 
{
10521 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10522 
    output_asm_insn (\"crxor 6,6,6\", operands);
10523 
 
10524 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10525 
    output_asm_insn (\"creqv 6,6,6\", operands);
10526 
 
10527 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10528 
}"
10529 
  [(set_attr "type" "branch")
10530 
   (set_attr "length" "4,8")])
10531 
 
10532 
(define_insn "*call_local64"
10533 
  [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10534 
         (match_operand 1 "" "g,g"))
10535 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
10536 
   (clobber (match_scratch:SI 3 "=l,l"))]
10537 
  "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10538 
  "*
10539 
{
10540 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10541 
    output_asm_insn (\"crxor 6,6,6\", operands);
10542 
 
10543 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10544 
    output_asm_insn (\"creqv 6,6,6\", operands);
10545 
 
10546 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10547 
}"
10548 
  [(set_attr "type" "branch")
10549 
   (set_attr "length" "4,8")])
10550 
 
10551 
(define_insn "*call_value_local32"
10552 
  [(set (match_operand 0 "" "")
10553 
        (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10554 
              (match_operand 2 "" "g,g")))
10555 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
10556 
   (clobber (match_scratch:SI 4 "=l,l"))]
10557 
  "(INTVAL (operands[3]) & CALL_LONG) == 0"
10558 
  "*
10559 
{
10560 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10561 
    output_asm_insn (\"crxor 6,6,6\", operands);
10562 
 
10563 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10564 
    output_asm_insn (\"creqv 6,6,6\", operands);
10565 
 
10566 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10567 
}"
10568 
  [(set_attr "type" "branch")
10569 
   (set_attr "length" "4,8")])
10570 
 
10571 
 
10572 
(define_insn "*call_value_local64"
10573 
  [(set (match_operand 0 "" "")
10574 
        (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10575 
              (match_operand 2 "" "g,g")))
10576 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
10577 
   (clobber (match_scratch:SI 4 "=l,l"))]
10578 
  "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10579 
  "*
10580 
{
10581 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10582 
    output_asm_insn (\"crxor 6,6,6\", operands);
10583 
 
10584 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10585 
    output_asm_insn (\"creqv 6,6,6\", operands);
10586 
 
10587 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10588 
}"
10589 
  [(set_attr "type" "branch")
10590 
   (set_attr "length" "4,8")])
10591 
 
10592 
;; Call to function which may be in another module.  Restore the TOC
10593 
;; pointer (r2) after the call unless this is System V.
10594 
;; Operand2 is nonzero if we are using the V.4 calling sequence and
10595 
;; either the function was not prototyped, or it was prototyped as a
10596 
;; variable argument function.  It is > 0 if FP registers were passed
10597 
;; and < 0 if they were not.
10598 
 
10599 
(define_insn "*call_indirect_nonlocal_aix32"
10600 
  [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10601 
         (match_operand 1 "" "g,g"))
10602 
   (use (reg:SI 2))
10603 
   (use (reg:SI 11))
10604 
   (set (reg:SI 2)
10605 
        (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10606 
   (clobber (match_scratch:SI 2 "=l,l"))]
10607 
  "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10608 
  "b%T0l\;{l|lwz} 2,20(1)"
10609 
  [(set_attr "type" "jmpreg")
10610 
   (set_attr "length" "8")])
10611 
 
10612 
(define_insn "*call_nonlocal_aix32"
10613 
  [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10614 
         (match_operand 1 "" "g"))
10615 
   (use (match_operand:SI 2 "immediate_operand" "O"))
10616 
   (clobber (match_scratch:SI 3 "=l"))]
10617 
  "TARGET_32BIT
10618 
   && DEFAULT_ABI == ABI_AIX
10619 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
10620 
  "bl %z0\;%."
10621 
  [(set_attr "type" "branch")
10622 
   (set_attr "length" "8")])
10623 
 
10624 
(define_insn "*call_indirect_nonlocal_aix64"
10625 
  [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10626 
         (match_operand 1 "" "g,g"))
10627 
   (use (reg:DI 2))
10628 
   (use (reg:DI 11))
10629 
   (set (reg:DI 2)
10630 
        (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10631 
   (clobber (match_scratch:SI 2 "=l,l"))]
10632 
  "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10633 
  "b%T0l\;ld 2,40(1)"
10634 
  [(set_attr "type" "jmpreg")
10635 
   (set_attr "length" "8")])
10636 
 
10637 
(define_insn "*call_nonlocal_aix64"
10638 
  [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10639 
         (match_operand 1 "" "g"))
10640 
   (use (match_operand:SI 2 "immediate_operand" "O"))
10641 
   (clobber (match_scratch:SI 3 "=l"))]
10642 
  "TARGET_64BIT
10643 
   && DEFAULT_ABI == ABI_AIX
10644 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
10645 
  "bl %z0\;%."
10646 
  [(set_attr "type" "branch")
10647 
   (set_attr "length" "8")])
10648 
 
10649 
(define_insn "*call_value_indirect_nonlocal_aix32"
10650 
  [(set (match_operand 0 "" "")
10651 
        (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10652 
              (match_operand 2 "" "g,g")))
10653 
   (use (reg:SI 2))
10654 
   (use (reg:SI 11))
10655 
   (set (reg:SI 2)
10656 
        (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10657 
   (clobber (match_scratch:SI 3 "=l,l"))]
10658 
  "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10659 
  "b%T1l\;{l|lwz} 2,20(1)"
10660 
  [(set_attr "type" "jmpreg")
10661 
   (set_attr "length" "8")])
10662 
 
10663 
(define_insn "*call_value_nonlocal_aix32"
10664 
  [(set (match_operand 0 "" "")
10665 
        (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10666 
              (match_operand 2 "" "g")))
10667 
   (use (match_operand:SI 3 "immediate_operand" "O"))
10668 
   (clobber (match_scratch:SI 4 "=l"))]
10669 
  "TARGET_32BIT
10670 
   && DEFAULT_ABI == ABI_AIX
10671 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
10672 
  "bl %z1\;%."
10673 
  [(set_attr "type" "branch")
10674 
   (set_attr "length" "8")])
10675 
 
10676 
(define_insn "*call_value_indirect_nonlocal_aix64"
10677 
  [(set (match_operand 0 "" "")
10678 
        (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10679 
              (match_operand 2 "" "g,g")))
10680 
   (use (reg:DI 2))
10681 
   (use (reg:DI 11))
10682 
   (set (reg:DI 2)
10683 
        (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10684 
   (clobber (match_scratch:SI 3 "=l,l"))]
10685 
  "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10686 
  "b%T1l\;ld 2,40(1)"
10687 
  [(set_attr "type" "jmpreg")
10688 
   (set_attr "length" "8")])
10689 
 
10690 
(define_insn "*call_value_nonlocal_aix64"
10691 
  [(set (match_operand 0 "" "")
10692 
        (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10693 
              (match_operand 2 "" "g")))
10694 
   (use (match_operand:SI 3 "immediate_operand" "O"))
10695 
   (clobber (match_scratch:SI 4 "=l"))]
10696 
  "TARGET_64BIT
10697 
   && DEFAULT_ABI == ABI_AIX
10698 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
10699 
  "bl %z1\;%."
10700 
  [(set_attr "type" "branch")
10701 
   (set_attr "length" "8")])
10702 
 
10703 
;; A function pointer under System V is just a normal pointer
10704 
;; operands[0] is the function pointer
10705 
;; operands[1] is the stack size to clean up
10706 
;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10707 
;; which indicates how to set cr1
10708 
 
10709 
(define_insn "*call_indirect_nonlocal_sysv"
10710 
  [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10711 
         (match_operand 1 "" "g,g,g,g"))
10712 
   (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10713 
   (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10714 
  "DEFAULT_ABI == ABI_V4
10715 
   || DEFAULT_ABI == ABI_DARWIN"
10716 
{
10717 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10718 
    output_asm_insn ("crxor 6,6,6", operands);
10719 
 
10720 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10721 
    output_asm_insn ("creqv 6,6,6", operands);
10722 
 
10723 
  return "b%T0l";
10724 
}
10725 
  [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10726 
   (set_attr "length" "4,4,8,8")])
10727 
 
10728 
(define_insn "*call_nonlocal_sysv"
10729 
  [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10730 
         (match_operand 1 "" "g,g"))
10731 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
10732 
   (clobber (match_scratch:SI 3 "=l,l"))]
10733 
  "(DEFAULT_ABI == ABI_DARWIN
10734 
   || (DEFAULT_ABI == ABI_V4
10735 
       && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10736 
{
10737 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10738 
    output_asm_insn ("crxor 6,6,6", operands);
10739 
 
10740 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10741 
    output_asm_insn ("creqv 6,6,6", operands);
10742 
 
10743 
#if TARGET_MACHO
10744 
  return output_call(insn, operands, 0, 2);
10745 
#else
10746 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
10747 
    {
10748 
      if (TARGET_SECURE_PLT && flag_pic == 2)
10749 
        /* The magic 32768 offset here and in the other sysv call insns
10750 
           corresponds to the offset of r30 in .got2, as given by LCTOC1.
10751 
           See sysv4.h:toc_section.  */
10752 
        return "bl %z0+32768@plt";
10753 
      else
10754 
        return "bl %z0@plt";
10755 
    }
10756 
  else
10757 
    return "bl %z0";
10758 
#endif
10759 
}
10760 
  [(set_attr "type" "branch,branch")
10761 
   (set_attr "length" "4,8")])
10762 
 
10763 
(define_insn "*call_value_indirect_nonlocal_sysv"
10764 
  [(set (match_operand 0 "" "")
10765 
        (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10766 
              (match_operand 2 "" "g,g,g,g")))
10767 
   (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10768 
   (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10769 
  "DEFAULT_ABI == ABI_V4
10770 
   || DEFAULT_ABI == ABI_DARWIN"
10771 
{
10772 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10773 
    output_asm_insn ("crxor 6,6,6", operands);
10774 
 
10775 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10776 
    output_asm_insn ("creqv 6,6,6", operands);
10777 
 
10778 
  return "b%T1l";
10779 
}
10780 
  [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10781 
   (set_attr "length" "4,4,8,8")])
10782 
 
10783 
(define_insn "*call_value_nonlocal_sysv"
10784 
  [(set (match_operand 0 "" "")
10785 
        (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10786 
              (match_operand 2 "" "g,g")))
10787 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
10788 
   (clobber (match_scratch:SI 4 "=l,l"))]
10789 
  "(DEFAULT_ABI == ABI_DARWIN
10790 
   || (DEFAULT_ABI == ABI_V4
10791 
       && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10792 
{
10793 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10794 
    output_asm_insn ("crxor 6,6,6", operands);
10795 
 
10796 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10797 
    output_asm_insn ("creqv 6,6,6", operands);
10798 
 
10799 
#if TARGET_MACHO
10800 
  return output_call(insn, operands, 1, 3);
10801 
#else
10802 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
10803 
    {
10804 
      if (TARGET_SECURE_PLT && flag_pic == 2)
10805 
        return "bl %z1+32768@plt";
10806 
      else
10807 
        return "bl %z1@plt";
10808 
    }
10809 
  else
10810 
    return "bl %z1";
10811 
#endif
10812 
}
10813 
  [(set_attr "type" "branch,branch")
10814 
   (set_attr "length" "4,8")])
10815 
 
10816 
;; Call subroutine returning any type.
10817 
(define_expand "untyped_call"
10818 
  [(parallel [(call (match_operand 0 "" "")
10819 
                    (const_int 0))
10820 
              (match_operand 1 "" "")
10821 
              (match_operand 2 "" "")])]
10822 
  ""
10823 
  "
10824 
{
10825 
  int i;
10826 
 
10827 
  emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10828 
 
10829 
  for (i = 0; i < XVECLEN (operands[2], 0); i++)
10830 
    {
10831 
      rtx set = XVECEXP (operands[2], 0, i);
10832 
      emit_move_insn (SET_DEST (set), SET_SRC (set));
10833 
    }
10834 
 
10835 
  /* The optimizer does not know that the call sets the function value
10836 
     registers we stored in the result block.  We avoid problems by
10837 
     claiming that all hard registers are used and clobbered at this
10838 
     point.  */
10839 
  emit_insn (gen_blockage ());
10840 
 
10841 
  DONE;
10842 
}")
10843 
 
10844 
;; sibling call patterns
10845 
(define_expand "sibcall"
10846 
  [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10847 
                    (match_operand 1 "" ""))
10848 
              (use (match_operand 2 "" ""))
10849 
              (use (match_operand 3 "" ""))
10850 
              (return)])]
10851 
  ""
10852 
  "
10853 
{
10854 
#if TARGET_MACHO
10855 
  if (MACHOPIC_INDIRECT)
10856 
    operands[0] = machopic_indirect_call_target (operands[0]);
10857 
#endif
10858 
 
10859 
  gcc_assert (GET_CODE (operands[0]) == MEM);
10860 
  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10861 
 
10862 
  operands[0] = XEXP (operands[0], 0);
10863 
  operands[3] = gen_reg_rtx (SImode);
10864 
 
10865 
}")
10866 
 
10867 
;; this and similar patterns must be marked as using LR, otherwise
10868 
;; dataflow will try to delete the store into it.  This is true
10869 
;; even when the actual reg to jump to is in CTR, when LR was
10870 
;; saved and restored around the PIC-setting BCL.
10871 
(define_insn "*sibcall_local32"
10872 
  [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10873 
         (match_operand 1 "" "g,g"))
10874 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
10875 
   (use (match_operand:SI 3 "register_operand" "l,l"))
10876 
   (return)]
10877 
  "(INTVAL (operands[2]) & CALL_LONG) == 0"
10878 
  "*
10879 
{
10880 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10881 
    output_asm_insn (\"crxor 6,6,6\", operands);
10882 
 
10883 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10884 
    output_asm_insn (\"creqv 6,6,6\", operands);
10885 
 
10886 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10887 
}"
10888 
  [(set_attr "type" "branch")
10889 
   (set_attr "length" "4,8")])
10890 
 
10891 
(define_insn "*sibcall_local64"
10892 
  [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10893 
         (match_operand 1 "" "g,g"))
10894 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
10895 
   (use (match_operand:SI 3 "register_operand" "l,l"))
10896 
   (return)]
10897 
  "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10898 
  "*
10899 
{
10900 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10901 
    output_asm_insn (\"crxor 6,6,6\", operands);
10902 
 
10903 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10904 
    output_asm_insn (\"creqv 6,6,6\", operands);
10905 
 
10906 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10907 
}"
10908 
  [(set_attr "type" "branch")
10909 
   (set_attr "length" "4,8")])
10910 
 
10911 
(define_insn "*sibcall_value_local32"
10912 
  [(set (match_operand 0 "" "")
10913 
        (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10914 
              (match_operand 2 "" "g,g")))
10915 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
10916 
   (use (match_operand:SI 4 "register_operand" "l,l"))
10917 
   (return)]
10918 
  "(INTVAL (operands[3]) & CALL_LONG) == 0"
10919 
  "*
10920 
{
10921 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10922 
    output_asm_insn (\"crxor 6,6,6\", operands);
10923 
 
10924 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10925 
    output_asm_insn (\"creqv 6,6,6\", operands);
10926 
 
10927 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10928 
}"
10929 
  [(set_attr "type" "branch")
10930 
   (set_attr "length" "4,8")])
10931 
 
10932 
 
10933 
(define_insn "*sibcall_value_local64"
10934 
  [(set (match_operand 0 "" "")
10935 
        (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10936 
              (match_operand 2 "" "g,g")))
10937 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
10938 
   (use (match_operand:SI 4 "register_operand" "l,l"))
10939 
   (return)]
10940 
  "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10941 
  "*
10942 
{
10943 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10944 
    output_asm_insn (\"crxor 6,6,6\", operands);
10945 
 
10946 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10947 
    output_asm_insn (\"creqv 6,6,6\", operands);
10948 
 
10949 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10950 
}"
10951 
  [(set_attr "type" "branch")
10952 
   (set_attr "length" "4,8")])
10953 
 
10954 
(define_insn "*sibcall_nonlocal_aix32"
10955 
  [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10956 
         (match_operand 1 "" "g"))
10957 
   (use (match_operand:SI 2 "immediate_operand" "O"))
10958 
   (use (match_operand:SI 3 "register_operand" "l"))
10959 
   (return)]
10960 
  "TARGET_32BIT
10961 
   && DEFAULT_ABI == ABI_AIX
10962 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
10963 
  "b %z0"
10964 
  [(set_attr "type" "branch")
10965 
   (set_attr "length" "4")])
10966 
 
10967 
(define_insn "*sibcall_nonlocal_aix64"
10968 
  [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10969 
         (match_operand 1 "" "g"))
10970 
   (use (match_operand:SI 2 "immediate_operand" "O"))
10971 
   (use (match_operand:SI 3 "register_operand" "l"))
10972 
   (return)]
10973 
  "TARGET_64BIT
10974 
   && DEFAULT_ABI == ABI_AIX
10975 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
10976 
  "b %z0"
10977 
  [(set_attr "type" "branch")
10978 
   (set_attr "length" "4")])
10979 
 
10980 
(define_insn "*sibcall_value_nonlocal_aix32"
10981 
  [(set (match_operand 0 "" "")
10982 
        (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10983 
              (match_operand 2 "" "g")))
10984 
   (use (match_operand:SI 3 "immediate_operand" "O"))
10985 
   (use (match_operand:SI 4 "register_operand" "l"))
10986 
   (return)]
10987 
  "TARGET_32BIT
10988 
   && DEFAULT_ABI == ABI_AIX
10989 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
10990 
  "b %z1"
10991 
  [(set_attr "type" "branch")
10992 
   (set_attr "length" "4")])
10993 
 
10994 
(define_insn "*sibcall_value_nonlocal_aix64"
10995 
  [(set (match_operand 0 "" "")
10996 
        (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10997 
              (match_operand 2 "" "g")))
10998 
   (use (match_operand:SI 3 "immediate_operand" "O"))
10999 
   (use (match_operand:SI 4 "register_operand" "l"))
11000 
   (return)]
11001 
  "TARGET_64BIT
11002 
   && DEFAULT_ABI == ABI_AIX
11003 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
11004 
  "b %z1"
11005 
  [(set_attr "type" "branch")
11006 
   (set_attr "length" "4")])
11007 
 
11008 
(define_insn "*sibcall_nonlocal_sysv"
11009 
  [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11010 
         (match_operand 1 "" ""))
11011 
   (use (match_operand 2 "immediate_operand" "O,n"))
11012 
   (use (match_operand:SI 3 "register_operand" "l,l"))
11013 
   (return)]
11014 
  "(DEFAULT_ABI == ABI_DARWIN
11015 
     || DEFAULT_ABI == ABI_V4)
11016 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
11017 
  "*
11018 
{
11019 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11020 
    output_asm_insn (\"crxor 6,6,6\", operands);
11021 
 
11022 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11023 
    output_asm_insn (\"creqv 6,6,6\", operands);
11024 
 
11025 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
11026 
    {
11027 
      if (TARGET_SECURE_PLT && flag_pic == 2)
11028 
        return \"b %z0+32768@plt\";
11029 
      else
11030 
        return \"b %z0@plt\";
11031 
    }
11032 
  else
11033 
    return \"b %z0\";
11034 
}"
11035 
  [(set_attr "type" "branch,branch")
11036 
   (set_attr "length" "4,8")])
11037 
 
11038 
(define_expand "sibcall_value"
11039 
  [(parallel [(set (match_operand 0 "register_operand" "")
11040 
                (call (mem:SI (match_operand 1 "address_operand" ""))
11041 
                      (match_operand 2 "" "")))
11042 
              (use (match_operand 3 "" ""))
11043 
              (use (match_operand 4 "" ""))
11044 
              (return)])]
11045 
  ""
11046 
  "
11047 
{
11048 
#if TARGET_MACHO
11049 
  if (MACHOPIC_INDIRECT)
11050 
    operands[1] = machopic_indirect_call_target (operands[1]);
11051 
#endif
11052 
 
11053 
  gcc_assert (GET_CODE (operands[1]) == MEM);
11054 
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11055 
 
11056 
  operands[1] = XEXP (operands[1], 0);
11057 
  operands[4] = gen_reg_rtx (SImode);
11058 
 
11059 
}")
11060 
 
11061 
(define_insn "*sibcall_value_nonlocal_sysv"
11062 
  [(set (match_operand 0 "" "")
11063 
        (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11064 
              (match_operand 2 "" "")))
11065 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
11066 
   (use (match_operand:SI 4 "register_operand" "l,l"))
11067 
   (return)]
11068 
  "(DEFAULT_ABI == ABI_DARWIN
11069 
       || DEFAULT_ABI == ABI_V4)
11070 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
11071 
  "*
11072 
{
11073 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11074 
    output_asm_insn (\"crxor 6,6,6\", operands);
11075 
 
11076 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11077 
    output_asm_insn (\"creqv 6,6,6\", operands);
11078 
 
11079 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
11080 
    {
11081 
      if (TARGET_SECURE_PLT && flag_pic == 2)
11082 
        return \"b %z1+32768@plt\";
11083 
      else
11084 
        return \"b %z1@plt\";
11085 
    }
11086 
  else
11087 
    return \"b %z1\";
11088 
}"
11089 
  [(set_attr "type" "branch,branch")
11090 
   (set_attr "length" "4,8")])
11091 
 
11092 
(define_expand "sibcall_epilogue"
11093 
  [(use (const_int 0))]
11094 
  "TARGET_SCHED_PROLOG"
11095 
  "
11096 
{
11097 
      rs6000_emit_epilogue (TRUE);
11098 
      DONE;
11099 
}")
11100 
 
11101 
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11102 
;; all of memory.  This blocks insns from being moved across this point.
11103 
 
11104 
(define_insn "blockage"
11105 
  [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11106 
  ""
11107 
  "")
11108 
 
11109 
;; Compare insns are next.  Note that the RS/6000 has two types of compares,
11110 
;; signed & unsigned, and one type of branch.
11111 
;;
11112 
;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11113 
;; insns, and branches.  We store the operands of compares until we see
11114 
;; how it is used.
11115 
(define_expand "cmp"
11116 
  [(set (cc0)
11117 
        (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11118 
                 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11119 
  ""
11120 
  "
11121 
{
11122 
  /* Take care of the possibility that operands[1] might be negative but
11123 
     this might be a logical operation.  That insn doesn't exist.  */
11124 
  if (GET_CODE (operands[1]) == CONST_INT
11125 
      && INTVAL (operands[1]) < 0)
11126 
    operands[1] = force_reg (mode, operands[1]);
11127 
 
11128 
  rs6000_compare_op0 = operands[0];
11129 
  rs6000_compare_op1 = operands[1];
11130 
  rs6000_compare_fp_p = 0;
11131 
  DONE;
11132 
}")
11133 
 
11134 
(define_expand "cmp"
11135 
  [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11136 
                       (match_operand:FP 1 "gpc_reg_operand" "")))]
11137 
  ""
11138 
  "
11139 
{
11140 
  rs6000_compare_op0 = operands[0];
11141 
  rs6000_compare_op1 = operands[1];
11142 
  rs6000_compare_fp_p = 1;
11143 
  DONE;
11144 
}")
11145 
 
11146 
(define_expand "beq"
11147 
  [(use (match_operand 0 "" ""))]
11148 
  ""
11149 
  "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11150 
 
11151 
(define_expand "bne"
11152 
  [(use (match_operand 0 "" ""))]
11153 
  ""
11154 
  "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11155 
 
11156 
(define_expand "bge"
11157 
  [(use (match_operand 0 "" ""))]
11158 
  ""
11159 
  "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11160 
 
11161 
(define_expand "bgt"
11162 
  [(use (match_operand 0 "" ""))]
11163 
  ""
11164 
  "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11165 
 
11166 
(define_expand "ble"
11167 
  [(use (match_operand 0 "" ""))]
11168 
  ""
11169 
  "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11170 
 
11171 
(define_expand "blt"
11172 
  [(use (match_operand 0 "" ""))]
11173 
  ""
11174 
  "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11175 
 
11176 
(define_expand "bgeu"
11177 
  [(use (match_operand 0 "" ""))]
11178 
  ""
11179 
  "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11180 
 
11181 
(define_expand "bgtu"
11182 
  [(use (match_operand 0 "" ""))]
11183 
  ""
11184 
  "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11185 
 
11186 
(define_expand "bleu"
11187 
  [(use (match_operand 0 "" ""))]
11188 
  ""
11189 
  "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11190 
 
11191 
(define_expand "bltu"
11192 
  [(use (match_operand 0 "" ""))]
11193 
  ""
11194 
  "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11195 
 
11196 
(define_expand "bunordered"
11197 
  [(use (match_operand 0 "" ""))]
11198 
  "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11199 
  "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11200 
 
11201 
(define_expand "bordered"
11202 
  [(use (match_operand 0 "" ""))]
11203 
  "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11204 
  "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11205 
 
11206 
(define_expand "buneq"
11207 
  [(use (match_operand 0 "" ""))]
11208 
  ""
11209 
  "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11210 
 
11211 
(define_expand "bunge"
11212 
  [(use (match_operand 0 "" ""))]
11213 
  ""
11214 
  "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11215 
 
11216 
(define_expand "bungt"
11217 
  [(use (match_operand 0 "" ""))]
11218 
  ""
11219 
  "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11220 
 
11221 
(define_expand "bunle"
11222 
  [(use (match_operand 0 "" ""))]
11223 
  ""
11224 
  "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11225 
 
11226 
(define_expand "bunlt"
11227 
  [(use (match_operand 0 "" ""))]
11228 
  ""
11229 
  "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11230 
 
11231 
(define_expand "bltgt"
11232 
  [(use (match_operand 0 "" ""))]
11233 
  ""
11234 
  "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11235 
 
11236 
;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11237 
;; For SEQ, likewise, except that comparisons with zero should be done
11238 
;; with an scc insns.  However, due to the order that combine see the
11239 
;; resulting insns, we must, in fact, allow SEQ for integers.  Fail in
11240 
;; the cases we don't want to handle.
11241 
(define_expand "seq"
11242 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11243 
  ""
11244 
  "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11245 
 
11246 
(define_expand "sne"
11247 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11248 
  ""
11249 
  "
11250 
{
11251 
  if (! rs6000_compare_fp_p)
11252 
    FAIL;
11253 
 
11254 
  rs6000_emit_sCOND (NE, operands[0]);
11255 
  DONE;
11256 
}")
11257 
 
11258 
;; A >= 0 is best done the portable way for A an integer.
11259 
(define_expand "sge"
11260 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11261 
  ""
11262 
  "
11263 
{
11264 
  if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11265 
    FAIL;
11266 
 
11267 
  rs6000_emit_sCOND (GE, operands[0]);
11268 
  DONE;
11269 
}")
11270 
 
11271 
;; A > 0 is best done using the portable sequence, so fail in that case.
11272 
(define_expand "sgt"
11273 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11274 
  ""
11275 
  "
11276 
{
11277 
  if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11278 
    FAIL;
11279 
 
11280 
  rs6000_emit_sCOND (GT, operands[0]);
11281 
  DONE;
11282 
}")
11283 
 
11284 
;; A <= 0 is best done the portable way for A an integer.
11285 
(define_expand "sle"
11286 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11287 
  ""
11288 
  "
11289 
{
11290 
  if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11291 
    FAIL;
11292 
 
11293 
  rs6000_emit_sCOND (LE, operands[0]);
11294 
  DONE;
11295 
}")
11296 
 
11297 
;; A < 0 is best done in the portable way for A an integer.
11298 
(define_expand "slt"
11299 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11300 
  ""
11301 
  "
11302 
{
11303 
  if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11304 
    FAIL;
11305 
 
11306 
  rs6000_emit_sCOND (LT, operands[0]);
11307 
  DONE;
11308 
}")
11309 
 
11310 
(define_expand "sgeu"
11311 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11312 
  ""
11313 
  "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11314 
 
11315 
(define_expand "sgtu"
11316 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11317 
  ""
11318 
  "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11319 
 
11320 
(define_expand "sleu"
11321 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11322 
  ""
11323 
  "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11324 
 
11325 
(define_expand "sltu"
11326 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11327 
  ""
11328 
  "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11329 
 
11330 
(define_expand "sunordered"
11331 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11332 
  "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11333 
  "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11334 
 
11335 
(define_expand "sordered"
11336 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11337 
  "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11338 
  "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11339 
 
11340 
(define_expand "suneq"
11341 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11342 
  ""
11343 
  "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11344 
 
11345 
(define_expand "sunge"
11346 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11347 
  ""
11348 
  "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11349 
 
11350 
(define_expand "sungt"
11351 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11352 
  ""
11353 
  "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11354 
 
11355 
(define_expand "sunle"
11356 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11357 
  ""
11358 
  "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11359 
 
11360 
(define_expand "sunlt"
11361 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11362 
  ""
11363 
  "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11364 
 
11365 
(define_expand "sltgt"
11366 
  [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11367 
  ""
11368 
  "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11369 
 
11370 
(define_expand "stack_protect_set"
11371 
  [(match_operand 0 "memory_operand" "")
11372 
   (match_operand 1 "memory_operand" "")]
11373 
  ""
11374 
{
11375 
#ifdef TARGET_THREAD_SSP_OFFSET
11376 
  rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11377 
  rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11378 
  operands[1] = gen_rtx_MEM (Pmode, addr);
11379 
#endif
11380 
  if (TARGET_64BIT)
11381 
    emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11382 
  else
11383 
    emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11384 
  DONE;
11385 
})
11386 
 
11387 
(define_insn "stack_protect_setsi"
11388 
  [(set (match_operand:SI 0 "memory_operand" "=m")
11389 
        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11390 
   (set (match_scratch:SI 2 "=&r") (const_int 0))]
11391 
  "TARGET_32BIT"
11392 
  "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11393 
  [(set_attr "type" "three")
11394 
   (set_attr "length" "12")])
11395 
 
11396 
(define_insn "stack_protect_setdi"
11397 
  [(set (match_operand:DI 0 "memory_operand" "=m")
11398 
        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11399 
   (set (match_scratch:DI 2 "=&r") (const_int 0))]
11400 
  "TARGET_64BIT"
11401 
  "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11402 
  [(set_attr "type" "three")
11403 
   (set_attr "length" "12")])
11404 
 
11405 
(define_expand "stack_protect_test"
11406 
  [(match_operand 0 "memory_operand" "")
11407 
   (match_operand 1 "memory_operand" "")
11408 
   (match_operand 2 "" "")]
11409 
  ""
11410 
{
11411 
#ifdef TARGET_THREAD_SSP_OFFSET
11412 
  rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11413 
  rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11414 
  operands[1] = gen_rtx_MEM (Pmode, addr);
11415 
#endif
11416 
  rs6000_compare_op0 = operands[0];
11417 
  rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11418 
                                       UNSPEC_SP_TEST);
11419 
  rs6000_compare_fp_p = 0;
11420 
  emit_jump_insn (gen_beq (operands[2]));
11421 
  DONE;
11422 
})
11423 
 
11424 
(define_insn "stack_protect_testsi"
11425 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11426 
        (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11427 
                      (match_operand:SI 2 "memory_operand" "m,m")]
11428 
                     UNSPEC_SP_TEST))
11429 
   (set (match_scratch:SI 4 "=r,r") (const_int 0))
11430 
   (clobber (match_scratch:SI 3 "=&r,&r"))]
11431 
  "TARGET_32BIT"
11432 
  "@
11433 
   {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11434 
   {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11435 
  [(set_attr "length" "16,20")])
11436 
 
11437 
(define_insn "stack_protect_testdi"
11438 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11439 
        (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11440 
                      (match_operand:DI 2 "memory_operand" "m,m")]
11441 
                     UNSPEC_SP_TEST))
11442 
   (set (match_scratch:DI 4 "=r,r") (const_int 0))
11443 
   (clobber (match_scratch:DI 3 "=&r,&r"))]
11444 
  "TARGET_64BIT"
11445 
  "@
11446 
   ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11447 
   ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11448 
  [(set_attr "length" "16,20")])
11449 
 
11450 
 
11451 
;; Here are the actual compare insns.
11452 
(define_insn "*cmp_internal1"
11453 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11454 
        (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11455 
                    (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11456 
  ""
11457 
  "{cmp%I2|cmp%I2} %0,%1,%2"
11458 
  [(set_attr "type" "cmp")])
11459 
 
11460 
;; If we are comparing a register for equality with a large constant,
11461 
;; we can do this with an XOR followed by a compare.  But this is profitable
11462 
;; only if the large constant is only used for the comparison (and in this
11463 
;; case we already have a register to reuse as scratch).
11464 
;;
11465 
;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11466 
;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11467 
 
11468 
(define_peephole2
11469 
  [(set (match_operand:SI 0 "register_operand")
11470 
        (match_operand:SI 1 "logical_const_operand" ""))
11471 
   (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11472 
                       [(match_dup 0)
11473 
                        (match_operand:SI 2 "logical_const_operand" "")]))
11474 
   (set (match_operand:CC 4 "cc_reg_operand" "")
11475 
        (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11476 
                    (match_dup 0)))
11477 
   (set (pc)
11478 
        (if_then_else (match_operator 6 "equality_operator"
11479 
                       [(match_dup 4) (const_int 0)])
11480 
                      (match_operand 7 "" "")
11481 
                      (match_operand 8 "" "")))]
11482 
  "peep2_reg_dead_p (3, operands[0])
11483 
   && peep2_reg_dead_p (4, operands[4])"
11484 
 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11485 
  (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11486 
  (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11487 
 
11488 
{
11489 
  /* Get the constant we are comparing against, and see what it looks like
11490 
     when sign-extended from 16 to 32 bits.  Then see what constant we could
11491 
     XOR with SEXTC to get the sign-extended value.  */
11492 
  rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11493 
                                              SImode,
11494 
                                              operands[1], operands[2]);
11495 
  HOST_WIDE_INT c = INTVAL (cnst);
11496 
  HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11497 
  HOST_WIDE_INT xorv = c ^ sextc;
11498 
 
11499 
  operands[9] = GEN_INT (xorv);
11500 
  operands[10] = GEN_INT (sextc);
11501 
})
11502 
 
11503 
(define_insn "*cmpsi_internal2"
11504 
  [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11505 
        (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11506 
                       (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11507 
  ""
11508 
  "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11509 
  [(set_attr "type" "cmp")])
11510 
 
11511 
(define_insn "*cmpdi_internal2"
11512 
  [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11513 
        (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11514 
                       (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11515 
  ""
11516 
  "cmpld%I2 %0,%1,%b2"
11517 
  [(set_attr "type" "cmp")])
11518 
 
11519 
;; The following two insns don't exist as single insns, but if we provide
11520 
;; them, we can swap an add and compare, which will enable us to overlap more
11521 
;; of the required delay between a compare and branch.  We generate code for
11522 
;; them by splitting.
11523 
 
11524 
(define_insn ""
11525 
  [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11526 
        (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11527 
                    (match_operand:SI 2 "short_cint_operand" "i")))
11528 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11529 
        (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11530 
  ""
11531 
  "#"
11532 
  [(set_attr "length" "8")])
11533 
 
11534 
(define_insn ""
11535 
  [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11536 
        (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11537 
                       (match_operand:SI 2 "u_short_cint_operand" "i")))
11538 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11539 
        (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11540 
  ""
11541 
  "#"
11542 
  [(set_attr "length" "8")])
11543 
 
11544 
(define_split
11545 
  [(set (match_operand:CC 3 "cc_reg_operand" "")
11546 
        (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11547 
                    (match_operand:SI 2 "short_cint_operand" "")))
11548 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
11549 
        (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11550 
  ""
11551 
  [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11552 
   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11553 
 
11554 
(define_split
11555 
  [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11556 
        (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11557 
                       (match_operand:SI 2 "u_short_cint_operand" "")))
11558 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
11559 
        (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11560 
  ""
11561 
  [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11562 
   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11563 
 
11564 
(define_insn "*cmpsf_internal1"
11565 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11566 
        (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11567 
                      (match_operand:SF 2 "gpc_reg_operand" "f")))]
11568 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
11569 
  "fcmpu %0,%1,%2"
11570 
  [(set_attr "type" "fpcompare")])
11571 
 
11572 
(define_insn "*cmpdf_internal1"
11573 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11574 
        (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11575 
                      (match_operand:DF 2 "gpc_reg_operand" "f")))]
11576 
  "TARGET_HARD_FLOAT && TARGET_FPRS"
11577 
  "fcmpu %0,%1,%2"
11578 
  [(set_attr "type" "fpcompare")])
11579 
 
11580 
;; Only need to compare second words if first words equal
11581 
(define_insn "*cmptf_internal1"
11582 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11583 
        (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11584 
                      (match_operand:TF 2 "gpc_reg_operand" "f")))]
11585 
  "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11586 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11587 
  "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11588 
  [(set_attr "type" "fpcompare")
11589 
   (set_attr "length" "12")])
11590 
 
11591 
(define_insn_and_split "*cmptf_internal2"
11592 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11593 
        (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11594 
                      (match_operand:TF 2 "gpc_reg_operand" "f")))
11595 
    (clobber (match_scratch:DF 3 "=f"))
11596 
    (clobber (match_scratch:DF 4 "=f"))
11597 
    (clobber (match_scratch:DF 5 "=f"))
11598 
    (clobber (match_scratch:DF 6 "=f"))
11599 
    (clobber (match_scratch:DF 7 "=f"))
11600 
    (clobber (match_scratch:DF 8 "=f"))
11601 
    (clobber (match_scratch:DF 9 "=f"))
11602 
    (clobber (match_scratch:DF 10 "=f"))]
11603 
  "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11604 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11605 
  "#"
11606 
  "&& reload_completed"
11607 
  [(set (match_dup 3) (match_dup 13))
11608 
   (set (match_dup 4) (match_dup 14))
11609 
   (set (match_dup 9) (abs:DF (match_dup 5)))
11610 
   (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11611 
   (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11612 
                           (label_ref (match_dup 11))
11613 
                           (pc)))
11614 
   (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11615 
   (set (pc) (label_ref (match_dup 12)))
11616 
   (match_dup 11)
11617 
   (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11618 
   (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11619 
   (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11620 
   (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11621 
   (match_dup 12)]
11622 
{
11623 
  REAL_VALUE_TYPE rv;
11624 
  const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11625 
  const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11626 
 
11627 
  operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11628 
  operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11629 
  operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11630 
  operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11631 
  operands[11] = gen_label_rtx ();
11632 
  operands[12] = gen_label_rtx ();
11633 
  real_inf (&rv);
11634 
  operands[13] = force_const_mem (DFmode,
11635 
                                  CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11636 
  operands[14] = force_const_mem (DFmode,
11637 
                                  CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11638 
                                                                DFmode));
11639 
  if (TARGET_TOC)
11640 
    {
11641 
      operands[13] = gen_const_mem (DFmode,
11642 
                                    create_TOC_reference (XEXP (operands[13], 0)));
11643 
      operands[14] = gen_const_mem (DFmode,
11644 
                                    create_TOC_reference (XEXP (operands[14], 0)));
11645 
      set_mem_alias_set (operands[13], get_TOC_alias_set ());
11646 
      set_mem_alias_set (operands[14], get_TOC_alias_set ());
11647 
    }
11648 
})
11649 
 
11650 
;; Now we have the scc insns.  We can do some combinations because of the
11651 
;; way the machine works.
11652 
;;
11653 
;; Note that this is probably faster if we can put an insn between the
11654 
;; mfcr and rlinm, but this is tricky.  Let's leave it for now.  In most
11655 
;; cases the insns below which don't use an intermediate CR field will
11656 
;; be used instead.
11657 
(define_insn ""
11658 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11659 
        (match_operator:SI 1 "scc_comparison_operator"
11660 
                           [(match_operand 2 "cc_reg_operand" "y")
11661 
                            (const_int 0)]))]
11662 
  ""
11663 
  "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11664 
  [(set (attr "type")
11665 
     (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11666 
                (const_string "mfcrf")
11667 
           ]
11668 
        (const_string "mfcr")))
11669 
   (set_attr "length" "8")])
11670 
 
11671 
;; Same as above, but get the GT bit.
11672 
(define_insn "move_from_CR_gt_bit"
11673 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11674 
        (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11675 
  "TARGET_E500"
11676 
  "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11677 
  [(set_attr "type" "mfcr")
11678 
   (set_attr "length" "8")])
11679 
 
11680 
;; Same as above, but get the OV/ORDERED bit.
11681 
(define_insn "move_from_CR_ov_bit"
11682 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11683 
        (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11684 
  "TARGET_ISEL"
11685 
  "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11686 
  [(set_attr "type" "mfcr")
11687 
   (set_attr "length" "8")])
11688 
 
11689 
(define_insn ""
11690 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11691 
        (match_operator:DI 1 "scc_comparison_operator"
11692 
                           [(match_operand 2 "cc_reg_operand" "y")
11693 
                            (const_int 0)]))]
11694 
  "TARGET_POWERPC64"
11695 
  "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11696 
  [(set (attr "type")
11697 
     (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11698 
                (const_string "mfcrf")
11699 
           ]
11700 
        (const_string "mfcr")))
11701 
   (set_attr "length" "8")])
11702 
 
11703 
(define_insn ""
11704 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11705 
        (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11706 
                                       [(match_operand 2 "cc_reg_operand" "y,y")
11707 
                                        (const_int 0)])
11708 
                    (const_int 0)))
11709 
   (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11710 
        (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11711 
  "TARGET_32BIT"
11712 
  "@
11713 
   mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11714 
   #"
11715 
  [(set_attr "type" "delayed_compare")
11716 
   (set_attr "length" "8,16")])
11717 
 
11718 
(define_split
11719 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11720 
        (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11721 
                                       [(match_operand 2 "cc_reg_operand" "")
11722 
                                        (const_int 0)])
11723 
                    (const_int 0)))
11724 
   (set (match_operand:SI 3 "gpc_reg_operand" "")
11725 
        (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11726 
  "TARGET_32BIT && reload_completed"
11727 
  [(set (match_dup 3)
11728 
        (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11729 
   (set (match_dup 0)
11730 
        (compare:CC (match_dup 3)
11731 
                    (const_int 0)))]
11732 
  "")
11733 
 
11734 
(define_insn ""
11735 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11736 
        (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11737 
                                      [(match_operand 2 "cc_reg_operand" "y")
11738 
                                       (const_int 0)])
11739 
                   (match_operand:SI 3 "const_int_operand" "n")))]
11740 
  ""
11741 
  "*
11742 
{
11743 
  int is_bit = ccr_bit (operands[1], 1);
11744 
  int put_bit = 31 - (INTVAL (operands[3]) & 31);
11745 
  int count;
11746 
 
11747 
  if (is_bit >= put_bit)
11748 
    count = is_bit - put_bit;
11749 
  else
11750 
    count = 32 - (put_bit - is_bit);
11751 
 
11752 
  operands[4] = GEN_INT (count);
11753 
  operands[5] = GEN_INT (put_bit);
11754 
 
11755 
  return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11756 
}"
11757 
  [(set (attr "type")
11758 
     (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11759 
                (const_string "mfcrf")
11760 
           ]
11761 
        (const_string "mfcr")))
11762 
   (set_attr "length" "8")])
11763 
 
11764 
(define_insn ""
11765 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11766 
        (compare:CC
11767 
         (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11768 
                                       [(match_operand 2 "cc_reg_operand" "y,y")
11769 
                                        (const_int 0)])
11770 
                    (match_operand:SI 3 "const_int_operand" "n,n"))
11771 
         (const_int 0)))
11772 
   (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11773 
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11774 
                   (match_dup 3)))]
11775 
  ""
11776 
  "*
11777 
{
11778 
  int is_bit = ccr_bit (operands[1], 1);
11779 
  int put_bit = 31 - (INTVAL (operands[3]) & 31);
11780 
  int count;
11781 
 
11782 
  /* Force split for non-cc0 compare.  */
11783 
  if (which_alternative == 1)
11784 
     return \"#\";
11785 
 
11786 
  if (is_bit >= put_bit)
11787 
    count = is_bit - put_bit;
11788 
  else
11789 
    count = 32 - (put_bit - is_bit);
11790 
 
11791 
  operands[5] = GEN_INT (count);
11792 
  operands[6] = GEN_INT (put_bit);
11793 
 
11794 
  return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11795 
}"
11796 
  [(set_attr "type" "delayed_compare")
11797 
   (set_attr "length" "8,16")])
11798 
 
11799 
(define_split
11800 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11801 
        (compare:CC
11802 
         (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11803 
                                       [(match_operand 2 "cc_reg_operand" "")
11804 
                                        (const_int 0)])
11805 
                    (match_operand:SI 3 "const_int_operand" ""))
11806 
         (const_int 0)))
11807 
   (set (match_operand:SI 4 "gpc_reg_operand" "")
11808 
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11809 
                   (match_dup 3)))]
11810 
  "reload_completed"
11811 
  [(set (match_dup 4)
11812 
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11813 
                   (match_dup 3)))
11814 
   (set (match_dup 0)
11815 
        (compare:CC (match_dup 4)
11816 
                    (const_int 0)))]
11817 
  "")
11818 
 
11819 
;; There is a 3 cycle delay between consecutive mfcr instructions
11820 
;; so it is useful to combine 2 scc instructions to use only one mfcr.
11821 
 
11822 
(define_peephole
11823 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11824 
        (match_operator:SI 1 "scc_comparison_operator"
11825 
                           [(match_operand 2 "cc_reg_operand" "y")
11826 
                            (const_int 0)]))
11827 
   (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11828 
        (match_operator:SI 4 "scc_comparison_operator"
11829 
                           [(match_operand 5 "cc_reg_operand" "y")
11830 
                            (const_int 0)]))]
11831 
  "REGNO (operands[2]) != REGNO (operands[5])"
11832 
  "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11833 
  [(set_attr "type" "mfcr")
11834 
   (set_attr "length" "12")])
11835 
 
11836 
(define_peephole
11837 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11838 
        (match_operator:DI 1 "scc_comparison_operator"
11839 
                           [(match_operand 2 "cc_reg_operand" "y")
11840 
                            (const_int 0)]))
11841 
   (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11842 
        (match_operator:DI 4 "scc_comparison_operator"
11843 
                           [(match_operand 5 "cc_reg_operand" "y")
11844 
                            (const_int 0)]))]
11845 
  "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11846 
  "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11847 
  [(set_attr "type" "mfcr")
11848 
   (set_attr "length" "12")])
11849 
 
11850 
;; There are some scc insns that can be done directly, without a compare.
11851 
;; These are faster because they don't involve the communications between
11852 
;; the FXU and branch units.   In fact, we will be replacing all of the
11853 
;; integer scc insns here or in the portable methods in emit_store_flag.
11854 
;;
11855 
;; Also support (neg (scc ..)) since that construct is used to replace
11856 
;; branches, (plus (scc ..) ..) since that construct is common and
11857 
;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11858 
;; cases where it is no more expensive than (neg (scc ..)).
11859 
 
11860 
;; Have reload force a constant into a register for the simple insns that
11861 
;; otherwise won't accept constants.  We do this because it is faster than
11862 
;; the cmp/mfcr sequence we would otherwise generate.
11863 
 
11864 
(define_mode_attr scc_eq_op2 [(SI "rKLI")
11865 
                              (DI "rKJI")])
11866 
 
11867 
(define_insn_and_split "*eq"
11868 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11869 
        (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11870 
                (match_operand:GPR 2 "scc_eq_operand" "")))]
11871 
  "!TARGET_POWER"
11872 
  "#"
11873 
  "!TARGET_POWER"
11874 
  [(set (match_dup 0)
11875 
        (clz:GPR (match_dup 3)))
11876 
   (set (match_dup 0)
11877 
        (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11878 
  {
11879 
    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11880 
      {
11881 
        /* Use output operand as intermediate.  */
11882 
        operands[3] = operands[0];
11883 
 
11884 
        if (logical_operand (operands[2], mode))
11885 
          emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11886 
                                  gen_rtx_XOR (mode,
11887 
                                               operands[1], operands[2])));
11888 
        else
11889 
          emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11890 
                                  gen_rtx_PLUS (mode, operands[1],
11891 
                                                negate_rtx (mode,
11892 
                                                            operands[2]))));
11893 
      }
11894 
    else
11895 
      operands[3] = operands[1];
11896 
 
11897 
    operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (mode)));
11898 
  })
11899 
 
11900 
(define_insn_and_split "*eq_compare"
11901 
  [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11902 
        (compare:CC
11903 
         (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11904 
               (match_operand:P 2 "scc_eq_operand" ""))
11905 
         (const_int 0)))
11906 
   (set (match_operand:P 0 "gpc_reg_operand" "=r")
11907 
        (eq:P (match_dup 1) (match_dup 2)))]
11908 
  "!TARGET_POWER && optimize_size"
11909 
  "#"
11910 
  "!TARGET_POWER && optimize_size"
11911 
  [(set (match_dup 0)
11912 
        (clz:P (match_dup 4)))
11913 
   (parallel [(set (match_dup 3)
11914 
                   (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11915 
                               (const_int 0)))
11916 
              (set (match_dup 0)
11917 
                   (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11918 
  {
11919 
    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11920 
      {
11921 
        /* Use output operand as intermediate.  */
11922 
        operands[4] = operands[0];
11923 
 
11924 
        if (logical_operand (operands[2], mode))
11925 
          emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11926 
                                  gen_rtx_XOR (mode,
11927 
                                               operands[1], operands[2])));
11928 
        else
11929 
          emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11930 
                                  gen_rtx_PLUS (mode, operands[1],
11931 
                                                negate_rtx (mode,
11932 
                                                            operands[2]))));
11933 
      }
11934 
    else
11935 
      operands[4] = operands[1];
11936 
 
11937 
    operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (mode)));
11938 
  })
11939 
 
11940 
(define_insn "*eqsi_power"
11941 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11942 
        (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11943 
               (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11944 
   (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11945 
  "TARGET_POWER"
11946 
  "@
11947 
   xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11948 
   {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11949 
   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11950 
   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11951 
   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11952 
  [(set_attr "type" "three,two,three,three,three")
11953 
   (set_attr "length" "12,8,12,12,12")])
11954 
 
11955 
;; We have insns of the form shown by the first define_insn below.  If
11956 
;; there is something inside the comparison operation, we must split it.
11957 
(define_split
11958 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
11959 
        (plus:SI (match_operator 1 "comparison_operator"
11960 
                                 [(match_operand:SI 2 "" "")
11961 
                                  (match_operand:SI 3
11962 
                                                    "reg_or_cint_operand" "")])
11963 
                 (match_operand:SI 4 "gpc_reg_operand" "")))
11964 
   (clobber (match_operand:SI 5 "register_operand" ""))]
11965 
  "! gpc_reg_operand (operands[2], SImode)"
11966 
  [(set (match_dup 5) (match_dup 2))
11967 
   (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11968 
                               (match_dup 4)))])
11969 
 
11970 
(define_insn "*plus_eqsi"
11971 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11972 
        (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11973 
                        (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11974 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11975 
  "TARGET_32BIT"
11976 
  "@
11977 
   xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11978 
   {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11979 
   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11980 
   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11981 
   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11982 
  [(set_attr "type" "three,two,three,three,three")
11983 
   (set_attr "length" "12,8,12,12,12")])
11984 
 
11985 
(define_insn "*compare_plus_eqsi"
11986 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11987 
        (compare:CC
11988 
         (plus:SI
11989 
          (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11990 
                 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11991 
          (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11992 
         (const_int 0)))
11993 
   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11994 
  "TARGET_32BIT && optimize_size"
11995 
  "@
11996 
   xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11997 
   {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11998 
   {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11999 
   {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12000 
   {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12001 
   #
12002 
   #
12003 
   #
12004 
   #
12005 
   #"
12006 
  [(set_attr "type" "compare")
12007 
   (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12008 
 
12009 
(define_split
12010 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12011 
        (compare:CC
12012 
         (plus:SI
12013 
          (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12014 
                 (match_operand:SI 2 "scc_eq_operand" ""))
12015 
          (match_operand:SI 3 "gpc_reg_operand" ""))
12016 
         (const_int 0)))
12017 
   (clobber (match_scratch:SI 4 ""))]
12018 
  "TARGET_32BIT && optimize_size && reload_completed"
12019 
  [(set (match_dup 4)
12020 
        (plus:SI (eq:SI (match_dup 1)
12021 
                 (match_dup 2))
12022 
          (match_dup 3)))
12023 
   (set (match_dup 0)
12024 
        (compare:CC (match_dup 4)
12025 
                    (const_int 0)))]
12026 
  "")
12027 
 
12028 
(define_insn "*plus_eqsi_compare"
12029 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12030 
        (compare:CC
12031 
         (plus:SI
12032 
          (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12033 
                 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12034 
          (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12035 
         (const_int 0)))
12036 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12037 
        (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12038 
  "TARGET_32BIT && optimize_size"
12039 
  "@
12040 
   xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12041 
   {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12042 
   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12043 
   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12044 
   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12045 
   #
12046 
   #
12047 
   #
12048 
   #
12049 
   #"
12050 
  [(set_attr "type" "compare")
12051 
   (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12052 
 
12053 
(define_split
12054 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12055 
        (compare:CC
12056 
         (plus:SI
12057 
          (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12058 
                 (match_operand:SI 2 "scc_eq_operand" ""))
12059 
          (match_operand:SI 3 "gpc_reg_operand" ""))
12060 
         (const_int 0)))
12061 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12062 
        (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12063 
  "TARGET_32BIT && optimize_size && reload_completed"
12064 
  [(set (match_dup 0)
12065 
        (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12066 
   (set (match_dup 4)
12067 
        (compare:CC (match_dup 0)
12068 
                    (const_int 0)))]
12069 
  "")
12070 
 
12071 
(define_insn "*neg_eq0"
12072 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12073 
        (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12074 
                     (const_int 0))))]
12075 
  ""
12076 
  "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12077 
  [(set_attr "type" "two")
12078 
   (set_attr "length" "8")])
12079 
 
12080 
(define_insn_and_split "*neg_eq"
12081 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12082 
        (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12083 
                     (match_operand:P 2 "scc_eq_operand" ""))))]
12084 
  ""
12085 
  "#"
12086 
  ""
12087 
  [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12088 
  {
12089 
    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12090 
      {
12091 
        /* Use output operand as intermediate.  */
12092 
        operands[3] = operands[0];
12093 
 
12094 
        if (logical_operand (operands[2], mode))
12095 
          emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12096 
                                  gen_rtx_XOR (mode,
12097 
                                               operands[1], operands[2])));
12098 
        else
12099 
          emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12100 
                                  gen_rtx_PLUS (mode, operands[1],
12101 
                                                negate_rtx (mode,
12102 
                                                            operands[2]))));
12103 
      }
12104 
    else
12105 
      operands[3] = operands[1];
12106 
  })
12107 
 
12108 
;; Simplify (ne X (const_int 0)) on the PowerPC.  No need to on the Power,
12109 
;; since it nabs/sr is just as fast.
12110 
(define_insn "*ne0si"
12111 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12112 
        (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12113 
                     (const_int 31)))
12114 
   (clobber (match_scratch:SI 2 "=&r"))]
12115 
  "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12116 
  "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12117 
  [(set_attr "type" "two")
12118 
   (set_attr "length" "8")])
12119 
 
12120 
(define_insn "*ne0di"
12121 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12122 
        (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12123 
                     (const_int 63)))
12124 
   (clobber (match_scratch:DI 2 "=&r"))]
12125 
  "TARGET_64BIT"
12126 
  "addic %2,%1,-1\;subfe %0,%2,%1"
12127 
  [(set_attr "type" "two")
12128 
   (set_attr "length" "8")])
12129 
 
12130 
;; This is what (plus (ne X (const_int 0)) Y) looks like.
12131 
(define_insn "*plus_ne0si"
12132 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12133 
        (plus:SI (lshiftrt:SI
12134 
                  (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12135 
                  (const_int 31))
12136 
                 (match_operand:SI 2 "gpc_reg_operand" "r")))
12137 
   (clobber (match_scratch:SI 3 "=&r"))]
12138 
  "TARGET_32BIT"
12139 
  "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12140 
  [(set_attr "type" "two")
12141 
   (set_attr "length" "8")])
12142 
 
12143 
(define_insn "*plus_ne0di"
12144 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12145 
        (plus:DI (lshiftrt:DI
12146 
                  (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12147 
                  (const_int 63))
12148 
                 (match_operand:DI 2 "gpc_reg_operand" "r")))
12149 
   (clobber (match_scratch:DI 3 "=&r"))]
12150 
  "TARGET_64BIT"
12151 
  "addic %3,%1,-1\;addze %0,%2"
12152 
  [(set_attr "type" "two")
12153 
   (set_attr "length" "8")])
12154 
 
12155 
(define_insn "*compare_plus_ne0si"
12156 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12157 
        (compare:CC
12158 
         (plus:SI (lshiftrt:SI
12159 
                   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12160 
                   (const_int 31))
12161 
                  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12162 
         (const_int 0)))
12163 
   (clobber (match_scratch:SI 3 "=&r,&r"))
12164 
   (clobber (match_scratch:SI 4 "=X,&r"))]
12165 
  "TARGET_32BIT"
12166 
  "@
12167 
   {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12168 
   #"
12169 
  [(set_attr "type" "compare")
12170 
   (set_attr "length" "8,12")])
12171 
 
12172 
(define_split
12173 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12174 
        (compare:CC
12175 
         (plus:SI (lshiftrt:SI
12176 
                   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12177 
                   (const_int 31))
12178 
                  (match_operand:SI 2 "gpc_reg_operand" ""))
12179 
         (const_int 0)))
12180 
   (clobber (match_scratch:SI 3 ""))
12181 
   (clobber (match_scratch:SI 4 ""))]
12182 
  "TARGET_32BIT && reload_completed"
12183 
  [(parallel [(set (match_dup 3)
12184 
                   (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12185 
                                         (const_int 31))
12186 
                            (match_dup 2)))
12187 
              (clobber (match_dup 4))])
12188 
   (set (match_dup 0)
12189 
        (compare:CC (match_dup 3)
12190 
                    (const_int 0)))]
12191 
  "")
12192 
 
12193 
(define_insn "*compare_plus_ne0di"
12194 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12195 
        (compare:CC
12196 
         (plus:DI (lshiftrt:DI
12197 
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12198 
                   (const_int 63))
12199 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12200 
         (const_int 0)))
12201 
   (clobber (match_scratch:DI 3 "=&r,&r"))]
12202 
  "TARGET_64BIT"
12203 
  "@
12204 
   addic %3,%1,-1\;addze. %3,%2
12205 
   #"
12206 
  [(set_attr "type" "compare")
12207 
   (set_attr "length" "8,12")])
12208 
 
12209 
(define_split
12210 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12211 
        (compare:CC
12212 
         (plus:DI (lshiftrt:DI
12213 
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12214 
                   (const_int 63))
12215 
                  (match_operand:DI 2 "gpc_reg_operand" ""))
12216 
         (const_int 0)))
12217 
   (clobber (match_scratch:DI 3 ""))]
12218 
  "TARGET_64BIT && reload_completed"
12219 
  [(set (match_dup 3)
12220 
        (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12221 
                   (const_int 63))
12222 
                  (match_dup 2)))
12223 
   (set (match_dup 0)
12224 
        (compare:CC (match_dup 3)
12225 
                    (const_int 0)))]
12226 
  "")
12227 
 
12228 
(define_insn "*plus_ne0si_compare"
12229 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12230 
        (compare:CC
12231 
         (plus:SI (lshiftrt:SI
12232 
                   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12233 
                   (const_int 31))
12234 
                  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12235 
         (const_int 0)))
12236 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12237 
        (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12238 
                 (match_dup 2)))
12239 
   (clobber (match_scratch:SI 3 "=&r,&r"))]
12240 
  "TARGET_32BIT"
12241 
  "@
12242 
   {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12243 
   #"
12244 
  [(set_attr "type" "compare")
12245 
   (set_attr "length" "8,12")])
12246 
 
12247 
(define_split
12248 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12249 
        (compare:CC
12250 
         (plus:SI (lshiftrt:SI
12251 
                   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12252 
                   (const_int 31))
12253 
                  (match_operand:SI 2 "gpc_reg_operand" ""))
12254 
         (const_int 0)))
12255 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12256 
        (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12257 
                 (match_dup 2)))
12258 
   (clobber (match_scratch:SI 3 ""))]
12259 
  "TARGET_32BIT && reload_completed"
12260 
  [(parallel [(set (match_dup 0)
12261 
        (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12262 
                 (match_dup 2)))
12263 
   (clobber (match_dup 3))])
12264 
   (set (match_dup 4)
12265 
        (compare:CC (match_dup 0)
12266 
                    (const_int 0)))]
12267 
  "")
12268 
 
12269 
(define_insn "*plus_ne0di_compare"
12270 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12271 
        (compare:CC
12272 
         (plus:DI (lshiftrt:DI
12273 
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12274 
                   (const_int 63))
12275 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12276 
         (const_int 0)))
12277 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12278 
        (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12279 
                 (match_dup 2)))
12280 
   (clobber (match_scratch:DI 3 "=&r,&r"))]
12281 
  "TARGET_64BIT"
12282 
  "@
12283 
   addic %3,%1,-1\;addze. %0,%2
12284 
   #"
12285 
  [(set_attr "type" "compare")
12286 
   (set_attr "length" "8,12")])
12287 
 
12288 
(define_split
12289 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12290 
        (compare:CC
12291 
         (plus:DI (lshiftrt:DI
12292 
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12293 
                   (const_int 63))
12294 
                  (match_operand:DI 2 "gpc_reg_operand" ""))
12295 
         (const_int 0)))
12296 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
12297 
        (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12298 
                 (match_dup 2)))
12299 
   (clobber (match_scratch:DI 3 ""))]
12300 
  "TARGET_64BIT && reload_completed"
12301 
  [(parallel [(set (match_dup 0)
12302 
        (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12303 
                 (match_dup 2)))
12304 
   (clobber (match_dup 3))])
12305 
   (set (match_dup 4)
12306 
        (compare:CC (match_dup 0)
12307 
                    (const_int 0)))]
12308 
  "")
12309 
 
12310 
(define_insn ""
12311 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12312 
        (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12313 
               (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12314 
   (clobber (match_scratch:SI 3 "=r,X"))]
12315 
  "TARGET_POWER"
12316 
  "@
12317 
   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12318 
   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12319 
  [(set_attr "length" "12")])
12320 
 
12321 
(define_insn ""
12322 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12323 
        (compare:CC
12324 
         (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12325 
                (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12326 
         (const_int 0)))
12327 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12328 
        (le:SI (match_dup 1) (match_dup 2)))
12329 
   (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12330 
  "TARGET_POWER"
12331 
  "@
12332 
   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12333 
   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12334 
   #
12335 
   #"
12336 
  [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12337 
   (set_attr "length" "12,12,16,16")])
12338 
 
12339 
(define_split
12340 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12341 
        (compare:CC
12342 
         (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12343 
                (match_operand:SI 2 "reg_or_short_operand" ""))
12344 
         (const_int 0)))
12345 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12346 
        (le:SI (match_dup 1) (match_dup 2)))
12347 
   (clobber (match_scratch:SI 3 ""))]
12348 
  "TARGET_POWER && reload_completed"
12349 
  [(parallel [(set (match_dup 0)
12350 
        (le:SI (match_dup 1) (match_dup 2)))
12351 
   (clobber (match_dup 3))])
12352 
   (set (match_dup 4)
12353 
        (compare:CC (match_dup 0)
12354 
                    (const_int 0)))]
12355 
  "")
12356 
 
12357 
(define_insn ""
12358 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12359 
        (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12360 
                        (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12361 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12362 
  "TARGET_POWER"
12363 
  "@
12364 
   doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12365 
   {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12366 
  [(set_attr "length" "12")])
12367 
 
12368 
(define_insn ""
12369 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12370 
        (compare:CC
12371 
         (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12372 
                         (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12373 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12374 
         (const_int 0)))
12375 
   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12376 
  "TARGET_POWER"
12377 
  "@
12378 
   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12379 
   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12380 
   #
12381 
   #"
12382 
  [(set_attr "type" "compare")
12383 
   (set_attr "length" "12,12,16,16")])
12384 
 
12385 
(define_split
12386 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12387 
        (compare:CC
12388 
         (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12389 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
12390 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
12391 
         (const_int 0)))
12392 
   (clobber (match_scratch:SI 4 ""))]
12393 
  "TARGET_POWER && reload_completed"
12394 
  [(set (match_dup 4)
12395 
        (plus:SI (le:SI (match_dup 1) (match_dup 2))
12396 
                 (match_dup 3)))
12397 
   (set (match_dup 0)
12398 
        (compare:CC (match_dup 4)
12399 
                    (const_int 0)))]
12400 
  "")
12401 
 
12402 
(define_insn ""
12403 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12404 
        (compare:CC
12405 
         (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12406 
                         (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12407 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12408 
         (const_int 0)))
12409 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12410 
        (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12411 
  "TARGET_POWER"
12412 
  "@
12413 
   doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12414 
   {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12415 
   #
12416 
   #"
12417 
  [(set_attr "type" "compare")
12418 
   (set_attr "length" "12,12,16,16")])
12419 
 
12420 
(define_split
12421 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12422 
        (compare:CC
12423 
         (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12424 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
12425 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
12426 
         (const_int 0)))
12427 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12428 
        (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12429 
  "TARGET_POWER && reload_completed"
12430 
  [(set (match_dup 0)
12431 
        (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12432 
   (set (match_dup 4)
12433 
        (compare:CC (match_dup 0)
12434 
                    (const_int 0)))]
12435 
  "")
12436 
 
12437 
(define_insn ""
12438 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12439 
        (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12440 
                       (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12441 
  "TARGET_POWER"
12442 
  "@
12443 
   doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12444 
   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12445 
  [(set_attr "length" "12")])
12446 
 
12447 
(define_insn "*leu"
12448 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12449 
        (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12450 
               (match_operand:P 2 "reg_or_short_operand" "rI")))]
12451 
  ""
12452 
  "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12453 
  [(set_attr "type" "three")
12454 
   (set_attr "length" "12")])
12455 
 
12456 
(define_insn "*leu_compare"
12457 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12458 
        (compare:CC
12459 
         (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12460 
                (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12461 
         (const_int 0)))
12462 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12463 
        (leu:P (match_dup 1) (match_dup 2)))]
12464 
  ""
12465 
  "@
12466 
   {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12467 
   #"
12468 
  [(set_attr "type" "compare")
12469 
   (set_attr "length" "12,16")])
12470 
 
12471 
(define_split
12472 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12473 
        (compare:CC
12474 
         (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12475 
                (match_operand:P 2 "reg_or_short_operand" ""))
12476 
         (const_int 0)))
12477 
   (set (match_operand:P 0 "gpc_reg_operand" "")
12478 
        (leu:P (match_dup 1) (match_dup 2)))]
12479 
  "reload_completed"
12480 
  [(set (match_dup 0)
12481 
        (leu:P (match_dup 1) (match_dup 2)))
12482 
   (set (match_dup 3)
12483 
        (compare:CC (match_dup 0)
12484 
                    (const_int 0)))]
12485 
  "")
12486 
 
12487 
(define_insn "*plus_leu"
12488 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12489 
        (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12490 
                       (match_operand:P 2 "reg_or_short_operand" "rI"))
12491 
                (match_operand:P 3 "gpc_reg_operand" "r")))]
12492 
  ""
12493 
  "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12494 
  [(set_attr "type" "two")
12495 
   (set_attr "length" "8")])
12496 
 
12497 
(define_insn ""
12498 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12499 
        (compare:CC
12500 
         (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12501 
                          (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12502 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12503 
         (const_int 0)))
12504 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
12505 
  "TARGET_32BIT"
12506 
  "@
12507 
   {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12508 
   #"
12509 
  [(set_attr "type" "compare")
12510 
   (set_attr "length" "8,12")])
12511 
 
12512 
(define_split
12513 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12514 
        (compare:CC
12515 
         (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12516 
                          (match_operand:SI 2 "reg_or_short_operand" ""))
12517 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
12518 
         (const_int 0)))
12519 
   (clobber (match_scratch:SI 4 ""))]
12520 
  "TARGET_32BIT && reload_completed"
12521 
  [(set (match_dup 4)
12522 
        (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12523 
                  (match_dup 3)))
12524 
   (set (match_dup 0)
12525 
        (compare:CC (match_dup 4)
12526 
                    (const_int 0)))]
12527 
  "")
12528 
 
12529 
(define_insn ""
12530 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12531 
        (compare:CC
12532 
         (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12533 
                          (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12534 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12535 
         (const_int 0)))
12536 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12537 
        (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12538 
  "TARGET_32BIT"
12539 
  "@
12540 
   {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12541 
   #"
12542 
  [(set_attr "type" "compare")
12543 
   (set_attr "length" "8,12")])
12544 
 
12545 
(define_split
12546 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12547 
        (compare:CC
12548 
         (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12549 
                          (match_operand:SI 2 "reg_or_short_operand" ""))
12550 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
12551 
         (const_int 0)))
12552 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12553 
        (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12554 
  "TARGET_32BIT && reload_completed"
12555 
  [(set (match_dup 0)
12556 
        (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12557 
   (set (match_dup 4)
12558 
        (compare:CC (match_dup 0)
12559 
                    (const_int 0)))]
12560 
  "")
12561 
 
12562 
(define_insn "*neg_leu"
12563 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12564 
        (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12565 
                      (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12566 
  ""
12567 
  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12568 
   [(set_attr "type" "three")
12569 
    (set_attr "length" "12")])
12570 
 
12571 
(define_insn "*and_neg_leu"
12572 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12573 
        (and:P (neg:P
12574 
                 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12575 
                        (match_operand:P 2 "reg_or_short_operand" "rI")))
12576 
                (match_operand:P 3 "gpc_reg_operand" "r")))]
12577 
  ""
12578 
  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12579 
  [(set_attr "type" "three")
12580 
   (set_attr "length" "12")])
12581 
 
12582 
(define_insn ""
12583 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12584 
        (compare:CC
12585 
         (and:SI (neg:SI
12586 
                  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12587 
                          (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12588 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12589 
         (const_int 0)))
12590 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
12591 
  "TARGET_32BIT"
12592 
  "@
12593 
   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12594 
   #"
12595 
  [(set_attr "type" "compare")
12596 
   (set_attr "length" "12,16")])
12597 
 
12598 
(define_split
12599 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12600 
        (compare:CC
12601 
         (and:SI (neg:SI
12602 
                  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12603 
                          (match_operand:SI 2 "reg_or_short_operand" "")))
12604 
                 (match_operand:SI 3 "gpc_reg_operand" ""))
12605 
         (const_int 0)))
12606 
   (clobber (match_scratch:SI 4 ""))]
12607 
  "TARGET_32BIT && reload_completed"
12608 
  [(set (match_dup 4)
12609 
        (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12610 
                (match_dup 3)))
12611 
   (set (match_dup 0)
12612 
        (compare:CC (match_dup 4)
12613 
                    (const_int 0)))]
12614 
  "")
12615 
 
12616 
(define_insn ""
12617 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12618 
        (compare:CC
12619 
         (and:SI (neg:SI
12620 
                  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12621 
                          (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12622 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12623 
         (const_int 0)))
12624 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12625 
        (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12626 
  "TARGET_32BIT"
12627 
  "@
12628 
   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12629 
   #"
12630 
  [(set_attr "type" "compare")
12631 
   (set_attr "length" "12,16")])
12632 
 
12633 
(define_split
12634 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12635 
        (compare:CC
12636 
         (and:SI (neg:SI
12637 
                  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12638 
                          (match_operand:SI 2 "reg_or_short_operand" "")))
12639 
                 (match_operand:SI 3 "gpc_reg_operand" ""))
12640 
         (const_int 0)))
12641 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12642 
        (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12643 
  "TARGET_32BIT && reload_completed"
12644 
  [(set (match_dup 0)
12645 
        (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12646 
                (match_dup 3)))
12647 
   (set (match_dup 4)
12648 
        (compare:CC (match_dup 0)
12649 
                    (const_int 0)))]
12650 
  "")
12651 
 
12652 
(define_insn ""
12653 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12654 
        (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12655 
               (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12656 
  "TARGET_POWER"
12657 
  "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12658 
   [(set_attr "length" "12")])
12659 
 
12660 
(define_insn ""
12661 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12662 
        (compare:CC
12663 
         (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12664 
                (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12665 
         (const_int 0)))
12666 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12667 
        (lt:SI (match_dup 1) (match_dup 2)))]
12668 
  "TARGET_POWER"
12669 
  "@
12670 
   doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12671 
   #"
12672 
  [(set_attr "type" "delayed_compare")
12673 
   (set_attr "length" "12,16")])
12674 
 
12675 
(define_split
12676 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12677 
        (compare:CC
12678 
         (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12679 
                (match_operand:SI 2 "reg_or_short_operand" ""))
12680 
         (const_int 0)))
12681 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12682 
        (lt:SI (match_dup 1) (match_dup 2)))]
12683 
  "TARGET_POWER && reload_completed"
12684 
  [(set (match_dup 0)
12685 
        (lt:SI (match_dup 1) (match_dup 2)))
12686 
   (set (match_dup 3)
12687 
        (compare:CC (match_dup 0)
12688 
                    (const_int 0)))]
12689 
  "")
12690 
 
12691 
(define_insn ""
12692 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12693 
        (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12694 
                        (match_operand:SI 2 "reg_or_short_operand" "rI"))
12695 
                 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12696 
  "TARGET_POWER"
12697 
  "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12698 
  [(set_attr "length" "12")])
12699 
 
12700 
(define_insn ""
12701 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12702 
        (compare:CC
12703 
         (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12704 
                         (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12705 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12706 
         (const_int 0)))
12707 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
12708 
  "TARGET_POWER"
12709 
  "@
12710 
   doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12711 
   #"
12712 
  [(set_attr "type" "compare")
12713 
   (set_attr "length" "12,16")])
12714 
 
12715 
(define_split
12716 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12717 
        (compare:CC
12718 
         (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12719 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
12720 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
12721 
         (const_int 0)))
12722 
   (clobber (match_scratch:SI 4 ""))]
12723 
  "TARGET_POWER && reload_completed"
12724 
  [(set (match_dup 4)
12725 
        (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12726 
                 (match_dup 3)))
12727 
   (set (match_dup 0)
12728 
        (compare:CC (match_dup 4)
12729 
                    (const_int 0)))]
12730 
  "")
12731 
 
12732 
(define_insn ""
12733 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12734 
        (compare:CC
12735 
         (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12736 
                         (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12737 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12738 
         (const_int 0)))
12739 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12740 
        (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12741 
  "TARGET_POWER"
12742 
  "@
12743 
   doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12744 
   #"
12745 
  [(set_attr "type" "compare")
12746 
   (set_attr "length" "12,16")])
12747 
 
12748 
(define_split
12749 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12750 
        (compare:CC
12751 
         (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12752 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
12753 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
12754 
         (const_int 0)))
12755 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12756 
        (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12757 
  "TARGET_POWER && reload_completed"
12758 
  [(set (match_dup 0)
12759 
        (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12760 
   (set (match_dup 4)
12761 
        (compare:CC (match_dup 0)
12762 
                    (const_int 0)))]
12763 
  "")
12764 
 
12765 
(define_insn ""
12766 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12767 
        (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12768 
                       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12769 
  "TARGET_POWER"
12770 
  "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12771 
  [(set_attr "length" "12")])
12772 
 
12773 
(define_insn_and_split "*ltu"
12774 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12775 
        (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12776 
               (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12777 
  ""
12778 
  "#"
12779 
  ""
12780 
  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12781 
   (set (match_dup 0) (neg:P (match_dup 0)))]
12782 
  "")
12783 
 
12784 
(define_insn_and_split "*ltu_compare"
12785 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12786 
        (compare:CC
12787 
         (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12788 
                (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12789 
         (const_int 0)))
12790 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12791 
        (ltu:P (match_dup 1) (match_dup 2)))]
12792 
  ""
12793 
  "#"
12794 
  ""
12795 
  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12796 
   (parallel [(set (match_dup 3)
12797 
                   (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12798 
              (set (match_dup 0) (neg:P (match_dup 0)))])]
12799 
  "")
12800 
 
12801 
(define_insn_and_split "*plus_ltu"
12802 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12803 
        (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12804 
                       (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12805 
                (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12806 
  ""
12807 
  "#"
12808 
  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12809 
  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12810 
   (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12811 
  "")
12812 
 
12813 
(define_insn_and_split "*plus_ltu_compare"
12814 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12815 
        (compare:CC
12816 
         (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12817 
                        (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12818 
                 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12819 
         (const_int 0)))
12820 
   (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12821 
        (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12822 
  ""
12823 
  "#"
12824 
  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12825 
  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12826 
   (parallel [(set (match_dup 4)
12827 
                   (compare:CC (minus:P (match_dup 3) (match_dup 0))
12828 
                               (const_int 0)))
12829 
              (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12830 
  "")
12831 
 
12832 
(define_insn "*neg_ltu"
12833 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12834 
        (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12835 
                      (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12836 
  ""
12837 
  "@
12838 
   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12839 
   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12840 
  [(set_attr "type" "two")
12841 
   (set_attr "length" "8")])
12842 
 
12843 
(define_insn ""
12844 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12845 
        (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12846 
               (match_operand:SI 2 "reg_or_short_operand" "rI")))
12847 
   (clobber (match_scratch:SI 3 "=r"))]
12848 
  "TARGET_POWER"
12849 
  "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12850 
   [(set_attr "length" "12")])
12851 
 
12852 
(define_insn ""
12853 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12854 
        (compare:CC
12855 
         (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12856 
                (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12857 
         (const_int 0)))
12858 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12859 
        (ge:SI (match_dup 1) (match_dup 2)))
12860 
   (clobber (match_scratch:SI 3 "=r,r"))]
12861 
  "TARGET_POWER"
12862 
  "@
12863 
   doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12864 
   #"
12865 
  [(set_attr "type" "compare")
12866 
   (set_attr "length" "12,16")])
12867 
 
12868 
(define_split
12869 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12870 
        (compare:CC
12871 
         (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12872 
                (match_operand:SI 2 "reg_or_short_operand" ""))
12873 
         (const_int 0)))
12874 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12875 
        (ge:SI (match_dup 1) (match_dup 2)))
12876 
   (clobber (match_scratch:SI 3 ""))]
12877 
  "TARGET_POWER && reload_completed"
12878 
  [(parallel [(set (match_dup 0)
12879 
                   (ge:SI (match_dup 1) (match_dup 2)))
12880 
              (clobber (match_dup 3))])
12881 
   (set (match_dup 4)
12882 
        (compare:CC (match_dup 0)
12883 
                    (const_int 0)))]
12884 
  "")
12885 
 
12886 
(define_insn ""
12887 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12888 
        (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12889 
                        (match_operand:SI 2 "reg_or_short_operand" "rI"))
12890 
                 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12891 
  "TARGET_POWER"
12892 
  "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12893 
  [(set_attr "length" "12")])
12894 
 
12895 
(define_insn ""
12896 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12897 
        (compare:CC
12898 
         (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12899 
                         (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12900 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12901 
         (const_int 0)))
12902 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
12903 
  "TARGET_POWER"
12904 
  "@
12905 
   doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12906 
   #"
12907 
  [(set_attr "type" "compare")
12908 
   (set_attr "length" "12,16")])
12909 
 
12910 
(define_split
12911 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12912 
        (compare:CC
12913 
         (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12914 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
12915 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
12916 
         (const_int 0)))
12917 
   (clobber (match_scratch:SI 4 ""))]
12918 
  "TARGET_POWER && reload_completed"
12919 
  [(set (match_dup 4)
12920 
        (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12921 
                 (match_dup 3)))
12922 
   (set (match_dup 0)
12923 
        (compare:CC (match_dup 4)
12924 
                    (const_int 0)))]
12925 
  "")
12926 
 
12927 
(define_insn ""
12928 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12929 
        (compare:CC
12930 
         (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12931 
                         (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12932 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12933 
         (const_int 0)))
12934 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12935 
        (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12936 
  "TARGET_POWER"
12937 
  "@
12938 
   doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12939 
   #"
12940 
  [(set_attr "type" "compare")
12941 
   (set_attr "length" "12,16")])
12942 
 
12943 
(define_split
12944 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12945 
        (compare:CC
12946 
         (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12947 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
12948 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
12949 
         (const_int 0)))
12950 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12951 
        (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12952 
  "TARGET_POWER && reload_completed"
12953 
  [(set (match_dup 0)
12954 
        (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12955 
   (set (match_dup 4)
12956 
        (compare:CC (match_dup 0)
12957 
                    (const_int 0)))]
12958 
  "")
12959 
 
12960 
(define_insn ""
12961 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12962 
        (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12963 
                       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12964 
  "TARGET_POWER"
12965 
  "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12966 
  [(set_attr "length" "12")])
12967 
 
12968 
(define_insn "*geu"
12969 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12970 
        (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12971 
               (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12972 
  ""
12973 
  "@
12974 
   {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12975 
   {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12976 
  [(set_attr "type" "three")
12977 
   (set_attr "length" "12")])
12978 
 
12979 
(define_insn "*geu_compare"
12980 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12981 
        (compare:CC
12982 
         (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12983 
                (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12984 
         (const_int 0)))
12985 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12986 
        (geu:P (match_dup 1) (match_dup 2)))]
12987 
  ""
12988 
  "@
12989 
   {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12990 
   {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12991 
   #
12992 
   #"
12993 
  [(set_attr "type" "compare")
12994 
   (set_attr "length" "12,12,16,16")])
12995 
 
12996 
(define_split
12997 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12998 
        (compare:CC
12999 
         (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13000 
                (match_operand:P 2 "reg_or_neg_short_operand" ""))
13001 
         (const_int 0)))
13002 
   (set (match_operand:P 0 "gpc_reg_operand" "")
13003 
        (geu:P (match_dup 1) (match_dup 2)))]
13004 
  "reload_completed"
13005 
  [(set (match_dup 0)
13006 
        (geu:P (match_dup 1) (match_dup 2)))
13007 
   (set (match_dup 3)
13008 
        (compare:CC (match_dup 0)
13009 
                    (const_int 0)))]
13010 
  "")
13011 
 
13012 
(define_insn "*plus_geu"
13013 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13014 
        (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13015 
                       (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13016 
                (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13017 
  ""
13018 
  "@
13019 
   {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13020 
   {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13021 
  [(set_attr "type" "two")
13022 
   (set_attr "length" "8")])
13023 
 
13024 
(define_insn ""
13025 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13026 
        (compare:CC
13027 
         (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13028 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13029 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13030 
         (const_int 0)))
13031 
   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13032 
  "TARGET_32BIT"
13033 
  "@
13034 
   {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13035 
   {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13036 
   #
13037 
   #"
13038 
  [(set_attr "type" "compare")
13039 
   (set_attr "length" "8,8,12,12")])
13040 
 
13041 
(define_split
13042 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13043 
        (compare:CC
13044 
         (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13045 
                          (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13046 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13047 
         (const_int 0)))
13048 
   (clobber (match_scratch:SI 4 ""))]
13049 
  "TARGET_32BIT && reload_completed"
13050 
  [(set (match_dup 4)
13051 
        (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13052 
                  (match_dup 3)))
13053 
   (set (match_dup 0)
13054 
        (compare:CC (match_dup 4)
13055 
                    (const_int 0)))]
13056 
  "")
13057 
 
13058 
(define_insn ""
13059 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13060 
        (compare:CC
13061 
         (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13062 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13063 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13064 
         (const_int 0)))
13065 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13066 
        (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13067 
  "TARGET_32BIT"
13068 
  "@
13069 
   {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13070 
   {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13071 
   #
13072 
   #"
13073 
  [(set_attr "type" "compare")
13074 
   (set_attr "length" "8,8,12,12")])
13075 
 
13076 
(define_split
13077 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13078 
        (compare:CC
13079 
         (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13080 
                          (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13081 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13082 
         (const_int 0)))
13083 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13084 
        (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13085 
  "TARGET_32BIT && reload_completed"
13086 
  [(set (match_dup 0)
13087 
        (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13088 
   (set (match_dup 4)
13089 
        (compare:CC (match_dup 0)
13090 
                    (const_int 0)))]
13091 
  "")
13092 
 
13093 
(define_insn "*neg_geu"
13094 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13095 
        (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13096 
                      (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13097 
  ""
13098 
  "@
13099 
   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13100 
   {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13101 
  [(set_attr "type" "three")
13102 
   (set_attr "length" "12")])
13103 
 
13104 
(define_insn "*and_neg_geu"
13105 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13106 
        (and:P (neg:P
13107 
                 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13108 
                        (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13109 
                (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13110 
  ""
13111 
  "@
13112 
   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13113 
   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13114 
  [(set_attr "type" "three")
13115 
   (set_attr "length" "12")])
13116 
 
13117 
(define_insn ""
13118 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13119 
        (compare:CC
13120 
         (and:SI (neg:SI
13121 
                  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13122 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13123 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13124 
         (const_int 0)))
13125 
   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13126 
  "TARGET_32BIT"
13127 
  "@
13128 
   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13129 
   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13130 
   #
13131 
   #"
13132 
  [(set_attr "type" "compare")
13133 
   (set_attr "length" "12,12,16,16")])
13134 
 
13135 
(define_split
13136 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13137 
        (compare:CC
13138 
         (and:SI (neg:SI
13139 
                  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13140 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13141 
                 (match_operand:SI 3 "gpc_reg_operand" ""))
13142 
         (const_int 0)))
13143 
   (clobber (match_scratch:SI 4 ""))]
13144 
  "TARGET_32BIT && reload_completed"
13145 
  [(set (match_dup 4)
13146 
        (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13147 
                (match_dup 3)))
13148 
   (set (match_dup 0)
13149 
        (compare:CC (match_dup 4)
13150 
                    (const_int 0)))]
13151 
  "")
13152 
 
13153 
(define_insn ""
13154 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13155 
        (compare:CC
13156 
         (and:SI (neg:SI
13157 
                  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13158 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13159 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13160 
         (const_int 0)))
13161 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13162 
        (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13163 
  "TARGET_32BIT"
13164 
  "@
13165 
   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13166 
   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13167 
   #
13168 
   #"
13169 
  [(set_attr "type" "compare")
13170 
   (set_attr "length" "12,12,16,16")])
13171 
 
13172 
(define_split
13173 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13174 
        (compare:CC
13175 
         (and:SI (neg:SI
13176 
                  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13177 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13178 
                 (match_operand:SI 3 "gpc_reg_operand" ""))
13179 
         (const_int 0)))
13180 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13181 
        (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13182 
  "TARGET_32BIT && reload_completed"
13183 
  [(set (match_dup 0)
13184 
        (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13185 
   (set (match_dup 4)
13186 
        (compare:CC (match_dup 0)
13187 
                    (const_int 0)))]
13188 
  "")
13189 
 
13190 
(define_insn ""
13191 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13192 
        (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13193 
               (match_operand:SI 2 "reg_or_short_operand" "r")))]
13194 
  "TARGET_POWER"
13195 
  "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13196 
  [(set_attr "length" "12")])
13197 
 
13198 
(define_insn ""
13199 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13200 
        (compare:CC
13201 
         (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13202 
                (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13203 
         (const_int 0)))
13204 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13205 
        (gt:SI (match_dup 1) (match_dup 2)))]
13206 
  "TARGET_POWER"
13207 
  "@
13208 
   doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13209 
   #"
13210 
  [(set_attr "type" "delayed_compare")
13211 
   (set_attr "length" "12,16")])
13212 
 
13213 
(define_split
13214 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13215 
        (compare:CC
13216 
         (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13217 
                (match_operand:SI 2 "reg_or_short_operand" ""))
13218 
         (const_int 0)))
13219 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13220 
        (gt:SI (match_dup 1) (match_dup 2)))]
13221 
  "TARGET_POWER && reload_completed"
13222 
  [(set (match_dup 0)
13223 
        (gt:SI (match_dup 1) (match_dup 2)))
13224 
   (set (match_dup 3)
13225 
        (compare:CC (match_dup 0)
13226 
                    (const_int 0)))]
13227 
  "")
13228 
 
13229 
(define_insn "*plus_gt0"
13230 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13231 
        (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13232 
                      (const_int 0))
13233 
                 (match_operand:P 2 "gpc_reg_operand" "r")))]
13234 
  ""
13235 
  "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13236 
  [(set_attr "type" "three")
13237 
   (set_attr "length" "12")])
13238 
 
13239 
(define_insn ""
13240 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13241 
        (compare:CC
13242 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13243 
                         (const_int 0))
13244 
                  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13245 
         (const_int 0)))
13246 
   (clobber (match_scratch:SI 3 "=&r,&r"))]
13247 
  "TARGET_32BIT"
13248 
  "@
13249 
   {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13250 
   #"
13251 
  [(set_attr "type" "compare")
13252 
   (set_attr "length" "12,16")])
13253 
 
13254 
(define_split
13255 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13256 
        (compare:CC
13257 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13258 
                         (const_int 0))
13259 
                  (match_operand:SI 2 "gpc_reg_operand" ""))
13260 
         (const_int 0)))
13261 
   (clobber (match_scratch:SI 3 ""))]
13262 
  "TARGET_32BIT && reload_completed"
13263 
  [(set (match_dup 3)
13264 
        (plus:SI (gt:SI (match_dup 1) (const_int 0))
13265 
                  (match_dup 2)))
13266 
   (set (match_dup 0)
13267 
        (compare:CC (match_dup 3)
13268 
                    (const_int 0)))]
13269 
  "")
13270 
 
13271 
(define_insn ""
13272 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13273 
        (compare:CC
13274 
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13275 
                         (const_int 0))
13276 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13277 
         (const_int 0)))
13278 
   (clobber (match_scratch:DI 3 "=&r,&r"))]
13279 
  "TARGET_64BIT"
13280 
  "@
13281 
   addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13282 
   #"
13283 
  [(set_attr "type" "compare")
13284 
   (set_attr "length" "12,16")])
13285 
 
13286 
(define_split
13287 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13288 
        (compare:CC
13289 
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13290 
                         (const_int 0))
13291 
                  (match_operand:DI 2 "gpc_reg_operand" ""))
13292 
         (const_int 0)))
13293 
   (clobber (match_scratch:DI 3 ""))]
13294 
  "TARGET_64BIT && reload_completed"
13295 
  [(set (match_dup 3)
13296 
        (plus:DI (gt:DI (match_dup 1) (const_int 0))
13297 
                 (match_dup 2)))
13298 
   (set (match_dup 0)
13299 
        (compare:CC (match_dup 3)
13300 
                    (const_int 0)))]
13301 
  "")
13302 
 
13303 
(define_insn ""
13304 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13305 
        (compare:CC
13306 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13307 
                         (const_int 0))
13308 
                  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13309 
         (const_int 0)))
13310 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13311 
        (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13312 
  "TARGET_32BIT"
13313 
  "@
13314 
   {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13315 
   #"
13316 
  [(set_attr "type" "compare")
13317 
   (set_attr "length" "12,16")])
13318 
 
13319 
(define_split
13320 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13321 
        (compare:CC
13322 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13323 
                         (const_int 0))
13324 
                  (match_operand:SI 2 "gpc_reg_operand" ""))
13325 
         (const_int 0)))
13326 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13327 
        (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13328 
  "TARGET_32BIT && reload_completed"
13329 
  [(set (match_dup 0)
13330 
        (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13331 
   (set (match_dup 3)
13332 
        (compare:CC (match_dup 0)
13333 
                    (const_int 0)))]
13334 
  "")
13335 
 
13336 
(define_insn ""
13337 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13338 
        (compare:CC
13339 
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13340 
                         (const_int 0))
13341 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13342 
         (const_int 0)))
13343 
   (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13344 
        (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13345 
  "TARGET_64BIT"
13346 
  "@
13347 
   addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13348 
   #"
13349 
  [(set_attr "type" "compare")
13350 
   (set_attr "length" "12,16")])
13351 
 
13352 
(define_split
13353 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13354 
        (compare:CC
13355 
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13356 
                         (const_int 0))
13357 
                  (match_operand:DI 2 "gpc_reg_operand" ""))
13358 
         (const_int 0)))
13359 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
13360 
        (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13361 
  "TARGET_64BIT && reload_completed"
13362 
  [(set (match_dup 0)
13363 
        (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13364 
   (set (match_dup 3)
13365 
        (compare:CC (match_dup 0)
13366 
                    (const_int 0)))]
13367 
  "")
13368 
 
13369 
(define_insn ""
13370 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13371 
        (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13372 
                        (match_operand:SI 2 "reg_or_short_operand" "r"))
13373 
                 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13374 
  "TARGET_POWER"
13375 
  "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13376 
  [(set_attr "length" "12")])
13377 
 
13378 
(define_insn ""
13379 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13380 
        (compare:CC
13381 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13382 
                         (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13383 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13384 
         (const_int 0)))
13385 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
13386 
  "TARGET_POWER"
13387 
  "@
13388 
   doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13389 
   #"
13390 
  [(set_attr "type" "compare")
13391 
   (set_attr "length" "12,16")])
13392 
 
13393 
(define_split
13394 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13395 
        (compare:CC
13396 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13397 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
13398 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13399 
         (const_int 0)))
13400 
   (clobber (match_scratch:SI 4 ""))]
13401 
  "TARGET_POWER && reload_completed"
13402 
  [(set (match_dup 4)
13403 
        (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13404 
   (set (match_dup 0)
13405 
        (compare:CC (match_dup 4)
13406 
                    (const_int 0)))]
13407 
  "")
13408 
 
13409 
(define_insn ""
13410 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13411 
        (compare:CC
13412 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13413 
                         (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13414 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13415 
         (const_int 0)))
13416 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13417 
        (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13418 
  "TARGET_POWER"
13419 
  "@
13420 
   doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13421 
   #"
13422 
  [(set_attr "type" "compare")
13423 
   (set_attr "length" "12,16")])
13424 
 
13425 
(define_split
13426 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13427 
        (compare:CC
13428 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13429 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
13430 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13431 
         (const_int 0)))
13432 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13433 
        (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13434 
  "TARGET_POWER && reload_completed"
13435 
  [(set (match_dup 0)
13436 
        (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13437 
   (set (match_dup 4)
13438 
        (compare:CC (match_dup 0)
13439 
                    (const_int 0)))]
13440 
  "")
13441 
 
13442 
(define_insn ""
13443 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13444 
        (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13445 
                       (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13446 
  "TARGET_POWER"
13447 
  "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13448 
  [(set_attr "length" "12")])
13449 
 
13450 
(define_insn_and_split "*gtu"
13451 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13452 
        (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13453 
               (match_operand:P 2 "reg_or_short_operand" "rI")))]
13454 
  ""
13455 
  "#"
13456 
  ""
13457 
  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13458 
   (set (match_dup 0) (neg:P (match_dup 0)))]
13459 
  "")
13460 
 
13461 
(define_insn_and_split "*gtu_compare"
13462 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13463 
        (compare:CC
13464 
         (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13465 
                 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13466 
         (const_int 0)))
13467 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13468 
        (gtu:P (match_dup 1) (match_dup 2)))]
13469 
  ""
13470 
  "#"
13471 
  ""
13472 
  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13473 
   (parallel [(set (match_dup 3)
13474 
                   (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13475 
              (set (match_dup 0) (neg:P (match_dup 0)))])]
13476 
  "")
13477 
 
13478 
(define_insn_and_split "*plus_gtu"
13479 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13480 
        (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13481 
                       (match_operand:P 2 "reg_or_short_operand" "rI"))
13482 
                (match_operand:P 3 "reg_or_short_operand" "rI")))]
13483 
  ""
13484 
  "#"
13485 
  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13486 
  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13487 
   (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13488 
  "")
13489 
 
13490 
(define_insn_and_split "*plus_gtu_compare"
13491 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13492 
        (compare:CC
13493 
         (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13494 
                        (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13495 
                 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13496 
         (const_int 0)))
13497 
   (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13498 
        (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13499 
  ""
13500 
  "#"
13501 
  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13502 
  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13503 
   (parallel [(set (match_dup 4)
13504 
                   (compare:CC (minus:P (match_dup 3) (match_dup 0))
13505 
                               (const_int 0)))
13506 
              (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13507 
  "")
13508 
 
13509 
(define_insn "*neg_gtu"
13510 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13511 
        (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13512 
                      (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13513 
  ""
13514 
  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13515 
  [(set_attr "type" "two")
13516 
   (set_attr "length" "8")])
13517 
 
13518 
 
13519 
;; Define both directions of branch and return.  If we need a reload
13520 
;; register, we'd rather use CR0 since it is much easier to copy a
13521 
;; register CC value to there.
13522 
 
13523 
(define_insn ""
13524 
  [(set (pc)
13525 
        (if_then_else (match_operator 1 "branch_comparison_operator"
13526 
                                      [(match_operand 2
13527 
                                                      "cc_reg_operand" "y")
13528 
                                       (const_int 0)])
13529 
                      (label_ref (match_operand 0 "" ""))
13530 
                      (pc)))]
13531 
  ""
13532 
  "*
13533 
{
13534 
  return output_cbranch (operands[1], \"%l0\", 0, insn);
13535 
}"
13536 
  [(set_attr "type" "branch")])
13537 
 
13538 
(define_insn ""
13539 
  [(set (pc)
13540 
        (if_then_else (match_operator 0 "branch_comparison_operator"
13541 
                                      [(match_operand 1
13542 
                                                      "cc_reg_operand" "y")
13543 
                                       (const_int 0)])
13544 
                      (return)
13545 
                      (pc)))]
13546 
  "direct_return ()"
13547 
  "*
13548 
{
13549 
  return output_cbranch (operands[0], NULL, 0, insn);
13550 
}"
13551 
  [(set_attr "type" "jmpreg")
13552 
   (set_attr "length" "4")])
13553 
 
13554 
(define_insn ""
13555 
  [(set (pc)
13556 
        (if_then_else (match_operator 1 "branch_comparison_operator"
13557 
                                      [(match_operand 2
13558 
                                                      "cc_reg_operand" "y")
13559 
                                       (const_int 0)])
13560 
                      (pc)
13561 
                      (label_ref (match_operand 0 "" ""))))]
13562 
  ""
13563 
  "*
13564 
{
13565 
  return output_cbranch (operands[1], \"%l0\", 1, insn);
13566 
}"
13567 
  [(set_attr "type" "branch")])
13568 
 
13569 
(define_insn ""
13570 
  [(set (pc)
13571 
        (if_then_else (match_operator 0 "branch_comparison_operator"
13572 
                                      [(match_operand 1
13573 
                                                      "cc_reg_operand" "y")
13574 
                                       (const_int 0)])
13575 
                      (pc)
13576 
                      (return)))]
13577 
  "direct_return ()"
13578 
  "*
13579 
{
13580 
  return output_cbranch (operands[0], NULL, 1, insn);
13581 
}"
13582 
  [(set_attr "type" "jmpreg")
13583 
   (set_attr "length" "4")])
13584 
 
13585 
;; Logic on condition register values.
13586 
 
13587 
; This pattern matches things like
13588 
; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13589 
;                                          (eq:SI (reg:CCFP 68) (const_int 0)))
13590 
;                                  (const_int 1)))
13591 
; which are generated by the branch logic.
13592 
; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13593 
 
13594 
(define_insn "*cceq_ior_compare"
13595 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13596 
        (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13597 
                        [(match_operator:SI 2
13598 
                                      "branch_positive_comparison_operator"
13599 
                                      [(match_operand 3
13600 
                                                      "cc_reg_operand" "y,y")
13601 
                                       (const_int 0)])
13602 
                         (match_operator:SI 4
13603 
                                      "branch_positive_comparison_operator"
13604 
                                      [(match_operand 5
13605 
                                                      "cc_reg_operand" "0,y")
13606 
                                       (const_int 0)])])
13607 
                      (const_int 1)))]
13608 
  ""
13609 
  "cr%q1 %E0,%j2,%j4"
13610 
  [(set_attr "type" "cr_logical,delayed_cr")])
13611 
 
13612 
; Why is the constant -1 here, but 1 in the previous pattern?
13613 
; Because ~1 has all but the low bit set.
13614 
(define_insn ""
13615 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13616 
        (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13617 
                        [(not:SI (match_operator:SI 2
13618 
                                      "branch_positive_comparison_operator"
13619 
                                      [(match_operand 3
13620 
                                                      "cc_reg_operand" "y,y")
13621 
                                       (const_int 0)]))
13622 
                         (match_operator:SI 4
13623 
                                "branch_positive_comparison_operator"
13624 
                                [(match_operand 5
13625 
                                                "cc_reg_operand" "0,y")
13626 
                                 (const_int 0)])])
13627 
                      (const_int -1)))]
13628 
  ""
13629 
  "cr%q1 %E0,%j2,%j4"
13630 
  [(set_attr "type" "cr_logical,delayed_cr")])
13631 
 
13632 
(define_insn "*cceq_rev_compare"
13633 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13634 
        (compare:CCEQ (match_operator:SI 1
13635 
                                      "branch_positive_comparison_operator"
13636 
                                      [(match_operand 2
13637 
                                                      "cc_reg_operand" "0,y")
13638 
                                       (const_int 0)])
13639 
                      (const_int 0)))]
13640 
  ""
13641 
  "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13642 
  [(set_attr "type" "cr_logical,delayed_cr")])
13643 
 
13644 
;; If we are comparing the result of two comparisons, this can be done
13645 
;; using creqv or crxor.
13646 
 
13647 
(define_insn_and_split ""
13648 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13649 
        (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13650 
                              [(match_operand 2 "cc_reg_operand" "y")
13651 
                               (const_int 0)])
13652 
                      (match_operator 3 "branch_comparison_operator"
13653 
                              [(match_operand 4 "cc_reg_operand" "y")
13654 
                               (const_int 0)])))]
13655 
  ""
13656 
  "#"
13657 
  ""
13658 
  [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13659 
                                    (match_dup 5)))]
13660 
  "
13661 
{
13662 
  int positive_1, positive_2;
13663 
 
13664 
  positive_1 = branch_positive_comparison_operator (operands[1],
13665 
                                                    GET_MODE (operands[1]));
13666 
  positive_2 = branch_positive_comparison_operator (operands[3],
13667 
                                                    GET_MODE (operands[3]));
13668 
 
13669 
  if (! positive_1)
13670 
    operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13671 
                                                            GET_CODE (operands[1])),
13672 
                                  SImode,
13673 
                                  operands[2], const0_rtx);
13674 
  else if (GET_MODE (operands[1]) != SImode)
13675 
    operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13676 
                                  operands[2], const0_rtx);
13677 
 
13678 
  if (! positive_2)
13679 
    operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13680 
                                                            GET_CODE (operands[3])),
13681 
                                  SImode,
13682 
                                  operands[4], const0_rtx);
13683 
  else if (GET_MODE (operands[3]) != SImode)
13684 
    operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13685 
                                  operands[4], const0_rtx);
13686 
 
13687 
  if (positive_1 == positive_2)
13688 
    {
13689 
      operands[1] = gen_rtx_NOT (SImode, operands[1]);
13690 
      operands[5] = constm1_rtx;
13691 
    }
13692 
  else
13693 
    {
13694 
      operands[5] = const1_rtx;
13695 
    }
13696 
}")
13697 
 
13698 
;; Unconditional branch and return.
13699 
 
13700 
(define_insn "jump"
13701 
  [(set (pc)
13702 
        (label_ref (match_operand 0 "" "")))]
13703 
  ""
13704 
  "b %l0"
13705 
  [(set_attr "type" "branch")])
13706 
 
13707 
(define_insn "return"
13708 
  [(return)]
13709 
  "direct_return ()"
13710 
  "{br|blr}"
13711 
  [(set_attr "type" "jmpreg")])
13712 
 
13713 
(define_expand "indirect_jump"
13714 
  [(set (pc) (match_operand 0 "register_operand" ""))])
13715 
 
13716 
(define_insn "*indirect_jump"
13717 
  [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13718 
  ""
13719 
  "@
13720 
   bctr
13721 
   {br|blr}"
13722 
  [(set_attr "type" "jmpreg")])
13723 
 
13724 
;; Table jump for switch statements:
13725 
(define_expand "tablejump"
13726 
  [(use (match_operand 0 "" ""))
13727 
   (use (label_ref (match_operand 1 "" "")))]
13728 
  ""
13729 
  "
13730 
{
13731 
  if (TARGET_32BIT)
13732 
    emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13733 
  else
13734 
    emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13735 
  DONE;
13736 
}")
13737 
 
13738 
(define_expand "tablejumpsi"
13739 
  [(set (match_dup 3)
13740 
        (plus:SI (match_operand:SI 0 "" "")
13741 
                 (match_dup 2)))
13742 
   (parallel [(set (pc) (match_dup 3))
13743 
              (use (label_ref (match_operand 1 "" "")))])]
13744 
  "TARGET_32BIT"
13745 
  "
13746 
{ operands[0] = force_reg (SImode, operands[0]);
13747 
  operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13748 
  operands[3] = gen_reg_rtx (SImode);
13749 
}")
13750 
 
13751 
(define_expand "tablejumpdi"
13752 
  [(set (match_dup 4)
13753 
        (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13754 
   (set (match_dup 3)
13755 
        (plus:DI (match_dup 4)
13756 
                 (match_dup 2)))
13757 
   (parallel [(set (pc) (match_dup 3))
13758 
              (use (label_ref (match_operand 1 "" "")))])]
13759 
  "TARGET_64BIT"
13760 
  "
13761 
{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13762 
  operands[3] = gen_reg_rtx (DImode);
13763 
  operands[4] = gen_reg_rtx (DImode);
13764 
}")
13765 
 
13766 
(define_insn "*tablejump_internal1"
13767 
  [(set (pc)
13768 
        (match_operand:P 0 "register_operand" "c,*l"))
13769 
   (use (label_ref (match_operand 1 "" "")))]
13770 
  ""
13771 
  "@
13772 
   bctr
13773 
   {br|blr}"
13774 
  [(set_attr "type" "jmpreg")])
13775 
 
13776 
(define_insn "nop"
13777 
  [(const_int 0)]
13778 
  ""
13779 
  "{cror 0,0,0|nop}")
13780 
 
13781 
;; Define the subtract-one-and-jump insns, starting with the template
13782 
;; so loop.c knows what to generate.
13783 
 
13784 
(define_expand "doloop_end"
13785 
  [(use (match_operand 0 "" ""))        ; loop pseudo
13786 
   (use (match_operand 1 "" ""))        ; iterations; zero if unknown
13787 
   (use (match_operand 2 "" ""))        ; max iterations
13788 
   (use (match_operand 3 "" ""))        ; loop level
13789 
   (use (match_operand 4 "" ""))]       ; label
13790 
  ""
13791 
  "
13792 
{
13793 
  /* Only use this on innermost loops.  */
13794 
  if (INTVAL (operands[3]) > 1)
13795 
    FAIL;
13796 
  if (TARGET_64BIT)
13797 
    {
13798 
      if (GET_MODE (operands[0]) != DImode)
13799 
        FAIL;
13800 
      emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13801 
    }
13802 
  else
13803 
    {
13804 
      if (GET_MODE (operands[0]) != SImode)
13805 
        FAIL;
13806 
      emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13807 
    }
13808 
  DONE;
13809 
}")
13810 
 
13811 
(define_expand "ctr"
13812 
  [(parallel [(set (pc)
13813 
                   (if_then_else (ne (match_operand:P 0 "register_operand" "")
13814 
                                     (const_int 1))
13815 
                                 (label_ref (match_operand 1 "" ""))
13816 
                                 (pc)))
13817 
              (set (match_dup 0)
13818 
                   (plus:P (match_dup 0)
13819 
                            (const_int -1)))
13820 
              (clobber (match_scratch:CC 2 ""))
13821 
              (clobber (match_scratch:P 3 ""))])]
13822 
  ""
13823 
  "")
13824 
 
13825 
;; We need to be able to do this for any operand, including MEM, or we
13826 
;; will cause reload to blow up since we don't allow output reloads on
13827 
;; JUMP_INSNs.
13828 
;; For the length attribute to be calculated correctly, the
13829 
;; label MUST be operand 0.
13830 
 
13831 
(define_insn "*ctr_internal1"
13832 
  [(set (pc)
13833 
        (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13834 
                          (const_int 1))
13835 
                      (label_ref (match_operand 0 "" ""))
13836 
                      (pc)))
13837 
   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13838 
        (plus:P (match_dup 1)
13839 
                 (const_int -1)))
13840 
   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13841 
   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13842 
  ""
13843 
  "*
13844 
{
13845 
  if (which_alternative != 0)
13846 
    return \"#\";
13847 
  else if (get_attr_length (insn) == 4)
13848 
    return \"{bdn|bdnz} %l0\";
13849 
  else
13850 
    return \"bdz $+8\;b %l0\";
13851 
}"
13852 
  [(set_attr "type" "branch")
13853 
   (set_attr "length" "*,12,16,16")])
13854 
 
13855 
(define_insn "*ctr_internal2"
13856 
  [(set (pc)
13857 
        (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13858 
                          (const_int 1))
13859 
                      (pc)
13860 
                      (label_ref (match_operand 0 "" ""))))
13861 
   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13862 
        (plus:P (match_dup 1)
13863 
                 (const_int -1)))
13864 
   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13865 
   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13866 
  ""
13867 
  "*
13868 
{
13869 
  if (which_alternative != 0)
13870 
    return \"#\";
13871 
  else if (get_attr_length (insn) == 4)
13872 
    return \"bdz %l0\";
13873 
  else
13874 
    return \"{bdn|bdnz} $+8\;b %l0\";
13875 
}"
13876 
  [(set_attr "type" "branch")
13877 
   (set_attr "length" "*,12,16,16")])
13878 
 
13879 
;; Similar but use EQ
13880 
 
13881 
(define_insn "*ctr_internal5"
13882 
  [(set (pc)
13883 
        (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13884 
                          (const_int 1))
13885 
                      (label_ref (match_operand 0 "" ""))
13886 
                      (pc)))
13887 
   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13888 
        (plus:P (match_dup 1)
13889 
                 (const_int -1)))
13890 
   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13891 
   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13892 
  ""
13893 
  "*
13894 
{
13895 
  if (which_alternative != 0)
13896 
    return \"#\";
13897 
  else if (get_attr_length (insn) == 4)
13898 
    return \"bdz %l0\";
13899 
  else
13900 
    return \"{bdn|bdnz} $+8\;b %l0\";
13901 
}"
13902 
  [(set_attr "type" "branch")
13903 
   (set_attr "length" "*,12,16,16")])
13904 
 
13905 
(define_insn "*ctr_internal6"
13906 
  [(set (pc)
13907 
        (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13908 
                          (const_int 1))
13909 
                      (pc)
13910 
                      (label_ref (match_operand 0 "" ""))))
13911 
   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13912 
        (plus:P (match_dup 1)
13913 
                 (const_int -1)))
13914 
   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13915 
   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13916 
  ""
13917 
  "*
13918 
{
13919 
  if (which_alternative != 0)
13920 
    return \"#\";
13921 
  else if (get_attr_length (insn) == 4)
13922 
    return \"{bdn|bdnz} %l0\";
13923 
  else
13924 
    return \"bdz $+8\;b %l0\";
13925 
}"
13926 
  [(set_attr "type" "branch")
13927 
   (set_attr "length" "*,12,16,16")])
13928 
 
13929 
;; Now the splitters if we could not allocate the CTR register
13930 
 
13931 
(define_split
13932 
  [(set (pc)
13933 
        (if_then_else (match_operator 2 "comparison_operator"
13934 
                                      [(match_operand:P 1 "gpc_reg_operand" "")
13935 
                                       (const_int 1)])
13936 
                      (match_operand 5 "" "")
13937 
                      (match_operand 6 "" "")))
13938 
   (set (match_operand:P 0 "gpc_reg_operand" "")
13939 
        (plus:P (match_dup 1) (const_int -1)))
13940 
   (clobber (match_scratch:CC 3 ""))
13941 
   (clobber (match_scratch:P 4 ""))]
13942 
  "reload_completed"
13943 
  [(parallel [(set (match_dup 3)
13944 
                   (compare:CC (plus:P (match_dup 1)
13945 
                                        (const_int -1))
13946 
                               (const_int 0)))
13947 
              (set (match_dup 0)
13948 
                   (plus:P (match_dup 1)
13949 
                            (const_int -1)))])
13950 
   (set (pc) (if_then_else (match_dup 7)
13951 
                           (match_dup 5)
13952 
                           (match_dup 6)))]
13953 
  "
13954 
{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13955 
                                operands[3], const0_rtx); }")
13956 
 
13957 
(define_split
13958 
  [(set (pc)
13959 
        (if_then_else (match_operator 2 "comparison_operator"
13960 
                                      [(match_operand:P 1 "gpc_reg_operand" "")
13961 
                                       (const_int 1)])
13962 
                      (match_operand 5 "" "")
13963 
                      (match_operand 6 "" "")))
13964 
   (set (match_operand:P 0 "nonimmediate_operand" "")
13965 
        (plus:P (match_dup 1) (const_int -1)))
13966 
   (clobber (match_scratch:CC 3 ""))
13967 
   (clobber (match_scratch:P 4 ""))]
13968 
  "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13969 
  [(parallel [(set (match_dup 3)
13970 
                   (compare:CC (plus:P (match_dup 1)
13971 
                                        (const_int -1))
13972 
                               (const_int 0)))
13973 
              (set (match_dup 4)
13974 
                   (plus:P (match_dup 1)
13975 
                            (const_int -1)))])
13976 
   (set (match_dup 0)
13977 
        (match_dup 4))
13978 
   (set (pc) (if_then_else (match_dup 7)
13979 
                           (match_dup 5)
13980 
                           (match_dup 6)))]
13981 
  "
13982 
{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13983 
                                operands[3], const0_rtx); }")
13984 
 
13985 
(define_insn "trap"
13986 
  [(trap_if (const_int 1) (const_int 0))]
13987 
  ""
13988 
  "{t 31,0,0|trap}")
13989 
 
13990 
(define_expand "conditional_trap"
13991 
  [(trap_if (match_operator 0 "trap_comparison_operator"
13992 
                            [(match_dup 2) (match_dup 3)])
13993 
            (match_operand 1 "const_int_operand" ""))]
13994 
  ""
13995 
  "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13996 
   operands[2] = rs6000_compare_op0;
13997 
   operands[3] = rs6000_compare_op1;")
13998 
 
13999 
(define_insn ""
14000 
  [(trap_if (match_operator 0 "trap_comparison_operator"
14001 
                            [(match_operand:GPR 1 "register_operand" "r")
14002 
                             (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14003 
            (const_int 0))]
14004 
  ""
14005 
  "{t|t}%V0%I2 %1,%2")
14006 
 
14007 
;; Insns related to generating the function prologue and epilogue.
14008 
 
14009 
(define_expand "prologue"
14010 
  [(use (const_int 0))]
14011 
  "TARGET_SCHED_PROLOG"
14012 
  "
14013 
{
14014 
      rs6000_emit_prologue ();
14015 
      DONE;
14016 
}")
14017 
 
14018 
(define_insn "*movesi_from_cr_one"
14019 
  [(match_parallel 0 "mfcr_operation"
14020 
                   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14021 
                         (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14022 
                                     (match_operand 3 "immediate_operand" "n")]
14023 
                          UNSPEC_MOVESI_FROM_CR))])]
14024 
  "TARGET_MFCRF"
14025 
  "*
14026 
{
14027 
  int mask = 0;
14028 
  int i;
14029 
  for (i = 0; i < XVECLEN (operands[0], 0); i++)
14030 
  {
14031 
    mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14032 
    operands[4] = GEN_INT (mask);
14033 
    output_asm_insn (\"mfcr %1,%4\", operands);
14034 
  }
14035 
  return \"\";
14036 
}"
14037 
  [(set_attr "type" "mfcrf")])
14038 
 
14039 
(define_insn "movesi_from_cr"
14040 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14041 
        (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14042 
                    (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14043 
                   UNSPEC_MOVESI_FROM_CR))]
14044 
  ""
14045 
  "mfcr %0"
14046 
  [(set_attr "type" "mfcr")])
14047 
 
14048 
(define_insn "*stmw"
14049 
  [(match_parallel 0 "stmw_operation"
14050 
                   [(set (match_operand:SI 1 "memory_operand" "=m")
14051 
                         (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14052 
  "TARGET_MULTIPLE"
14053 
  "{stm|stmw} %2,%1"
14054 
  [(set_attr "type" "store_ux")])
14055 
 
14056 
(define_insn "*save_fpregs_"
14057 
  [(match_parallel 0 "any_parallel_operand"
14058 
                   [(clobber (match_operand:P 1 "register_operand" "=l"))
14059 
                    (use (match_operand:P 2 "call_operand" "s"))
14060 
                    (set (match_operand:DF 3 "memory_operand" "=m")
14061 
                         (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14062 
  ""
14063 
  "bl %z2"
14064 
  [(set_attr "type" "branch")
14065 
   (set_attr "length" "4")])
14066 
 
14067 
; These are to explain that changes to the stack pointer should
14068 
; not be moved over stores to stack memory.
14069 
(define_insn "stack_tie"
14070 
  [(set (match_operand:BLK 0 "memory_operand" "+m")
14071 
        (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14072 
  ""
14073 
  ""
14074 
  [(set_attr "length" "0")])
14075 
 
14076 
 
14077 
(define_expand "epilogue"
14078 
  [(use (const_int 0))]
14079 
  "TARGET_SCHED_PROLOG"
14080 
  "
14081 
{
14082 
      rs6000_emit_epilogue (FALSE);
14083 
      DONE;
14084 
}")
14085 
 
14086 
; On some processors, doing the mtcrf one CC register at a time is
14087 
; faster (like on the 604e).  On others, doing them all at once is
14088 
; faster; for instance, on the 601 and 750.
14089 
 
14090 
(define_expand "movsi_to_cr_one"
14091 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14092 
        (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14093 
                    (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14094 
  ""
14095 
  "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14096 
 
14097 
(define_insn "*movsi_to_cr"
14098 
  [(match_parallel 0 "mtcrf_operation"
14099 
                   [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14100 
                         (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14101 
                                     (match_operand 3 "immediate_operand" "n")]
14102 
                                    UNSPEC_MOVESI_TO_CR))])]
14103 
 ""
14104 
 "*
14105 
{
14106 
  int mask = 0;
14107 
  int i;
14108 
  for (i = 0; i < XVECLEN (operands[0], 0); i++)
14109 
    mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14110 
  operands[4] = GEN_INT (mask);
14111 
  return \"mtcrf %4,%2\";
14112 
}"
14113 
  [(set_attr "type" "mtcr")])
14114 
 
14115 
(define_insn "*mtcrfsi"
14116 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14117 
        (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14118 
                    (match_operand 2 "immediate_operand" "n")]
14119 
                   UNSPEC_MOVESI_TO_CR))]
14120 
  "GET_CODE (operands[0]) == REG
14121 
   && CR_REGNO_P (REGNO (operands[0]))
14122 
   && GET_CODE (operands[2]) == CONST_INT
14123 
   && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14124 
  "mtcrf %R0,%1"
14125 
  [(set_attr "type" "mtcr")])
14126 
 
14127 
; The load-multiple instructions have similar properties.
14128 
; Note that "load_multiple" is a name known to the machine-independent
14129 
; code that actually corresponds to the PowerPC load-string.
14130 
 
14131 
(define_insn "*lmw"
14132 
  [(match_parallel 0 "lmw_operation"
14133 
                   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14134 
                         (match_operand:SI 2 "memory_operand" "m"))])]
14135 
  "TARGET_MULTIPLE"
14136 
  "{lm|lmw} %1,%2"
14137 
  [(set_attr "type" "load_ux")])
14138 
 
14139 
(define_insn "*return_internal_"
14140 
  [(return)
14141 
   (use (match_operand:P 0 "register_operand" "lc"))]
14142 
  ""
14143 
  "b%T0"
14144 
  [(set_attr "type" "jmpreg")])
14145 
 
14146 
; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14147 
; stuff was in GCC.  Oh, and "any_parallel_operand" is a bit flexible...
14148 
 
14149 
(define_insn "*return_and_restore_fpregs_"
14150 
 [(match_parallel 0 "any_parallel_operand"
14151 
                  [(return)
14152 
                   (use (match_operand:P 1 "register_operand" "l"))
14153 
                   (use (match_operand:P 2 "call_operand" "s"))
14154 
                   (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14155 
                        (match_operand:DF 4 "memory_operand" "m"))])]
14156 
 ""
14157 
 "b %z2")
14158 
 
14159 
; This is used in compiling the unwind routines.
14160 
(define_expand "eh_return"
14161 
  [(use (match_operand 0 "general_operand" ""))]
14162 
  ""
14163 
  "
14164 
{
14165 
  if (TARGET_32BIT)
14166 
    emit_insn (gen_eh_set_lr_si (operands[0]));
14167 
  else
14168 
    emit_insn (gen_eh_set_lr_di (operands[0]));
14169 
  DONE;
14170 
}")
14171 
 
14172 
; We can't expand this before we know where the link register is stored.
14173 
(define_insn "eh_set_lr_"
14174 
  [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14175 
                    UNSPECV_EH_RR)
14176 
   (clobber (match_scratch:P 1 "=&b"))]
14177 
  ""
14178 
  "#")
14179 
 
14180 
(define_split
14181 
  [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14182 
   (clobber (match_scratch 1 ""))]
14183 
  "reload_completed"
14184 
  [(const_int 0)]
14185 
  "
14186 
{
14187 
  rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14188 
  DONE;
14189 
}")
14190 
 
14191 
(define_insn "prefetch"
14192 
  [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14193 
             (match_operand:SI 1 "const_int_operand" "n")
14194 
             (match_operand:SI 2 "const_int_operand" "n"))]
14195 
  "TARGET_POWERPC"
14196 
  "*
14197 
{
14198 
  if (GET_CODE (operands[0]) == REG)
14199 
    return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14200 
  return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14201 
}"
14202 
  [(set_attr "type" "load")])
14203 
 
14204 
 
14205 
(include "sync.md")
14206 
(include "altivec.md")
14207 
(include "spe.md")

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