OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [rs6000/] [sysv4.opt] - Blame information for rev 825

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
; SYSV4 options for PPC port.
2
;
3
; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
4
; Contributed by Aldy Hernandez .
5
;
6
; This file is part of GCC.
7
;
8
; GCC is free software; you can redistribute it and/or modify it under
9
; the terms of the GNU General Public License as published by the Free
10
; Software Foundation; either version 3, or (at your option) any later
11
; version.
12
;
13
; GCC is distributed in the hope that it will be useful, but WITHOUT
14
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
; License for more details.
17
;
18
; You should have received a copy of the GNU General Public License
19
; along with GCC; see the file COPYING3.  If not see
20
; .
21
 
22
mcall-
23
Target RejectNegative Joined
24
Select ABI calling convention
25
 
26
msdata=
27
Target RejectNegative Joined
28
Select method for sdata handling
29
 
30
mtls-size=
31
Target RejectNegative Joined
32
Specify bit size of immediate TLS offsets
33
 
34
mbit-align
35
Target Report Mask(NO_BITFIELD_TYPE)
36
Align to the base type of the bit-field
37
 
38
mstrict-align
39
Target Report Mask(STRICT_ALIGN)
40
Align to the base type of the bit-field
41
Don't assume that unaligned accesses are handled by the system
42
 
43
mrelocatable
44
Target Report Mask(RELOCATABLE)
45
Produce code relocatable at runtime
46
 
47
mrelocatable-lib
48
Target
49
Produce code relocatable at runtime
50
 
51
mlittle-endian
52
Target Report RejectNegative Mask(LITTLE_ENDIAN)
53
Produce little endian code
54
 
55
mlittle
56
Target Report RejectNegative Mask(LITTLE_ENDIAN) MaskExists
57
Produce little endian code
58
 
59
mbig-endian
60
Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
61
Produce big endian code
62
 
63
mbig
64
Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
65
Produce big endian code
66
 
67
;; FIXME: This does nothing.  What should be done?
68
mno-toc
69
Target RejectNegative
70
no description yet
71
 
72
mtoc
73
Target RejectNegative
74
no description yet
75
 
76
mprototype
77
Target Mask(PROTOTYPE)
78
Assume all variable arg functions are prototyped
79
 
80
;; FIXME: Does nothing.
81
mno-traceback
82
Target RejectNegative
83
no description yet
84
 
85
meabi
86
Target Report Mask(EABI)
87
Use EABI
88
 
89
mbit-word
90
Target Report Mask(NO_BITFIELD_WORD)
91
Allow bit-fields to cross word boundaries
92
 
93
mregnames
94
Target Mask(REGNAMES)
95
Use alternate register names
96
 
97
;; FIXME: Does nothing.
98
msdata
99
Target
100
no description yet
101
 
102
msim
103
Target RejectNegative
104
Link with libsim.a, libc.a and sim-crt0.o
105
 
106
mads
107
Target RejectNegative
108
Link with libads.a, libc.a and crt0.o
109
 
110
myellowknife
111
Target RejectNegative
112
Link with libyk.a, libc.a and crt0.o
113
 
114
mmvme
115
Target RejectNegative
116
Link with libmvme.a, libc.a and crt0.o
117
 
118
memb
119
Target RejectNegative
120
Set the PPC_EMB bit in the ELF flags header
121
 
122
mwindiss
123
Target RejectNegative
124
Use the WindISS simulator
125
 
126
mshlib
127
Target RejectNegative
128
no description yet
129
 
130
m64
131
Target Report RejectNegative Mask(64BIT)
132
Generate 64-bit code
133
 
134
m32
135
Target Report RejectNegative InverseMask(64BIT)
136
Generate 32-bit code
137
 
138
mnewlib
139
Target RejectNegative
140
no description yet
141
 
142
msecure-plt
143
Target Report RejectNegative Var(secure_plt, 1)
144
Generate code to use a non-exec PLT and GOT
145
 
146
mbss-plt
147
Target Report RejectNegative Var(secure_plt, 0)
148
Generate code for old exec BSS PLT

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.