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julius |
;;- Machine description for GNU compiler -- S/390 / zSeries version.
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;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
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;; Free Software Foundation, Inc.
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;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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;; Ulrich Weigand (uweigand@de.ibm.com).
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it under
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;; the terms of the GNU General Public License as published by the Free
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;; Software Foundation; either version 3, or (at your option) any later
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;; version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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;; for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;;
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;; See constraints.md for a description of constraints specific to s390.
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;;
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;; Special formats used for outputting 390 instructions.
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;;
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;; %C: print opcode suffix for branch condition.
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;; %D: print opcode suffix for inverse branch condition.
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;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
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;; %G: print the size of the operand in bytes.
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;; %O: print only the displacement of a memory reference.
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;; %R: print only the base register of a memory reference.
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;; %S: print S-type memory reference (base+displacement).
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;; %N: print the second word of a DImode operand.
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;; %M: print the second word of a TImode operand.
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;; %Y: print shift count operand.
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;;
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;; %b: print integer X as if it's an unsigned byte.
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;; %x: print integer X as if it's an unsigned halfword.
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;; %h: print integer X as if it's a signed halfword.
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;; %i: print the first nonzero HImode part of X.
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;; %j: print the first HImode part unequal to -1 of X.
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;; %k: print the first nonzero SImode part of X.
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;; %m: print the first SImode part unequal to -1 of X.
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;; %o: print integer X as if it's an unsigned 32bit word.
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;;
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;; We have a special constraint for pattern matching.
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;;
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;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
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;;
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;;
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;; UNSPEC usage
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;;
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(define_constants
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[; Miscellaneous
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(UNSPEC_ROUND 1)
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(UNSPEC_CMPINT 2)
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(UNSPEC_ICM 10)
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; GOT/PLT and lt-relative accesses
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(UNSPEC_LTREL_OFFSET 100)
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(UNSPEC_LTREL_BASE 101)
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(UNSPEC_GOTENT 110)
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(UNSPEC_GOT 111)
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(UNSPEC_GOTOFF 112)
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(UNSPEC_PLT 113)
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(UNSPEC_PLTOFF 114)
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; Literal pool
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(UNSPEC_RELOAD_BASE 210)
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(UNSPEC_MAIN_BASE 211)
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(UNSPEC_LTREF 212)
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(UNSPEC_INSN 213)
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(UNSPEC_EXECUTE 214)
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; TLS relocation specifiers
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(UNSPEC_TLSGD 500)
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(UNSPEC_TLSLDM 501)
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(UNSPEC_NTPOFF 502)
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(UNSPEC_DTPOFF 503)
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(UNSPEC_GOTNTPOFF 504)
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(UNSPEC_INDNTPOFF 505)
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; TLS support
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(UNSPEC_TLSLDM_NTPOFF 511)
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(UNSPEC_TLS_LOAD 512)
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; String Functions
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(UNSPEC_SRST 600)
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(UNSPEC_MVST 601)
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; Stack Smashing Protector
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(UNSPEC_SP_SET 700)
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(UNSPEC_SP_TEST 701)
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])
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;;
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;; UNSPEC_VOLATILE usage
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;;
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(define_constants
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[; Blockage
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(UNSPECV_BLOCKAGE 0)
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; TPF Support
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(UNSPECV_TPF_PROLOGUE 20)
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(UNSPECV_TPF_EPILOGUE 21)
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; Literal pool
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(UNSPECV_POOL 200)
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(UNSPECV_POOL_SECTION 201)
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(UNSPECV_POOL_ALIGN 202)
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(UNSPECV_POOL_ENTRY 203)
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(UNSPECV_MAIN_POOL 300)
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; TLS support
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(UNSPECV_SET_TP 500)
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; Atomic Support
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(UNSPECV_MB 700)
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(UNSPECV_CAS 701)
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])
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;;
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;; Registers
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;;
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(define_constants
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[
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; Sibling call register.
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(SIBCALL_REGNUM 1)
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; Literal pool base register.
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(BASE_REGNUM 13)
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; Return address register.
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(RETURN_REGNUM 14)
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; Condition code register.
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(CC_REGNUM 33)
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; Thread local storage pointer register.
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(TP_REGNUM 36)
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])
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;; Instruction operand type as used in the Principles of Operation.
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;; Used to determine defaults for length and other attribute values.
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(define_attr "op_type"
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"NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
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(const_string "NN"))
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;; Instruction type attribute used for scheduling.
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(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
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cs,vs,store,sem,idiv,
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imulhi,imulsi,imuldi,
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branch,jsr,fsimptf,fsimpdf,fsimpsf,
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floadtf,floaddf,floadsf,fstoredf,fstoresf,
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fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
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ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
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ftrunctf,ftruncdf,other"
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(cond [(eq_attr "op_type" "NN") (const_string "other")
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(eq_attr "op_type" "SS") (const_string "cs")]
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(const_string "integer")))
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;; Another attribute used for scheduling purposes:
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;; agen: Instruction uses the address generation unit
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;; reg: Instruction does not use the agen unit
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(define_attr "atype" "agen,reg"
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(if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
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(const_string "reg")
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(const_string "agen")))
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;; Length in bytes.
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(define_attr "length" ""
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(cond [(eq_attr "op_type" "E,RR") (const_int 2)
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(eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
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(const_int 6)))
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;; Processor type. This attribute must exactly match the processor_type
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;; enumeration in s390.h. The current machine description does not
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;; distinguish between g5 and g6, but there are differences between the two
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;; CPUs could in theory be modeled.
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(define_attr "cpu" "g5,g6,z900,z990,z9_109"
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(const (symbol_ref "s390_tune")))
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;; Pipeline description for z900. For lack of anything better,
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;; this description is also used for the g5 and g6.
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(include "2064.md")
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;; Pipeline description for z990.
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(include "2084.md")
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;; Predicates
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(include "predicates.md")
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;; Constraint definitions
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(include "constraints.md")
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;; Other includes
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(include "tpf.md")
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;; Macros
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;; This mode macro allows floating point patterns to be generated from the
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;; same template.
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(define_mode_macro FPR [TF DF SF])
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(define_mode_macro DSF [DF SF])
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;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
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;; from the same template.
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(define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
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;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
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;; from the same template.
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(define_mode_macro GPR [(DI "TARGET_64BIT") SI])
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(define_mode_macro DSI [DI SI])
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;; This mode macro allows :P to be used for patterns that operate on
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;; pointer-sized quantities. Exactly one of the two alternatives will match.
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(define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
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(define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
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;; This mode macro allows the QI and HI patterns to be defined from
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;; the same template.
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(define_mode_macro HQI [HI QI])
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;; This mode macro allows the integer patterns to be defined from the
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;; same template.
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(define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
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;; This macro allows to unify all 'bCOND' expander patterns.
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(define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
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ordered uneq unlt ungt unle unge ltgt])
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;; This macro allows to unify all 'sCOND' patterns.
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(define_code_macro SCOND [ltu gtu leu geu])
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;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
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;; the same template.
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(define_code_macro SHIFT [ashift lshiftrt])
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;; These macros allow to combine most atomic operations.
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(define_code_macro ATOMIC [and ior xor plus minus mult])
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(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
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(plus "add") (minus "sub") (mult "nand")])
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;; In FPR templates, a string like "ltbr" will expand to "ltxbr" in TFmode,
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;; "ltdbr" in DFmode, and "ltebr" in SFmode.
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(define_mode_attr xde [(TF "x") (DF "d") (SF "e")])
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;; In FPR templates, a string like "mbr" will expand to "mxbr" in TFmode,
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;; "mdbr" in DFmode, and "meebr" in SFmode.
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(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")])
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;; In FPR templates, "" will expand to "RRE" in TFmode and "RR" otherwise.
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;; Likewise for "".
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(define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
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(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
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;; In FPR templates, "" will expand to "f" in TFmode and "R" otherwise.
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;; This is used to disable the memory alternative in TFmode patterns.
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(define_mode_attr Rf [(TF "f") (DF "R") (SF "R")])
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;; In GPR and P templates, a constraint like "" will expand to "d" in DImode
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;; and "0" in SImode. This allows to combine instructions of which the 31bit
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;; version only operates on one register.
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(define_mode_attr d0 [(DI "d") (SI "0")])
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;; In combination with d0 this allows to combine instructions of which the 31bit
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;; version only operates on one register. The DImode version needs an additional
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;; register for the assembler output.
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(define_mode_attr 1 [(DI "%1,") (SI "")])
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;; In SHIFT templates, a string like "sdl" will expand to "sldl" in
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;; 'ashift' and "srdl" in 'lshiftrt'.
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(define_code_attr lr [(ashift "l") (lshiftrt "r")])
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;; In SHIFT templates, this attribute holds the correct standard name for the
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;; pattern itself and the corresponding function calls.
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(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
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;; This attribute handles differences in the instruction 'type' and will result
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;; in "RRE" for DImode and "RR" for SImode.
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(define_mode_attr E [(DI "E") (SI "")])
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;; This attribute handles differences in the instruction 'type' and makes RX
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;; to result in "RXY" for DImode and "RX" for SImode.
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(define_mode_attr Y [(DI "Y") (SI "")])
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;; This attribute handles differences in the instruction 'type' and will result
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;; in "RSE" for TImode and "RS" for DImode.
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(define_mode_attr TE [(TI "E") (DI "")])
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;; In GPR templates, a string like "lcr" will expand to "lcgr" in DImode
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;; and "lcr" in SImode.
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(define_mode_attr g [(DI "g") (SI "")])
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;; In GPR templates, a string like "sl" will expand to "slg" in DImode
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;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
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;; were enhanced with long displacements whereas 31bit instructions got a ..y
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;; variant for long displacements.
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(define_mode_attr y [(DI "g") (SI "y")])
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;; In DP templates, a string like "cds" will expand to "cdsg" in TImode
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;; and "cds" in DImode.
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(define_mode_attr tg [(TI "g") (DI "")])
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;; In GPR templates, a string like "cdbr" will expand to "cgdbr" in DImode
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;; and "cfdbr" in SImode.
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(define_mode_attr gf [(DI "g") (SI "f")])
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;; ICM mask required to load MODE value into the lowest subreg
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;; of a SImode register.
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(define_mode_attr icm_lo [(HI "3") (QI "1")])
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|
| 324 |
|
|
;; In HQI templates, a string like "llg" will expand to "llgh" in
|
| 325 |
|
|
;; HImode and "llgc" in QImode.
|
| 326 |
|
|
(define_mode_attr hc [(HI "h") (QI "c")])
|
| 327 |
|
|
|
| 328 |
|
|
;; In P templates, the mode will expand to "TI" in DImode and "DI"
|
| 329 |
|
|
;; in SImode.
|
| 330 |
|
|
(define_mode_attr DBL [(DI "TI") (SI "DI")])
|
| 331 |
|
|
|
| 332 |
|
|
;; Maximum unsigned integer that fits in MODE.
|
| 333 |
|
|
(define_mode_attr max_uint [(HI "65535") (QI "255")])
|
| 334 |
|
|
|
| 335 |
|
|
|
| 336 |
|
|
;;
|
| 337 |
|
|
;;- Compare instructions.
|
| 338 |
|
|
;;
|
| 339 |
|
|
|
| 340 |
|
|
(define_expand "cmp"
|
| 341 |
|
|
[(set (reg:CC CC_REGNUM)
|
| 342 |
|
|
(compare:CC (match_operand:GPR 0 "register_operand" "")
|
| 343 |
|
|
(match_operand:GPR 1 "general_operand" "")))]
|
| 344 |
|
|
""
|
| 345 |
|
|
{
|
| 346 |
|
|
s390_compare_op0 = operands[0];
|
| 347 |
|
|
s390_compare_op1 = operands[1];
|
| 348 |
|
|
DONE;
|
| 349 |
|
|
})
|
| 350 |
|
|
|
| 351 |
|
|
(define_expand "cmp"
|
| 352 |
|
|
[(set (reg:CC CC_REGNUM)
|
| 353 |
|
|
(compare:CC (match_operand:FPR 0 "register_operand" "")
|
| 354 |
|
|
(match_operand:FPR 1 "general_operand" "")))]
|
| 355 |
|
|
"TARGET_HARD_FLOAT"
|
| 356 |
|
|
{
|
| 357 |
|
|
s390_compare_op0 = operands[0];
|
| 358 |
|
|
s390_compare_op1 = operands[1];
|
| 359 |
|
|
DONE;
|
| 360 |
|
|
})
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
; Test-under-Mask instructions
|
| 364 |
|
|
|
| 365 |
|
|
(define_insn "*tmqi_mem"
|
| 366 |
|
|
[(set (reg CC_REGNUM)
|
| 367 |
|
|
(compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
|
| 368 |
|
|
(match_operand:QI 1 "immediate_operand" "n,n"))
|
| 369 |
|
|
(match_operand:QI 2 "immediate_operand" "n,n")))]
|
| 370 |
|
|
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
|
| 371 |
|
|
"@
|
| 372 |
|
|
tm\t%S0,%b1
|
| 373 |
|
|
tmy\t%S0,%b1"
|
| 374 |
|
|
[(set_attr "op_type" "SI,SIY")])
|
| 375 |
|
|
|
| 376 |
|
|
(define_insn "*tmdi_reg"
|
| 377 |
|
|
[(set (reg CC_REGNUM)
|
| 378 |
|
|
(compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
|
| 379 |
|
|
(match_operand:DI 1 "immediate_operand"
|
| 380 |
|
|
"N0HD0,N1HD0,N2HD0,N3HD0"))
|
| 381 |
|
|
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
|
| 382 |
|
|
"TARGET_64BIT
|
| 383 |
|
|
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
|
| 384 |
|
|
&& s390_single_part (operands[1], DImode, HImode, 0) >= 0"
|
| 385 |
|
|
"@
|
| 386 |
|
|
tmhh\t%0,%i1
|
| 387 |
|
|
tmhl\t%0,%i1
|
| 388 |
|
|
tmlh\t%0,%i1
|
| 389 |
|
|
tmll\t%0,%i1"
|
| 390 |
|
|
[(set_attr "op_type" "RI")])
|
| 391 |
|
|
|
| 392 |
|
|
(define_insn "*tmsi_reg"
|
| 393 |
|
|
[(set (reg CC_REGNUM)
|
| 394 |
|
|
(compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
|
| 395 |
|
|
(match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
|
| 396 |
|
|
(match_operand:SI 2 "immediate_operand" "n,n")))]
|
| 397 |
|
|
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
|
| 398 |
|
|
&& s390_single_part (operands[1], SImode, HImode, 0) >= 0"
|
| 399 |
|
|
"@
|
| 400 |
|
|
tmh\t%0,%i1
|
| 401 |
|
|
tml\t%0,%i1"
|
| 402 |
|
|
[(set_attr "op_type" "RI")])
|
| 403 |
|
|
|
| 404 |
|
|
(define_insn "*tm_full"
|
| 405 |
|
|
[(set (reg CC_REGNUM)
|
| 406 |
|
|
(compare (match_operand:HQI 0 "register_operand" "d")
|
| 407 |
|
|
(match_operand:HQI 1 "immediate_operand" "n")))]
|
| 408 |
|
|
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
|
| 409 |
|
|
"tml\t%0,"
|
| 410 |
|
|
[(set_attr "op_type" "RI")])
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
;
|
| 414 |
|
|
; Load-and-Test instructions
|
| 415 |
|
|
;
|
| 416 |
|
|
|
| 417 |
|
|
; tst(di|si) instruction pattern(s).
|
| 418 |
|
|
|
| 419 |
|
|
(define_insn "*tstdi_sign"
|
| 420 |
|
|
[(set (reg CC_REGNUM)
|
| 421 |
|
|
(compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
|
| 422 |
|
|
(const_int 32)) (const_int 32))
|
| 423 |
|
|
(match_operand:DI 1 "const0_operand" "")))
|
| 424 |
|
|
(set (match_operand:DI 2 "register_operand" "=d")
|
| 425 |
|
|
(sign_extend:DI (match_dup 0)))]
|
| 426 |
|
|
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
|
| 427 |
|
|
"ltgfr\t%2,%0"
|
| 428 |
|
|
[(set_attr "op_type" "RRE")])
|
| 429 |
|
|
|
| 430 |
|
|
; ltr, lt, ltgr, ltg
|
| 431 |
|
|
(define_insn "*tst_extimm"
|
| 432 |
|
|
[(set (reg CC_REGNUM)
|
| 433 |
|
|
(compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
|
| 434 |
|
|
(match_operand:GPR 1 "const0_operand" "")))
|
| 435 |
|
|
(set (match_operand:GPR 2 "register_operand" "=d,d")
|
| 436 |
|
|
(match_dup 0))]
|
| 437 |
|
|
"s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
|
| 438 |
|
|
"@
|
| 439 |
|
|
ltr\t%2,%0
|
| 440 |
|
|
lt\t%2,%0"
|
| 441 |
|
|
[(set_attr "op_type" "RR,RXY")])
|
| 442 |
|
|
|
| 443 |
|
|
; ltr, lt, ltgr, ltg
|
| 444 |
|
|
(define_insn "*tst_cconly_extimm"
|
| 445 |
|
|
[(set (reg CC_REGNUM)
|
| 446 |
|
|
(compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
|
| 447 |
|
|
(match_operand:GPR 1 "const0_operand" "")))
|
| 448 |
|
|
(clobber (match_scratch:GPR 2 "=X,d"))]
|
| 449 |
|
|
"s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
|
| 450 |
|
|
"@
|
| 451 |
|
|
ltr\t%0,%0
|
| 452 |
|
|
lt\t%2,%0"
|
| 453 |
|
|
[(set_attr "op_type" "RR,RXY")])
|
| 454 |
|
|
|
| 455 |
|
|
(define_insn "*tstdi"
|
| 456 |
|
|
[(set (reg CC_REGNUM)
|
| 457 |
|
|
(compare (match_operand:DI 0 "register_operand" "d")
|
| 458 |
|
|
(match_operand:DI 1 "const0_operand" "")))
|
| 459 |
|
|
(set (match_operand:DI 2 "register_operand" "=d")
|
| 460 |
|
|
(match_dup 0))]
|
| 461 |
|
|
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
|
| 462 |
|
|
"ltgr\t%2,%0"
|
| 463 |
|
|
[(set_attr "op_type" "RRE")])
|
| 464 |
|
|
|
| 465 |
|
|
(define_insn "*tstsi"
|
| 466 |
|
|
[(set (reg CC_REGNUM)
|
| 467 |
|
|
(compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
|
| 468 |
|
|
(match_operand:SI 1 "const0_operand" "")))
|
| 469 |
|
|
(set (match_operand:SI 2 "register_operand" "=d,d,d")
|
| 470 |
|
|
(match_dup 0))]
|
| 471 |
|
|
"s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
|
| 472 |
|
|
"@
|
| 473 |
|
|
ltr\t%2,%0
|
| 474 |
|
|
icm\t%2,15,%S0
|
| 475 |
|
|
icmy\t%2,15,%S0"
|
| 476 |
|
|
[(set_attr "op_type" "RR,RS,RSY")])
|
| 477 |
|
|
|
| 478 |
|
|
(define_insn "*tstsi_cconly"
|
| 479 |
|
|
[(set (reg CC_REGNUM)
|
| 480 |
|
|
(compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
|
| 481 |
|
|
(match_operand:SI 1 "const0_operand" "")))
|
| 482 |
|
|
(clobber (match_scratch:SI 2 "=X,d,d"))]
|
| 483 |
|
|
"s390_match_ccmode(insn, CCSmode)"
|
| 484 |
|
|
"@
|
| 485 |
|
|
ltr\t%0,%0
|
| 486 |
|
|
icm\t%2,15,%S0
|
| 487 |
|
|
icmy\t%2,15,%S0"
|
| 488 |
|
|
[(set_attr "op_type" "RR,RS,RSY")])
|
| 489 |
|
|
|
| 490 |
|
|
(define_insn "*tstdi_cconly_31"
|
| 491 |
|
|
[(set (reg CC_REGNUM)
|
| 492 |
|
|
(compare (match_operand:DI 0 "register_operand" "d")
|
| 493 |
|
|
(match_operand:DI 1 "const0_operand" "")))]
|
| 494 |
|
|
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
|
| 495 |
|
|
"srda\t%0,0"
|
| 496 |
|
|
[(set_attr "op_type" "RS")
|
| 497 |
|
|
(set_attr "atype" "reg")])
|
| 498 |
|
|
|
| 499 |
|
|
; ltr, ltgr
|
| 500 |
|
|
(define_insn "*tst_cconly2"
|
| 501 |
|
|
[(set (reg CC_REGNUM)
|
| 502 |
|
|
(compare (match_operand:GPR 0 "register_operand" "d")
|
| 503 |
|
|
(match_operand:GPR 1 "const0_operand" "")))]
|
| 504 |
|
|
"s390_match_ccmode(insn, CCSmode)"
|
| 505 |
|
|
"ltr\t%0,%0"
|
| 506 |
|
|
[(set_attr "op_type" "RR")])
|
| 507 |
|
|
|
| 508 |
|
|
; tst(hi|qi) instruction pattern(s).
|
| 509 |
|
|
|
| 510 |
|
|
(define_insn "*tstCCT"
|
| 511 |
|
|
[(set (reg CC_REGNUM)
|
| 512 |
|
|
(compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
|
| 513 |
|
|
(match_operand:HQI 1 "const0_operand" "")))
|
| 514 |
|
|
(set (match_operand:HQI 2 "register_operand" "=d,d,0")
|
| 515 |
|
|
(match_dup 0))]
|
| 516 |
|
|
"s390_match_ccmode(insn, CCTmode)"
|
| 517 |
|
|
"@
|
| 518 |
|
|
icm\t%2,,%S0
|
| 519 |
|
|
icmy\t%2,,%S0
|
| 520 |
|
|
tml\t%0,"
|
| 521 |
|
|
[(set_attr "op_type" "RS,RSY,RI")])
|
| 522 |
|
|
|
| 523 |
|
|
(define_insn "*tsthiCCT_cconly"
|
| 524 |
|
|
[(set (reg CC_REGNUM)
|
| 525 |
|
|
(compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
|
| 526 |
|
|
(match_operand:HI 1 "const0_operand" "")))
|
| 527 |
|
|
(clobber (match_scratch:HI 2 "=d,d,X"))]
|
| 528 |
|
|
"s390_match_ccmode(insn, CCTmode)"
|
| 529 |
|
|
"@
|
| 530 |
|
|
icm\t%2,3,%S0
|
| 531 |
|
|
icmy\t%2,3,%S0
|
| 532 |
|
|
tml\t%0,65535"
|
| 533 |
|
|
[(set_attr "op_type" "RS,RSY,RI")])
|
| 534 |
|
|
|
| 535 |
|
|
(define_insn "*tstqiCCT_cconly"
|
| 536 |
|
|
[(set (reg CC_REGNUM)
|
| 537 |
|
|
(compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
|
| 538 |
|
|
(match_operand:QI 1 "const0_operand" "")))]
|
| 539 |
|
|
"s390_match_ccmode(insn, CCTmode)"
|
| 540 |
|
|
"@
|
| 541 |
|
|
cli\t%S0,0
|
| 542 |
|
|
cliy\t%S0,0
|
| 543 |
|
|
tml\t%0,255"
|
| 544 |
|
|
[(set_attr "op_type" "SI,SIY,RI")])
|
| 545 |
|
|
|
| 546 |
|
|
(define_insn "*tst"
|
| 547 |
|
|
[(set (reg CC_REGNUM)
|
| 548 |
|
|
(compare (match_operand:HQI 0 "s_operand" "Q,S")
|
| 549 |
|
|
(match_operand:HQI 1 "const0_operand" "")))
|
| 550 |
|
|
(set (match_operand:HQI 2 "register_operand" "=d,d")
|
| 551 |
|
|
(match_dup 0))]
|
| 552 |
|
|
"s390_match_ccmode(insn, CCSmode)"
|
| 553 |
|
|
"@
|
| 554 |
|
|
icm\t%2,,%S0
|
| 555 |
|
|
icmy\t%2,,%S0"
|
| 556 |
|
|
[(set_attr "op_type" "RS,RSY")])
|
| 557 |
|
|
|
| 558 |
|
|
(define_insn "*tst_cconly"
|
| 559 |
|
|
[(set (reg CC_REGNUM)
|
| 560 |
|
|
(compare (match_operand:HQI 0 "s_operand" "Q,S")
|
| 561 |
|
|
(match_operand:HQI 1 "const0_operand" "")))
|
| 562 |
|
|
(clobber (match_scratch:HQI 2 "=d,d"))]
|
| 563 |
|
|
"s390_match_ccmode(insn, CCSmode)"
|
| 564 |
|
|
"@
|
| 565 |
|
|
icm\t%2,,%S0
|
| 566 |
|
|
icmy\t%2,,%S0"
|
| 567 |
|
|
[(set_attr "op_type" "RS,RSY")])
|
| 568 |
|
|
|
| 569 |
|
|
|
| 570 |
|
|
; Compare (equality) instructions
|
| 571 |
|
|
|
| 572 |
|
|
(define_insn "*cmpdi_cct"
|
| 573 |
|
|
[(set (reg CC_REGNUM)
|
| 574 |
|
|
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
|
| 575 |
|
|
(match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
|
| 576 |
|
|
"s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
|
| 577 |
|
|
"@
|
| 578 |
|
|
cgr\t%0,%1
|
| 579 |
|
|
cghi\t%0,%h1
|
| 580 |
|
|
cgfi\t%0,%1
|
| 581 |
|
|
cg\t%0,%1
|
| 582 |
|
|
#"
|
| 583 |
|
|
[(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
|
| 584 |
|
|
|
| 585 |
|
|
(define_insn "*cmpsi_cct"
|
| 586 |
|
|
[(set (reg CC_REGNUM)
|
| 587 |
|
|
(compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
|
| 588 |
|
|
(match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
|
| 589 |
|
|
"s390_match_ccmode (insn, CCTmode)"
|
| 590 |
|
|
"@
|
| 591 |
|
|
cr\t%0,%1
|
| 592 |
|
|
chi\t%0,%h1
|
| 593 |
|
|
cfi\t%0,%1
|
| 594 |
|
|
c\t%0,%1
|
| 595 |
|
|
cy\t%0,%1
|
| 596 |
|
|
#"
|
| 597 |
|
|
[(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
|
| 598 |
|
|
|
| 599 |
|
|
|
| 600 |
|
|
; Compare (signed) instructions
|
| 601 |
|
|
|
| 602 |
|
|
(define_insn "*cmpdi_ccs_sign"
|
| 603 |
|
|
[(set (reg CC_REGNUM)
|
| 604 |
|
|
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
|
| 605 |
|
|
(match_operand:DI 0 "register_operand" "d,d")))]
|
| 606 |
|
|
"s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
|
| 607 |
|
|
"@
|
| 608 |
|
|
cgfr\t%0,%1
|
| 609 |
|
|
cgf\t%0,%1"
|
| 610 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 611 |
|
|
|
| 612 |
|
|
(define_insn "*cmpsi_ccs_sign"
|
| 613 |
|
|
[(set (reg CC_REGNUM)
|
| 614 |
|
|
(compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
|
| 615 |
|
|
(match_operand:SI 0 "register_operand" "d,d")))]
|
| 616 |
|
|
"s390_match_ccmode(insn, CCSRmode)"
|
| 617 |
|
|
"@
|
| 618 |
|
|
ch\t%0,%1
|
| 619 |
|
|
chy\t%0,%1"
|
| 620 |
|
|
[(set_attr "op_type" "RX,RXY")])
|
| 621 |
|
|
|
| 622 |
|
|
; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg
|
| 623 |
|
|
(define_insn "*cmp_ccs"
|
| 624 |
|
|
[(set (reg CC_REGNUM)
|
| 625 |
|
|
(compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
|
| 626 |
|
|
(match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
|
| 627 |
|
|
"s390_match_ccmode(insn, CCSmode)"
|
| 628 |
|
|
"@
|
| 629 |
|
|
cr\t%0,%1
|
| 630 |
|
|
chi\t%0,%h1
|
| 631 |
|
|
cfi\t%0,%1
|
| 632 |
|
|
c\t%0,%1
|
| 633 |
|
|
c\t%0,%1"
|
| 634 |
|
|
[(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
|
| 635 |
|
|
|
| 636 |
|
|
|
| 637 |
|
|
; Compare (unsigned) instructions
|
| 638 |
|
|
|
| 639 |
|
|
(define_insn "*cmpdi_ccu_zero"
|
| 640 |
|
|
[(set (reg CC_REGNUM)
|
| 641 |
|
|
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
|
| 642 |
|
|
(match_operand:DI 0 "register_operand" "d,d")))]
|
| 643 |
|
|
"s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
|
| 644 |
|
|
"@
|
| 645 |
|
|
clgfr\t%0,%1
|
| 646 |
|
|
clgf\t%0,%1"
|
| 647 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 648 |
|
|
|
| 649 |
|
|
(define_insn "*cmpdi_ccu"
|
| 650 |
|
|
[(set (reg CC_REGNUM)
|
| 651 |
|
|
(compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
|
| 652 |
|
|
(match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
|
| 653 |
|
|
"s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
|
| 654 |
|
|
"@
|
| 655 |
|
|
clgr\t%0,%1
|
| 656 |
|
|
clgfi\t%0,%1
|
| 657 |
|
|
clg\t%0,%1
|
| 658 |
|
|
#
|
| 659 |
|
|
#"
|
| 660 |
|
|
[(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
|
| 661 |
|
|
|
| 662 |
|
|
(define_insn "*cmpsi_ccu"
|
| 663 |
|
|
[(set (reg CC_REGNUM)
|
| 664 |
|
|
(compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
|
| 665 |
|
|
(match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
|
| 666 |
|
|
"s390_match_ccmode (insn, CCUmode)"
|
| 667 |
|
|
"@
|
| 668 |
|
|
clr\t%0,%1
|
| 669 |
|
|
clfi\t%0,%o1
|
| 670 |
|
|
cl\t%0,%1
|
| 671 |
|
|
cly\t%0,%1
|
| 672 |
|
|
#
|
| 673 |
|
|
#"
|
| 674 |
|
|
[(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
|
| 675 |
|
|
|
| 676 |
|
|
(define_insn "*cmphi_ccu"
|
| 677 |
|
|
[(set (reg CC_REGNUM)
|
| 678 |
|
|
(compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
|
| 679 |
|
|
(match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
|
| 680 |
|
|
"s390_match_ccmode (insn, CCUmode)
|
| 681 |
|
|
&& !register_operand (operands[1], HImode)"
|
| 682 |
|
|
"@
|
| 683 |
|
|
clm\t%0,3,%S1
|
| 684 |
|
|
clmy\t%0,3,%S1
|
| 685 |
|
|
#
|
| 686 |
|
|
#"
|
| 687 |
|
|
[(set_attr "op_type" "RS,RSY,SS,SS")])
|
| 688 |
|
|
|
| 689 |
|
|
(define_insn "*cmpqi_ccu"
|
| 690 |
|
|
[(set (reg CC_REGNUM)
|
| 691 |
|
|
(compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
|
| 692 |
|
|
(match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
|
| 693 |
|
|
"s390_match_ccmode (insn, CCUmode)
|
| 694 |
|
|
&& !register_operand (operands[1], QImode)"
|
| 695 |
|
|
"@
|
| 696 |
|
|
clm\t%0,1,%S1
|
| 697 |
|
|
clmy\t%0,1,%S1
|
| 698 |
|
|
cli\t%S0,%b1
|
| 699 |
|
|
cliy\t%S0,%b1
|
| 700 |
|
|
#
|
| 701 |
|
|
#"
|
| 702 |
|
|
[(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
|
| 703 |
|
|
|
| 704 |
|
|
|
| 705 |
|
|
; Block compare (CLC) instruction patterns.
|
| 706 |
|
|
|
| 707 |
|
|
(define_insn "*clc"
|
| 708 |
|
|
[(set (reg CC_REGNUM)
|
| 709 |
|
|
(compare (match_operand:BLK 0 "memory_operand" "Q")
|
| 710 |
|
|
(match_operand:BLK 1 "memory_operand" "Q")))
|
| 711 |
|
|
(use (match_operand 2 "const_int_operand" "n"))]
|
| 712 |
|
|
"s390_match_ccmode (insn, CCUmode)
|
| 713 |
|
|
&& INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
|
| 714 |
|
|
"clc\t%O0(%2,%R0),%S1"
|
| 715 |
|
|
[(set_attr "op_type" "SS")])
|
| 716 |
|
|
|
| 717 |
|
|
(define_split
|
| 718 |
|
|
[(set (reg CC_REGNUM)
|
| 719 |
|
|
(compare (match_operand 0 "memory_operand" "")
|
| 720 |
|
|
(match_operand 1 "memory_operand" "")))]
|
| 721 |
|
|
"reload_completed
|
| 722 |
|
|
&& s390_match_ccmode (insn, CCUmode)
|
| 723 |
|
|
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
|
| 724 |
|
|
&& GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
|
| 725 |
|
|
[(parallel
|
| 726 |
|
|
[(set (match_dup 0) (match_dup 1))
|
| 727 |
|
|
(use (match_dup 2))])]
|
| 728 |
|
|
{
|
| 729 |
|
|
operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
|
| 730 |
|
|
operands[0] = adjust_address (operands[0], BLKmode, 0);
|
| 731 |
|
|
operands[1] = adjust_address (operands[1], BLKmode, 0);
|
| 732 |
|
|
|
| 733 |
|
|
operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
|
| 734 |
|
|
operands[0], operands[1]);
|
| 735 |
|
|
operands[0] = SET_DEST (PATTERN (curr_insn));
|
| 736 |
|
|
})
|
| 737 |
|
|
|
| 738 |
|
|
|
| 739 |
|
|
; (DF|SF) instructions
|
| 740 |
|
|
|
| 741 |
|
|
; ltxbr, ltdbr, ltebr
|
| 742 |
|
|
(define_insn "*cmp_ccs_0"
|
| 743 |
|
|
[(set (reg CC_REGNUM)
|
| 744 |
|
|
(compare (match_operand:FPR 0 "register_operand" "f")
|
| 745 |
|
|
(match_operand:FPR 1 "const0_operand" "")))]
|
| 746 |
|
|
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 747 |
|
|
"ltbr\t%0,%0"
|
| 748 |
|
|
[(set_attr "op_type" "RRE")
|
| 749 |
|
|
(set_attr "type" "fsimp")])
|
| 750 |
|
|
|
| 751 |
|
|
; ltxr, ltdr, lter
|
| 752 |
|
|
(define_insn "*cmp_ccs_0_ibm"
|
| 753 |
|
|
[(set (reg CC_REGNUM)
|
| 754 |
|
|
(compare (match_operand:FPR 0 "register_operand" "f")
|
| 755 |
|
|
(match_operand:FPR 1 "const0_operand" "")))]
|
| 756 |
|
|
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 757 |
|
|
"ltr\t%0,%0"
|
| 758 |
|
|
[(set_attr "op_type" "")
|
| 759 |
|
|
(set_attr "type" "fsimp")])
|
| 760 |
|
|
|
| 761 |
|
|
; cxbr, cdbr, cebr, cxb, cdb, ceb
|
| 762 |
|
|
(define_insn "*cmp_ccs"
|
| 763 |
|
|
[(set (reg CC_REGNUM)
|
| 764 |
|
|
(compare (match_operand:FPR 0 "register_operand" "f,f")
|
| 765 |
|
|
(match_operand:FPR 1 "general_operand" "f,")))]
|
| 766 |
|
|
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 767 |
|
|
"@
|
| 768 |
|
|
cbr\t%0,%1
|
| 769 |
|
|
cb\t%0,%1"
|
| 770 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 771 |
|
|
(set_attr "type" "fsimp")])
|
| 772 |
|
|
|
| 773 |
|
|
; cxr, cdr, cer, cx, cd, ce
|
| 774 |
|
|
(define_insn "*cmp_ccs_ibm"
|
| 775 |
|
|
[(set (reg CC_REGNUM)
|
| 776 |
|
|
(compare (match_operand:FPR 0 "register_operand" "f,f")
|
| 777 |
|
|
(match_operand:FPR 1 "general_operand" "f,")))]
|
| 778 |
|
|
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 779 |
|
|
"@
|
| 780 |
|
|
cr\t%0,%1
|
| 781 |
|
|
c\t%0,%1"
|
| 782 |
|
|
[(set_attr "op_type" ",")
|
| 783 |
|
|
(set_attr "type" "fsimp")])
|
| 784 |
|
|
|
| 785 |
|
|
|
| 786 |
|
|
;;
|
| 787 |
|
|
;;- Move instructions.
|
| 788 |
|
|
;;
|
| 789 |
|
|
|
| 790 |
|
|
;
|
| 791 |
|
|
; movti instruction pattern(s).
|
| 792 |
|
|
;
|
| 793 |
|
|
|
| 794 |
|
|
(define_insn "movti"
|
| 795 |
|
|
[(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
|
| 796 |
|
|
(match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
|
| 797 |
|
|
"TARGET_64BIT"
|
| 798 |
|
|
"@
|
| 799 |
|
|
lmg\t%0,%N0,%S1
|
| 800 |
|
|
stmg\t%1,%N1,%S0
|
| 801 |
|
|
#
|
| 802 |
|
|
#
|
| 803 |
|
|
#"
|
| 804 |
|
|
[(set_attr "op_type" "RSY,RSY,*,*,SS")
|
| 805 |
|
|
(set_attr "type" "lm,stm,*,*,*")])
|
| 806 |
|
|
|
| 807 |
|
|
(define_split
|
| 808 |
|
|
[(set (match_operand:TI 0 "nonimmediate_operand" "")
|
| 809 |
|
|
(match_operand:TI 1 "general_operand" ""))]
|
| 810 |
|
|
"TARGET_64BIT && reload_completed
|
| 811 |
|
|
&& s390_split_ok_p (operands[0], operands[1], TImode, 0)"
|
| 812 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 813 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 814 |
|
|
{
|
| 815 |
|
|
operands[2] = operand_subword (operands[0], 0, 0, TImode);
|
| 816 |
|
|
operands[3] = operand_subword (operands[0], 1, 0, TImode);
|
| 817 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, TImode);
|
| 818 |
|
|
operands[5] = operand_subword (operands[1], 1, 0, TImode);
|
| 819 |
|
|
})
|
| 820 |
|
|
|
| 821 |
|
|
(define_split
|
| 822 |
|
|
[(set (match_operand:TI 0 "nonimmediate_operand" "")
|
| 823 |
|
|
(match_operand:TI 1 "general_operand" ""))]
|
| 824 |
|
|
"TARGET_64BIT && reload_completed
|
| 825 |
|
|
&& s390_split_ok_p (operands[0], operands[1], TImode, 1)"
|
| 826 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 827 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 828 |
|
|
{
|
| 829 |
|
|
operands[2] = operand_subword (operands[0], 1, 0, TImode);
|
| 830 |
|
|
operands[3] = operand_subword (operands[0], 0, 0, TImode);
|
| 831 |
|
|
operands[4] = operand_subword (operands[1], 1, 0, TImode);
|
| 832 |
|
|
operands[5] = operand_subword (operands[1], 0, 0, TImode);
|
| 833 |
|
|
})
|
| 834 |
|
|
|
| 835 |
|
|
(define_split
|
| 836 |
|
|
[(set (match_operand:TI 0 "register_operand" "")
|
| 837 |
|
|
(match_operand:TI 1 "memory_operand" ""))]
|
| 838 |
|
|
"TARGET_64BIT && reload_completed
|
| 839 |
|
|
&& !s_operand (operands[1], VOIDmode)"
|
| 840 |
|
|
[(set (match_dup 0) (match_dup 1))]
|
| 841 |
|
|
{
|
| 842 |
|
|
rtx addr = operand_subword (operands[0], 1, 0, TImode);
|
| 843 |
|
|
s390_load_address (addr, XEXP (operands[1], 0));
|
| 844 |
|
|
operands[1] = replace_equiv_address (operands[1], addr);
|
| 845 |
|
|
})
|
| 846 |
|
|
|
| 847 |
|
|
(define_expand "reload_outti"
|
| 848 |
|
|
[(parallel [(match_operand:TI 0 "" "")
|
| 849 |
|
|
(match_operand:TI 1 "register_operand" "d")
|
| 850 |
|
|
(match_operand:DI 2 "register_operand" "=&a")])]
|
| 851 |
|
|
"TARGET_64BIT"
|
| 852 |
|
|
{
|
| 853 |
|
|
gcc_assert (MEM_P (operands[0]));
|
| 854 |
|
|
s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
|
| 855 |
|
|
operands[0] = replace_equiv_address (operands[0], operands[2]);
|
| 856 |
|
|
emit_move_insn (operands[0], operands[1]);
|
| 857 |
|
|
DONE;
|
| 858 |
|
|
})
|
| 859 |
|
|
|
| 860 |
|
|
;
|
| 861 |
|
|
; movdi instruction pattern(s).
|
| 862 |
|
|
;
|
| 863 |
|
|
|
| 864 |
|
|
(define_expand "movdi"
|
| 865 |
|
|
[(set (match_operand:DI 0 "general_operand" "")
|
| 866 |
|
|
(match_operand:DI 1 "general_operand" ""))]
|
| 867 |
|
|
""
|
| 868 |
|
|
{
|
| 869 |
|
|
/* Handle symbolic constants. */
|
| 870 |
|
|
if (TARGET_64BIT
|
| 871 |
|
|
&& (SYMBOLIC_CONST (operands[1])
|
| 872 |
|
|
|| (GET_CODE (operands[1]) == PLUS
|
| 873 |
|
|
&& XEXP (operands[1], 0) == pic_offset_table_rtx
|
| 874 |
|
|
&& SYMBOLIC_CONST (XEXP (operands[1], 1)))))
|
| 875 |
|
|
emit_symbolic_move (operands);
|
| 876 |
|
|
})
|
| 877 |
|
|
|
| 878 |
|
|
(define_insn "*movdi_larl"
|
| 879 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 880 |
|
|
(match_operand:DI 1 "larl_operand" "X"))]
|
| 881 |
|
|
"TARGET_64BIT
|
| 882 |
|
|
&& !FP_REG_P (operands[0])"
|
| 883 |
|
|
"larl\t%0,%1"
|
| 884 |
|
|
[(set_attr "op_type" "RIL")
|
| 885 |
|
|
(set_attr "type" "larl")])
|
| 886 |
|
|
|
| 887 |
|
|
(define_insn "*movdi_64extimm"
|
| 888 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand"
|
| 889 |
|
|
"=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
|
| 890 |
|
|
(match_operand:DI 1 "general_operand"
|
| 891 |
|
|
"K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
|
| 892 |
|
|
"TARGET_64BIT && TARGET_EXTIMM"
|
| 893 |
|
|
"@
|
| 894 |
|
|
lghi\t%0,%h1
|
| 895 |
|
|
llihh\t%0,%i1
|
| 896 |
|
|
llihl\t%0,%i1
|
| 897 |
|
|
llilh\t%0,%i1
|
| 898 |
|
|
llill\t%0,%i1
|
| 899 |
|
|
lgfi\t%0,%1
|
| 900 |
|
|
llihf\t%0,%k1
|
| 901 |
|
|
llilf\t%0,%k1
|
| 902 |
|
|
lay\t%0,%a1
|
| 903 |
|
|
lgr\t%0,%1
|
| 904 |
|
|
lg\t%0,%1
|
| 905 |
|
|
stg\t%1,%0
|
| 906 |
|
|
ldr\t%0,%1
|
| 907 |
|
|
ld\t%0,%1
|
| 908 |
|
|
ldy\t%0,%1
|
| 909 |
|
|
std\t%1,%0
|
| 910 |
|
|
stdy\t%1,%0
|
| 911 |
|
|
#
|
| 912 |
|
|
#
|
| 913 |
|
|
stam\t%1,%N1,%S0
|
| 914 |
|
|
lam\t%0,%N0,%S1
|
| 915 |
|
|
#"
|
| 916 |
|
|
[(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
|
| 917 |
|
|
RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
|
| 918 |
|
|
(set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
|
| 919 |
|
|
floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
|
| 920 |
|
|
|
| 921 |
|
|
(define_insn "*movdi_64"
|
| 922 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand"
|
| 923 |
|
|
"=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
|
| 924 |
|
|
(match_operand:DI 1 "general_operand"
|
| 925 |
|
|
"K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
|
| 926 |
|
|
"TARGET_64BIT && !TARGET_EXTIMM"
|
| 927 |
|
|
"@
|
| 928 |
|
|
lghi\t%0,%h1
|
| 929 |
|
|
llihh\t%0,%i1
|
| 930 |
|
|
llihl\t%0,%i1
|
| 931 |
|
|
llilh\t%0,%i1
|
| 932 |
|
|
llill\t%0,%i1
|
| 933 |
|
|
lay\t%0,%a1
|
| 934 |
|
|
lgr\t%0,%1
|
| 935 |
|
|
lg\t%0,%1
|
| 936 |
|
|
stg\t%1,%0
|
| 937 |
|
|
ldr\t%0,%1
|
| 938 |
|
|
ld\t%0,%1
|
| 939 |
|
|
ldy\t%0,%1
|
| 940 |
|
|
std\t%1,%0
|
| 941 |
|
|
stdy\t%1,%0
|
| 942 |
|
|
#
|
| 943 |
|
|
#
|
| 944 |
|
|
stam\t%1,%N1,%S0
|
| 945 |
|
|
lam\t%0,%N0,%S1
|
| 946 |
|
|
#"
|
| 947 |
|
|
[(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
|
| 948 |
|
|
RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
|
| 949 |
|
|
(set_attr "type" "*,*,*,*,*,la,lr,load,store,
|
| 950 |
|
|
floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
|
| 951 |
|
|
|
| 952 |
|
|
(define_split
|
| 953 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 954 |
|
|
(match_operand:DI 1 "register_operand" ""))]
|
| 955 |
|
|
"TARGET_64BIT && ACCESS_REG_P (operands[1])"
|
| 956 |
|
|
[(set (match_dup 2) (match_dup 3))
|
| 957 |
|
|
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
|
| 958 |
|
|
(set (strict_low_part (match_dup 2)) (match_dup 4))]
|
| 959 |
|
|
"operands[2] = gen_lowpart (SImode, operands[0]);
|
| 960 |
|
|
s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
|
| 961 |
|
|
|
| 962 |
|
|
(define_split
|
| 963 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 964 |
|
|
(match_operand:DI 1 "register_operand" ""))]
|
| 965 |
|
|
"TARGET_64BIT && ACCESS_REG_P (operands[0])
|
| 966 |
|
|
&& dead_or_set_p (insn, operands[1])"
|
| 967 |
|
|
[(set (match_dup 3) (match_dup 2))
|
| 968 |
|
|
(set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
|
| 969 |
|
|
(set (match_dup 4) (match_dup 2))]
|
| 970 |
|
|
"operands[2] = gen_lowpart (SImode, operands[1]);
|
| 971 |
|
|
s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
|
| 972 |
|
|
|
| 973 |
|
|
(define_split
|
| 974 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 975 |
|
|
(match_operand:DI 1 "register_operand" ""))]
|
| 976 |
|
|
"TARGET_64BIT && ACCESS_REG_P (operands[0])
|
| 977 |
|
|
&& !dead_or_set_p (insn, operands[1])"
|
| 978 |
|
|
[(set (match_dup 3) (match_dup 2))
|
| 979 |
|
|
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
|
| 980 |
|
|
(set (match_dup 4) (match_dup 2))
|
| 981 |
|
|
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
|
| 982 |
|
|
"operands[2] = gen_lowpart (SImode, operands[1]);
|
| 983 |
|
|
s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
|
| 984 |
|
|
|
| 985 |
|
|
(define_insn "*movdi_31"
|
| 986 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
|
| 987 |
|
|
(match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
|
| 988 |
|
|
"!TARGET_64BIT"
|
| 989 |
|
|
"@
|
| 990 |
|
|
lm\t%0,%N0,%S1
|
| 991 |
|
|
lmy\t%0,%N0,%S1
|
| 992 |
|
|
stm\t%1,%N1,%S0
|
| 993 |
|
|
stmy\t%1,%N1,%S0
|
| 994 |
|
|
#
|
| 995 |
|
|
#
|
| 996 |
|
|
ldr\t%0,%1
|
| 997 |
|
|
ld\t%0,%1
|
| 998 |
|
|
ldy\t%0,%1
|
| 999 |
|
|
std\t%1,%0
|
| 1000 |
|
|
stdy\t%1,%0
|
| 1001 |
|
|
#"
|
| 1002 |
|
|
[(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
|
| 1003 |
|
|
(set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
|
| 1004 |
|
|
|
| 1005 |
|
|
(define_split
|
| 1006 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "")
|
| 1007 |
|
|
(match_operand:DI 1 "general_operand" ""))]
|
| 1008 |
|
|
"!TARGET_64BIT && reload_completed
|
| 1009 |
|
|
&& s390_split_ok_p (operands[0], operands[1], DImode, 0)"
|
| 1010 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 1011 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 1012 |
|
|
{
|
| 1013 |
|
|
operands[2] = operand_subword (operands[0], 0, 0, DImode);
|
| 1014 |
|
|
operands[3] = operand_subword (operands[0], 1, 0, DImode);
|
| 1015 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, DImode);
|
| 1016 |
|
|
operands[5] = operand_subword (operands[1], 1, 0, DImode);
|
| 1017 |
|
|
})
|
| 1018 |
|
|
|
| 1019 |
|
|
(define_split
|
| 1020 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "")
|
| 1021 |
|
|
(match_operand:DI 1 "general_operand" ""))]
|
| 1022 |
|
|
"!TARGET_64BIT && reload_completed
|
| 1023 |
|
|
&& s390_split_ok_p (operands[0], operands[1], DImode, 1)"
|
| 1024 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 1025 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 1026 |
|
|
{
|
| 1027 |
|
|
operands[2] = operand_subword (operands[0], 1, 0, DImode);
|
| 1028 |
|
|
operands[3] = operand_subword (operands[0], 0, 0, DImode);
|
| 1029 |
|
|
operands[4] = operand_subword (operands[1], 1, 0, DImode);
|
| 1030 |
|
|
operands[5] = operand_subword (operands[1], 0, 0, DImode);
|
| 1031 |
|
|
})
|
| 1032 |
|
|
|
| 1033 |
|
|
(define_split
|
| 1034 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 1035 |
|
|
(match_operand:DI 1 "memory_operand" ""))]
|
| 1036 |
|
|
"!TARGET_64BIT && reload_completed
|
| 1037 |
|
|
&& !FP_REG_P (operands[0])
|
| 1038 |
|
|
&& !s_operand (operands[1], VOIDmode)"
|
| 1039 |
|
|
[(set (match_dup 0) (match_dup 1))]
|
| 1040 |
|
|
{
|
| 1041 |
|
|
rtx addr = operand_subword (operands[0], 1, 0, DImode);
|
| 1042 |
|
|
s390_load_address (addr, XEXP (operands[1], 0));
|
| 1043 |
|
|
operands[1] = replace_equiv_address (operands[1], addr);
|
| 1044 |
|
|
})
|
| 1045 |
|
|
|
| 1046 |
|
|
(define_expand "reload_outdi"
|
| 1047 |
|
|
[(parallel [(match_operand:DI 0 "" "")
|
| 1048 |
|
|
(match_operand:DI 1 "register_operand" "d")
|
| 1049 |
|
|
(match_operand:SI 2 "register_operand" "=&a")])]
|
| 1050 |
|
|
"!TARGET_64BIT"
|
| 1051 |
|
|
{
|
| 1052 |
|
|
gcc_assert (MEM_P (operands[0]));
|
| 1053 |
|
|
s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
|
| 1054 |
|
|
operands[0] = replace_equiv_address (operands[0], operands[2]);
|
| 1055 |
|
|
emit_move_insn (operands[0], operands[1]);
|
| 1056 |
|
|
DONE;
|
| 1057 |
|
|
})
|
| 1058 |
|
|
|
| 1059 |
|
|
(define_peephole2
|
| 1060 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 1061 |
|
|
(mem:DI (match_operand 1 "address_operand" "")))]
|
| 1062 |
|
|
"TARGET_64BIT
|
| 1063 |
|
|
&& !FP_REG_P (operands[0])
|
| 1064 |
|
|
&& GET_CODE (operands[1]) == SYMBOL_REF
|
| 1065 |
|
|
&& CONSTANT_POOL_ADDRESS_P (operands[1])
|
| 1066 |
|
|
&& get_pool_mode (operands[1]) == DImode
|
| 1067 |
|
|
&& legitimate_reload_constant_p (get_pool_constant (operands[1]))"
|
| 1068 |
|
|
[(set (match_dup 0) (match_dup 2))]
|
| 1069 |
|
|
"operands[2] = get_pool_constant (operands[1]);")
|
| 1070 |
|
|
|
| 1071 |
|
|
(define_insn "*la_64"
|
| 1072 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 1073 |
|
|
(match_operand:QI 1 "address_operand" "U,W"))]
|
| 1074 |
|
|
"TARGET_64BIT"
|
| 1075 |
|
|
"@
|
| 1076 |
|
|
la\t%0,%a1
|
| 1077 |
|
|
lay\t%0,%a1"
|
| 1078 |
|
|
[(set_attr "op_type" "RX,RXY")
|
| 1079 |
|
|
(set_attr "type" "la")])
|
| 1080 |
|
|
|
| 1081 |
|
|
(define_peephole2
|
| 1082 |
|
|
[(parallel
|
| 1083 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 1084 |
|
|
(match_operand:QI 1 "address_operand" ""))
|
| 1085 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 1086 |
|
|
"TARGET_64BIT
|
| 1087 |
|
|
&& preferred_la_operand_p (operands[1], const0_rtx)"
|
| 1088 |
|
|
[(set (match_dup 0) (match_dup 1))]
|
| 1089 |
|
|
"")
|
| 1090 |
|
|
|
| 1091 |
|
|
(define_peephole2
|
| 1092 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 1093 |
|
|
(match_operand:DI 1 "register_operand" ""))
|
| 1094 |
|
|
(parallel
|
| 1095 |
|
|
[(set (match_dup 0)
|
| 1096 |
|
|
(plus:DI (match_dup 0)
|
| 1097 |
|
|
(match_operand:DI 2 "nonmemory_operand" "")))
|
| 1098 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 1099 |
|
|
"TARGET_64BIT
|
| 1100 |
|
|
&& !reg_overlap_mentioned_p (operands[0], operands[2])
|
| 1101 |
|
|
&& preferred_la_operand_p (operands[1], operands[2])"
|
| 1102 |
|
|
[(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
|
| 1103 |
|
|
"")
|
| 1104 |
|
|
|
| 1105 |
|
|
(define_expand "reload_indi"
|
| 1106 |
|
|
[(parallel [(match_operand:DI 0 "register_operand" "=a")
|
| 1107 |
|
|
(match_operand:DI 1 "s390_plus_operand" "")
|
| 1108 |
|
|
(match_operand:DI 2 "register_operand" "=&a")])]
|
| 1109 |
|
|
"TARGET_64BIT"
|
| 1110 |
|
|
{
|
| 1111 |
|
|
s390_expand_plus_operand (operands[0], operands[1], operands[2]);
|
| 1112 |
|
|
DONE;
|
| 1113 |
|
|
})
|
| 1114 |
|
|
|
| 1115 |
|
|
;
|
| 1116 |
|
|
; movsi instruction pattern(s).
|
| 1117 |
|
|
;
|
| 1118 |
|
|
|
| 1119 |
|
|
(define_expand "movsi"
|
| 1120 |
|
|
[(set (match_operand:SI 0 "general_operand" "")
|
| 1121 |
|
|
(match_operand:SI 1 "general_operand" ""))]
|
| 1122 |
|
|
""
|
| 1123 |
|
|
{
|
| 1124 |
|
|
/* Handle symbolic constants. */
|
| 1125 |
|
|
if (!TARGET_64BIT
|
| 1126 |
|
|
&& (SYMBOLIC_CONST (operands[1])
|
| 1127 |
|
|
|| (GET_CODE (operands[1]) == PLUS
|
| 1128 |
|
|
&& XEXP (operands[1], 0) == pic_offset_table_rtx
|
| 1129 |
|
|
&& SYMBOLIC_CONST (XEXP(operands[1], 1)))))
|
| 1130 |
|
|
emit_symbolic_move (operands);
|
| 1131 |
|
|
})
|
| 1132 |
|
|
|
| 1133 |
|
|
(define_insn "*movsi_larl"
|
| 1134 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 1135 |
|
|
(match_operand:SI 1 "larl_operand" "X"))]
|
| 1136 |
|
|
"!TARGET_64BIT && TARGET_CPU_ZARCH
|
| 1137 |
|
|
&& !FP_REG_P (operands[0])"
|
| 1138 |
|
|
"larl\t%0,%1"
|
| 1139 |
|
|
[(set_attr "op_type" "RIL")
|
| 1140 |
|
|
(set_attr "type" "larl")])
|
| 1141 |
|
|
|
| 1142 |
|
|
(define_insn "*movsi_zarch"
|
| 1143 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand"
|
| 1144 |
|
|
"=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
|
| 1145 |
|
|
(match_operand:SI 1 "general_operand"
|
| 1146 |
|
|
"K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
|
| 1147 |
|
|
"TARGET_ZARCH"
|
| 1148 |
|
|
"@
|
| 1149 |
|
|
lhi\t%0,%h1
|
| 1150 |
|
|
llilh\t%0,%i1
|
| 1151 |
|
|
llill\t%0,%i1
|
| 1152 |
|
|
iilf\t%0,%o1
|
| 1153 |
|
|
lay\t%0,%a1
|
| 1154 |
|
|
lr\t%0,%1
|
| 1155 |
|
|
l\t%0,%1
|
| 1156 |
|
|
ly\t%0,%1
|
| 1157 |
|
|
st\t%1,%0
|
| 1158 |
|
|
sty\t%1,%0
|
| 1159 |
|
|
ler\t%0,%1
|
| 1160 |
|
|
le\t%0,%1
|
| 1161 |
|
|
ley\t%0,%1
|
| 1162 |
|
|
ste\t%1,%0
|
| 1163 |
|
|
stey\t%1,%0
|
| 1164 |
|
|
ear\t%0,%1
|
| 1165 |
|
|
sar\t%0,%1
|
| 1166 |
|
|
stam\t%1,%1,%S0
|
| 1167 |
|
|
lam\t%0,%0,%S1
|
| 1168 |
|
|
#"
|
| 1169 |
|
|
[(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
|
| 1170 |
|
|
RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
|
| 1171 |
|
|
(set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
|
| 1172 |
|
|
floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
|
| 1173 |
|
|
|
| 1174 |
|
|
(define_insn "*movsi_esa"
|
| 1175 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
|
| 1176 |
|
|
(match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
|
| 1177 |
|
|
"!TARGET_ZARCH"
|
| 1178 |
|
|
"@
|
| 1179 |
|
|
lhi\t%0,%h1
|
| 1180 |
|
|
lr\t%0,%1
|
| 1181 |
|
|
l\t%0,%1
|
| 1182 |
|
|
st\t%1,%0
|
| 1183 |
|
|
ler\t%0,%1
|
| 1184 |
|
|
le\t%0,%1
|
| 1185 |
|
|
ste\t%1,%0
|
| 1186 |
|
|
ear\t%0,%1
|
| 1187 |
|
|
sar\t%0,%1
|
| 1188 |
|
|
stam\t%1,%1,%S0
|
| 1189 |
|
|
lam\t%0,%0,%S1
|
| 1190 |
|
|
#"
|
| 1191 |
|
|
[(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
|
| 1192 |
|
|
(set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
|
| 1193 |
|
|
|
| 1194 |
|
|
(define_peephole2
|
| 1195 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 1196 |
|
|
(mem:SI (match_operand 1 "address_operand" "")))]
|
| 1197 |
|
|
"!FP_REG_P (operands[0])
|
| 1198 |
|
|
&& GET_CODE (operands[1]) == SYMBOL_REF
|
| 1199 |
|
|
&& CONSTANT_POOL_ADDRESS_P (operands[1])
|
| 1200 |
|
|
&& get_pool_mode (operands[1]) == SImode
|
| 1201 |
|
|
&& legitimate_reload_constant_p (get_pool_constant (operands[1]))"
|
| 1202 |
|
|
[(set (match_dup 0) (match_dup 2))]
|
| 1203 |
|
|
"operands[2] = get_pool_constant (operands[1]);")
|
| 1204 |
|
|
|
| 1205 |
|
|
(define_insn "*la_31"
|
| 1206 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 1207 |
|
|
(match_operand:QI 1 "address_operand" "U,W"))]
|
| 1208 |
|
|
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
|
| 1209 |
|
|
"@
|
| 1210 |
|
|
la\t%0,%a1
|
| 1211 |
|
|
lay\t%0,%a1"
|
| 1212 |
|
|
[(set_attr "op_type" "RX,RXY")
|
| 1213 |
|
|
(set_attr "type" "la")])
|
| 1214 |
|
|
|
| 1215 |
|
|
(define_peephole2
|
| 1216 |
|
|
[(parallel
|
| 1217 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 1218 |
|
|
(match_operand:QI 1 "address_operand" ""))
|
| 1219 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 1220 |
|
|
"!TARGET_64BIT
|
| 1221 |
|
|
&& preferred_la_operand_p (operands[1], const0_rtx)"
|
| 1222 |
|
|
[(set (match_dup 0) (match_dup 1))]
|
| 1223 |
|
|
"")
|
| 1224 |
|
|
|
| 1225 |
|
|
(define_peephole2
|
| 1226 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 1227 |
|
|
(match_operand:SI 1 "register_operand" ""))
|
| 1228 |
|
|
(parallel
|
| 1229 |
|
|
[(set (match_dup 0)
|
| 1230 |
|
|
(plus:SI (match_dup 0)
|
| 1231 |
|
|
(match_operand:SI 2 "nonmemory_operand" "")))
|
| 1232 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 1233 |
|
|
"!TARGET_64BIT
|
| 1234 |
|
|
&& !reg_overlap_mentioned_p (operands[0], operands[2])
|
| 1235 |
|
|
&& preferred_la_operand_p (operands[1], operands[2])"
|
| 1236 |
|
|
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
|
| 1237 |
|
|
"")
|
| 1238 |
|
|
|
| 1239 |
|
|
(define_insn "*la_31_and"
|
| 1240 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 1241 |
|
|
(and:SI (match_operand:QI 1 "address_operand" "U,W")
|
| 1242 |
|
|
(const_int 2147483647)))]
|
| 1243 |
|
|
"!TARGET_64BIT"
|
| 1244 |
|
|
"@
|
| 1245 |
|
|
la\t%0,%a1
|
| 1246 |
|
|
lay\t%0,%a1"
|
| 1247 |
|
|
[(set_attr "op_type" "RX,RXY")
|
| 1248 |
|
|
(set_attr "type" "la")])
|
| 1249 |
|
|
|
| 1250 |
|
|
(define_insn_and_split "*la_31_and_cc"
|
| 1251 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 1252 |
|
|
(and:SI (match_operand:QI 1 "address_operand" "p")
|
| 1253 |
|
|
(const_int 2147483647)))
|
| 1254 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 1255 |
|
|
"!TARGET_64BIT"
|
| 1256 |
|
|
"#"
|
| 1257 |
|
|
"&& reload_completed"
|
| 1258 |
|
|
[(set (match_dup 0)
|
| 1259 |
|
|
(and:SI (match_dup 1) (const_int 2147483647)))]
|
| 1260 |
|
|
""
|
| 1261 |
|
|
[(set_attr "op_type" "RX")
|
| 1262 |
|
|
(set_attr "type" "la")])
|
| 1263 |
|
|
|
| 1264 |
|
|
(define_insn "force_la_31"
|
| 1265 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 1266 |
|
|
(match_operand:QI 1 "address_operand" "U,W"))
|
| 1267 |
|
|
(use (const_int 0))]
|
| 1268 |
|
|
"!TARGET_64BIT"
|
| 1269 |
|
|
"@
|
| 1270 |
|
|
la\t%0,%a1
|
| 1271 |
|
|
lay\t%0,%a1"
|
| 1272 |
|
|
[(set_attr "op_type" "RX")
|
| 1273 |
|
|
(set_attr "type" "la")])
|
| 1274 |
|
|
|
| 1275 |
|
|
(define_expand "reload_insi"
|
| 1276 |
|
|
[(parallel [(match_operand:SI 0 "register_operand" "=a")
|
| 1277 |
|
|
(match_operand:SI 1 "s390_plus_operand" "")
|
| 1278 |
|
|
(match_operand:SI 2 "register_operand" "=&a")])]
|
| 1279 |
|
|
"!TARGET_64BIT"
|
| 1280 |
|
|
{
|
| 1281 |
|
|
s390_expand_plus_operand (operands[0], operands[1], operands[2]);
|
| 1282 |
|
|
DONE;
|
| 1283 |
|
|
})
|
| 1284 |
|
|
|
| 1285 |
|
|
;
|
| 1286 |
|
|
; movhi instruction pattern(s).
|
| 1287 |
|
|
;
|
| 1288 |
|
|
|
| 1289 |
|
|
(define_expand "movhi"
|
| 1290 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "")
|
| 1291 |
|
|
(match_operand:HI 1 "general_operand" ""))]
|
| 1292 |
|
|
""
|
| 1293 |
|
|
{
|
| 1294 |
|
|
/* Make it explicit that loading a register from memory
|
| 1295 |
|
|
always sign-extends (at least) to SImode. */
|
| 1296 |
|
|
if (optimize && !no_new_pseudos
|
| 1297 |
|
|
&& register_operand (operands[0], VOIDmode)
|
| 1298 |
|
|
&& GET_CODE (operands[1]) == MEM)
|
| 1299 |
|
|
{
|
| 1300 |
|
|
rtx tmp = gen_reg_rtx (SImode);
|
| 1301 |
|
|
rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
|
| 1302 |
|
|
emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
|
| 1303 |
|
|
operands[1] = gen_lowpart (HImode, tmp);
|
| 1304 |
|
|
}
|
| 1305 |
|
|
})
|
| 1306 |
|
|
|
| 1307 |
|
|
(define_insn "*movhi"
|
| 1308 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
|
| 1309 |
|
|
(match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
|
| 1310 |
|
|
""
|
| 1311 |
|
|
"@
|
| 1312 |
|
|
lr\t%0,%1
|
| 1313 |
|
|
lhi\t%0,%h1
|
| 1314 |
|
|
lh\t%0,%1
|
| 1315 |
|
|
lhy\t%0,%1
|
| 1316 |
|
|
sth\t%1,%0
|
| 1317 |
|
|
sthy\t%1,%0
|
| 1318 |
|
|
#"
|
| 1319 |
|
|
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
|
| 1320 |
|
|
(set_attr "type" "lr,*,*,*,store,store,*")])
|
| 1321 |
|
|
|
| 1322 |
|
|
(define_peephole2
|
| 1323 |
|
|
[(set (match_operand:HI 0 "register_operand" "")
|
| 1324 |
|
|
(mem:HI (match_operand 1 "address_operand" "")))]
|
| 1325 |
|
|
"GET_CODE (operands[1]) == SYMBOL_REF
|
| 1326 |
|
|
&& CONSTANT_POOL_ADDRESS_P (operands[1])
|
| 1327 |
|
|
&& get_pool_mode (operands[1]) == HImode
|
| 1328 |
|
|
&& GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
|
| 1329 |
|
|
[(set (match_dup 0) (match_dup 2))]
|
| 1330 |
|
|
"operands[2] = get_pool_constant (operands[1]);")
|
| 1331 |
|
|
|
| 1332 |
|
|
;
|
| 1333 |
|
|
; movqi instruction pattern(s).
|
| 1334 |
|
|
;
|
| 1335 |
|
|
|
| 1336 |
|
|
(define_expand "movqi"
|
| 1337 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "")
|
| 1338 |
|
|
(match_operand:QI 1 "general_operand" ""))]
|
| 1339 |
|
|
""
|
| 1340 |
|
|
{
|
| 1341 |
|
|
/* On z/Architecture, zero-extending from memory to register
|
| 1342 |
|
|
is just as fast as a QImode load. */
|
| 1343 |
|
|
if (TARGET_ZARCH && optimize && !no_new_pseudos
|
| 1344 |
|
|
&& register_operand (operands[0], VOIDmode)
|
| 1345 |
|
|
&& GET_CODE (operands[1]) == MEM)
|
| 1346 |
|
|
{
|
| 1347 |
|
|
rtx tmp = gen_reg_rtx (word_mode);
|
| 1348 |
|
|
rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
|
| 1349 |
|
|
emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
|
| 1350 |
|
|
operands[1] = gen_lowpart (QImode, tmp);
|
| 1351 |
|
|
}
|
| 1352 |
|
|
})
|
| 1353 |
|
|
|
| 1354 |
|
|
(define_insn "*movqi"
|
| 1355 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
|
| 1356 |
|
|
(match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
|
| 1357 |
|
|
""
|
| 1358 |
|
|
"@
|
| 1359 |
|
|
lr\t%0,%1
|
| 1360 |
|
|
lhi\t%0,%b1
|
| 1361 |
|
|
ic\t%0,%1
|
| 1362 |
|
|
icy\t%0,%1
|
| 1363 |
|
|
stc\t%1,%0
|
| 1364 |
|
|
stcy\t%1,%0
|
| 1365 |
|
|
mvi\t%S0,%b1
|
| 1366 |
|
|
mviy\t%S0,%b1
|
| 1367 |
|
|
#"
|
| 1368 |
|
|
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
|
| 1369 |
|
|
(set_attr "type" "lr,*,*,*,store,store,store,store,*")])
|
| 1370 |
|
|
|
| 1371 |
|
|
(define_peephole2
|
| 1372 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "")
|
| 1373 |
|
|
(mem:QI (match_operand 1 "address_operand" "")))]
|
| 1374 |
|
|
"GET_CODE (operands[1]) == SYMBOL_REF
|
| 1375 |
|
|
&& CONSTANT_POOL_ADDRESS_P (operands[1])
|
| 1376 |
|
|
&& get_pool_mode (operands[1]) == QImode
|
| 1377 |
|
|
&& GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
|
| 1378 |
|
|
[(set (match_dup 0) (match_dup 2))]
|
| 1379 |
|
|
"operands[2] = get_pool_constant (operands[1]);")
|
| 1380 |
|
|
|
| 1381 |
|
|
;
|
| 1382 |
|
|
; movstrictqi instruction pattern(s).
|
| 1383 |
|
|
;
|
| 1384 |
|
|
|
| 1385 |
|
|
(define_insn "*movstrictqi"
|
| 1386 |
|
|
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
|
| 1387 |
|
|
(match_operand:QI 1 "memory_operand" "R,T"))]
|
| 1388 |
|
|
""
|
| 1389 |
|
|
"@
|
| 1390 |
|
|
ic\t%0,%1
|
| 1391 |
|
|
icy\t%0,%1"
|
| 1392 |
|
|
[(set_attr "op_type" "RX,RXY")])
|
| 1393 |
|
|
|
| 1394 |
|
|
;
|
| 1395 |
|
|
; movstricthi instruction pattern(s).
|
| 1396 |
|
|
;
|
| 1397 |
|
|
|
| 1398 |
|
|
(define_insn "*movstricthi"
|
| 1399 |
|
|
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
|
| 1400 |
|
|
(match_operand:HI 1 "memory_operand" "Q,S"))
|
| 1401 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 1402 |
|
|
""
|
| 1403 |
|
|
"@
|
| 1404 |
|
|
icm\t%0,3,%S1
|
| 1405 |
|
|
icmy\t%0,3,%S1"
|
| 1406 |
|
|
[(set_attr "op_type" "RS,RSY")])
|
| 1407 |
|
|
|
| 1408 |
|
|
;
|
| 1409 |
|
|
; movstrictsi instruction pattern(s).
|
| 1410 |
|
|
;
|
| 1411 |
|
|
|
| 1412 |
|
|
(define_insn "movstrictsi"
|
| 1413 |
|
|
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
|
| 1414 |
|
|
(match_operand:SI 1 "general_operand" "d,R,T,t"))]
|
| 1415 |
|
|
"TARGET_64BIT"
|
| 1416 |
|
|
"@
|
| 1417 |
|
|
lr\t%0,%1
|
| 1418 |
|
|
l\t%0,%1
|
| 1419 |
|
|
ly\t%0,%1
|
| 1420 |
|
|
ear\t%0,%1"
|
| 1421 |
|
|
[(set_attr "op_type" "RR,RX,RXY,RRE")
|
| 1422 |
|
|
(set_attr "type" "lr,load,load,*")])
|
| 1423 |
|
|
|
| 1424 |
|
|
;
|
| 1425 |
|
|
; movtf instruction pattern(s).
|
| 1426 |
|
|
;
|
| 1427 |
|
|
|
| 1428 |
|
|
(define_expand "movtf"
|
| 1429 |
|
|
[(set (match_operand:TF 0 "nonimmediate_operand" "")
|
| 1430 |
|
|
(match_operand:TF 1 "general_operand" ""))]
|
| 1431 |
|
|
""
|
| 1432 |
|
|
"")
|
| 1433 |
|
|
|
| 1434 |
|
|
(define_insn "*movtf_64"
|
| 1435 |
|
|
[(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,d,QS,d,o,Q")
|
| 1436 |
|
|
(match_operand:TF 1 "general_operand" "G,f,o,f,QS,d,dm,d,Q"))]
|
| 1437 |
|
|
"TARGET_64BIT"
|
| 1438 |
|
|
"@
|
| 1439 |
|
|
lzxr\t%0
|
| 1440 |
|
|
lxr\t%0,%1
|
| 1441 |
|
|
#
|
| 1442 |
|
|
#
|
| 1443 |
|
|
lmg\t%0,%N0,%S1
|
| 1444 |
|
|
stmg\t%1,%N1,%S0
|
| 1445 |
|
|
#
|
| 1446 |
|
|
#
|
| 1447 |
|
|
#"
|
| 1448 |
|
|
[(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
|
| 1449 |
|
|
(set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
|
| 1450 |
|
|
|
| 1451 |
|
|
(define_insn "*movtf_31"
|
| 1452 |
|
|
[(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
|
| 1453 |
|
|
(match_operand:TF 1 "general_operand" "G,f,o,f,Q"))]
|
| 1454 |
|
|
"!TARGET_64BIT"
|
| 1455 |
|
|
"@
|
| 1456 |
|
|
lzxr\t%0
|
| 1457 |
|
|
lxr\t%0,%1
|
| 1458 |
|
|
#
|
| 1459 |
|
|
#
|
| 1460 |
|
|
#"
|
| 1461 |
|
|
[(set_attr "op_type" "RRE,RRE,*,*,*")
|
| 1462 |
|
|
(set_attr "type" "fsimptf,fsimptf,*,*,*")])
|
| 1463 |
|
|
|
| 1464 |
|
|
; TFmode in GPRs splitters
|
| 1465 |
|
|
|
| 1466 |
|
|
(define_split
|
| 1467 |
|
|
[(set (match_operand:TF 0 "nonimmediate_operand" "")
|
| 1468 |
|
|
(match_operand:TF 1 "general_operand" ""))]
|
| 1469 |
|
|
"TARGET_64BIT && reload_completed
|
| 1470 |
|
|
&& s390_split_ok_p (operands[0], operands[1], TFmode, 0)"
|
| 1471 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 1472 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 1473 |
|
|
{
|
| 1474 |
|
|
operands[2] = operand_subword (operands[0], 0, 0, TFmode);
|
| 1475 |
|
|
operands[3] = operand_subword (operands[0], 1, 0, TFmode);
|
| 1476 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, TFmode);
|
| 1477 |
|
|
operands[5] = operand_subword (operands[1], 1, 0, TFmode);
|
| 1478 |
|
|
})
|
| 1479 |
|
|
|
| 1480 |
|
|
(define_split
|
| 1481 |
|
|
[(set (match_operand:TF 0 "nonimmediate_operand" "")
|
| 1482 |
|
|
(match_operand:TF 1 "general_operand" ""))]
|
| 1483 |
|
|
"TARGET_64BIT && reload_completed
|
| 1484 |
|
|
&& s390_split_ok_p (operands[0], operands[1], TFmode, 1)"
|
| 1485 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 1486 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 1487 |
|
|
{
|
| 1488 |
|
|
operands[2] = operand_subword (operands[0], 1, 0, TFmode);
|
| 1489 |
|
|
operands[3] = operand_subword (operands[0], 0, 0, TFmode);
|
| 1490 |
|
|
operands[4] = operand_subword (operands[1], 1, 0, TFmode);
|
| 1491 |
|
|
operands[5] = operand_subword (operands[1], 0, 0, TFmode);
|
| 1492 |
|
|
})
|
| 1493 |
|
|
|
| 1494 |
|
|
(define_split
|
| 1495 |
|
|
[(set (match_operand:TF 0 "register_operand" "")
|
| 1496 |
|
|
(match_operand:TF 1 "memory_operand" ""))]
|
| 1497 |
|
|
"TARGET_64BIT && reload_completed
|
| 1498 |
|
|
&& !FP_REG_P (operands[0])
|
| 1499 |
|
|
&& !s_operand (operands[1], VOIDmode)"
|
| 1500 |
|
|
[(set (match_dup 0) (match_dup 1))]
|
| 1501 |
|
|
{
|
| 1502 |
|
|
rtx addr = operand_subword (operands[0], 1, 0, TFmode);
|
| 1503 |
|
|
s390_load_address (addr, XEXP (operands[1], 0));
|
| 1504 |
|
|
operands[1] = replace_equiv_address (operands[1], addr);
|
| 1505 |
|
|
})
|
| 1506 |
|
|
|
| 1507 |
|
|
; TFmode in FPRs splitters
|
| 1508 |
|
|
|
| 1509 |
|
|
(define_split
|
| 1510 |
|
|
[(set (match_operand:TF 0 "register_operand" "")
|
| 1511 |
|
|
(match_operand:TF 1 "memory_operand" ""))]
|
| 1512 |
|
|
"reload_completed && offsettable_memref_p (operands[1])
|
| 1513 |
|
|
&& FP_REG_P (operands[0])"
|
| 1514 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 1515 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 1516 |
|
|
{
|
| 1517 |
|
|
operands[2] = simplify_gen_subreg (DFmode, operands[0], TFmode, 0);
|
| 1518 |
|
|
operands[3] = simplify_gen_subreg (DFmode, operands[0], TFmode, 8);
|
| 1519 |
|
|
operands[4] = adjust_address_nv (operands[1], DFmode, 0);
|
| 1520 |
|
|
operands[5] = adjust_address_nv (operands[1], DFmode, 8);
|
| 1521 |
|
|
})
|
| 1522 |
|
|
|
| 1523 |
|
|
(define_split
|
| 1524 |
|
|
[(set (match_operand:TF 0 "memory_operand" "")
|
| 1525 |
|
|
(match_operand:TF 1 "register_operand" ""))]
|
| 1526 |
|
|
"reload_completed && offsettable_memref_p (operands[0])
|
| 1527 |
|
|
&& FP_REG_P (operands[1])"
|
| 1528 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 1529 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 1530 |
|
|
{
|
| 1531 |
|
|
operands[2] = adjust_address_nv (operands[0], DFmode, 0);
|
| 1532 |
|
|
operands[3] = adjust_address_nv (operands[0], DFmode, 8);
|
| 1533 |
|
|
operands[4] = simplify_gen_subreg (DFmode, operands[1], TFmode, 0);
|
| 1534 |
|
|
operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, 8);
|
| 1535 |
|
|
})
|
| 1536 |
|
|
|
| 1537 |
|
|
(define_expand "reload_outtf"
|
| 1538 |
|
|
[(parallel [(match_operand:TF 0 "" "")
|
| 1539 |
|
|
(match_operand:TF 1 "register_operand" "f")
|
| 1540 |
|
|
(match_operand:SI 2 "register_operand" "=&a")])]
|
| 1541 |
|
|
""
|
| 1542 |
|
|
{
|
| 1543 |
|
|
rtx addr = gen_lowpart (Pmode, operands[2]);
|
| 1544 |
|
|
|
| 1545 |
|
|
gcc_assert (MEM_P (operands[0]));
|
| 1546 |
|
|
s390_load_address (addr, find_replacement (&XEXP (operands[0], 0)));
|
| 1547 |
|
|
operands[0] = replace_equiv_address (operands[0], addr);
|
| 1548 |
|
|
emit_move_insn (operands[0], operands[1]);
|
| 1549 |
|
|
DONE;
|
| 1550 |
|
|
})
|
| 1551 |
|
|
|
| 1552 |
|
|
(define_expand "reload_intf"
|
| 1553 |
|
|
[(parallel [(match_operand:TF 0 "register_operand" "=f")
|
| 1554 |
|
|
(match_operand:TF 1 "" "")
|
| 1555 |
|
|
(match_operand:SI 2 "register_operand" "=&a")])]
|
| 1556 |
|
|
""
|
| 1557 |
|
|
{
|
| 1558 |
|
|
rtx addr = gen_lowpart (Pmode, operands[2]);
|
| 1559 |
|
|
|
| 1560 |
|
|
gcc_assert (MEM_P (operands[1]));
|
| 1561 |
|
|
s390_load_address (addr, find_replacement (&XEXP (operands[1], 0)));
|
| 1562 |
|
|
operands[1] = replace_equiv_address (operands[1], addr);
|
| 1563 |
|
|
emit_move_insn (operands[0], operands[1]);
|
| 1564 |
|
|
DONE;
|
| 1565 |
|
|
})
|
| 1566 |
|
|
|
| 1567 |
|
|
;
|
| 1568 |
|
|
; movdf instruction pattern(s).
|
| 1569 |
|
|
;
|
| 1570 |
|
|
|
| 1571 |
|
|
(define_expand "movdf"
|
| 1572 |
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "")
|
| 1573 |
|
|
(match_operand:DF 1 "general_operand" ""))]
|
| 1574 |
|
|
""
|
| 1575 |
|
|
"")
|
| 1576 |
|
|
|
| 1577 |
|
|
(define_insn "*movdf_64"
|
| 1578 |
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
|
| 1579 |
|
|
(match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
|
| 1580 |
|
|
"TARGET_64BIT"
|
| 1581 |
|
|
"@
|
| 1582 |
|
|
lzdr\t%0
|
| 1583 |
|
|
ldr\t%0,%1
|
| 1584 |
|
|
ld\t%0,%1
|
| 1585 |
|
|
ldy\t%0,%1
|
| 1586 |
|
|
std\t%1,%0
|
| 1587 |
|
|
stdy\t%1,%0
|
| 1588 |
|
|
lgr\t%0,%1
|
| 1589 |
|
|
lg\t%0,%1
|
| 1590 |
|
|
stg\t%1,%0
|
| 1591 |
|
|
#"
|
| 1592 |
|
|
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
|
| 1593 |
|
|
(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
|
| 1594 |
|
|
|
| 1595 |
|
|
(define_insn "*movdf_31"
|
| 1596 |
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
|
| 1597 |
|
|
(match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
|
| 1598 |
|
|
"!TARGET_64BIT"
|
| 1599 |
|
|
"@
|
| 1600 |
|
|
lzdr\t%0
|
| 1601 |
|
|
ldr\t%0,%1
|
| 1602 |
|
|
ld\t%0,%1
|
| 1603 |
|
|
ldy\t%0,%1
|
| 1604 |
|
|
std\t%1,%0
|
| 1605 |
|
|
stdy\t%1,%0
|
| 1606 |
|
|
lm\t%0,%N0,%S1
|
| 1607 |
|
|
lmy\t%0,%N0,%S1
|
| 1608 |
|
|
stm\t%1,%N1,%S0
|
| 1609 |
|
|
stmy\t%1,%N1,%S0
|
| 1610 |
|
|
#
|
| 1611 |
|
|
#
|
| 1612 |
|
|
#"
|
| 1613 |
|
|
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
|
| 1614 |
|
|
(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
|
| 1615 |
|
|
lm,lm,stm,stm,*,*,*")])
|
| 1616 |
|
|
|
| 1617 |
|
|
(define_split
|
| 1618 |
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "")
|
| 1619 |
|
|
(match_operand:DF 1 "general_operand" ""))]
|
| 1620 |
|
|
"!TARGET_64BIT && reload_completed
|
| 1621 |
|
|
&& s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
|
| 1622 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 1623 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 1624 |
|
|
{
|
| 1625 |
|
|
operands[2] = operand_subword (operands[0], 0, 0, DFmode);
|
| 1626 |
|
|
operands[3] = operand_subword (operands[0], 1, 0, DFmode);
|
| 1627 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, DFmode);
|
| 1628 |
|
|
operands[5] = operand_subword (operands[1], 1, 0, DFmode);
|
| 1629 |
|
|
})
|
| 1630 |
|
|
|
| 1631 |
|
|
(define_split
|
| 1632 |
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "")
|
| 1633 |
|
|
(match_operand:DF 1 "general_operand" ""))]
|
| 1634 |
|
|
"!TARGET_64BIT && reload_completed
|
| 1635 |
|
|
&& s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
|
| 1636 |
|
|
[(set (match_dup 2) (match_dup 4))
|
| 1637 |
|
|
(set (match_dup 3) (match_dup 5))]
|
| 1638 |
|
|
{
|
| 1639 |
|
|
operands[2] = operand_subword (operands[0], 1, 0, DFmode);
|
| 1640 |
|
|
operands[3] = operand_subword (operands[0], 0, 0, DFmode);
|
| 1641 |
|
|
operands[4] = operand_subword (operands[1], 1, 0, DFmode);
|
| 1642 |
|
|
operands[5] = operand_subword (operands[1], 0, 0, DFmode);
|
| 1643 |
|
|
})
|
| 1644 |
|
|
|
| 1645 |
|
|
(define_split
|
| 1646 |
|
|
[(set (match_operand:DF 0 "register_operand" "")
|
| 1647 |
|
|
(match_operand:DF 1 "memory_operand" ""))]
|
| 1648 |
|
|
"!TARGET_64BIT && reload_completed
|
| 1649 |
|
|
&& !FP_REG_P (operands[0])
|
| 1650 |
|
|
&& !s_operand (operands[1], VOIDmode)"
|
| 1651 |
|
|
[(set (match_dup 0) (match_dup 1))]
|
| 1652 |
|
|
{
|
| 1653 |
|
|
rtx addr = operand_subword (operands[0], 1, 0, DFmode);
|
| 1654 |
|
|
s390_load_address (addr, XEXP (operands[1], 0));
|
| 1655 |
|
|
operands[1] = replace_equiv_address (operands[1], addr);
|
| 1656 |
|
|
})
|
| 1657 |
|
|
|
| 1658 |
|
|
(define_expand "reload_outdf"
|
| 1659 |
|
|
[(parallel [(match_operand:DF 0 "" "")
|
| 1660 |
|
|
(match_operand:DF 1 "register_operand" "d")
|
| 1661 |
|
|
(match_operand:SI 2 "register_operand" "=&a")])]
|
| 1662 |
|
|
"!TARGET_64BIT"
|
| 1663 |
|
|
{
|
| 1664 |
|
|
gcc_assert (MEM_P (operands[0]));
|
| 1665 |
|
|
s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
|
| 1666 |
|
|
operands[0] = replace_equiv_address (operands[0], operands[2]);
|
| 1667 |
|
|
emit_move_insn (operands[0], operands[1]);
|
| 1668 |
|
|
DONE;
|
| 1669 |
|
|
})
|
| 1670 |
|
|
|
| 1671 |
|
|
;
|
| 1672 |
|
|
; movsf instruction pattern(s).
|
| 1673 |
|
|
;
|
| 1674 |
|
|
|
| 1675 |
|
|
(define_insn "movsf"
|
| 1676 |
|
|
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
|
| 1677 |
|
|
(match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
|
| 1678 |
|
|
""
|
| 1679 |
|
|
"@
|
| 1680 |
|
|
lzer\t%0
|
| 1681 |
|
|
ler\t%0,%1
|
| 1682 |
|
|
le\t%0,%1
|
| 1683 |
|
|
ley\t%0,%1
|
| 1684 |
|
|
ste\t%1,%0
|
| 1685 |
|
|
stey\t%1,%0
|
| 1686 |
|
|
lr\t%0,%1
|
| 1687 |
|
|
l\t%0,%1
|
| 1688 |
|
|
ly\t%0,%1
|
| 1689 |
|
|
st\t%1,%0
|
| 1690 |
|
|
sty\t%1,%0
|
| 1691 |
|
|
#"
|
| 1692 |
|
|
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
|
| 1693 |
|
|
(set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
|
| 1694 |
|
|
lr,load,load,store,store,*")])
|
| 1695 |
|
|
|
| 1696 |
|
|
;
|
| 1697 |
|
|
; movcc instruction pattern
|
| 1698 |
|
|
;
|
| 1699 |
|
|
|
| 1700 |
|
|
(define_insn "movcc"
|
| 1701 |
|
|
[(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
|
| 1702 |
|
|
(match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
|
| 1703 |
|
|
""
|
| 1704 |
|
|
"@
|
| 1705 |
|
|
lr\t%0,%1
|
| 1706 |
|
|
tmh\t%1,12288
|
| 1707 |
|
|
ipm\t%0
|
| 1708 |
|
|
st\t%0,%1
|
| 1709 |
|
|
sty\t%0,%1
|
| 1710 |
|
|
l\t%1,%0
|
| 1711 |
|
|
ly\t%1,%0"
|
| 1712 |
|
|
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
|
| 1713 |
|
|
(set_attr "type" "lr,*,*,store,store,load,load")])
|
| 1714 |
|
|
|
| 1715 |
|
|
;
|
| 1716 |
|
|
; Block move (MVC) patterns.
|
| 1717 |
|
|
;
|
| 1718 |
|
|
|
| 1719 |
|
|
(define_insn "*mvc"
|
| 1720 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "=Q")
|
| 1721 |
|
|
(match_operand:BLK 1 "memory_operand" "Q"))
|
| 1722 |
|
|
(use (match_operand 2 "const_int_operand" "n"))]
|
| 1723 |
|
|
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
|
| 1724 |
|
|
"mvc\t%O0(%2,%R0),%S1"
|
| 1725 |
|
|
[(set_attr "op_type" "SS")])
|
| 1726 |
|
|
|
| 1727 |
|
|
(define_split
|
| 1728 |
|
|
[(set (match_operand 0 "memory_operand" "")
|
| 1729 |
|
|
(match_operand 1 "memory_operand" ""))]
|
| 1730 |
|
|
"reload_completed
|
| 1731 |
|
|
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
|
| 1732 |
|
|
&& GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
|
| 1733 |
|
|
[(parallel
|
| 1734 |
|
|
[(set (match_dup 0) (match_dup 1))
|
| 1735 |
|
|
(use (match_dup 2))])]
|
| 1736 |
|
|
{
|
| 1737 |
|
|
operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
|
| 1738 |
|
|
operands[0] = adjust_address (operands[0], BLKmode, 0);
|
| 1739 |
|
|
operands[1] = adjust_address (operands[1], BLKmode, 0);
|
| 1740 |
|
|
})
|
| 1741 |
|
|
|
| 1742 |
|
|
(define_peephole2
|
| 1743 |
|
|
[(parallel
|
| 1744 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 1745 |
|
|
(match_operand:BLK 1 "memory_operand" ""))
|
| 1746 |
|
|
(use (match_operand 2 "const_int_operand" ""))])
|
| 1747 |
|
|
(parallel
|
| 1748 |
|
|
[(set (match_operand:BLK 3 "memory_operand" "")
|
| 1749 |
|
|
(match_operand:BLK 4 "memory_operand" ""))
|
| 1750 |
|
|
(use (match_operand 5 "const_int_operand" ""))])]
|
| 1751 |
|
|
"s390_offset_p (operands[0], operands[3], operands[2])
|
| 1752 |
|
|
&& s390_offset_p (operands[1], operands[4], operands[2])
|
| 1753 |
|
|
&& !s390_overlap_p (operands[0], operands[1],
|
| 1754 |
|
|
INTVAL (operands[2]) + INTVAL (operands[5]))
|
| 1755 |
|
|
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
|
| 1756 |
|
|
[(parallel
|
| 1757 |
|
|
[(set (match_dup 6) (match_dup 7))
|
| 1758 |
|
|
(use (match_dup 8))])]
|
| 1759 |
|
|
"operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
|
| 1760 |
|
|
operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
|
| 1761 |
|
|
operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
|
| 1762 |
|
|
|
| 1763 |
|
|
|
| 1764 |
|
|
;
|
| 1765 |
|
|
; load_multiple pattern(s).
|
| 1766 |
|
|
;
|
| 1767 |
|
|
; ??? Due to reload problems with replacing registers inside match_parallel
|
| 1768 |
|
|
; we currently support load_multiple/store_multiple only after reload.
|
| 1769 |
|
|
;
|
| 1770 |
|
|
|
| 1771 |
|
|
(define_expand "load_multiple"
|
| 1772 |
|
|
[(match_par_dup 3 [(set (match_operand 0 "" "")
|
| 1773 |
|
|
(match_operand 1 "" ""))
|
| 1774 |
|
|
(use (match_operand 2 "" ""))])]
|
| 1775 |
|
|
"reload_completed"
|
| 1776 |
|
|
{
|
| 1777 |
|
|
enum machine_mode mode;
|
| 1778 |
|
|
int regno;
|
| 1779 |
|
|
int count;
|
| 1780 |
|
|
rtx from;
|
| 1781 |
|
|
int i, off;
|
| 1782 |
|
|
|
| 1783 |
|
|
/* Support only loading a constant number of fixed-point registers from
|
| 1784 |
|
|
memory and only bother with this if more than two */
|
| 1785 |
|
|
if (GET_CODE (operands[2]) != CONST_INT
|
| 1786 |
|
|
|| INTVAL (operands[2]) < 2
|
| 1787 |
|
|
|| INTVAL (operands[2]) > 16
|
| 1788 |
|
|
|| GET_CODE (operands[1]) != MEM
|
| 1789 |
|
|
|| GET_CODE (operands[0]) != REG
|
| 1790 |
|
|
|| REGNO (operands[0]) >= 16)
|
| 1791 |
|
|
FAIL;
|
| 1792 |
|
|
|
| 1793 |
|
|
count = INTVAL (operands[2]);
|
| 1794 |
|
|
regno = REGNO (operands[0]);
|
| 1795 |
|
|
mode = GET_MODE (operands[0]);
|
| 1796 |
|
|
if (mode != SImode && mode != word_mode)
|
| 1797 |
|
|
FAIL;
|
| 1798 |
|
|
|
| 1799 |
|
|
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
|
| 1800 |
|
|
if (no_new_pseudos)
|
| 1801 |
|
|
{
|
| 1802 |
|
|
if (GET_CODE (XEXP (operands[1], 0)) == REG)
|
| 1803 |
|
|
{
|
| 1804 |
|
|
from = XEXP (operands[1], 0);
|
| 1805 |
|
|
off = 0;
|
| 1806 |
|
|
}
|
| 1807 |
|
|
else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
|
| 1808 |
|
|
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
|
| 1809 |
|
|
&& GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
|
| 1810 |
|
|
{
|
| 1811 |
|
|
from = XEXP (XEXP (operands[1], 0), 0);
|
| 1812 |
|
|
off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
|
| 1813 |
|
|
}
|
| 1814 |
|
|
else
|
| 1815 |
|
|
FAIL;
|
| 1816 |
|
|
}
|
| 1817 |
|
|
else
|
| 1818 |
|
|
{
|
| 1819 |
|
|
from = force_reg (Pmode, XEXP (operands[1], 0));
|
| 1820 |
|
|
off = 0;
|
| 1821 |
|
|
}
|
| 1822 |
|
|
|
| 1823 |
|
|
for (i = 0; i < count; i++)
|
| 1824 |
|
|
XVECEXP (operands[3], 0, i)
|
| 1825 |
|
|
= gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
|
| 1826 |
|
|
change_address (operands[1], mode,
|
| 1827 |
|
|
plus_constant (from, off + i * GET_MODE_SIZE (mode))));
|
| 1828 |
|
|
})
|
| 1829 |
|
|
|
| 1830 |
|
|
(define_insn "*load_multiple_di"
|
| 1831 |
|
|
[(match_parallel 0 "load_multiple_operation"
|
| 1832 |
|
|
[(set (match_operand:DI 1 "register_operand" "=r")
|
| 1833 |
|
|
(match_operand:DI 2 "s_operand" "QS"))])]
|
| 1834 |
|
|
"reload_completed && word_mode == DImode"
|
| 1835 |
|
|
{
|
| 1836 |
|
|
int words = XVECLEN (operands[0], 0);
|
| 1837 |
|
|
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
|
| 1838 |
|
|
return "lmg\t%1,%0,%S2";
|
| 1839 |
|
|
}
|
| 1840 |
|
|
[(set_attr "op_type" "RSY")
|
| 1841 |
|
|
(set_attr "type" "lm")])
|
| 1842 |
|
|
|
| 1843 |
|
|
(define_insn "*load_multiple_si"
|
| 1844 |
|
|
[(match_parallel 0 "load_multiple_operation"
|
| 1845 |
|
|
[(set (match_operand:SI 1 "register_operand" "=r,r")
|
| 1846 |
|
|
(match_operand:SI 2 "s_operand" "Q,S"))])]
|
| 1847 |
|
|
"reload_completed"
|
| 1848 |
|
|
{
|
| 1849 |
|
|
int words = XVECLEN (operands[0], 0);
|
| 1850 |
|
|
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
|
| 1851 |
|
|
return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
|
| 1852 |
|
|
}
|
| 1853 |
|
|
[(set_attr "op_type" "RS,RSY")
|
| 1854 |
|
|
(set_attr "type" "lm")])
|
| 1855 |
|
|
|
| 1856 |
|
|
;
|
| 1857 |
|
|
; store multiple pattern(s).
|
| 1858 |
|
|
;
|
| 1859 |
|
|
|
| 1860 |
|
|
(define_expand "store_multiple"
|
| 1861 |
|
|
[(match_par_dup 3 [(set (match_operand 0 "" "")
|
| 1862 |
|
|
(match_operand 1 "" ""))
|
| 1863 |
|
|
(use (match_operand 2 "" ""))])]
|
| 1864 |
|
|
"reload_completed"
|
| 1865 |
|
|
{
|
| 1866 |
|
|
enum machine_mode mode;
|
| 1867 |
|
|
int regno;
|
| 1868 |
|
|
int count;
|
| 1869 |
|
|
rtx to;
|
| 1870 |
|
|
int i, off;
|
| 1871 |
|
|
|
| 1872 |
|
|
/* Support only storing a constant number of fixed-point registers to
|
| 1873 |
|
|
memory and only bother with this if more than two. */
|
| 1874 |
|
|
if (GET_CODE (operands[2]) != CONST_INT
|
| 1875 |
|
|
|| INTVAL (operands[2]) < 2
|
| 1876 |
|
|
|| INTVAL (operands[2]) > 16
|
| 1877 |
|
|
|| GET_CODE (operands[0]) != MEM
|
| 1878 |
|
|
|| GET_CODE (operands[1]) != REG
|
| 1879 |
|
|
|| REGNO (operands[1]) >= 16)
|
| 1880 |
|
|
FAIL;
|
| 1881 |
|
|
|
| 1882 |
|
|
count = INTVAL (operands[2]);
|
| 1883 |
|
|
regno = REGNO (operands[1]);
|
| 1884 |
|
|
mode = GET_MODE (operands[1]);
|
| 1885 |
|
|
if (mode != SImode && mode != word_mode)
|
| 1886 |
|
|
FAIL;
|
| 1887 |
|
|
|
| 1888 |
|
|
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
|
| 1889 |
|
|
|
| 1890 |
|
|
if (no_new_pseudos)
|
| 1891 |
|
|
{
|
| 1892 |
|
|
if (GET_CODE (XEXP (operands[0], 0)) == REG)
|
| 1893 |
|
|
{
|
| 1894 |
|
|
to = XEXP (operands[0], 0);
|
| 1895 |
|
|
off = 0;
|
| 1896 |
|
|
}
|
| 1897 |
|
|
else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
|
| 1898 |
|
|
&& GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
|
| 1899 |
|
|
&& GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
|
| 1900 |
|
|
{
|
| 1901 |
|
|
to = XEXP (XEXP (operands[0], 0), 0);
|
| 1902 |
|
|
off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
|
| 1903 |
|
|
}
|
| 1904 |
|
|
else
|
| 1905 |
|
|
FAIL;
|
| 1906 |
|
|
}
|
| 1907 |
|
|
else
|
| 1908 |
|
|
{
|
| 1909 |
|
|
to = force_reg (Pmode, XEXP (operands[0], 0));
|
| 1910 |
|
|
off = 0;
|
| 1911 |
|
|
}
|
| 1912 |
|
|
|
| 1913 |
|
|
for (i = 0; i < count; i++)
|
| 1914 |
|
|
XVECEXP (operands[3], 0, i)
|
| 1915 |
|
|
= gen_rtx_SET (VOIDmode,
|
| 1916 |
|
|
change_address (operands[0], mode,
|
| 1917 |
|
|
plus_constant (to, off + i * GET_MODE_SIZE (mode))),
|
| 1918 |
|
|
gen_rtx_REG (mode, regno + i));
|
| 1919 |
|
|
})
|
| 1920 |
|
|
|
| 1921 |
|
|
(define_insn "*store_multiple_di"
|
| 1922 |
|
|
[(match_parallel 0 "store_multiple_operation"
|
| 1923 |
|
|
[(set (match_operand:DI 1 "s_operand" "=QS")
|
| 1924 |
|
|
(match_operand:DI 2 "register_operand" "r"))])]
|
| 1925 |
|
|
"reload_completed && word_mode == DImode"
|
| 1926 |
|
|
{
|
| 1927 |
|
|
int words = XVECLEN (operands[0], 0);
|
| 1928 |
|
|
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
|
| 1929 |
|
|
return "stmg\t%2,%0,%S1";
|
| 1930 |
|
|
}
|
| 1931 |
|
|
[(set_attr "op_type" "RSY")
|
| 1932 |
|
|
(set_attr "type" "stm")])
|
| 1933 |
|
|
|
| 1934 |
|
|
|
| 1935 |
|
|
(define_insn "*store_multiple_si"
|
| 1936 |
|
|
[(match_parallel 0 "store_multiple_operation"
|
| 1937 |
|
|
[(set (match_operand:SI 1 "s_operand" "=Q,S")
|
| 1938 |
|
|
(match_operand:SI 2 "register_operand" "r,r"))])]
|
| 1939 |
|
|
"reload_completed"
|
| 1940 |
|
|
{
|
| 1941 |
|
|
int words = XVECLEN (operands[0], 0);
|
| 1942 |
|
|
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
|
| 1943 |
|
|
return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
|
| 1944 |
|
|
}
|
| 1945 |
|
|
[(set_attr "op_type" "RS,RSY")
|
| 1946 |
|
|
(set_attr "type" "stm")])
|
| 1947 |
|
|
|
| 1948 |
|
|
;;
|
| 1949 |
|
|
;; String instructions.
|
| 1950 |
|
|
;;
|
| 1951 |
|
|
|
| 1952 |
|
|
(define_insn "*execute"
|
| 1953 |
|
|
[(match_parallel 0 ""
|
| 1954 |
|
|
[(unspec [(match_operand 1 "register_operand" "a")
|
| 1955 |
|
|
(match_operand:BLK 2 "memory_operand" "R")
|
| 1956 |
|
|
(match_operand 3 "" "")] UNSPEC_EXECUTE)])]
|
| 1957 |
|
|
"GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
|
| 1958 |
|
|
&& GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
|
| 1959 |
|
|
"ex\t%1,%2"
|
| 1960 |
|
|
[(set_attr "op_type" "RX")
|
| 1961 |
|
|
(set_attr "type" "cs")])
|
| 1962 |
|
|
|
| 1963 |
|
|
|
| 1964 |
|
|
;
|
| 1965 |
|
|
; strlenM instruction pattern(s).
|
| 1966 |
|
|
;
|
| 1967 |
|
|
|
| 1968 |
|
|
(define_expand "strlen"
|
| 1969 |
|
|
[(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
|
| 1970 |
|
|
(parallel
|
| 1971 |
|
|
[(set (match_dup 4)
|
| 1972 |
|
|
(unspec:P [(const_int 0)
|
| 1973 |
|
|
(match_operand:BLK 1 "memory_operand" "")
|
| 1974 |
|
|
(reg:SI 0)
|
| 1975 |
|
|
(match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
|
| 1976 |
|
|
(clobber (scratch:P))
|
| 1977 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 1978 |
|
|
(parallel
|
| 1979 |
|
|
[(set (match_operand:P 0 "register_operand" "")
|
| 1980 |
|
|
(minus:P (match_dup 4) (match_dup 5)))
|
| 1981 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 1982 |
|
|
""
|
| 1983 |
|
|
{
|
| 1984 |
|
|
operands[4] = gen_reg_rtx (Pmode);
|
| 1985 |
|
|
operands[5] = gen_reg_rtx (Pmode);
|
| 1986 |
|
|
emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
|
| 1987 |
|
|
operands[1] = replace_equiv_address (operands[1], operands[5]);
|
| 1988 |
|
|
})
|
| 1989 |
|
|
|
| 1990 |
|
|
(define_insn "*strlen"
|
| 1991 |
|
|
[(set (match_operand:P 0 "register_operand" "=a")
|
| 1992 |
|
|
(unspec:P [(match_operand:P 2 "general_operand" "0")
|
| 1993 |
|
|
(mem:BLK (match_operand:P 3 "register_operand" "1"))
|
| 1994 |
|
|
(reg:SI 0)
|
| 1995 |
|
|
(match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
|
| 1996 |
|
|
(clobber (match_scratch:P 1 "=a"))
|
| 1997 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 1998 |
|
|
""
|
| 1999 |
|
|
"srst\t%0,%1\;jo\t.-4"
|
| 2000 |
|
|
[(set_attr "length" "8")
|
| 2001 |
|
|
(set_attr "type" "vs")])
|
| 2002 |
|
|
|
| 2003 |
|
|
;
|
| 2004 |
|
|
; cmpstrM instruction pattern(s).
|
| 2005 |
|
|
;
|
| 2006 |
|
|
|
| 2007 |
|
|
(define_expand "cmpstrsi"
|
| 2008 |
|
|
[(set (reg:SI 0) (const_int 0))
|
| 2009 |
|
|
(parallel
|
| 2010 |
|
|
[(clobber (match_operand 3 "" ""))
|
| 2011 |
|
|
(clobber (match_dup 4))
|
| 2012 |
|
|
(set (reg:CCU CC_REGNUM)
|
| 2013 |
|
|
(compare:CCU (match_operand:BLK 1 "memory_operand" "")
|
| 2014 |
|
|
(match_operand:BLK 2 "memory_operand" "")))
|
| 2015 |
|
|
(use (reg:SI 0))])
|
| 2016 |
|
|
(parallel
|
| 2017 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 2018 |
|
|
(unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
|
| 2019 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2020 |
|
|
""
|
| 2021 |
|
|
{
|
| 2022 |
|
|
/* As the result of CMPINT is inverted compared to what we need,
|
| 2023 |
|
|
we have to swap the operands. */
|
| 2024 |
|
|
rtx op1 = operands[2];
|
| 2025 |
|
|
rtx op2 = operands[1];
|
| 2026 |
|
|
rtx addr1 = gen_reg_rtx (Pmode);
|
| 2027 |
|
|
rtx addr2 = gen_reg_rtx (Pmode);
|
| 2028 |
|
|
|
| 2029 |
|
|
emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
|
| 2030 |
|
|
emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
|
| 2031 |
|
|
operands[1] = replace_equiv_address_nv (op1, addr1);
|
| 2032 |
|
|
operands[2] = replace_equiv_address_nv (op2, addr2);
|
| 2033 |
|
|
operands[3] = addr1;
|
| 2034 |
|
|
operands[4] = addr2;
|
| 2035 |
|
|
})
|
| 2036 |
|
|
|
| 2037 |
|
|
(define_insn "*cmpstr"
|
| 2038 |
|
|
[(clobber (match_operand:P 0 "register_operand" "=d"))
|
| 2039 |
|
|
(clobber (match_operand:P 1 "register_operand" "=d"))
|
| 2040 |
|
|
(set (reg:CCU CC_REGNUM)
|
| 2041 |
|
|
(compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
|
| 2042 |
|
|
(mem:BLK (match_operand:P 3 "register_operand" "1"))))
|
| 2043 |
|
|
(use (reg:SI 0))]
|
| 2044 |
|
|
""
|
| 2045 |
|
|
"clst\t%0,%1\;jo\t.-4"
|
| 2046 |
|
|
[(set_attr "length" "8")
|
| 2047 |
|
|
(set_attr "type" "vs")])
|
| 2048 |
|
|
|
| 2049 |
|
|
;
|
| 2050 |
|
|
; movstr instruction pattern.
|
| 2051 |
|
|
;
|
| 2052 |
|
|
|
| 2053 |
|
|
(define_expand "movstr"
|
| 2054 |
|
|
[(set (reg:SI 0) (const_int 0))
|
| 2055 |
|
|
(parallel
|
| 2056 |
|
|
[(clobber (match_dup 3))
|
| 2057 |
|
|
(set (match_operand:BLK 1 "memory_operand" "")
|
| 2058 |
|
|
(match_operand:BLK 2 "memory_operand" ""))
|
| 2059 |
|
|
(set (match_operand 0 "register_operand" "")
|
| 2060 |
|
|
(unspec [(match_dup 1)
|
| 2061 |
|
|
(match_dup 2)
|
| 2062 |
|
|
(reg:SI 0)] UNSPEC_MVST))
|
| 2063 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2064 |
|
|
""
|
| 2065 |
|
|
{
|
| 2066 |
|
|
rtx addr1 = gen_reg_rtx (Pmode);
|
| 2067 |
|
|
rtx addr2 = gen_reg_rtx (Pmode);
|
| 2068 |
|
|
|
| 2069 |
|
|
emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
|
| 2070 |
|
|
emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
|
| 2071 |
|
|
operands[1] = replace_equiv_address_nv (operands[1], addr1);
|
| 2072 |
|
|
operands[2] = replace_equiv_address_nv (operands[2], addr2);
|
| 2073 |
|
|
operands[3] = addr2;
|
| 2074 |
|
|
})
|
| 2075 |
|
|
|
| 2076 |
|
|
(define_insn "*movstr"
|
| 2077 |
|
|
[(clobber (match_operand:P 2 "register_operand" "=d"))
|
| 2078 |
|
|
(set (mem:BLK (match_operand:P 1 "register_operand" "0"))
|
| 2079 |
|
|
(mem:BLK (match_operand:P 3 "register_operand" "2")))
|
| 2080 |
|
|
(set (match_operand:P 0 "register_operand" "=d")
|
| 2081 |
|
|
(unspec [(mem:BLK (match_dup 1))
|
| 2082 |
|
|
(mem:BLK (match_dup 3))
|
| 2083 |
|
|
(reg:SI 0)] UNSPEC_MVST))
|
| 2084 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2085 |
|
|
""
|
| 2086 |
|
|
"mvst\t%1,%2\;jo\t.-4"
|
| 2087 |
|
|
[(set_attr "length" "8")
|
| 2088 |
|
|
(set_attr "type" "vs")])
|
| 2089 |
|
|
|
| 2090 |
|
|
|
| 2091 |
|
|
;
|
| 2092 |
|
|
; movmemM instruction pattern(s).
|
| 2093 |
|
|
;
|
| 2094 |
|
|
|
| 2095 |
|
|
(define_expand "movmem"
|
| 2096 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2097 |
|
|
(match_operand:BLK 1 "memory_operand" ""))
|
| 2098 |
|
|
(use (match_operand:GPR 2 "general_operand" ""))
|
| 2099 |
|
|
(match_operand 3 "" "")]
|
| 2100 |
|
|
""
|
| 2101 |
|
|
"s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
|
| 2102 |
|
|
|
| 2103 |
|
|
; Move a block that is up to 256 bytes in length.
|
| 2104 |
|
|
; The block length is taken as (operands[2] % 256) + 1.
|
| 2105 |
|
|
|
| 2106 |
|
|
(define_expand "movmem_short"
|
| 2107 |
|
|
[(parallel
|
| 2108 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2109 |
|
|
(match_operand:BLK 1 "memory_operand" ""))
|
| 2110 |
|
|
(use (match_operand 2 "nonmemory_operand" ""))
|
| 2111 |
|
|
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
|
| 2112 |
|
|
(clobber (match_dup 3))])]
|
| 2113 |
|
|
""
|
| 2114 |
|
|
"operands[3] = gen_rtx_SCRATCH (Pmode);")
|
| 2115 |
|
|
|
| 2116 |
|
|
(define_insn "*movmem_short"
|
| 2117 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
|
| 2118 |
|
|
(match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
|
| 2119 |
|
|
(use (match_operand 2 "nonmemory_operand" "n,a,a"))
|
| 2120 |
|
|
(use (match_operand 3 "immediate_operand" "X,R,X"))
|
| 2121 |
|
|
(clobber (match_scratch 4 "=X,X,&a"))]
|
| 2122 |
|
|
"(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
|
| 2123 |
|
|
&& GET_MODE (operands[4]) == Pmode"
|
| 2124 |
|
|
"#"
|
| 2125 |
|
|
[(set_attr "type" "cs")])
|
| 2126 |
|
|
|
| 2127 |
|
|
(define_split
|
| 2128 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2129 |
|
|
(match_operand:BLK 1 "memory_operand" ""))
|
| 2130 |
|
|
(use (match_operand 2 "const_int_operand" ""))
|
| 2131 |
|
|
(use (match_operand 3 "immediate_operand" ""))
|
| 2132 |
|
|
(clobber (scratch))]
|
| 2133 |
|
|
"reload_completed"
|
| 2134 |
|
|
[(parallel
|
| 2135 |
|
|
[(set (match_dup 0) (match_dup 1))
|
| 2136 |
|
|
(use (match_dup 2))])]
|
| 2137 |
|
|
"operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
|
| 2138 |
|
|
|
| 2139 |
|
|
(define_split
|
| 2140 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2141 |
|
|
(match_operand:BLK 1 "memory_operand" ""))
|
| 2142 |
|
|
(use (match_operand 2 "register_operand" ""))
|
| 2143 |
|
|
(use (match_operand 3 "memory_operand" ""))
|
| 2144 |
|
|
(clobber (scratch))]
|
| 2145 |
|
|
"reload_completed"
|
| 2146 |
|
|
[(parallel
|
| 2147 |
|
|
[(unspec [(match_dup 2) (match_dup 3)
|
| 2148 |
|
|
(const_int 0)] UNSPEC_EXECUTE)
|
| 2149 |
|
|
(set (match_dup 0) (match_dup 1))
|
| 2150 |
|
|
(use (const_int 1))])]
|
| 2151 |
|
|
"")
|
| 2152 |
|
|
|
| 2153 |
|
|
(define_split
|
| 2154 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2155 |
|
|
(match_operand:BLK 1 "memory_operand" ""))
|
| 2156 |
|
|
(use (match_operand 2 "register_operand" ""))
|
| 2157 |
|
|
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
|
| 2158 |
|
|
(clobber (match_operand 3 "register_operand" ""))]
|
| 2159 |
|
|
"reload_completed && TARGET_CPU_ZARCH"
|
| 2160 |
|
|
[(set (match_dup 3) (label_ref (match_dup 4)))
|
| 2161 |
|
|
(parallel
|
| 2162 |
|
|
[(unspec [(match_dup 2) (mem:BLK (match_dup 3))
|
| 2163 |
|
|
(label_ref (match_dup 4))] UNSPEC_EXECUTE)
|
| 2164 |
|
|
(set (match_dup 0) (match_dup 1))
|
| 2165 |
|
|
(use (const_int 1))])]
|
| 2166 |
|
|
"operands[4] = gen_label_rtx ();")
|
| 2167 |
|
|
|
| 2168 |
|
|
; Move a block of arbitrary length.
|
| 2169 |
|
|
|
| 2170 |
|
|
(define_expand "movmem_long"
|
| 2171 |
|
|
[(parallel
|
| 2172 |
|
|
[(clobber (match_dup 2))
|
| 2173 |
|
|
(clobber (match_dup 3))
|
| 2174 |
|
|
(set (match_operand:BLK 0 "memory_operand" "")
|
| 2175 |
|
|
(match_operand:BLK 1 "memory_operand" ""))
|
| 2176 |
|
|
(use (match_operand 2 "general_operand" ""))
|
| 2177 |
|
|
(use (match_dup 3))
|
| 2178 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2179 |
|
|
""
|
| 2180 |
|
|
{
|
| 2181 |
|
|
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
|
| 2182 |
|
|
rtx reg0 = gen_reg_rtx (dword_mode);
|
| 2183 |
|
|
rtx reg1 = gen_reg_rtx (dword_mode);
|
| 2184 |
|
|
rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
|
| 2185 |
|
|
rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
|
| 2186 |
|
|
rtx len0 = gen_lowpart (Pmode, reg0);
|
| 2187 |
|
|
rtx len1 = gen_lowpart (Pmode, reg1);
|
| 2188 |
|
|
|
| 2189 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
|
| 2190 |
|
|
emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
|
| 2191 |
|
|
emit_move_insn (len0, operands[2]);
|
| 2192 |
|
|
|
| 2193 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
|
| 2194 |
|
|
emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
|
| 2195 |
|
|
emit_move_insn (len1, operands[2]);
|
| 2196 |
|
|
|
| 2197 |
|
|
operands[0] = replace_equiv_address_nv (operands[0], addr0);
|
| 2198 |
|
|
operands[1] = replace_equiv_address_nv (operands[1], addr1);
|
| 2199 |
|
|
operands[2] = reg0;
|
| 2200 |
|
|
operands[3] = reg1;
|
| 2201 |
|
|
})
|
| 2202 |
|
|
|
| 2203 |
|
|
(define_insn "*movmem_long"
|
| 2204 |
|
|
[(clobber (match_operand: 0 "register_operand" "=d"))
|
| 2205 |
|
|
(clobber (match_operand: 1 "register_operand" "=d"))
|
| 2206 |
|
|
(set (mem:BLK (subreg:P (match_operand: 2 "register_operand" "0") 0))
|
| 2207 |
|
|
(mem:BLK (subreg:P (match_operand: 3 "register_operand" "1") 0)))
|
| 2208 |
|
|
(use (match_dup 2))
|
| 2209 |
|
|
(use (match_dup 3))
|
| 2210 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2211 |
|
|
""
|
| 2212 |
|
|
"mvcle\t%0,%1,0\;jo\t.-4"
|
| 2213 |
|
|
[(set_attr "length" "8")
|
| 2214 |
|
|
(set_attr "type" "vs")])
|
| 2215 |
|
|
|
| 2216 |
|
|
;
|
| 2217 |
|
|
; setmemM instruction pattern(s).
|
| 2218 |
|
|
;
|
| 2219 |
|
|
|
| 2220 |
|
|
(define_expand "setmem"
|
| 2221 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2222 |
|
|
(match_operand:QI 2 "general_operand" ""))
|
| 2223 |
|
|
(use (match_operand:GPR 1 "general_operand" ""))
|
| 2224 |
|
|
(match_operand 3 "" "")]
|
| 2225 |
|
|
""
|
| 2226 |
|
|
"s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
|
| 2227 |
|
|
|
| 2228 |
|
|
; Clear a block that is up to 256 bytes in length.
|
| 2229 |
|
|
; The block length is taken as (operands[1] % 256) + 1.
|
| 2230 |
|
|
|
| 2231 |
|
|
(define_expand "clrmem_short"
|
| 2232 |
|
|
[(parallel
|
| 2233 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2234 |
|
|
(const_int 0))
|
| 2235 |
|
|
(use (match_operand 1 "nonmemory_operand" ""))
|
| 2236 |
|
|
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
|
| 2237 |
|
|
(clobber (match_dup 2))
|
| 2238 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2239 |
|
|
""
|
| 2240 |
|
|
"operands[2] = gen_rtx_SCRATCH (Pmode);")
|
| 2241 |
|
|
|
| 2242 |
|
|
(define_insn "*clrmem_short"
|
| 2243 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
|
| 2244 |
|
|
(const_int 0))
|
| 2245 |
|
|
(use (match_operand 1 "nonmemory_operand" "n,a,a"))
|
| 2246 |
|
|
(use (match_operand 2 "immediate_operand" "X,R,X"))
|
| 2247 |
|
|
(clobber (match_scratch 3 "=X,X,&a"))
|
| 2248 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2249 |
|
|
"(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
|
| 2250 |
|
|
&& GET_MODE (operands[3]) == Pmode"
|
| 2251 |
|
|
"#"
|
| 2252 |
|
|
[(set_attr "type" "cs")])
|
| 2253 |
|
|
|
| 2254 |
|
|
(define_split
|
| 2255 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2256 |
|
|
(const_int 0))
|
| 2257 |
|
|
(use (match_operand 1 "const_int_operand" ""))
|
| 2258 |
|
|
(use (match_operand 2 "immediate_operand" ""))
|
| 2259 |
|
|
(clobber (scratch))
|
| 2260 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2261 |
|
|
"reload_completed"
|
| 2262 |
|
|
[(parallel
|
| 2263 |
|
|
[(set (match_dup 0) (const_int 0))
|
| 2264 |
|
|
(use (match_dup 1))
|
| 2265 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2266 |
|
|
"operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
|
| 2267 |
|
|
|
| 2268 |
|
|
(define_split
|
| 2269 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2270 |
|
|
(const_int 0))
|
| 2271 |
|
|
(use (match_operand 1 "register_operand" ""))
|
| 2272 |
|
|
(use (match_operand 2 "memory_operand" ""))
|
| 2273 |
|
|
(clobber (scratch))
|
| 2274 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2275 |
|
|
"reload_completed"
|
| 2276 |
|
|
[(parallel
|
| 2277 |
|
|
[(unspec [(match_dup 1) (match_dup 2)
|
| 2278 |
|
|
(const_int 0)] UNSPEC_EXECUTE)
|
| 2279 |
|
|
(set (match_dup 0) (const_int 0))
|
| 2280 |
|
|
(use (const_int 1))
|
| 2281 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2282 |
|
|
"")
|
| 2283 |
|
|
|
| 2284 |
|
|
(define_split
|
| 2285 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 2286 |
|
|
(const_int 0))
|
| 2287 |
|
|
(use (match_operand 1 "register_operand" ""))
|
| 2288 |
|
|
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
|
| 2289 |
|
|
(clobber (match_operand 2 "register_operand" ""))
|
| 2290 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2291 |
|
|
"reload_completed && TARGET_CPU_ZARCH"
|
| 2292 |
|
|
[(set (match_dup 2) (label_ref (match_dup 3)))
|
| 2293 |
|
|
(parallel
|
| 2294 |
|
|
[(unspec [(match_dup 1) (mem:BLK (match_dup 2))
|
| 2295 |
|
|
(label_ref (match_dup 3))] UNSPEC_EXECUTE)
|
| 2296 |
|
|
(set (match_dup 0) (const_int 0))
|
| 2297 |
|
|
(use (const_int 1))
|
| 2298 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2299 |
|
|
"operands[3] = gen_label_rtx ();")
|
| 2300 |
|
|
|
| 2301 |
|
|
; Initialize a block of arbitrary length with (operands[2] % 256).
|
| 2302 |
|
|
|
| 2303 |
|
|
(define_expand "setmem_long"
|
| 2304 |
|
|
[(parallel
|
| 2305 |
|
|
[(clobber (match_dup 1))
|
| 2306 |
|
|
(set (match_operand:BLK 0 "memory_operand" "")
|
| 2307 |
|
|
(match_operand 2 "shift_count_or_setmem_operand" ""))
|
| 2308 |
|
|
(use (match_operand 1 "general_operand" ""))
|
| 2309 |
|
|
(use (match_dup 3))
|
| 2310 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2311 |
|
|
""
|
| 2312 |
|
|
{
|
| 2313 |
|
|
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
|
| 2314 |
|
|
rtx reg0 = gen_reg_rtx (dword_mode);
|
| 2315 |
|
|
rtx reg1 = gen_reg_rtx (dword_mode);
|
| 2316 |
|
|
rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
|
| 2317 |
|
|
rtx len0 = gen_lowpart (Pmode, reg0);
|
| 2318 |
|
|
|
| 2319 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
|
| 2320 |
|
|
emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
|
| 2321 |
|
|
emit_move_insn (len0, operands[1]);
|
| 2322 |
|
|
|
| 2323 |
|
|
emit_move_insn (reg1, const0_rtx);
|
| 2324 |
|
|
|
| 2325 |
|
|
operands[0] = replace_equiv_address_nv (operands[0], addr0);
|
| 2326 |
|
|
operands[1] = reg0;
|
| 2327 |
|
|
operands[3] = reg1;
|
| 2328 |
|
|
})
|
| 2329 |
|
|
|
| 2330 |
|
|
(define_insn "*setmem_long"
|
| 2331 |
|
|
[(clobber (match_operand: 0 "register_operand" "=d"))
|
| 2332 |
|
|
(set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0))
|
| 2333 |
|
|
(match_operand 2 "shift_count_or_setmem_operand" "Y"))
|
| 2334 |
|
|
(use (match_dup 3))
|
| 2335 |
|
|
(use (match_operand: 1 "register_operand" "d"))
|
| 2336 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2337 |
|
|
""
|
| 2338 |
|
|
"mvcle\t%0,%1,%Y2\;jo\t.-4"
|
| 2339 |
|
|
[(set_attr "length" "8")
|
| 2340 |
|
|
(set_attr "type" "vs")])
|
| 2341 |
|
|
|
| 2342 |
|
|
(define_insn "*setmem_long_and"
|
| 2343 |
|
|
[(clobber (match_operand: 0 "register_operand" "=d"))
|
| 2344 |
|
|
(set (mem:BLK (subreg:P (match_operand: 3 "register_operand" "0") 0))
|
| 2345 |
|
|
(and (match_operand 2 "shift_count_or_setmem_operand" "Y")
|
| 2346 |
|
|
(match_operand 4 "const_int_operand" "n")))
|
| 2347 |
|
|
(use (match_dup 3))
|
| 2348 |
|
|
(use (match_operand: 1 "register_operand" "d"))
|
| 2349 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2350 |
|
|
"(INTVAL (operands[4]) & 255) == 255"
|
| 2351 |
|
|
"mvcle\t%0,%1,%Y2\;jo\t.-4"
|
| 2352 |
|
|
[(set_attr "length" "8")
|
| 2353 |
|
|
(set_attr "type" "vs")])
|
| 2354 |
|
|
;
|
| 2355 |
|
|
; cmpmemM instruction pattern(s).
|
| 2356 |
|
|
;
|
| 2357 |
|
|
|
| 2358 |
|
|
(define_expand "cmpmemsi"
|
| 2359 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 2360 |
|
|
(compare:SI (match_operand:BLK 1 "memory_operand" "")
|
| 2361 |
|
|
(match_operand:BLK 2 "memory_operand" "") ) )
|
| 2362 |
|
|
(use (match_operand:SI 3 "general_operand" ""))
|
| 2363 |
|
|
(use (match_operand:SI 4 "" ""))]
|
| 2364 |
|
|
""
|
| 2365 |
|
|
"s390_expand_cmpmem (operands[0], operands[1],
|
| 2366 |
|
|
operands[2], operands[3]); DONE;")
|
| 2367 |
|
|
|
| 2368 |
|
|
; Compare a block that is up to 256 bytes in length.
|
| 2369 |
|
|
; The block length is taken as (operands[2] % 256) + 1.
|
| 2370 |
|
|
|
| 2371 |
|
|
(define_expand "cmpmem_short"
|
| 2372 |
|
|
[(parallel
|
| 2373 |
|
|
[(set (reg:CCU CC_REGNUM)
|
| 2374 |
|
|
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
|
| 2375 |
|
|
(match_operand:BLK 1 "memory_operand" "")))
|
| 2376 |
|
|
(use (match_operand 2 "nonmemory_operand" ""))
|
| 2377 |
|
|
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
|
| 2378 |
|
|
(clobber (match_dup 3))])]
|
| 2379 |
|
|
""
|
| 2380 |
|
|
"operands[3] = gen_rtx_SCRATCH (Pmode);")
|
| 2381 |
|
|
|
| 2382 |
|
|
(define_insn "*cmpmem_short"
|
| 2383 |
|
|
[(set (reg:CCU CC_REGNUM)
|
| 2384 |
|
|
(compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
|
| 2385 |
|
|
(match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
|
| 2386 |
|
|
(use (match_operand 2 "nonmemory_operand" "n,a,a"))
|
| 2387 |
|
|
(use (match_operand 3 "immediate_operand" "X,R,X"))
|
| 2388 |
|
|
(clobber (match_scratch 4 "=X,X,&a"))]
|
| 2389 |
|
|
"(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
|
| 2390 |
|
|
&& GET_MODE (operands[4]) == Pmode"
|
| 2391 |
|
|
"#"
|
| 2392 |
|
|
[(set_attr "type" "cs")])
|
| 2393 |
|
|
|
| 2394 |
|
|
(define_split
|
| 2395 |
|
|
[(set (reg:CCU CC_REGNUM)
|
| 2396 |
|
|
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
|
| 2397 |
|
|
(match_operand:BLK 1 "memory_operand" "")))
|
| 2398 |
|
|
(use (match_operand 2 "const_int_operand" ""))
|
| 2399 |
|
|
(use (match_operand 3 "immediate_operand" ""))
|
| 2400 |
|
|
(clobber (scratch))]
|
| 2401 |
|
|
"reload_completed"
|
| 2402 |
|
|
[(parallel
|
| 2403 |
|
|
[(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
|
| 2404 |
|
|
(use (match_dup 2))])]
|
| 2405 |
|
|
"operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
|
| 2406 |
|
|
|
| 2407 |
|
|
(define_split
|
| 2408 |
|
|
[(set (reg:CCU CC_REGNUM)
|
| 2409 |
|
|
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
|
| 2410 |
|
|
(match_operand:BLK 1 "memory_operand" "")))
|
| 2411 |
|
|
(use (match_operand 2 "register_operand" ""))
|
| 2412 |
|
|
(use (match_operand 3 "memory_operand" ""))
|
| 2413 |
|
|
(clobber (scratch))]
|
| 2414 |
|
|
"reload_completed"
|
| 2415 |
|
|
[(parallel
|
| 2416 |
|
|
[(unspec [(match_dup 2) (match_dup 3)
|
| 2417 |
|
|
(const_int 0)] UNSPEC_EXECUTE)
|
| 2418 |
|
|
(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
|
| 2419 |
|
|
(use (const_int 1))])]
|
| 2420 |
|
|
"")
|
| 2421 |
|
|
|
| 2422 |
|
|
(define_split
|
| 2423 |
|
|
[(set (reg:CCU CC_REGNUM)
|
| 2424 |
|
|
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
|
| 2425 |
|
|
(match_operand:BLK 1 "memory_operand" "")))
|
| 2426 |
|
|
(use (match_operand 2 "register_operand" ""))
|
| 2427 |
|
|
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
|
| 2428 |
|
|
(clobber (match_operand 3 "register_operand" ""))]
|
| 2429 |
|
|
"reload_completed && TARGET_CPU_ZARCH"
|
| 2430 |
|
|
[(set (match_dup 3) (label_ref (match_dup 4)))
|
| 2431 |
|
|
(parallel
|
| 2432 |
|
|
[(unspec [(match_dup 2) (mem:BLK (match_dup 3))
|
| 2433 |
|
|
(label_ref (match_dup 4))] UNSPEC_EXECUTE)
|
| 2434 |
|
|
(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
|
| 2435 |
|
|
(use (const_int 1))])]
|
| 2436 |
|
|
"operands[4] = gen_label_rtx ();")
|
| 2437 |
|
|
|
| 2438 |
|
|
; Compare a block of arbitrary length.
|
| 2439 |
|
|
|
| 2440 |
|
|
(define_expand "cmpmem_long"
|
| 2441 |
|
|
[(parallel
|
| 2442 |
|
|
[(clobber (match_dup 2))
|
| 2443 |
|
|
(clobber (match_dup 3))
|
| 2444 |
|
|
(set (reg:CCU CC_REGNUM)
|
| 2445 |
|
|
(compare:CCU (match_operand:BLK 0 "memory_operand" "")
|
| 2446 |
|
|
(match_operand:BLK 1 "memory_operand" "")))
|
| 2447 |
|
|
(use (match_operand 2 "general_operand" ""))
|
| 2448 |
|
|
(use (match_dup 3))])]
|
| 2449 |
|
|
""
|
| 2450 |
|
|
{
|
| 2451 |
|
|
enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
|
| 2452 |
|
|
rtx reg0 = gen_reg_rtx (dword_mode);
|
| 2453 |
|
|
rtx reg1 = gen_reg_rtx (dword_mode);
|
| 2454 |
|
|
rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
|
| 2455 |
|
|
rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
|
| 2456 |
|
|
rtx len0 = gen_lowpart (Pmode, reg0);
|
| 2457 |
|
|
rtx len1 = gen_lowpart (Pmode, reg1);
|
| 2458 |
|
|
|
| 2459 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
|
| 2460 |
|
|
emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
|
| 2461 |
|
|
emit_move_insn (len0, operands[2]);
|
| 2462 |
|
|
|
| 2463 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
|
| 2464 |
|
|
emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
|
| 2465 |
|
|
emit_move_insn (len1, operands[2]);
|
| 2466 |
|
|
|
| 2467 |
|
|
operands[0] = replace_equiv_address_nv (operands[0], addr0);
|
| 2468 |
|
|
operands[1] = replace_equiv_address_nv (operands[1], addr1);
|
| 2469 |
|
|
operands[2] = reg0;
|
| 2470 |
|
|
operands[3] = reg1;
|
| 2471 |
|
|
})
|
| 2472 |
|
|
|
| 2473 |
|
|
(define_insn "*cmpmem_long"
|
| 2474 |
|
|
[(clobber (match_operand: 0 "register_operand" "=d"))
|
| 2475 |
|
|
(clobber (match_operand: 1 "register_operand" "=d"))
|
| 2476 |
|
|
(set (reg:CCU CC_REGNUM)
|
| 2477 |
|
|
(compare:CCU (mem:BLK (subreg:P (match_operand: 2 "register_operand" "0") 0))
|
| 2478 |
|
|
(mem:BLK (subreg:P (match_operand: 3 "register_operand" "1") 0))))
|
| 2479 |
|
|
(use (match_dup 2))
|
| 2480 |
|
|
(use (match_dup 3))]
|
| 2481 |
|
|
""
|
| 2482 |
|
|
"clcle\t%0,%1,0\;jo\t.-4"
|
| 2483 |
|
|
[(set_attr "length" "8")
|
| 2484 |
|
|
(set_attr "type" "vs")])
|
| 2485 |
|
|
|
| 2486 |
|
|
; Convert CCUmode condition code to integer.
|
| 2487 |
|
|
; Result is zero if EQ, positive if LTU, negative if GTU.
|
| 2488 |
|
|
|
| 2489 |
|
|
(define_insn_and_split "cmpint"
|
| 2490 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 2491 |
|
|
(unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
|
| 2492 |
|
|
UNSPEC_CMPINT))
|
| 2493 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2494 |
|
|
""
|
| 2495 |
|
|
"#"
|
| 2496 |
|
|
"reload_completed"
|
| 2497 |
|
|
[(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
|
| 2498 |
|
|
(parallel
|
| 2499 |
|
|
[(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
|
| 2500 |
|
|
(clobber (reg:CC CC_REGNUM))])])
|
| 2501 |
|
|
|
| 2502 |
|
|
(define_insn_and_split "*cmpint_cc"
|
| 2503 |
|
|
[(set (reg CC_REGNUM)
|
| 2504 |
|
|
(compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
|
| 2505 |
|
|
UNSPEC_CMPINT)
|
| 2506 |
|
|
(const_int 0)))
|
| 2507 |
|
|
(set (match_operand:SI 0 "register_operand" "=d")
|
| 2508 |
|
|
(unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
|
| 2509 |
|
|
"s390_match_ccmode (insn, CCSmode)"
|
| 2510 |
|
|
"#"
|
| 2511 |
|
|
"&& reload_completed"
|
| 2512 |
|
|
[(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
|
| 2513 |
|
|
(parallel
|
| 2514 |
|
|
[(set (match_dup 2) (match_dup 3))
|
| 2515 |
|
|
(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
|
| 2516 |
|
|
{
|
| 2517 |
|
|
rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
|
| 2518 |
|
|
operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
|
| 2519 |
|
|
operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
|
| 2520 |
|
|
})
|
| 2521 |
|
|
|
| 2522 |
|
|
(define_insn_and_split "*cmpint_sign"
|
| 2523 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 2524 |
|
|
(sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
|
| 2525 |
|
|
UNSPEC_CMPINT)))
|
| 2526 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2527 |
|
|
"TARGET_64BIT"
|
| 2528 |
|
|
"#"
|
| 2529 |
|
|
"&& reload_completed"
|
| 2530 |
|
|
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
|
| 2531 |
|
|
(parallel
|
| 2532 |
|
|
[(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
|
| 2533 |
|
|
(clobber (reg:CC CC_REGNUM))])])
|
| 2534 |
|
|
|
| 2535 |
|
|
(define_insn_and_split "*cmpint_sign_cc"
|
| 2536 |
|
|
[(set (reg CC_REGNUM)
|
| 2537 |
|
|
(compare (ashiftrt:DI (ashift:DI (subreg:DI
|
| 2538 |
|
|
(unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
|
| 2539 |
|
|
UNSPEC_CMPINT) 0)
|
| 2540 |
|
|
(const_int 32)) (const_int 32))
|
| 2541 |
|
|
(const_int 0)))
|
| 2542 |
|
|
(set (match_operand:DI 0 "register_operand" "=d")
|
| 2543 |
|
|
(sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
|
| 2544 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
|
| 2545 |
|
|
"#"
|
| 2546 |
|
|
"&& reload_completed"
|
| 2547 |
|
|
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
|
| 2548 |
|
|
(parallel
|
| 2549 |
|
|
[(set (match_dup 2) (match_dup 3))
|
| 2550 |
|
|
(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
|
| 2551 |
|
|
{
|
| 2552 |
|
|
rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
|
| 2553 |
|
|
operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
|
| 2554 |
|
|
operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
|
| 2555 |
|
|
})
|
| 2556 |
|
|
|
| 2557 |
|
|
|
| 2558 |
|
|
;;
|
| 2559 |
|
|
;;- Conversion instructions.
|
| 2560 |
|
|
;;
|
| 2561 |
|
|
|
| 2562 |
|
|
(define_insn "*sethighpartsi"
|
| 2563 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 2564 |
|
|
(unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
|
| 2565 |
|
|
(match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
|
| 2566 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2567 |
|
|
""
|
| 2568 |
|
|
"@
|
| 2569 |
|
|
icm\t%0,%2,%S1
|
| 2570 |
|
|
icmy\t%0,%2,%S1"
|
| 2571 |
|
|
[(set_attr "op_type" "RS,RSY")])
|
| 2572 |
|
|
|
| 2573 |
|
|
(define_insn "*sethighpartdi_64"
|
| 2574 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 2575 |
|
|
(unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
|
| 2576 |
|
|
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
|
| 2577 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2578 |
|
|
"TARGET_64BIT"
|
| 2579 |
|
|
"icmh\t%0,%2,%S1"
|
| 2580 |
|
|
[(set_attr "op_type" "RSY")])
|
| 2581 |
|
|
|
| 2582 |
|
|
(define_insn "*sethighpartdi_31"
|
| 2583 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 2584 |
|
|
(unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
|
| 2585 |
|
|
(match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
|
| 2586 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2587 |
|
|
"!TARGET_64BIT"
|
| 2588 |
|
|
"@
|
| 2589 |
|
|
icm\t%0,%2,%S1
|
| 2590 |
|
|
icmy\t%0,%2,%S1"
|
| 2591 |
|
|
[(set_attr "op_type" "RS,RSY")])
|
| 2592 |
|
|
|
| 2593 |
|
|
(define_insn_and_split "*extzv"
|
| 2594 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 2595 |
|
|
(zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
|
| 2596 |
|
|
(match_operand 2 "const_int_operand" "n")
|
| 2597 |
|
|
(const_int 0)))
|
| 2598 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2599 |
|
|
"INTVAL (operands[2]) > 0
|
| 2600 |
|
|
&& INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
|
| 2601 |
|
|
"#"
|
| 2602 |
|
|
"&& reload_completed"
|
| 2603 |
|
|
[(parallel
|
| 2604 |
|
|
[(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
|
| 2605 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 2606 |
|
|
(set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
|
| 2607 |
|
|
{
|
| 2608 |
|
|
int bitsize = INTVAL (operands[2]);
|
| 2609 |
|
|
int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
|
| 2610 |
|
|
int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
|
| 2611 |
|
|
|
| 2612 |
|
|
operands[1] = adjust_address (operands[1], BLKmode, 0);
|
| 2613 |
|
|
set_mem_size (operands[1], GEN_INT (size));
|
| 2614 |
|
|
operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - bitsize);
|
| 2615 |
|
|
operands[3] = GEN_INT (mask);
|
| 2616 |
|
|
})
|
| 2617 |
|
|
|
| 2618 |
|
|
(define_insn_and_split "*extv"
|
| 2619 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 2620 |
|
|
(sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
|
| 2621 |
|
|
(match_operand 2 "const_int_operand" "n")
|
| 2622 |
|
|
(const_int 0)))
|
| 2623 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2624 |
|
|
"INTVAL (operands[2]) > 0
|
| 2625 |
|
|
&& INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
|
| 2626 |
|
|
"#"
|
| 2627 |
|
|
"&& reload_completed"
|
| 2628 |
|
|
[(parallel
|
| 2629 |
|
|
[(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
|
| 2630 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 2631 |
|
|
(parallel
|
| 2632 |
|
|
[(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
|
| 2633 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2634 |
|
|
{
|
| 2635 |
|
|
int bitsize = INTVAL (operands[2]);
|
| 2636 |
|
|
int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
|
| 2637 |
|
|
int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
|
| 2638 |
|
|
|
| 2639 |
|
|
operands[1] = adjust_address (operands[1], BLKmode, 0);
|
| 2640 |
|
|
set_mem_size (operands[1], GEN_INT (size));
|
| 2641 |
|
|
operands[2] = GEN_INT (GET_MODE_BITSIZE (mode) - bitsize);
|
| 2642 |
|
|
operands[3] = GEN_INT (mask);
|
| 2643 |
|
|
})
|
| 2644 |
|
|
|
| 2645 |
|
|
;
|
| 2646 |
|
|
; insv instruction patterns
|
| 2647 |
|
|
;
|
| 2648 |
|
|
|
| 2649 |
|
|
(define_expand "insv"
|
| 2650 |
|
|
[(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
|
| 2651 |
|
|
(match_operand 1 "const_int_operand" "")
|
| 2652 |
|
|
(match_operand 2 "const_int_operand" ""))
|
| 2653 |
|
|
(match_operand 3 "general_operand" ""))]
|
| 2654 |
|
|
""
|
| 2655 |
|
|
{
|
| 2656 |
|
|
if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
|
| 2657 |
|
|
DONE;
|
| 2658 |
|
|
FAIL;
|
| 2659 |
|
|
})
|
| 2660 |
|
|
|
| 2661 |
|
|
(define_insn "*insv_mem_reg"
|
| 2662 |
|
|
[(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
|
| 2663 |
|
|
(match_operand 1 "const_int_operand" "n,n")
|
| 2664 |
|
|
(const_int 0))
|
| 2665 |
|
|
(match_operand:P 2 "register_operand" "d,d"))]
|
| 2666 |
|
|
"INTVAL (operands[1]) > 0
|
| 2667 |
|
|
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
|
| 2668 |
|
|
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
|
| 2669 |
|
|
{
|
| 2670 |
|
|
int size = INTVAL (operands[1]) / BITS_PER_UNIT;
|
| 2671 |
|
|
|
| 2672 |
|
|
operands[1] = GEN_INT ((1ul << size) - 1);
|
| 2673 |
|
|
return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
|
| 2674 |
|
|
: "stcmy\t%2,%1,%S0";
|
| 2675 |
|
|
}
|
| 2676 |
|
|
[(set_attr "op_type" "RS,RSY")])
|
| 2677 |
|
|
|
| 2678 |
|
|
(define_insn "*insvdi_mem_reghigh"
|
| 2679 |
|
|
[(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
|
| 2680 |
|
|
(match_operand 1 "const_int_operand" "n")
|
| 2681 |
|
|
(const_int 0))
|
| 2682 |
|
|
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
|
| 2683 |
|
|
(const_int 32)))]
|
| 2684 |
|
|
"TARGET_64BIT
|
| 2685 |
|
|
&& INTVAL (operands[1]) > 0
|
| 2686 |
|
|
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
|
| 2687 |
|
|
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
|
| 2688 |
|
|
{
|
| 2689 |
|
|
int size = INTVAL (operands[1]) / BITS_PER_UNIT;
|
| 2690 |
|
|
|
| 2691 |
|
|
operands[1] = GEN_INT ((1ul << size) - 1);
|
| 2692 |
|
|
return "stcmh\t%2,%1,%S0";
|
| 2693 |
|
|
}
|
| 2694 |
|
|
[(set_attr "op_type" "RSY")])
|
| 2695 |
|
|
|
| 2696 |
|
|
(define_insn "*insv_reg_imm"
|
| 2697 |
|
|
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
|
| 2698 |
|
|
(const_int 16)
|
| 2699 |
|
|
(match_operand 1 "const_int_operand" "n"))
|
| 2700 |
|
|
(match_operand:P 2 "const_int_operand" "n"))]
|
| 2701 |
|
|
"TARGET_ZARCH
|
| 2702 |
|
|
&& INTVAL (operands[1]) >= 0
|
| 2703 |
|
|
&& INTVAL (operands[1]) < BITS_PER_WORD
|
| 2704 |
|
|
&& INTVAL (operands[1]) % 16 == 0"
|
| 2705 |
|
|
{
|
| 2706 |
|
|
switch (BITS_PER_WORD - INTVAL (operands[1]))
|
| 2707 |
|
|
{
|
| 2708 |
|
|
case 64: return "iihh\t%0,%x2"; break;
|
| 2709 |
|
|
case 48: return "iihl\t%0,%x2"; break;
|
| 2710 |
|
|
case 32: return "iilh\t%0,%x2"; break;
|
| 2711 |
|
|
case 16: return "iill\t%0,%x2"; break;
|
| 2712 |
|
|
default: gcc_unreachable();
|
| 2713 |
|
|
}
|
| 2714 |
|
|
}
|
| 2715 |
|
|
[(set_attr "op_type" "RI")])
|
| 2716 |
|
|
|
| 2717 |
|
|
(define_insn "*insv_reg_extimm"
|
| 2718 |
|
|
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
|
| 2719 |
|
|
(const_int 32)
|
| 2720 |
|
|
(match_operand 1 "const_int_operand" "n"))
|
| 2721 |
|
|
(match_operand:P 2 "const_int_operand" "n"))]
|
| 2722 |
|
|
"TARGET_EXTIMM
|
| 2723 |
|
|
&& INTVAL (operands[1]) >= 0
|
| 2724 |
|
|
&& INTVAL (operands[1]) < BITS_PER_WORD
|
| 2725 |
|
|
&& INTVAL (operands[1]) % 32 == 0"
|
| 2726 |
|
|
{
|
| 2727 |
|
|
switch (BITS_PER_WORD - INTVAL (operands[1]))
|
| 2728 |
|
|
{
|
| 2729 |
|
|
case 64: return "iihf\t%0,%o2"; break;
|
| 2730 |
|
|
case 32: return "iilf\t%0,%o2"; break;
|
| 2731 |
|
|
default: gcc_unreachable();
|
| 2732 |
|
|
}
|
| 2733 |
|
|
}
|
| 2734 |
|
|
[(set_attr "op_type" "RIL")])
|
| 2735 |
|
|
|
| 2736 |
|
|
;
|
| 2737 |
|
|
; extendsidi2 instruction pattern(s).
|
| 2738 |
|
|
;
|
| 2739 |
|
|
|
| 2740 |
|
|
(define_expand "extendsidi2"
|
| 2741 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 2742 |
|
|
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
|
| 2743 |
|
|
""
|
| 2744 |
|
|
{
|
| 2745 |
|
|
if (!TARGET_64BIT)
|
| 2746 |
|
|
{
|
| 2747 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
|
| 2748 |
|
|
emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
|
| 2749 |
|
|
emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
|
| 2750 |
|
|
emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
|
| 2751 |
|
|
DONE;
|
| 2752 |
|
|
}
|
| 2753 |
|
|
})
|
| 2754 |
|
|
|
| 2755 |
|
|
(define_insn "*extendsidi2"
|
| 2756 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 2757 |
|
|
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
|
| 2758 |
|
|
"TARGET_64BIT"
|
| 2759 |
|
|
"@
|
| 2760 |
|
|
lgfr\t%0,%1
|
| 2761 |
|
|
lgf\t%0,%1"
|
| 2762 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 2763 |
|
|
|
| 2764 |
|
|
;
|
| 2765 |
|
|
; extend(hi|qi)(si|di)2 instruction pattern(s).
|
| 2766 |
|
|
;
|
| 2767 |
|
|
|
| 2768 |
|
|
(define_expand "extend2"
|
| 2769 |
|
|
[(set (match_operand:DSI 0 "register_operand" "")
|
| 2770 |
|
|
(sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
|
| 2771 |
|
|
""
|
| 2772 |
|
|
{
|
| 2773 |
|
|
if (mode == DImode && !TARGET_64BIT)
|
| 2774 |
|
|
{
|
| 2775 |
|
|
rtx tmp = gen_reg_rtx (SImode);
|
| 2776 |
|
|
emit_insn (gen_extendsi2 (tmp, operands[1]));
|
| 2777 |
|
|
emit_insn (gen_extendsidi2 (operands[0], tmp));
|
| 2778 |
|
|
DONE;
|
| 2779 |
|
|
}
|
| 2780 |
|
|
else if (!TARGET_EXTIMM)
|
| 2781 |
|
|
{
|
| 2782 |
|
|
rtx bitcount = GEN_INT (GET_MODE_BITSIZE (mode) -
|
| 2783 |
|
|
GET_MODE_BITSIZE (mode));
|
| 2784 |
|
|
|
| 2785 |
|
|
operands[1] = gen_lowpart (mode, operands[1]);
|
| 2786 |
|
|
emit_insn (gen_ashl3 (operands[0], operands[1], bitcount));
|
| 2787 |
|
|
emit_insn (gen_ashr3 (operands[0], operands[0], bitcount));
|
| 2788 |
|
|
DONE;
|
| 2789 |
|
|
}
|
| 2790 |
|
|
})
|
| 2791 |
|
|
|
| 2792 |
|
|
;
|
| 2793 |
|
|
; extendhidi2 instruction pattern(s).
|
| 2794 |
|
|
;
|
| 2795 |
|
|
|
| 2796 |
|
|
(define_insn "*extendhidi2_extimm"
|
| 2797 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 2798 |
|
|
(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
| 2799 |
|
|
"TARGET_64BIT && TARGET_EXTIMM"
|
| 2800 |
|
|
"@
|
| 2801 |
|
|
lghr\t%0,%1
|
| 2802 |
|
|
lgh\t%0,%1"
|
| 2803 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 2804 |
|
|
|
| 2805 |
|
|
(define_insn "*extendhidi2"
|
| 2806 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 2807 |
|
|
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
|
| 2808 |
|
|
"TARGET_64BIT"
|
| 2809 |
|
|
"lgh\t%0,%1"
|
| 2810 |
|
|
[(set_attr "op_type" "RXY")])
|
| 2811 |
|
|
|
| 2812 |
|
|
;
|
| 2813 |
|
|
; extendhisi2 instruction pattern(s).
|
| 2814 |
|
|
;
|
| 2815 |
|
|
|
| 2816 |
|
|
(define_insn "*extendhisi2_extimm"
|
| 2817 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
|
| 2818 |
|
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
|
| 2819 |
|
|
"TARGET_EXTIMM"
|
| 2820 |
|
|
"@
|
| 2821 |
|
|
lhr\t%0,%1
|
| 2822 |
|
|
lh\t%0,%1
|
| 2823 |
|
|
lhy\t%0,%1"
|
| 2824 |
|
|
[(set_attr "op_type" "RRE,RX,RXY")])
|
| 2825 |
|
|
|
| 2826 |
|
|
(define_insn "*extendhisi2"
|
| 2827 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 2828 |
|
|
(sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
|
| 2829 |
|
|
"!TARGET_EXTIMM"
|
| 2830 |
|
|
"@
|
| 2831 |
|
|
lh\t%0,%1
|
| 2832 |
|
|
lhy\t%0,%1"
|
| 2833 |
|
|
[(set_attr "op_type" "RX,RXY")])
|
| 2834 |
|
|
|
| 2835 |
|
|
;
|
| 2836 |
|
|
; extendqi(si|di)2 instruction pattern(s).
|
| 2837 |
|
|
;
|
| 2838 |
|
|
|
| 2839 |
|
|
; lbr, lgbr, lb, lgb
|
| 2840 |
|
|
(define_insn "*extendqi2_extimm"
|
| 2841 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d,d")
|
| 2842 |
|
|
(sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
| 2843 |
|
|
"TARGET_EXTIMM"
|
| 2844 |
|
|
"@
|
| 2845 |
|
|
lbr\t%0,%1
|
| 2846 |
|
|
lb\t%0,%1"
|
| 2847 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 2848 |
|
|
|
| 2849 |
|
|
; lb, lgb
|
| 2850 |
|
|
(define_insn "*extendqi2"
|
| 2851 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 2852 |
|
|
(sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
|
| 2853 |
|
|
"!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
|
| 2854 |
|
|
"lb\t%0,%1"
|
| 2855 |
|
|
[(set_attr "op_type" "RXY")])
|
| 2856 |
|
|
|
| 2857 |
|
|
(define_insn_and_split "*extendqi2_short_displ"
|
| 2858 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 2859 |
|
|
(sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
|
| 2860 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2861 |
|
|
"!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
|
| 2862 |
|
|
"#"
|
| 2863 |
|
|
"&& reload_completed"
|
| 2864 |
|
|
[(parallel
|
| 2865 |
|
|
[(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
|
| 2866 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 2867 |
|
|
(parallel
|
| 2868 |
|
|
[(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
|
| 2869 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 2870 |
|
|
{
|
| 2871 |
|
|
operands[1] = adjust_address (operands[1], BLKmode, 0);
|
| 2872 |
|
|
set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
|
| 2873 |
|
|
operands[2] = GEN_INT (GET_MODE_BITSIZE (mode)
|
| 2874 |
|
|
- GET_MODE_BITSIZE (QImode));
|
| 2875 |
|
|
})
|
| 2876 |
|
|
|
| 2877 |
|
|
;
|
| 2878 |
|
|
; zero_extendsidi2 instruction pattern(s).
|
| 2879 |
|
|
;
|
| 2880 |
|
|
|
| 2881 |
|
|
(define_expand "zero_extendsidi2"
|
| 2882 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 2883 |
|
|
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
|
| 2884 |
|
|
""
|
| 2885 |
|
|
{
|
| 2886 |
|
|
if (!TARGET_64BIT)
|
| 2887 |
|
|
{
|
| 2888 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
|
| 2889 |
|
|
emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
|
| 2890 |
|
|
emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
|
| 2891 |
|
|
DONE;
|
| 2892 |
|
|
}
|
| 2893 |
|
|
})
|
| 2894 |
|
|
|
| 2895 |
|
|
(define_insn "*zero_extendsidi2"
|
| 2896 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 2897 |
|
|
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
|
| 2898 |
|
|
"TARGET_64BIT"
|
| 2899 |
|
|
"@
|
| 2900 |
|
|
llgfr\t%0,%1
|
| 2901 |
|
|
llgf\t%0,%1"
|
| 2902 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 2903 |
|
|
|
| 2904 |
|
|
;
|
| 2905 |
|
|
; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
|
| 2906 |
|
|
;
|
| 2907 |
|
|
|
| 2908 |
|
|
(define_insn "*llgt_sidi"
|
| 2909 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 2910 |
|
|
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
|
| 2911 |
|
|
(const_int 2147483647)))]
|
| 2912 |
|
|
"TARGET_64BIT"
|
| 2913 |
|
|
"llgt\t%0,%1"
|
| 2914 |
|
|
[(set_attr "op_type" "RXE")])
|
| 2915 |
|
|
|
| 2916 |
|
|
(define_insn_and_split "*llgt_sidi_split"
|
| 2917 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 2918 |
|
|
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
|
| 2919 |
|
|
(const_int 2147483647)))
|
| 2920 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2921 |
|
|
"TARGET_64BIT"
|
| 2922 |
|
|
"#"
|
| 2923 |
|
|
"&& reload_completed"
|
| 2924 |
|
|
[(set (match_dup 0)
|
| 2925 |
|
|
(and:DI (subreg:DI (match_dup 1) 0)
|
| 2926 |
|
|
(const_int 2147483647)))]
|
| 2927 |
|
|
"")
|
| 2928 |
|
|
|
| 2929 |
|
|
(define_insn "*llgt_sisi"
|
| 2930 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 2931 |
|
|
(and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
|
| 2932 |
|
|
(const_int 2147483647)))]
|
| 2933 |
|
|
"TARGET_ZARCH"
|
| 2934 |
|
|
"@
|
| 2935 |
|
|
llgtr\t%0,%1
|
| 2936 |
|
|
llgt\t%0,%1"
|
| 2937 |
|
|
[(set_attr "op_type" "RRE,RXE")])
|
| 2938 |
|
|
|
| 2939 |
|
|
(define_insn "*llgt_didi"
|
| 2940 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 2941 |
|
|
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
|
| 2942 |
|
|
(const_int 2147483647)))]
|
| 2943 |
|
|
"TARGET_64BIT"
|
| 2944 |
|
|
"@
|
| 2945 |
|
|
llgtr\t%0,%1
|
| 2946 |
|
|
llgt\t%0,%N1"
|
| 2947 |
|
|
[(set_attr "op_type" "RRE,RXE")])
|
| 2948 |
|
|
|
| 2949 |
|
|
(define_split
|
| 2950 |
|
|
[(set (match_operand:GPR 0 "register_operand" "")
|
| 2951 |
|
|
(and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
|
| 2952 |
|
|
(const_int 2147483647)))
|
| 2953 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 2954 |
|
|
"TARGET_ZARCH && reload_completed"
|
| 2955 |
|
|
[(set (match_dup 0)
|
| 2956 |
|
|
(and:GPR (match_dup 1)
|
| 2957 |
|
|
(const_int 2147483647)))]
|
| 2958 |
|
|
"")
|
| 2959 |
|
|
|
| 2960 |
|
|
;
|
| 2961 |
|
|
; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
|
| 2962 |
|
|
;
|
| 2963 |
|
|
|
| 2964 |
|
|
(define_expand "zero_extenddi2"
|
| 2965 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 2966 |
|
|
(zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
|
| 2967 |
|
|
""
|
| 2968 |
|
|
{
|
| 2969 |
|
|
if (!TARGET_64BIT)
|
| 2970 |
|
|
{
|
| 2971 |
|
|
rtx tmp = gen_reg_rtx (SImode);
|
| 2972 |
|
|
emit_insn (gen_zero_extendsi2 (tmp, operands[1]));
|
| 2973 |
|
|
emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
|
| 2974 |
|
|
DONE;
|
| 2975 |
|
|
}
|
| 2976 |
|
|
else if (!TARGET_EXTIMM)
|
| 2977 |
|
|
{
|
| 2978 |
|
|
rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
|
| 2979 |
|
|
GET_MODE_BITSIZE(mode));
|
| 2980 |
|
|
operands[1] = gen_lowpart (DImode, operands[1]);
|
| 2981 |
|
|
emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
|
| 2982 |
|
|
emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
|
| 2983 |
|
|
DONE;
|
| 2984 |
|
|
}
|
| 2985 |
|
|
})
|
| 2986 |
|
|
|
| 2987 |
|
|
(define_expand "zero_extendsi2"
|
| 2988 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 2989 |
|
|
(zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
|
| 2990 |
|
|
""
|
| 2991 |
|
|
{
|
| 2992 |
|
|
if (!TARGET_EXTIMM)
|
| 2993 |
|
|
{
|
| 2994 |
|
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
| 2995 |
|
|
emit_insn (gen_andsi3 (operands[0], operands[1],
|
| 2996 |
|
|
GEN_INT ((1 << GET_MODE_BITSIZE(mode)) - 1)));
|
| 2997 |
|
|
DONE;
|
| 2998 |
|
|
}
|
| 2999 |
|
|
})
|
| 3000 |
|
|
|
| 3001 |
|
|
; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
|
| 3002 |
|
|
(define_insn "*zero_extend2_extimm"
|
| 3003 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d,d")
|
| 3004 |
|
|
(zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
|
| 3005 |
|
|
"TARGET_EXTIMM"
|
| 3006 |
|
|
"@
|
| 3007 |
|
|
llr\t%0,%1
|
| 3008 |
|
|
ll\t%0,%1"
|
| 3009 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3010 |
|
|
|
| 3011 |
|
|
; llgh, llgc
|
| 3012 |
|
|
(define_insn "*zero_extend2"
|
| 3013 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 3014 |
|
|
(zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
|
| 3015 |
|
|
"TARGET_ZARCH && !TARGET_EXTIMM"
|
| 3016 |
|
|
"llg\t%0,%1"
|
| 3017 |
|
|
[(set_attr "op_type" "RXY")])
|
| 3018 |
|
|
|
| 3019 |
|
|
(define_insn_and_split "*zero_extendhisi2_31"
|
| 3020 |
|
|
[(set (match_operand:SI 0 "register_operand" "=&d")
|
| 3021 |
|
|
(zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
|
| 3022 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3023 |
|
|
"!TARGET_ZARCH"
|
| 3024 |
|
|
"#"
|
| 3025 |
|
|
"&& reload_completed"
|
| 3026 |
|
|
[(set (match_dup 0) (const_int 0))
|
| 3027 |
|
|
(parallel
|
| 3028 |
|
|
[(set (strict_low_part (match_dup 2)) (match_dup 1))
|
| 3029 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3030 |
|
|
"operands[2] = gen_lowpart (HImode, operands[0]);")
|
| 3031 |
|
|
|
| 3032 |
|
|
(define_insn_and_split "*zero_extendqisi2_31"
|
| 3033 |
|
|
[(set (match_operand:SI 0 "register_operand" "=&d")
|
| 3034 |
|
|
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
|
| 3035 |
|
|
"!TARGET_ZARCH"
|
| 3036 |
|
|
"#"
|
| 3037 |
|
|
"&& reload_completed"
|
| 3038 |
|
|
[(set (match_dup 0) (const_int 0))
|
| 3039 |
|
|
(set (strict_low_part (match_dup 2)) (match_dup 1))]
|
| 3040 |
|
|
"operands[2] = gen_lowpart (QImode, operands[0]);")
|
| 3041 |
|
|
|
| 3042 |
|
|
;
|
| 3043 |
|
|
; zero_extendqihi2 instruction pattern(s).
|
| 3044 |
|
|
;
|
| 3045 |
|
|
|
| 3046 |
|
|
(define_expand "zero_extendqihi2"
|
| 3047 |
|
|
[(set (match_operand:HI 0 "register_operand" "")
|
| 3048 |
|
|
(zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
|
| 3049 |
|
|
"TARGET_ZARCH && !TARGET_EXTIMM"
|
| 3050 |
|
|
{
|
| 3051 |
|
|
operands[1] = gen_lowpart (HImode, operands[1]);
|
| 3052 |
|
|
emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
|
| 3053 |
|
|
DONE;
|
| 3054 |
|
|
})
|
| 3055 |
|
|
|
| 3056 |
|
|
(define_insn "*zero_extendqihi2_64"
|
| 3057 |
|
|
[(set (match_operand:HI 0 "register_operand" "=d")
|
| 3058 |
|
|
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
|
| 3059 |
|
|
"TARGET_ZARCH && !TARGET_EXTIMM"
|
| 3060 |
|
|
"llgc\t%0,%1"
|
| 3061 |
|
|
[(set_attr "op_type" "RXY")])
|
| 3062 |
|
|
|
| 3063 |
|
|
(define_insn_and_split "*zero_extendqihi2_31"
|
| 3064 |
|
|
[(set (match_operand:HI 0 "register_operand" "=&d")
|
| 3065 |
|
|
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
|
| 3066 |
|
|
"!TARGET_ZARCH"
|
| 3067 |
|
|
"#"
|
| 3068 |
|
|
"&& reload_completed"
|
| 3069 |
|
|
[(set (match_dup 0) (const_int 0))
|
| 3070 |
|
|
(set (strict_low_part (match_dup 2)) (match_dup 1))]
|
| 3071 |
|
|
"operands[2] = gen_lowpart (QImode, operands[0]);")
|
| 3072 |
|
|
|
| 3073 |
|
|
|
| 3074 |
|
|
;
|
| 3075 |
|
|
; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
|
| 3076 |
|
|
;
|
| 3077 |
|
|
|
| 3078 |
|
|
(define_expand "fixuns_trunc2"
|
| 3079 |
|
|
[(set (match_operand:GPR 0 "register_operand" "")
|
| 3080 |
|
|
(unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
|
| 3081 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3082 |
|
|
{
|
| 3083 |
|
|
rtx label1 = gen_label_rtx ();
|
| 3084 |
|
|
rtx label2 = gen_label_rtx ();
|
| 3085 |
|
|
rtx temp = gen_reg_rtx (mode);
|
| 3086 |
|
|
REAL_VALUE_TYPE cmp, sub;
|
| 3087 |
|
|
|
| 3088 |
|
|
operands[1] = force_reg (mode, operands[1]);
|
| 3089 |
|
|
real_2expN (&cmp, GET_MODE_BITSIZE(mode) - 1);
|
| 3090 |
|
|
real_2expN (&sub, GET_MODE_BITSIZE(mode));
|
| 3091 |
|
|
|
| 3092 |
|
|
emit_insn (gen_cmp (operands[1],
|
| 3093 |
|
|
CONST_DOUBLE_FROM_REAL_VALUE (cmp, mode)));
|
| 3094 |
|
|
emit_jump_insn (gen_blt (label1));
|
| 3095 |
|
|
emit_insn (gen_sub3 (temp, operands[1],
|
| 3096 |
|
|
CONST_DOUBLE_FROM_REAL_VALUE (sub, mode)));
|
| 3097 |
|
|
emit_insn (gen_fix_trunc2_ieee (operands[0], temp,
|
| 3098 |
|
|
GEN_INT(7)));
|
| 3099 |
|
|
emit_jump (label2);
|
| 3100 |
|
|
|
| 3101 |
|
|
emit_label (label1);
|
| 3102 |
|
|
emit_insn (gen_fix_trunc2_ieee (operands[0],
|
| 3103 |
|
|
operands[1], GEN_INT(5)));
|
| 3104 |
|
|
emit_label (label2);
|
| 3105 |
|
|
DONE;
|
| 3106 |
|
|
})
|
| 3107 |
|
|
|
| 3108 |
|
|
(define_expand "fix_truncdi2"
|
| 3109 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 3110 |
|
|
(fix:DI (match_operand:DSF 1 "nonimmediate_operand" "")))]
|
| 3111 |
|
|
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3112 |
|
|
{
|
| 3113 |
|
|
operands[1] = force_reg (mode, operands[1]);
|
| 3114 |
|
|
emit_insn (gen_fix_truncdi2_ieee (operands[0], operands[1],
|
| 3115 |
|
|
GEN_INT(5)));
|
| 3116 |
|
|
DONE;
|
| 3117 |
|
|
})
|
| 3118 |
|
|
|
| 3119 |
|
|
; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
|
| 3120 |
|
|
(define_insn "fix_trunc2_ieee"
|
| 3121 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 3122 |
|
|
(fix:GPR (match_operand:FPR 1 "register_operand" "f")))
|
| 3123 |
|
|
(unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
|
| 3124 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3125 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3126 |
|
|
"cbr\t%0,%h2,%1"
|
| 3127 |
|
|
[(set_attr "op_type" "RRE")
|
| 3128 |
|
|
(set_attr "type" "ftoi")])
|
| 3129 |
|
|
|
| 3130 |
|
|
;
|
| 3131 |
|
|
; fix_trunctf(si|di)2 instruction pattern(s).
|
| 3132 |
|
|
;
|
| 3133 |
|
|
|
| 3134 |
|
|
(define_expand "fix_trunctf2"
|
| 3135 |
|
|
[(parallel [(set (match_operand:GPR 0 "register_operand" "")
|
| 3136 |
|
|
(fix:GPR (match_operand:TF 1 "register_operand" "")))
|
| 3137 |
|
|
(unspec:GPR [(const_int 5)] UNSPEC_ROUND)
|
| 3138 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3139 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3140 |
|
|
"")
|
| 3141 |
|
|
|
| 3142 |
|
|
;
|
| 3143 |
|
|
; fix_truncdfsi2 instruction pattern(s).
|
| 3144 |
|
|
;
|
| 3145 |
|
|
|
| 3146 |
|
|
(define_expand "fix_truncdfsi2"
|
| 3147 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 3148 |
|
|
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
|
| 3149 |
|
|
"TARGET_HARD_FLOAT"
|
| 3150 |
|
|
{
|
| 3151 |
|
|
if (TARGET_IBM_FLOAT)
|
| 3152 |
|
|
{
|
| 3153 |
|
|
/* This is the algorithm from POP chapter A.5.7.2. */
|
| 3154 |
|
|
|
| 3155 |
|
|
rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
|
| 3156 |
|
|
rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
|
| 3157 |
|
|
rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
|
| 3158 |
|
|
|
| 3159 |
|
|
operands[1] = force_reg (DFmode, operands[1]);
|
| 3160 |
|
|
emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
|
| 3161 |
|
|
two31r, two32, temp));
|
| 3162 |
|
|
}
|
| 3163 |
|
|
else
|
| 3164 |
|
|
{
|
| 3165 |
|
|
operands[1] = force_reg (DFmode, operands[1]);
|
| 3166 |
|
|
emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
|
| 3167 |
|
|
}
|
| 3168 |
|
|
|
| 3169 |
|
|
DONE;
|
| 3170 |
|
|
})
|
| 3171 |
|
|
|
| 3172 |
|
|
(define_insn "fix_truncdfsi2_ibm"
|
| 3173 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 3174 |
|
|
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
|
| 3175 |
|
|
(use (match_operand:DI 2 "immediate_operand" "m"))
|
| 3176 |
|
|
(use (match_operand:DI 3 "immediate_operand" "m"))
|
| 3177 |
|
|
(use (match_operand:BLK 4 "memory_operand" "m"))
|
| 3178 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3179 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3180 |
|
|
{
|
| 3181 |
|
|
output_asm_insn ("sd\t%1,%2", operands);
|
| 3182 |
|
|
output_asm_insn ("aw\t%1,%3", operands);
|
| 3183 |
|
|
output_asm_insn ("std\t%1,%4", operands);
|
| 3184 |
|
|
output_asm_insn ("xi\t%N4,128", operands);
|
| 3185 |
|
|
return "l\t%0,%N4";
|
| 3186 |
|
|
}
|
| 3187 |
|
|
[(set_attr "length" "20")])
|
| 3188 |
|
|
|
| 3189 |
|
|
;
|
| 3190 |
|
|
; fix_truncsfsi2 instruction pattern(s).
|
| 3191 |
|
|
;
|
| 3192 |
|
|
|
| 3193 |
|
|
(define_expand "fix_truncsfsi2"
|
| 3194 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 3195 |
|
|
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
|
| 3196 |
|
|
"TARGET_HARD_FLOAT"
|
| 3197 |
|
|
{
|
| 3198 |
|
|
if (TARGET_IBM_FLOAT)
|
| 3199 |
|
|
{
|
| 3200 |
|
|
/* Convert to DFmode and then use the POP algorithm. */
|
| 3201 |
|
|
rtx temp = gen_reg_rtx (DFmode);
|
| 3202 |
|
|
emit_insn (gen_extendsfdf2 (temp, operands[1]));
|
| 3203 |
|
|
emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
|
| 3204 |
|
|
}
|
| 3205 |
|
|
else
|
| 3206 |
|
|
{
|
| 3207 |
|
|
operands[1] = force_reg (SFmode, operands[1]);
|
| 3208 |
|
|
emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
|
| 3209 |
|
|
}
|
| 3210 |
|
|
|
| 3211 |
|
|
DONE;
|
| 3212 |
|
|
})
|
| 3213 |
|
|
|
| 3214 |
|
|
;
|
| 3215 |
|
|
; float(si|di)(tf|df|sf)2 instruction pattern(s).
|
| 3216 |
|
|
;
|
| 3217 |
|
|
|
| 3218 |
|
|
; cxgbr, cdgbr, cegbr
|
| 3219 |
|
|
(define_insn "floatdi2"
|
| 3220 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 3221 |
|
|
(float:FPR (match_operand:DI 1 "register_operand" "d")))]
|
| 3222 |
|
|
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3223 |
|
|
"cgbr\t%0,%1"
|
| 3224 |
|
|
[(set_attr "op_type" "RRE")
|
| 3225 |
|
|
(set_attr "type" "itof" )])
|
| 3226 |
|
|
|
| 3227 |
|
|
; cxfbr, cdfbr, cefbr
|
| 3228 |
|
|
(define_insn "floatsi2_ieee"
|
| 3229 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 3230 |
|
|
(float:FPR (match_operand:SI 1 "register_operand" "d")))]
|
| 3231 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3232 |
|
|
"cfbr\t%0,%1"
|
| 3233 |
|
|
[(set_attr "op_type" "RRE")
|
| 3234 |
|
|
(set_attr "type" "itof" )])
|
| 3235 |
|
|
|
| 3236 |
|
|
|
| 3237 |
|
|
;
|
| 3238 |
|
|
; floatsi(tf|df)2 instruction pattern(s).
|
| 3239 |
|
|
;
|
| 3240 |
|
|
|
| 3241 |
|
|
(define_expand "floatsitf2"
|
| 3242 |
|
|
[(set (match_operand:TF 0 "register_operand" "")
|
| 3243 |
|
|
(float:TF (match_operand:SI 1 "register_operand" "")))]
|
| 3244 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3245 |
|
|
"")
|
| 3246 |
|
|
|
| 3247 |
|
|
(define_expand "floatsidf2"
|
| 3248 |
|
|
[(set (match_operand:DF 0 "register_operand" "")
|
| 3249 |
|
|
(float:DF (match_operand:SI 1 "register_operand" "")))]
|
| 3250 |
|
|
"TARGET_HARD_FLOAT"
|
| 3251 |
|
|
{
|
| 3252 |
|
|
if (TARGET_IBM_FLOAT)
|
| 3253 |
|
|
{
|
| 3254 |
|
|
/* This is the algorithm from POP chapter A.5.7.1. */
|
| 3255 |
|
|
|
| 3256 |
|
|
rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
|
| 3257 |
|
|
rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
|
| 3258 |
|
|
|
| 3259 |
|
|
emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
|
| 3260 |
|
|
DONE;
|
| 3261 |
|
|
}
|
| 3262 |
|
|
})
|
| 3263 |
|
|
|
| 3264 |
|
|
(define_insn "floatsidf2_ibm"
|
| 3265 |
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
| 3266 |
|
|
(float:DF (match_operand:SI 1 "register_operand" "d")))
|
| 3267 |
|
|
(use (match_operand:DI 2 "immediate_operand" "m"))
|
| 3268 |
|
|
(use (match_operand:BLK 3 "memory_operand" "m"))
|
| 3269 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3270 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3271 |
|
|
{
|
| 3272 |
|
|
output_asm_insn ("st\t%1,%N3", operands);
|
| 3273 |
|
|
output_asm_insn ("xi\t%N3,128", operands);
|
| 3274 |
|
|
output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
|
| 3275 |
|
|
output_asm_insn ("ld\t%0,%3", operands);
|
| 3276 |
|
|
return "sd\t%0,%2";
|
| 3277 |
|
|
}
|
| 3278 |
|
|
[(set_attr "length" "20")])
|
| 3279 |
|
|
|
| 3280 |
|
|
;
|
| 3281 |
|
|
; floatsisf2 instruction pattern(s).
|
| 3282 |
|
|
;
|
| 3283 |
|
|
|
| 3284 |
|
|
(define_expand "floatsisf2"
|
| 3285 |
|
|
[(set (match_operand:SF 0 "register_operand" "")
|
| 3286 |
|
|
(float:SF (match_operand:SI 1 "register_operand" "")))]
|
| 3287 |
|
|
"TARGET_HARD_FLOAT"
|
| 3288 |
|
|
{
|
| 3289 |
|
|
if (TARGET_IBM_FLOAT)
|
| 3290 |
|
|
{
|
| 3291 |
|
|
/* Use the POP algorithm to convert to DFmode and then truncate. */
|
| 3292 |
|
|
rtx temp = gen_reg_rtx (DFmode);
|
| 3293 |
|
|
emit_insn (gen_floatsidf2 (temp, operands[1]));
|
| 3294 |
|
|
emit_insn (gen_truncdfsf2 (operands[0], temp));
|
| 3295 |
|
|
DONE;
|
| 3296 |
|
|
}
|
| 3297 |
|
|
})
|
| 3298 |
|
|
|
| 3299 |
|
|
;
|
| 3300 |
|
|
; truncdfsf2 instruction pattern(s).
|
| 3301 |
|
|
;
|
| 3302 |
|
|
|
| 3303 |
|
|
(define_expand "truncdfsf2"
|
| 3304 |
|
|
[(set (match_operand:SF 0 "register_operand" "")
|
| 3305 |
|
|
(float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
|
| 3306 |
|
|
"TARGET_HARD_FLOAT"
|
| 3307 |
|
|
"")
|
| 3308 |
|
|
|
| 3309 |
|
|
(define_insn "truncdfsf2_ieee"
|
| 3310 |
|
|
[(set (match_operand:SF 0 "register_operand" "=f")
|
| 3311 |
|
|
(float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
|
| 3312 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3313 |
|
|
"ledbr\t%0,%1"
|
| 3314 |
|
|
[(set_attr "op_type" "RRE")
|
| 3315 |
|
|
(set_attr "type" "ftruncdf")])
|
| 3316 |
|
|
|
| 3317 |
|
|
(define_insn "truncdfsf2_ibm"
|
| 3318 |
|
|
[(set (match_operand:SF 0 "register_operand" "=f,f")
|
| 3319 |
|
|
(float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
|
| 3320 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3321 |
|
|
"@
|
| 3322 |
|
|
ler\t%0,%1
|
| 3323 |
|
|
le\t%0,%1"
|
| 3324 |
|
|
[(set_attr "op_type" "RR,RX")
|
| 3325 |
|
|
(set_attr "type" "floadsf")])
|
| 3326 |
|
|
|
| 3327 |
|
|
;
|
| 3328 |
|
|
; trunctfdf2 instruction pattern(s).
|
| 3329 |
|
|
;
|
| 3330 |
|
|
|
| 3331 |
|
|
(define_expand "trunctfdf2"
|
| 3332 |
|
|
[(parallel
|
| 3333 |
|
|
[(set (match_operand:DF 0 "register_operand" "")
|
| 3334 |
|
|
(float_truncate:DF (match_operand:TF 1 "register_operand" "")))
|
| 3335 |
|
|
(clobber (match_scratch:TF 2 "=f"))])]
|
| 3336 |
|
|
"TARGET_HARD_FLOAT"
|
| 3337 |
|
|
"")
|
| 3338 |
|
|
|
| 3339 |
|
|
(define_insn "*trunctfdf2_ieee"
|
| 3340 |
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
| 3341 |
|
|
(float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
|
| 3342 |
|
|
(clobber (match_scratch:TF 2 "=f"))]
|
| 3343 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3344 |
|
|
"ldxbr\t%2,%1\;ldr\t%0,%2"
|
| 3345 |
|
|
[(set_attr "length" "6")
|
| 3346 |
|
|
(set_attr "type" "ftrunctf")])
|
| 3347 |
|
|
|
| 3348 |
|
|
(define_insn "*trunctfdf2_ibm"
|
| 3349 |
|
|
[(set (match_operand:DF 0 "register_operand" "=f")
|
| 3350 |
|
|
(float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
|
| 3351 |
|
|
(clobber (match_scratch:TF 2 "=f"))]
|
| 3352 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3353 |
|
|
"ldxr\t%2,%1\;ldr\t%0,%2"
|
| 3354 |
|
|
[(set_attr "length" "4")
|
| 3355 |
|
|
(set_attr "type" "ftrunctf")])
|
| 3356 |
|
|
|
| 3357 |
|
|
;
|
| 3358 |
|
|
; trunctfsf2 instruction pattern(s).
|
| 3359 |
|
|
;
|
| 3360 |
|
|
|
| 3361 |
|
|
(define_expand "trunctfsf2"
|
| 3362 |
|
|
[(parallel
|
| 3363 |
|
|
[(set (match_operand:SF 0 "register_operand" "=f")
|
| 3364 |
|
|
(float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
|
| 3365 |
|
|
(clobber (match_scratch:TF 2 "=f"))])]
|
| 3366 |
|
|
"TARGET_HARD_FLOAT"
|
| 3367 |
|
|
"")
|
| 3368 |
|
|
|
| 3369 |
|
|
(define_insn "*trunctfsf2_ieee"
|
| 3370 |
|
|
[(set (match_operand:SF 0 "register_operand" "=f")
|
| 3371 |
|
|
(float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
|
| 3372 |
|
|
(clobber (match_scratch:TF 2 "=f"))]
|
| 3373 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3374 |
|
|
"lexbr\t%2,%1\;ler\t%0,%2"
|
| 3375 |
|
|
[(set_attr "length" "6")
|
| 3376 |
|
|
(set_attr "type" "ftrunctf")])
|
| 3377 |
|
|
|
| 3378 |
|
|
(define_insn "*trunctfsf2_ibm"
|
| 3379 |
|
|
[(set (match_operand:SF 0 "register_operand" "=f")
|
| 3380 |
|
|
(float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
|
| 3381 |
|
|
(clobber (match_scratch:TF 2 "=f"))]
|
| 3382 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3383 |
|
|
"lexr\t%2,%1\;ler\t%0,%2"
|
| 3384 |
|
|
[(set_attr "length" "6")
|
| 3385 |
|
|
(set_attr "type" "ftrunctf")])
|
| 3386 |
|
|
|
| 3387 |
|
|
;
|
| 3388 |
|
|
; extendsfdf2 instruction pattern(s).
|
| 3389 |
|
|
;
|
| 3390 |
|
|
|
| 3391 |
|
|
(define_expand "extendsfdf2"
|
| 3392 |
|
|
[(set (match_operand:DF 0 "register_operand" "")
|
| 3393 |
|
|
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
|
| 3394 |
|
|
"TARGET_HARD_FLOAT"
|
| 3395 |
|
|
{
|
| 3396 |
|
|
if (TARGET_IBM_FLOAT)
|
| 3397 |
|
|
{
|
| 3398 |
|
|
emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
|
| 3399 |
|
|
DONE;
|
| 3400 |
|
|
}
|
| 3401 |
|
|
})
|
| 3402 |
|
|
|
| 3403 |
|
|
(define_insn "extendsfdf2_ieee"
|
| 3404 |
|
|
[(set (match_operand:DF 0 "register_operand" "=f,f")
|
| 3405 |
|
|
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
|
| 3406 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3407 |
|
|
"@
|
| 3408 |
|
|
ldebr\t%0,%1
|
| 3409 |
|
|
ldeb\t%0,%1"
|
| 3410 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 3411 |
|
|
(set_attr "type" "fsimpsf, floadsf")])
|
| 3412 |
|
|
|
| 3413 |
|
|
(define_insn "extendsfdf2_ibm"
|
| 3414 |
|
|
[(set (match_operand:DF 0 "register_operand" "=f,f")
|
| 3415 |
|
|
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
|
| 3416 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3417 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3418 |
|
|
"@
|
| 3419 |
|
|
sdr\t%0,%0\;ler\t%0,%1
|
| 3420 |
|
|
sdr\t%0,%0\;le\t%0,%1"
|
| 3421 |
|
|
[(set_attr "length" "4,6")
|
| 3422 |
|
|
(set_attr "type" "floadsf")])
|
| 3423 |
|
|
|
| 3424 |
|
|
;
|
| 3425 |
|
|
; extenddftf2 instruction pattern(s).
|
| 3426 |
|
|
;
|
| 3427 |
|
|
|
| 3428 |
|
|
(define_expand "extenddftf2"
|
| 3429 |
|
|
[(set (match_operand:TF 0 "register_operand" "")
|
| 3430 |
|
|
(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
|
| 3431 |
|
|
"TARGET_HARD_FLOAT"
|
| 3432 |
|
|
"")
|
| 3433 |
|
|
|
| 3434 |
|
|
(define_insn "*extenddftf2_ieee"
|
| 3435 |
|
|
[(set (match_operand:TF 0 "register_operand" "=f,f")
|
| 3436 |
|
|
(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
|
| 3437 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3438 |
|
|
"@
|
| 3439 |
|
|
lxdbr\t%0,%1
|
| 3440 |
|
|
lxdb\t%0,%1"
|
| 3441 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 3442 |
|
|
(set_attr "type" "fsimptf, floadtf")])
|
| 3443 |
|
|
|
| 3444 |
|
|
(define_insn "*extenddftf2_ibm"
|
| 3445 |
|
|
[(set (match_operand:TF 0 "register_operand" "=f,f")
|
| 3446 |
|
|
(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
|
| 3447 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3448 |
|
|
"@
|
| 3449 |
|
|
lxdr\t%0,%1
|
| 3450 |
|
|
lxd\t%0,%1"
|
| 3451 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 3452 |
|
|
(set_attr "type" "fsimptf, floadtf")])
|
| 3453 |
|
|
|
| 3454 |
|
|
;
|
| 3455 |
|
|
; extendsftf2 instruction pattern(s).
|
| 3456 |
|
|
;
|
| 3457 |
|
|
|
| 3458 |
|
|
(define_expand "extendsftf2"
|
| 3459 |
|
|
[(set (match_operand:TF 0 "register_operand" "")
|
| 3460 |
|
|
(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
|
| 3461 |
|
|
"TARGET_HARD_FLOAT"
|
| 3462 |
|
|
"")
|
| 3463 |
|
|
|
| 3464 |
|
|
(define_insn "*extendsftf2_ieee"
|
| 3465 |
|
|
[(set (match_operand:TF 0 "register_operand" "=f,f")
|
| 3466 |
|
|
(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
|
| 3467 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3468 |
|
|
"@
|
| 3469 |
|
|
lxebr\t%0,%1
|
| 3470 |
|
|
lxeb\t%0,%1"
|
| 3471 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 3472 |
|
|
(set_attr "type" "fsimptf, floadtf")])
|
| 3473 |
|
|
|
| 3474 |
|
|
(define_insn "*extendsftf2_ibm"
|
| 3475 |
|
|
[(set (match_operand:TF 0 "register_operand" "=f,f")
|
| 3476 |
|
|
(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
|
| 3477 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3478 |
|
|
"@
|
| 3479 |
|
|
lxer\t%0,%1
|
| 3480 |
|
|
lxe\t%0,%1"
|
| 3481 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 3482 |
|
|
(set_attr "type" "fsimptf, floadtf")])
|
| 3483 |
|
|
|
| 3484 |
|
|
|
| 3485 |
|
|
;;
|
| 3486 |
|
|
;; ARITHMETIC OPERATIONS
|
| 3487 |
|
|
;;
|
| 3488 |
|
|
; arithmetic operations set the ConditionCode,
|
| 3489 |
|
|
; because of unpredictable Bits in Register for Halfword and Byte
|
| 3490 |
|
|
; the ConditionCode can be set wrong in operations for Halfword and Byte
|
| 3491 |
|
|
|
| 3492 |
|
|
;;
|
| 3493 |
|
|
;;- Add instructions.
|
| 3494 |
|
|
;;
|
| 3495 |
|
|
|
| 3496 |
|
|
;
|
| 3497 |
|
|
; addti3 instruction pattern(s).
|
| 3498 |
|
|
;
|
| 3499 |
|
|
|
| 3500 |
|
|
(define_insn_and_split "addti3"
|
| 3501 |
|
|
[(set (match_operand:TI 0 "register_operand" "=&d")
|
| 3502 |
|
|
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
|
| 3503 |
|
|
(match_operand:TI 2 "general_operand" "do") ) )
|
| 3504 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3505 |
|
|
"TARGET_64BIT"
|
| 3506 |
|
|
"#"
|
| 3507 |
|
|
"&& reload_completed"
|
| 3508 |
|
|
[(parallel
|
| 3509 |
|
|
[(set (reg:CCL1 CC_REGNUM)
|
| 3510 |
|
|
(compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
|
| 3511 |
|
|
(match_dup 7)))
|
| 3512 |
|
|
(set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
|
| 3513 |
|
|
(parallel
|
| 3514 |
|
|
[(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
|
| 3515 |
|
|
(ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
|
| 3516 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3517 |
|
|
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
|
| 3518 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, TImode);
|
| 3519 |
|
|
operands[5] = operand_subword (operands[2], 0, 0, TImode);
|
| 3520 |
|
|
operands[6] = operand_subword (operands[0], 1, 0, TImode);
|
| 3521 |
|
|
operands[7] = operand_subword (operands[1], 1, 0, TImode);
|
| 3522 |
|
|
operands[8] = operand_subword (operands[2], 1, 0, TImode);")
|
| 3523 |
|
|
|
| 3524 |
|
|
;
|
| 3525 |
|
|
; adddi3 instruction pattern(s).
|
| 3526 |
|
|
;
|
| 3527 |
|
|
|
| 3528 |
|
|
(define_expand "adddi3"
|
| 3529 |
|
|
[(parallel
|
| 3530 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 3531 |
|
|
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
|
| 3532 |
|
|
(match_operand:DI 2 "general_operand" "")))
|
| 3533 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3534 |
|
|
""
|
| 3535 |
|
|
"")
|
| 3536 |
|
|
|
| 3537 |
|
|
(define_insn "*adddi3_sign"
|
| 3538 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 3539 |
|
|
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
|
| 3540 |
|
|
(match_operand:DI 1 "register_operand" "0,0")))
|
| 3541 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3542 |
|
|
"TARGET_64BIT"
|
| 3543 |
|
|
"@
|
| 3544 |
|
|
agfr\t%0,%2
|
| 3545 |
|
|
agf\t%0,%2"
|
| 3546 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3547 |
|
|
|
| 3548 |
|
|
(define_insn "*adddi3_zero_cc"
|
| 3549 |
|
|
[(set (reg CC_REGNUM)
|
| 3550 |
|
|
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
|
| 3551 |
|
|
(match_operand:DI 1 "register_operand" "0,0"))
|
| 3552 |
|
|
(const_int 0)))
|
| 3553 |
|
|
(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 3554 |
|
|
(plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
|
| 3555 |
|
|
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
|
| 3556 |
|
|
"@
|
| 3557 |
|
|
algfr\t%0,%2
|
| 3558 |
|
|
algf\t%0,%2"
|
| 3559 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3560 |
|
|
|
| 3561 |
|
|
(define_insn "*adddi3_zero_cconly"
|
| 3562 |
|
|
[(set (reg CC_REGNUM)
|
| 3563 |
|
|
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
|
| 3564 |
|
|
(match_operand:DI 1 "register_operand" "0,0"))
|
| 3565 |
|
|
(const_int 0)))
|
| 3566 |
|
|
(clobber (match_scratch:DI 0 "=d,d"))]
|
| 3567 |
|
|
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
|
| 3568 |
|
|
"@
|
| 3569 |
|
|
algfr\t%0,%2
|
| 3570 |
|
|
algf\t%0,%2"
|
| 3571 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3572 |
|
|
|
| 3573 |
|
|
(define_insn "*adddi3_zero"
|
| 3574 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 3575 |
|
|
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
|
| 3576 |
|
|
(match_operand:DI 1 "register_operand" "0,0")))
|
| 3577 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3578 |
|
|
"TARGET_64BIT"
|
| 3579 |
|
|
"@
|
| 3580 |
|
|
algfr\t%0,%2
|
| 3581 |
|
|
algf\t%0,%2"
|
| 3582 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3583 |
|
|
|
| 3584 |
|
|
(define_insn_and_split "*adddi3_31z"
|
| 3585 |
|
|
[(set (match_operand:DI 0 "register_operand" "=&d")
|
| 3586 |
|
|
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
|
| 3587 |
|
|
(match_operand:DI 2 "general_operand" "do") ) )
|
| 3588 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3589 |
|
|
"!TARGET_64BIT && TARGET_CPU_ZARCH"
|
| 3590 |
|
|
"#"
|
| 3591 |
|
|
"&& reload_completed"
|
| 3592 |
|
|
[(parallel
|
| 3593 |
|
|
[(set (reg:CCL1 CC_REGNUM)
|
| 3594 |
|
|
(compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
|
| 3595 |
|
|
(match_dup 7)))
|
| 3596 |
|
|
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
|
| 3597 |
|
|
(parallel
|
| 3598 |
|
|
[(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
|
| 3599 |
|
|
(ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
|
| 3600 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3601 |
|
|
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
|
| 3602 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, DImode);
|
| 3603 |
|
|
operands[5] = operand_subword (operands[2], 0, 0, DImode);
|
| 3604 |
|
|
operands[6] = operand_subword (operands[0], 1, 0, DImode);
|
| 3605 |
|
|
operands[7] = operand_subword (operands[1], 1, 0, DImode);
|
| 3606 |
|
|
operands[8] = operand_subword (operands[2], 1, 0, DImode);")
|
| 3607 |
|
|
|
| 3608 |
|
|
(define_insn_and_split "*adddi3_31"
|
| 3609 |
|
|
[(set (match_operand:DI 0 "register_operand" "=&d")
|
| 3610 |
|
|
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
|
| 3611 |
|
|
(match_operand:DI 2 "general_operand" "do") ) )
|
| 3612 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3613 |
|
|
"!TARGET_CPU_ZARCH"
|
| 3614 |
|
|
"#"
|
| 3615 |
|
|
"&& reload_completed"
|
| 3616 |
|
|
[(parallel
|
| 3617 |
|
|
[(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
|
| 3618 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 3619 |
|
|
(parallel
|
| 3620 |
|
|
[(set (reg:CCL1 CC_REGNUM)
|
| 3621 |
|
|
(compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
|
| 3622 |
|
|
(match_dup 7)))
|
| 3623 |
|
|
(set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
|
| 3624 |
|
|
(set (pc)
|
| 3625 |
|
|
(if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
|
| 3626 |
|
|
(pc)
|
| 3627 |
|
|
(label_ref (match_dup 9))))
|
| 3628 |
|
|
(parallel
|
| 3629 |
|
|
[(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
|
| 3630 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 3631 |
|
|
(match_dup 9)]
|
| 3632 |
|
|
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
|
| 3633 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, DImode);
|
| 3634 |
|
|
operands[5] = operand_subword (operands[2], 0, 0, DImode);
|
| 3635 |
|
|
operands[6] = operand_subword (operands[0], 1, 0, DImode);
|
| 3636 |
|
|
operands[7] = operand_subword (operands[1], 1, 0, DImode);
|
| 3637 |
|
|
operands[8] = operand_subword (operands[2], 1, 0, DImode);
|
| 3638 |
|
|
operands[9] = gen_label_rtx ();")
|
| 3639 |
|
|
|
| 3640 |
|
|
;
|
| 3641 |
|
|
; addsi3 instruction pattern(s).
|
| 3642 |
|
|
;
|
| 3643 |
|
|
|
| 3644 |
|
|
(define_expand "addsi3"
|
| 3645 |
|
|
[(parallel
|
| 3646 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 3647 |
|
|
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
|
| 3648 |
|
|
(match_operand:SI 2 "general_operand" "")))
|
| 3649 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3650 |
|
|
""
|
| 3651 |
|
|
"")
|
| 3652 |
|
|
|
| 3653 |
|
|
(define_insn "*addsi3_sign"
|
| 3654 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 3655 |
|
|
(plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
|
| 3656 |
|
|
(match_operand:SI 1 "register_operand" "0,0")))
|
| 3657 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3658 |
|
|
""
|
| 3659 |
|
|
"@
|
| 3660 |
|
|
ah\t%0,%2
|
| 3661 |
|
|
ahy\t%0,%2"
|
| 3662 |
|
|
[(set_attr "op_type" "RX,RXY")])
|
| 3663 |
|
|
|
| 3664 |
|
|
;
|
| 3665 |
|
|
; add(di|si)3 instruction pattern(s).
|
| 3666 |
|
|
;
|
| 3667 |
|
|
|
| 3668 |
|
|
; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag
|
| 3669 |
|
|
(define_insn "*add3"
|
| 3670 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
|
| 3671 |
|
|
(plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
|
| 3672 |
|
|
(match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
|
| 3673 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3674 |
|
|
""
|
| 3675 |
|
|
"@
|
| 3676 |
|
|
ar\t%0,%2
|
| 3677 |
|
|
ahi\t%0,%h2
|
| 3678 |
|
|
alfi\t%0,%2
|
| 3679 |
|
|
slfi\t%0,%n2
|
| 3680 |
|
|
a\t%0,%2
|
| 3681 |
|
|
a\t%0,%2"
|
| 3682 |
|
|
[(set_attr "op_type" "RR,RI,RIL,RIL,RX,RXY")])
|
| 3683 |
|
|
|
| 3684 |
|
|
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
|
| 3685 |
|
|
(define_insn "*add3_carry1_cc"
|
| 3686 |
|
|
[(set (reg CC_REGNUM)
|
| 3687 |
|
|
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
|
| 3688 |
|
|
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
|
| 3689 |
|
|
(match_dup 1)))
|
| 3690 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
|
| 3691 |
|
|
(plus:GPR (match_dup 1) (match_dup 2)))]
|
| 3692 |
|
|
"s390_match_ccmode (insn, CCL1mode)"
|
| 3693 |
|
|
"@
|
| 3694 |
|
|
alr\t%0,%2
|
| 3695 |
|
|
alfi\t%0,%2
|
| 3696 |
|
|
slfi\t%0,%n2
|
| 3697 |
|
|
al\t%0,%2
|
| 3698 |
|
|
al\t%0,%2"
|
| 3699 |
|
|
[(set_attr "op_type" "RR,RIL,RIL,RX,RXY")])
|
| 3700 |
|
|
|
| 3701 |
|
|
; alr, al, aly, algr, alg
|
| 3702 |
|
|
(define_insn "*add3_carry1_cconly"
|
| 3703 |
|
|
[(set (reg CC_REGNUM)
|
| 3704 |
|
|
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
|
| 3705 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T"))
|
| 3706 |
|
|
(match_dup 1)))
|
| 3707 |
|
|
(clobber (match_scratch:GPR 0 "=d,d,d"))]
|
| 3708 |
|
|
"s390_match_ccmode (insn, CCL1mode)"
|
| 3709 |
|
|
"@
|
| 3710 |
|
|
alr\t%0,%2
|
| 3711 |
|
|
al\t%0,%2
|
| 3712 |
|
|
al\t%0,%2"
|
| 3713 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 3714 |
|
|
|
| 3715 |
|
|
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
|
| 3716 |
|
|
(define_insn "*add3_carry2_cc"
|
| 3717 |
|
|
[(set (reg CC_REGNUM)
|
| 3718 |
|
|
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
|
| 3719 |
|
|
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
|
| 3720 |
|
|
(match_dup 2)))
|
| 3721 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
|
| 3722 |
|
|
(plus:GPR (match_dup 1) (match_dup 2)))]
|
| 3723 |
|
|
"s390_match_ccmode (insn, CCL1mode)"
|
| 3724 |
|
|
"@
|
| 3725 |
|
|
alr\t%0,%2
|
| 3726 |
|
|
alfi\t%0,%2
|
| 3727 |
|
|
slfi\t%0,%n2
|
| 3728 |
|
|
al\t%0,%2
|
| 3729 |
|
|
al\t%0,%2"
|
| 3730 |
|
|
[(set_attr "op_type" "RR,RIL,RIL,RX,RXY")])
|
| 3731 |
|
|
|
| 3732 |
|
|
; alr, al, aly, algr, alg
|
| 3733 |
|
|
(define_insn "*add3_carry2_cconly"
|
| 3734 |
|
|
[(set (reg CC_REGNUM)
|
| 3735 |
|
|
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
|
| 3736 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T"))
|
| 3737 |
|
|
(match_dup 2)))
|
| 3738 |
|
|
(clobber (match_scratch:GPR 0 "=d,d,d"))]
|
| 3739 |
|
|
"s390_match_ccmode (insn, CCL1mode)"
|
| 3740 |
|
|
"@
|
| 3741 |
|
|
alr\t%0,%2
|
| 3742 |
|
|
al\t%0,%2
|
| 3743 |
|
|
al\t%0,%2"
|
| 3744 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 3745 |
|
|
|
| 3746 |
|
|
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
|
| 3747 |
|
|
(define_insn "*add3_cc"
|
| 3748 |
|
|
[(set (reg CC_REGNUM)
|
| 3749 |
|
|
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
|
| 3750 |
|
|
(match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
|
| 3751 |
|
|
(const_int 0)))
|
| 3752 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
|
| 3753 |
|
|
(plus:GPR (match_dup 1) (match_dup 2)))]
|
| 3754 |
|
|
"s390_match_ccmode (insn, CCLmode)"
|
| 3755 |
|
|
"@
|
| 3756 |
|
|
alr\t%0,%2
|
| 3757 |
|
|
alfi\t%0,%2
|
| 3758 |
|
|
slfi\t%0,%n2
|
| 3759 |
|
|
al\t%0,%2
|
| 3760 |
|
|
al\t%0,%2"
|
| 3761 |
|
|
[(set_attr "op_type" "RR,RIL,RIL,RX,RXY")])
|
| 3762 |
|
|
|
| 3763 |
|
|
; alr, al, aly, algr, alg
|
| 3764 |
|
|
(define_insn "*add3_cconly"
|
| 3765 |
|
|
[(set (reg CC_REGNUM)
|
| 3766 |
|
|
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
|
| 3767 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T"))
|
| 3768 |
|
|
(const_int 0)))
|
| 3769 |
|
|
(clobber (match_scratch:GPR 0 "=d,d,d"))]
|
| 3770 |
|
|
"s390_match_ccmode (insn, CCLmode)"
|
| 3771 |
|
|
"@
|
| 3772 |
|
|
alr\t%0,%2
|
| 3773 |
|
|
al\t%0,%2
|
| 3774 |
|
|
al\t%0,%2"
|
| 3775 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 3776 |
|
|
|
| 3777 |
|
|
; alr, al, aly, algr, alg
|
| 3778 |
|
|
(define_insn "*add3_cconly2"
|
| 3779 |
|
|
[(set (reg CC_REGNUM)
|
| 3780 |
|
|
(compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
|
| 3781 |
|
|
(neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
|
| 3782 |
|
|
(clobber (match_scratch:GPR 0 "=d,d,d"))]
|
| 3783 |
|
|
"s390_match_ccmode(insn, CCLmode)"
|
| 3784 |
|
|
"@
|
| 3785 |
|
|
alr\t%0,%2
|
| 3786 |
|
|
al\t%0,%2
|
| 3787 |
|
|
al\t%0,%2"
|
| 3788 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 3789 |
|
|
|
| 3790 |
|
|
; ahi, afi, aghi, agfi
|
| 3791 |
|
|
(define_insn "*add3_imm_cc"
|
| 3792 |
|
|
[(set (reg CC_REGNUM)
|
| 3793 |
|
|
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
|
| 3794 |
|
|
(match_operand:GPR 2 "const_int_operand" "K,Os"))
|
| 3795 |
|
|
(const_int 0)))
|
| 3796 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d")
|
| 3797 |
|
|
(plus:GPR (match_dup 1) (match_dup 2)))]
|
| 3798 |
|
|
"s390_match_ccmode (insn, CCAmode)
|
| 3799 |
|
|
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
|
| 3800 |
|
|
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
|
| 3801 |
|
|
&& INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(mode) - 1))"
|
| 3802 |
|
|
"@
|
| 3803 |
|
|
ahi\t%0,%h2
|
| 3804 |
|
|
afi\t%0,%2"
|
| 3805 |
|
|
[(set_attr "op_type" "RI,RIL")])
|
| 3806 |
|
|
|
| 3807 |
|
|
;
|
| 3808 |
|
|
; add(df|sf)3 instruction pattern(s).
|
| 3809 |
|
|
;
|
| 3810 |
|
|
|
| 3811 |
|
|
(define_expand "add3"
|
| 3812 |
|
|
[(parallel
|
| 3813 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 3814 |
|
|
(plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
|
| 3815 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))
|
| 3816 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3817 |
|
|
"TARGET_HARD_FLOAT"
|
| 3818 |
|
|
"")
|
| 3819 |
|
|
|
| 3820 |
|
|
; axbr, adbr, aebr, axb, adb, aeb
|
| 3821 |
|
|
(define_insn "*add3"
|
| 3822 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 3823 |
|
|
(plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
|
| 3824 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))
|
| 3825 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3826 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3827 |
|
|
"@
|
| 3828 |
|
|
abr\t%0,%2
|
| 3829 |
|
|
ab\t%0,%2"
|
| 3830 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 3831 |
|
|
(set_attr "type" "fsimp")])
|
| 3832 |
|
|
|
| 3833 |
|
|
; axbr, adbr, aebr, axb, adb, aeb
|
| 3834 |
|
|
(define_insn "*add3_cc"
|
| 3835 |
|
|
[(set (reg CC_REGNUM)
|
| 3836 |
|
|
(compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
|
| 3837 |
|
|
(match_operand:FPR 2 "general_operand" "f,"))
|
| 3838 |
|
|
(match_operand:FPR 3 "const0_operand" "")))
|
| 3839 |
|
|
(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 3840 |
|
|
(plus:FPR (match_dup 1) (match_dup 2)))]
|
| 3841 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3842 |
|
|
"@
|
| 3843 |
|
|
abr\t%0,%2
|
| 3844 |
|
|
ab\t%0,%2"
|
| 3845 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 3846 |
|
|
(set_attr "type" "fsimp")])
|
| 3847 |
|
|
|
| 3848 |
|
|
; axbr, adbr, aebr, axb, adb, aeb
|
| 3849 |
|
|
(define_insn "*add3_cconly"
|
| 3850 |
|
|
[(set (reg CC_REGNUM)
|
| 3851 |
|
|
(compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
|
| 3852 |
|
|
(match_operand:FPR 2 "general_operand" "f,"))
|
| 3853 |
|
|
(match_operand:FPR 3 "const0_operand" "")))
|
| 3854 |
|
|
(clobber (match_scratch:FPR 0 "=f,f"))]
|
| 3855 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 3856 |
|
|
"@
|
| 3857 |
|
|
abr\t%0,%2
|
| 3858 |
|
|
ab\t%0,%2"
|
| 3859 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 3860 |
|
|
(set_attr "type" "fsimp")])
|
| 3861 |
|
|
|
| 3862 |
|
|
; axr, adr, aer, ax, ad, ae
|
| 3863 |
|
|
(define_insn "*add3_ibm"
|
| 3864 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 3865 |
|
|
(plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
|
| 3866 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))
|
| 3867 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3868 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 3869 |
|
|
"@
|
| 3870 |
|
|
ar\t%0,%2
|
| 3871 |
|
|
a\t%0,%2"
|
| 3872 |
|
|
[(set_attr "op_type" ",")
|
| 3873 |
|
|
(set_attr "type" "fsimp")])
|
| 3874 |
|
|
|
| 3875 |
|
|
|
| 3876 |
|
|
;;
|
| 3877 |
|
|
;;- Subtract instructions.
|
| 3878 |
|
|
;;
|
| 3879 |
|
|
|
| 3880 |
|
|
;
|
| 3881 |
|
|
; subti3 instruction pattern(s).
|
| 3882 |
|
|
;
|
| 3883 |
|
|
|
| 3884 |
|
|
(define_insn_and_split "subti3"
|
| 3885 |
|
|
[(set (match_operand:TI 0 "register_operand" "=&d")
|
| 3886 |
|
|
(minus:TI (match_operand:TI 1 "register_operand" "0")
|
| 3887 |
|
|
(match_operand:TI 2 "general_operand" "do") ) )
|
| 3888 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3889 |
|
|
"TARGET_64BIT"
|
| 3890 |
|
|
"#"
|
| 3891 |
|
|
"&& reload_completed"
|
| 3892 |
|
|
[(parallel
|
| 3893 |
|
|
[(set (reg:CCL2 CC_REGNUM)
|
| 3894 |
|
|
(compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
|
| 3895 |
|
|
(match_dup 7)))
|
| 3896 |
|
|
(set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
|
| 3897 |
|
|
(parallel
|
| 3898 |
|
|
[(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
|
| 3899 |
|
|
(gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
|
| 3900 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3901 |
|
|
"operands[3] = operand_subword (operands[0], 0, 0, TImode);
|
| 3902 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, TImode);
|
| 3903 |
|
|
operands[5] = operand_subword (operands[2], 0, 0, TImode);
|
| 3904 |
|
|
operands[6] = operand_subword (operands[0], 1, 0, TImode);
|
| 3905 |
|
|
operands[7] = operand_subword (operands[1], 1, 0, TImode);
|
| 3906 |
|
|
operands[8] = operand_subword (operands[2], 1, 0, TImode);")
|
| 3907 |
|
|
|
| 3908 |
|
|
;
|
| 3909 |
|
|
; subdi3 instruction pattern(s).
|
| 3910 |
|
|
;
|
| 3911 |
|
|
|
| 3912 |
|
|
(define_expand "subdi3"
|
| 3913 |
|
|
[(parallel
|
| 3914 |
|
|
[(set (match_operand:DI 0 "register_operand" "")
|
| 3915 |
|
|
(minus:DI (match_operand:DI 1 "register_operand" "")
|
| 3916 |
|
|
(match_operand:DI 2 "general_operand" "")))
|
| 3917 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3918 |
|
|
""
|
| 3919 |
|
|
"")
|
| 3920 |
|
|
|
| 3921 |
|
|
(define_insn "*subdi3_sign"
|
| 3922 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 3923 |
|
|
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
|
| 3924 |
|
|
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
|
| 3925 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3926 |
|
|
"TARGET_64BIT"
|
| 3927 |
|
|
"@
|
| 3928 |
|
|
sgfr\t%0,%2
|
| 3929 |
|
|
sgf\t%0,%2"
|
| 3930 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3931 |
|
|
|
| 3932 |
|
|
(define_insn "*subdi3_zero_cc"
|
| 3933 |
|
|
[(set (reg CC_REGNUM)
|
| 3934 |
|
|
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
|
| 3935 |
|
|
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
|
| 3936 |
|
|
(const_int 0)))
|
| 3937 |
|
|
(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 3938 |
|
|
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
|
| 3939 |
|
|
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
|
| 3940 |
|
|
"@
|
| 3941 |
|
|
slgfr\t%0,%2
|
| 3942 |
|
|
slgf\t%0,%2"
|
| 3943 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3944 |
|
|
|
| 3945 |
|
|
(define_insn "*subdi3_zero_cconly"
|
| 3946 |
|
|
[(set (reg CC_REGNUM)
|
| 3947 |
|
|
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
|
| 3948 |
|
|
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
|
| 3949 |
|
|
(const_int 0)))
|
| 3950 |
|
|
(clobber (match_scratch:DI 0 "=d,d"))]
|
| 3951 |
|
|
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
|
| 3952 |
|
|
"@
|
| 3953 |
|
|
slgfr\t%0,%2
|
| 3954 |
|
|
slgf\t%0,%2"
|
| 3955 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3956 |
|
|
|
| 3957 |
|
|
(define_insn "*subdi3_zero"
|
| 3958 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 3959 |
|
|
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
|
| 3960 |
|
|
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
|
| 3961 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3962 |
|
|
"TARGET_64BIT"
|
| 3963 |
|
|
"@
|
| 3964 |
|
|
slgfr\t%0,%2
|
| 3965 |
|
|
slgf\t%0,%2"
|
| 3966 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 3967 |
|
|
|
| 3968 |
|
|
(define_insn_and_split "*subdi3_31z"
|
| 3969 |
|
|
[(set (match_operand:DI 0 "register_operand" "=&d")
|
| 3970 |
|
|
(minus:DI (match_operand:DI 1 "register_operand" "0")
|
| 3971 |
|
|
(match_operand:DI 2 "general_operand" "do") ) )
|
| 3972 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3973 |
|
|
"!TARGET_64BIT && TARGET_CPU_ZARCH"
|
| 3974 |
|
|
"#"
|
| 3975 |
|
|
"&& reload_completed"
|
| 3976 |
|
|
[(parallel
|
| 3977 |
|
|
[(set (reg:CCL2 CC_REGNUM)
|
| 3978 |
|
|
(compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
|
| 3979 |
|
|
(match_dup 7)))
|
| 3980 |
|
|
(set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
|
| 3981 |
|
|
(parallel
|
| 3982 |
|
|
[(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
|
| 3983 |
|
|
(gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
|
| 3984 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 3985 |
|
|
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
|
| 3986 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, DImode);
|
| 3987 |
|
|
operands[5] = operand_subword (operands[2], 0, 0, DImode);
|
| 3988 |
|
|
operands[6] = operand_subword (operands[0], 1, 0, DImode);
|
| 3989 |
|
|
operands[7] = operand_subword (operands[1], 1, 0, DImode);
|
| 3990 |
|
|
operands[8] = operand_subword (operands[2], 1, 0, DImode);")
|
| 3991 |
|
|
|
| 3992 |
|
|
(define_insn_and_split "*subdi3_31"
|
| 3993 |
|
|
[(set (match_operand:DI 0 "register_operand" "=&d")
|
| 3994 |
|
|
(minus:DI (match_operand:DI 1 "register_operand" "0")
|
| 3995 |
|
|
(match_operand:DI 2 "general_operand" "do") ) )
|
| 3996 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 3997 |
|
|
"!TARGET_CPU_ZARCH"
|
| 3998 |
|
|
"#"
|
| 3999 |
|
|
"&& reload_completed"
|
| 4000 |
|
|
[(parallel
|
| 4001 |
|
|
[(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
|
| 4002 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 4003 |
|
|
(parallel
|
| 4004 |
|
|
[(set (reg:CCL2 CC_REGNUM)
|
| 4005 |
|
|
(compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
|
| 4006 |
|
|
(match_dup 7)))
|
| 4007 |
|
|
(set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
|
| 4008 |
|
|
(set (pc)
|
| 4009 |
|
|
(if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
|
| 4010 |
|
|
(pc)
|
| 4011 |
|
|
(label_ref (match_dup 9))))
|
| 4012 |
|
|
(parallel
|
| 4013 |
|
|
[(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
|
| 4014 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 4015 |
|
|
(match_dup 9)]
|
| 4016 |
|
|
"operands[3] = operand_subword (operands[0], 0, 0, DImode);
|
| 4017 |
|
|
operands[4] = operand_subword (operands[1], 0, 0, DImode);
|
| 4018 |
|
|
operands[5] = operand_subword (operands[2], 0, 0, DImode);
|
| 4019 |
|
|
operands[6] = operand_subword (operands[0], 1, 0, DImode);
|
| 4020 |
|
|
operands[7] = operand_subword (operands[1], 1, 0, DImode);
|
| 4021 |
|
|
operands[8] = operand_subword (operands[2], 1, 0, DImode);
|
| 4022 |
|
|
operands[9] = gen_label_rtx ();")
|
| 4023 |
|
|
|
| 4024 |
|
|
;
|
| 4025 |
|
|
; subsi3 instruction pattern(s).
|
| 4026 |
|
|
;
|
| 4027 |
|
|
|
| 4028 |
|
|
(define_expand "subsi3"
|
| 4029 |
|
|
[(parallel
|
| 4030 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 4031 |
|
|
(minus:SI (match_operand:SI 1 "register_operand" "")
|
| 4032 |
|
|
(match_operand:SI 2 "general_operand" "")))
|
| 4033 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 4034 |
|
|
""
|
| 4035 |
|
|
"")
|
| 4036 |
|
|
|
| 4037 |
|
|
(define_insn "*subsi3_sign"
|
| 4038 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 4039 |
|
|
(minus:SI (match_operand:SI 1 "register_operand" "0,0")
|
| 4040 |
|
|
(sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
|
| 4041 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4042 |
|
|
""
|
| 4043 |
|
|
"@
|
| 4044 |
|
|
sh\t%0,%2
|
| 4045 |
|
|
shy\t%0,%2"
|
| 4046 |
|
|
[(set_attr "op_type" "RX,RXY")])
|
| 4047 |
|
|
|
| 4048 |
|
|
;
|
| 4049 |
|
|
; sub(di|si)3 instruction pattern(s).
|
| 4050 |
|
|
;
|
| 4051 |
|
|
|
| 4052 |
|
|
; sr, s, sy, sgr, sg
|
| 4053 |
|
|
(define_insn "*sub3"
|
| 4054 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d,d,d")
|
| 4055 |
|
|
(minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
|
| 4056 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T") ) )
|
| 4057 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4058 |
|
|
""
|
| 4059 |
|
|
"@
|
| 4060 |
|
|
sr\t%0,%2
|
| 4061 |
|
|
s\t%0,%2
|
| 4062 |
|
|
s\t%0,%2"
|
| 4063 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 4064 |
|
|
|
| 4065 |
|
|
; slr, sl, sly, slgr, slg
|
| 4066 |
|
|
(define_insn "*sub3_borrow_cc"
|
| 4067 |
|
|
[(set (reg CC_REGNUM)
|
| 4068 |
|
|
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
|
| 4069 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T"))
|
| 4070 |
|
|
(match_dup 1)))
|
| 4071 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d,d")
|
| 4072 |
|
|
(minus:GPR (match_dup 1) (match_dup 2)))]
|
| 4073 |
|
|
"s390_match_ccmode (insn, CCL2mode)"
|
| 4074 |
|
|
"@
|
| 4075 |
|
|
slr\t%0,%2
|
| 4076 |
|
|
sl\t%0,%2
|
| 4077 |
|
|
sl\t%0,%2"
|
| 4078 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 4079 |
|
|
|
| 4080 |
|
|
; slr, sl, sly, slgr, slg
|
| 4081 |
|
|
(define_insn "*sub3_borrow_cconly"
|
| 4082 |
|
|
[(set (reg CC_REGNUM)
|
| 4083 |
|
|
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
|
| 4084 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T"))
|
| 4085 |
|
|
(match_dup 1)))
|
| 4086 |
|
|
(clobber (match_scratch:GPR 0 "=d,d,d"))]
|
| 4087 |
|
|
"s390_match_ccmode (insn, CCL2mode)"
|
| 4088 |
|
|
"@
|
| 4089 |
|
|
slr\t%0,%2
|
| 4090 |
|
|
sl\t%0,%2
|
| 4091 |
|
|
sl\t%0,%2"
|
| 4092 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 4093 |
|
|
|
| 4094 |
|
|
; slr, sl, sly, slgr, slg
|
| 4095 |
|
|
(define_insn "*sub3_cc"
|
| 4096 |
|
|
[(set (reg CC_REGNUM)
|
| 4097 |
|
|
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
|
| 4098 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T"))
|
| 4099 |
|
|
(const_int 0)))
|
| 4100 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d,d")
|
| 4101 |
|
|
(minus:GPR (match_dup 1) (match_dup 2)))]
|
| 4102 |
|
|
"s390_match_ccmode (insn, CCLmode)"
|
| 4103 |
|
|
"@
|
| 4104 |
|
|
slr\t%0,%2
|
| 4105 |
|
|
sl\t%0,%2
|
| 4106 |
|
|
sl\t%0,%2"
|
| 4107 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 4108 |
|
|
|
| 4109 |
|
|
; slr, sl, sly, slgr, slg
|
| 4110 |
|
|
(define_insn "*sub3_cc2"
|
| 4111 |
|
|
[(set (reg CC_REGNUM)
|
| 4112 |
|
|
(compare (match_operand:GPR 1 "register_operand" "0,0,0")
|
| 4113 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T")))
|
| 4114 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d,d")
|
| 4115 |
|
|
(minus:GPR (match_dup 1) (match_dup 2)))]
|
| 4116 |
|
|
"s390_match_ccmode (insn, CCL3mode)"
|
| 4117 |
|
|
"@
|
| 4118 |
|
|
slr\t%0,%2
|
| 4119 |
|
|
sl\t%0,%2
|
| 4120 |
|
|
sl\t%0,%2"
|
| 4121 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 4122 |
|
|
|
| 4123 |
|
|
; slr, sl, sly, slgr, slg
|
| 4124 |
|
|
(define_insn "*sub3_cconly"
|
| 4125 |
|
|
[(set (reg CC_REGNUM)
|
| 4126 |
|
|
(compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
|
| 4127 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T"))
|
| 4128 |
|
|
(const_int 0)))
|
| 4129 |
|
|
(clobber (match_scratch:GPR 0 "=d,d,d"))]
|
| 4130 |
|
|
"s390_match_ccmode (insn, CCLmode)"
|
| 4131 |
|
|
"@
|
| 4132 |
|
|
slr\t%0,%2
|
| 4133 |
|
|
sl\t%0,%2
|
| 4134 |
|
|
sl\t%0,%2"
|
| 4135 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 4136 |
|
|
|
| 4137 |
|
|
; slr, sl, sly, slgr, slg
|
| 4138 |
|
|
(define_insn "*sub3_cconly2"
|
| 4139 |
|
|
[(set (reg CC_REGNUM)
|
| 4140 |
|
|
(compare (match_operand:GPR 1 "register_operand" "0,0,0")
|
| 4141 |
|
|
(match_operand:GPR 2 "general_operand" "d,R,T")))
|
| 4142 |
|
|
(clobber (match_scratch:GPR 0 "=d,d,d"))]
|
| 4143 |
|
|
"s390_match_ccmode (insn, CCL3mode)"
|
| 4144 |
|
|
"@
|
| 4145 |
|
|
slr\t%0,%2
|
| 4146 |
|
|
sl\t%0,%2
|
| 4147 |
|
|
sl\t%0,%2"
|
| 4148 |
|
|
[(set_attr "op_type" "RR,RX,RXY")])
|
| 4149 |
|
|
|
| 4150 |
|
|
;
|
| 4151 |
|
|
; sub(df|sf)3 instruction pattern(s).
|
| 4152 |
|
|
;
|
| 4153 |
|
|
|
| 4154 |
|
|
(define_expand "sub3"
|
| 4155 |
|
|
[(parallel
|
| 4156 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4157 |
|
|
(minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
|
| 4158 |
|
|
(match_operand:FPR 2 "general_operand" "f,R")))
|
| 4159 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 4160 |
|
|
"TARGET_HARD_FLOAT"
|
| 4161 |
|
|
"")
|
| 4162 |
|
|
|
| 4163 |
|
|
; sxbr, sdbr, sebr, sxb, sdb, seb
|
| 4164 |
|
|
(define_insn "*sub3"
|
| 4165 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4166 |
|
|
(minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
|
| 4167 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))
|
| 4168 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4169 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 4170 |
|
|
"@
|
| 4171 |
|
|
sbr\t%0,%2
|
| 4172 |
|
|
sb\t%0,%2"
|
| 4173 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 4174 |
|
|
(set_attr "type" "fsimp")])
|
| 4175 |
|
|
|
| 4176 |
|
|
; sxbr, sdbr, sebr, sxb, sdb, seb
|
| 4177 |
|
|
(define_insn "*sub3_cc"
|
| 4178 |
|
|
[(set (reg CC_REGNUM)
|
| 4179 |
|
|
(compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
|
| 4180 |
|
|
(match_operand:FPR 2 "general_operand" "f,"))
|
| 4181 |
|
|
(match_operand:FPR 3 "const0_operand" "")))
|
| 4182 |
|
|
(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4183 |
|
|
(minus:FPR (match_dup 1) (match_dup 2)))]
|
| 4184 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 4185 |
|
|
"@
|
| 4186 |
|
|
sbr\t%0,%2
|
| 4187 |
|
|
sb\t%0,%2"
|
| 4188 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 4189 |
|
|
(set_attr "type" "fsimp")])
|
| 4190 |
|
|
|
| 4191 |
|
|
; sxbr, sdbr, sebr, sxb, sdb, seb
|
| 4192 |
|
|
(define_insn "*sub3_cconly"
|
| 4193 |
|
|
[(set (reg CC_REGNUM)
|
| 4194 |
|
|
(compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
|
| 4195 |
|
|
(match_operand:FPR 2 "general_operand" "f,"))
|
| 4196 |
|
|
(match_operand:FPR 3 "const0_operand" "")))
|
| 4197 |
|
|
(clobber (match_scratch:FPR 0 "=f,f"))]
|
| 4198 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 4199 |
|
|
"@
|
| 4200 |
|
|
sbr\t%0,%2
|
| 4201 |
|
|
sb\t%0,%2"
|
| 4202 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 4203 |
|
|
(set_attr "type" "fsimp")])
|
| 4204 |
|
|
|
| 4205 |
|
|
; sxr, sdr, ser, sx, sd, se
|
| 4206 |
|
|
(define_insn "*sub3_ibm"
|
| 4207 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4208 |
|
|
(minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
|
| 4209 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))
|
| 4210 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4211 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 4212 |
|
|
"@
|
| 4213 |
|
|
sr\t%0,%2
|
| 4214 |
|
|
s\t%0,%2"
|
| 4215 |
|
|
[(set_attr "op_type" ",")
|
| 4216 |
|
|
(set_attr "type" "fsimp")])
|
| 4217 |
|
|
|
| 4218 |
|
|
|
| 4219 |
|
|
;;
|
| 4220 |
|
|
;;- Conditional add/subtract instructions.
|
| 4221 |
|
|
;;
|
| 4222 |
|
|
|
| 4223 |
|
|
;
|
| 4224 |
|
|
; add(di|si)cc instruction pattern(s).
|
| 4225 |
|
|
;
|
| 4226 |
|
|
|
| 4227 |
|
|
; alcr, alc, alcgr, alcg
|
| 4228 |
|
|
(define_insn "*add3_alc_cc"
|
| 4229 |
|
|
[(set (reg CC_REGNUM)
|
| 4230 |
|
|
(compare
|
| 4231 |
|
|
(plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
|
| 4232 |
|
|
(match_operand:GPR 2 "general_operand" "d,m"))
|
| 4233 |
|
|
(match_operand:GPR 3 "s390_alc_comparison" ""))
|
| 4234 |
|
|
(const_int 0)))
|
| 4235 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d")
|
| 4236 |
|
|
(plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
| 4237 |
|
|
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
|
| 4238 |
|
|
"@
|
| 4239 |
|
|
alcr\t%0,%2
|
| 4240 |
|
|
alc\t%0,%2"
|
| 4241 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 4242 |
|
|
|
| 4243 |
|
|
; alcr, alc, alcgr, alcg
|
| 4244 |
|
|
(define_insn "*add3_alc"
|
| 4245 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d,d")
|
| 4246 |
|
|
(plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
|
| 4247 |
|
|
(match_operand:GPR 2 "general_operand" "d,m"))
|
| 4248 |
|
|
(match_operand:GPR 3 "s390_alc_comparison" "")))
|
| 4249 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4250 |
|
|
"TARGET_CPU_ZARCH"
|
| 4251 |
|
|
"@
|
| 4252 |
|
|
alcr\t%0,%2
|
| 4253 |
|
|
alc\t%0,%2"
|
| 4254 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 4255 |
|
|
|
| 4256 |
|
|
; slbr, slb, slbgr, slbg
|
| 4257 |
|
|
(define_insn "*sub3_slb_cc"
|
| 4258 |
|
|
[(set (reg CC_REGNUM)
|
| 4259 |
|
|
(compare
|
| 4260 |
|
|
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
|
| 4261 |
|
|
(match_operand:GPR 2 "general_operand" "d,m"))
|
| 4262 |
|
|
(match_operand:GPR 3 "s390_slb_comparison" ""))
|
| 4263 |
|
|
(const_int 0)))
|
| 4264 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d,d")
|
| 4265 |
|
|
(minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
| 4266 |
|
|
"s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
|
| 4267 |
|
|
"@
|
| 4268 |
|
|
slbr\t%0,%2
|
| 4269 |
|
|
slb\t%0,%2"
|
| 4270 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 4271 |
|
|
|
| 4272 |
|
|
; slbr, slb, slbgr, slbg
|
| 4273 |
|
|
(define_insn "*sub3_slb"
|
| 4274 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d,d")
|
| 4275 |
|
|
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
|
| 4276 |
|
|
(match_operand:GPR 2 "general_operand" "d,m"))
|
| 4277 |
|
|
(match_operand:GPR 3 "s390_slb_comparison" "")))
|
| 4278 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4279 |
|
|
"TARGET_CPU_ZARCH"
|
| 4280 |
|
|
"@
|
| 4281 |
|
|
slbr\t%0,%2
|
| 4282 |
|
|
slb\t%0,%2"
|
| 4283 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 4284 |
|
|
|
| 4285 |
|
|
(define_expand "addcc"
|
| 4286 |
|
|
[(match_operand:GPR 0 "register_operand" "")
|
| 4287 |
|
|
(match_operand 1 "comparison_operator" "")
|
| 4288 |
|
|
(match_operand:GPR 2 "register_operand" "")
|
| 4289 |
|
|
(match_operand:GPR 3 "const_int_operand" "")]
|
| 4290 |
|
|
"TARGET_CPU_ZARCH"
|
| 4291 |
|
|
"if (!s390_expand_addcc (GET_CODE (operands[1]),
|
| 4292 |
|
|
s390_compare_op0, s390_compare_op1,
|
| 4293 |
|
|
operands[0], operands[2],
|
| 4294 |
|
|
operands[3])) FAIL; DONE;")
|
| 4295 |
|
|
|
| 4296 |
|
|
;
|
| 4297 |
|
|
; scond instruction pattern(s).
|
| 4298 |
|
|
;
|
| 4299 |
|
|
|
| 4300 |
|
|
(define_insn_and_split "*scond"
|
| 4301 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=&d")
|
| 4302 |
|
|
(match_operand:GPR 1 "s390_alc_comparison" ""))
|
| 4303 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4304 |
|
|
"TARGET_CPU_ZARCH"
|
| 4305 |
|
|
"#"
|
| 4306 |
|
|
"&& reload_completed"
|
| 4307 |
|
|
[(set (match_dup 0) (const_int 0))
|
| 4308 |
|
|
(parallel
|
| 4309 |
|
|
[(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
|
| 4310 |
|
|
(match_dup 1)))
|
| 4311 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 4312 |
|
|
"")
|
| 4313 |
|
|
|
| 4314 |
|
|
(define_insn_and_split "*scond_neg"
|
| 4315 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=&d")
|
| 4316 |
|
|
(match_operand:GPR 1 "s390_slb_comparison" ""))
|
| 4317 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4318 |
|
|
"TARGET_CPU_ZARCH"
|
| 4319 |
|
|
"#"
|
| 4320 |
|
|
"&& reload_completed"
|
| 4321 |
|
|
[(set (match_dup 0) (const_int 0))
|
| 4322 |
|
|
(parallel
|
| 4323 |
|
|
[(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
|
| 4324 |
|
|
(match_dup 1)))
|
| 4325 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 4326 |
|
|
(parallel
|
| 4327 |
|
|
[(set (match_dup 0) (neg:GPR (match_dup 0)))
|
| 4328 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 4329 |
|
|
"")
|
| 4330 |
|
|
|
| 4331 |
|
|
|
| 4332 |
|
|
(define_expand "s"
|
| 4333 |
|
|
[(set (match_operand:SI 0 "register_operand" "")
|
| 4334 |
|
|
(SCOND (match_dup 0)
|
| 4335 |
|
|
(match_dup 0)))]
|
| 4336 |
|
|
"TARGET_CPU_ZARCH"
|
| 4337 |
|
|
"if (!s390_expand_addcc (, s390_compare_op0, s390_compare_op1,
|
| 4338 |
|
|
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
|
| 4339 |
|
|
|
| 4340 |
|
|
(define_expand "seq"
|
| 4341 |
|
|
[(parallel
|
| 4342 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 4343 |
|
|
(match_dup 1))
|
| 4344 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 4345 |
|
|
(parallel
|
| 4346 |
|
|
[(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
|
| 4347 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 4348 |
|
|
""
|
| 4349 |
|
|
{
|
| 4350 |
|
|
if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
|
| 4351 |
|
|
FAIL;
|
| 4352 |
|
|
operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
|
| 4353 |
|
|
PUT_MODE (operands[1], SImode);
|
| 4354 |
|
|
})
|
| 4355 |
|
|
|
| 4356 |
|
|
(define_insn_and_split "*sne"
|
| 4357 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 4358 |
|
|
(ne:SI (match_operand:CCZ1 1 "register_operand" "0")
|
| 4359 |
|
|
(const_int 0)))
|
| 4360 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 4361 |
|
|
""
|
| 4362 |
|
|
"#"
|
| 4363 |
|
|
"reload_completed"
|
| 4364 |
|
|
[(parallel
|
| 4365 |
|
|
[(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
|
| 4366 |
|
|
(clobber (reg:CC CC_REGNUM))])])
|
| 4367 |
|
|
|
| 4368 |
|
|
|
| 4369 |
|
|
;;
|
| 4370 |
|
|
;;- Multiply instructions.
|
| 4371 |
|
|
;;
|
| 4372 |
|
|
|
| 4373 |
|
|
;
|
| 4374 |
|
|
; muldi3 instruction pattern(s).
|
| 4375 |
|
|
;
|
| 4376 |
|
|
|
| 4377 |
|
|
(define_insn "*muldi3_sign"
|
| 4378 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 4379 |
|
|
(mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
|
| 4380 |
|
|
(match_operand:DI 1 "register_operand" "0,0")))]
|
| 4381 |
|
|
"TARGET_64BIT"
|
| 4382 |
|
|
"@
|
| 4383 |
|
|
msgfr\t%0,%2
|
| 4384 |
|
|
msgf\t%0,%2"
|
| 4385 |
|
|
[(set_attr "op_type" "RRE,RXY")
|
| 4386 |
|
|
(set_attr "type" "imuldi")])
|
| 4387 |
|
|
|
| 4388 |
|
|
(define_insn "muldi3"
|
| 4389 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
|
| 4390 |
|
|
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
|
| 4391 |
|
|
(match_operand:DI 2 "general_operand" "d,K,m")))]
|
| 4392 |
|
|
"TARGET_64BIT"
|
| 4393 |
|
|
"@
|
| 4394 |
|
|
msgr\t%0,%2
|
| 4395 |
|
|
mghi\t%0,%h2
|
| 4396 |
|
|
msg\t%0,%2"
|
| 4397 |
|
|
[(set_attr "op_type" "RRE,RI,RXY")
|
| 4398 |
|
|
(set_attr "type" "imuldi")])
|
| 4399 |
|
|
|
| 4400 |
|
|
;
|
| 4401 |
|
|
; mulsi3 instruction pattern(s).
|
| 4402 |
|
|
;
|
| 4403 |
|
|
|
| 4404 |
|
|
(define_insn "*mulsi3_sign"
|
| 4405 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 4406 |
|
|
(mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
|
| 4407 |
|
|
(match_operand:SI 1 "register_operand" "0")))]
|
| 4408 |
|
|
""
|
| 4409 |
|
|
"mh\t%0,%2"
|
| 4410 |
|
|
[(set_attr "op_type" "RX")
|
| 4411 |
|
|
(set_attr "type" "imulhi")])
|
| 4412 |
|
|
|
| 4413 |
|
|
(define_insn "mulsi3"
|
| 4414 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
| 4415 |
|
|
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 4416 |
|
|
(match_operand:SI 2 "general_operand" "d,K,R,T")))]
|
| 4417 |
|
|
""
|
| 4418 |
|
|
"@
|
| 4419 |
|
|
msr\t%0,%2
|
| 4420 |
|
|
mhi\t%0,%h2
|
| 4421 |
|
|
ms\t%0,%2
|
| 4422 |
|
|
msy\t%0,%2"
|
| 4423 |
|
|
[(set_attr "op_type" "RRE,RI,RX,RXY")
|
| 4424 |
|
|
(set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
|
| 4425 |
|
|
|
| 4426 |
|
|
;
|
| 4427 |
|
|
; mulsidi3 instruction pattern(s).
|
| 4428 |
|
|
;
|
| 4429 |
|
|
|
| 4430 |
|
|
(define_insn "mulsidi3"
|
| 4431 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 4432 |
|
|
(mult:DI (sign_extend:DI
|
| 4433 |
|
|
(match_operand:SI 1 "register_operand" "%0,0"))
|
| 4434 |
|
|
(sign_extend:DI
|
| 4435 |
|
|
(match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
|
| 4436 |
|
|
"!TARGET_64BIT"
|
| 4437 |
|
|
"@
|
| 4438 |
|
|
mr\t%0,%2
|
| 4439 |
|
|
m\t%0,%2"
|
| 4440 |
|
|
[(set_attr "op_type" "RR,RX")
|
| 4441 |
|
|
(set_attr "type" "imulsi")])
|
| 4442 |
|
|
|
| 4443 |
|
|
;
|
| 4444 |
|
|
; umulsidi3 instruction pattern(s).
|
| 4445 |
|
|
;
|
| 4446 |
|
|
|
| 4447 |
|
|
(define_insn "umulsidi3"
|
| 4448 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 4449 |
|
|
(mult:DI (zero_extend:DI
|
| 4450 |
|
|
(match_operand:SI 1 "register_operand" "%0,0"))
|
| 4451 |
|
|
(zero_extend:DI
|
| 4452 |
|
|
(match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
|
| 4453 |
|
|
"!TARGET_64BIT && TARGET_CPU_ZARCH"
|
| 4454 |
|
|
"@
|
| 4455 |
|
|
mlr\t%0,%2
|
| 4456 |
|
|
ml\t%0,%2"
|
| 4457 |
|
|
[(set_attr "op_type" "RRE,RXY")
|
| 4458 |
|
|
(set_attr "type" "imulsi")])
|
| 4459 |
|
|
|
| 4460 |
|
|
;
|
| 4461 |
|
|
; mul(df|sf)3 instruction pattern(s).
|
| 4462 |
|
|
;
|
| 4463 |
|
|
|
| 4464 |
|
|
(define_expand "mul3"
|
| 4465 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4466 |
|
|
(mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
|
| 4467 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))]
|
| 4468 |
|
|
"TARGET_HARD_FLOAT"
|
| 4469 |
|
|
"")
|
| 4470 |
|
|
|
| 4471 |
|
|
; mxbr mdbr, meebr, mxb, mxb, meeb
|
| 4472 |
|
|
(define_insn "*mul3"
|
| 4473 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4474 |
|
|
(mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
|
| 4475 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))]
|
| 4476 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 4477 |
|
|
"@
|
| 4478 |
|
|
mbr\t%0,%2
|
| 4479 |
|
|
mb\t%0,%2"
|
| 4480 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 4481 |
|
|
(set_attr "type" "fmul")])
|
| 4482 |
|
|
|
| 4483 |
|
|
; mxr, mdr, mer, mx, md, me
|
| 4484 |
|
|
(define_insn "*mul3_ibm"
|
| 4485 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4486 |
|
|
(mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
|
| 4487 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))]
|
| 4488 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 4489 |
|
|
"@
|
| 4490 |
|
|
mr\t%0,%2
|
| 4491 |
|
|
m\t%0,%2"
|
| 4492 |
|
|
[(set_attr "op_type" ",")
|
| 4493 |
|
|
(set_attr "type" "fmul")])
|
| 4494 |
|
|
|
| 4495 |
|
|
; maxbr, madbr, maebr, maxb, madb, maeb
|
| 4496 |
|
|
(define_insn "*fmadd"
|
| 4497 |
|
|
[(set (match_operand:DSF 0 "register_operand" "=f,f")
|
| 4498 |
|
|
(plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
|
| 4499 |
|
|
(match_operand:DSF 2 "nonimmediate_operand" "f,R"))
|
| 4500 |
|
|
(match_operand:DSF 3 "register_operand" "0,0")))]
|
| 4501 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
|
| 4502 |
|
|
"@
|
| 4503 |
|
|
mabr\t%0,%1,%2
|
| 4504 |
|
|
mab\t%0,%1,%2"
|
| 4505 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 4506 |
|
|
(set_attr "type" "fmul")])
|
| 4507 |
|
|
|
| 4508 |
|
|
; msxbr, msdbr, msebr, msxb, msdb, mseb
|
| 4509 |
|
|
(define_insn "*fmsub"
|
| 4510 |
|
|
[(set (match_operand:DSF 0 "register_operand" "=f,f")
|
| 4511 |
|
|
(minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
|
| 4512 |
|
|
(match_operand:DSF 2 "nonimmediate_operand" "f,R"))
|
| 4513 |
|
|
(match_operand:DSF 3 "register_operand" "0,0")))]
|
| 4514 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
|
| 4515 |
|
|
"@
|
| 4516 |
|
|
msbr\t%0,%1,%2
|
| 4517 |
|
|
msb\t%0,%1,%2"
|
| 4518 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 4519 |
|
|
(set_attr "type" "fmul")])
|
| 4520 |
|
|
|
| 4521 |
|
|
;;
|
| 4522 |
|
|
;;- Divide and modulo instructions.
|
| 4523 |
|
|
;;
|
| 4524 |
|
|
|
| 4525 |
|
|
;
|
| 4526 |
|
|
; divmoddi4 instruction pattern(s).
|
| 4527 |
|
|
;
|
| 4528 |
|
|
|
| 4529 |
|
|
(define_expand "divmoddi4"
|
| 4530 |
|
|
[(parallel [(set (match_operand:DI 0 "general_operand" "")
|
| 4531 |
|
|
(div:DI (match_operand:DI 1 "register_operand" "")
|
| 4532 |
|
|
(match_operand:DI 2 "general_operand" "")))
|
| 4533 |
|
|
(set (match_operand:DI 3 "general_operand" "")
|
| 4534 |
|
|
(mod:DI (match_dup 1) (match_dup 2)))])
|
| 4535 |
|
|
(clobber (match_dup 4))]
|
| 4536 |
|
|
"TARGET_64BIT"
|
| 4537 |
|
|
{
|
| 4538 |
|
|
rtx insn, div_equal, mod_equal;
|
| 4539 |
|
|
|
| 4540 |
|
|
div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
|
| 4541 |
|
|
mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
|
| 4542 |
|
|
|
| 4543 |
|
|
operands[4] = gen_reg_rtx(TImode);
|
| 4544 |
|
|
emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
|
| 4545 |
|
|
|
| 4546 |
|
|
insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
|
| 4547 |
|
|
REG_NOTES (insn) =
|
| 4548 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
|
| 4549 |
|
|
|
| 4550 |
|
|
insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
|
| 4551 |
|
|
REG_NOTES (insn) =
|
| 4552 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
|
| 4553 |
|
|
|
| 4554 |
|
|
DONE;
|
| 4555 |
|
|
})
|
| 4556 |
|
|
|
| 4557 |
|
|
(define_insn "divmodtidi3"
|
| 4558 |
|
|
[(set (match_operand:TI 0 "register_operand" "=d,d")
|
| 4559 |
|
|
(ior:TI
|
| 4560 |
|
|
(ashift:TI
|
| 4561 |
|
|
(zero_extend:TI
|
| 4562 |
|
|
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
|
| 4563 |
|
|
(match_operand:DI 2 "general_operand" "d,m")))
|
| 4564 |
|
|
(const_int 64))
|
| 4565 |
|
|
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
|
| 4566 |
|
|
"TARGET_64BIT"
|
| 4567 |
|
|
"@
|
| 4568 |
|
|
dsgr\t%0,%2
|
| 4569 |
|
|
dsg\t%0,%2"
|
| 4570 |
|
|
[(set_attr "op_type" "RRE,RXY")
|
| 4571 |
|
|
(set_attr "type" "idiv")])
|
| 4572 |
|
|
|
| 4573 |
|
|
(define_insn "divmodtisi3"
|
| 4574 |
|
|
[(set (match_operand:TI 0 "register_operand" "=d,d")
|
| 4575 |
|
|
(ior:TI
|
| 4576 |
|
|
(ashift:TI
|
| 4577 |
|
|
(zero_extend:TI
|
| 4578 |
|
|
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
|
| 4579 |
|
|
(sign_extend:DI
|
| 4580 |
|
|
(match_operand:SI 2 "nonimmediate_operand" "d,m"))))
|
| 4581 |
|
|
(const_int 64))
|
| 4582 |
|
|
(zero_extend:TI
|
| 4583 |
|
|
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
|
| 4584 |
|
|
"TARGET_64BIT"
|
| 4585 |
|
|
"@
|
| 4586 |
|
|
dsgfr\t%0,%2
|
| 4587 |
|
|
dsgf\t%0,%2"
|
| 4588 |
|
|
[(set_attr "op_type" "RRE,RXY")
|
| 4589 |
|
|
(set_attr "type" "idiv")])
|
| 4590 |
|
|
|
| 4591 |
|
|
;
|
| 4592 |
|
|
; udivmoddi4 instruction pattern(s).
|
| 4593 |
|
|
;
|
| 4594 |
|
|
|
| 4595 |
|
|
(define_expand "udivmoddi4"
|
| 4596 |
|
|
[(parallel [(set (match_operand:DI 0 "general_operand" "")
|
| 4597 |
|
|
(udiv:DI (match_operand:DI 1 "general_operand" "")
|
| 4598 |
|
|
(match_operand:DI 2 "nonimmediate_operand" "")))
|
| 4599 |
|
|
(set (match_operand:DI 3 "general_operand" "")
|
| 4600 |
|
|
(umod:DI (match_dup 1) (match_dup 2)))])
|
| 4601 |
|
|
(clobber (match_dup 4))]
|
| 4602 |
|
|
"TARGET_64BIT"
|
| 4603 |
|
|
{
|
| 4604 |
|
|
rtx insn, div_equal, mod_equal, equal;
|
| 4605 |
|
|
|
| 4606 |
|
|
div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
|
| 4607 |
|
|
mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
|
| 4608 |
|
|
equal = gen_rtx_IOR (TImode,
|
| 4609 |
|
|
gen_rtx_ASHIFT (TImode,
|
| 4610 |
|
|
gen_rtx_ZERO_EXTEND (TImode, mod_equal),
|
| 4611 |
|
|
GEN_INT (64)),
|
| 4612 |
|
|
gen_rtx_ZERO_EXTEND (TImode, div_equal));
|
| 4613 |
|
|
|
| 4614 |
|
|
operands[4] = gen_reg_rtx(TImode);
|
| 4615 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
|
| 4616 |
|
|
emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
|
| 4617 |
|
|
emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
|
| 4618 |
|
|
insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
|
| 4619 |
|
|
REG_NOTES (insn) =
|
| 4620 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
|
| 4621 |
|
|
|
| 4622 |
|
|
insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
|
| 4623 |
|
|
REG_NOTES (insn) =
|
| 4624 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
|
| 4625 |
|
|
|
| 4626 |
|
|
insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
|
| 4627 |
|
|
REG_NOTES (insn) =
|
| 4628 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
|
| 4629 |
|
|
|
| 4630 |
|
|
DONE;
|
| 4631 |
|
|
})
|
| 4632 |
|
|
|
| 4633 |
|
|
(define_insn "udivmodtidi3"
|
| 4634 |
|
|
[(set (match_operand:TI 0 "register_operand" "=d,d")
|
| 4635 |
|
|
(ior:TI
|
| 4636 |
|
|
(ashift:TI
|
| 4637 |
|
|
(zero_extend:TI
|
| 4638 |
|
|
(truncate:DI
|
| 4639 |
|
|
(umod:TI (match_operand:TI 1 "register_operand" "0,0")
|
| 4640 |
|
|
(zero_extend:TI
|
| 4641 |
|
|
(match_operand:DI 2 "nonimmediate_operand" "d,m")))))
|
| 4642 |
|
|
(const_int 64))
|
| 4643 |
|
|
(zero_extend:TI
|
| 4644 |
|
|
(truncate:DI
|
| 4645 |
|
|
(udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
|
| 4646 |
|
|
"TARGET_64BIT"
|
| 4647 |
|
|
"@
|
| 4648 |
|
|
dlgr\t%0,%2
|
| 4649 |
|
|
dlg\t%0,%2"
|
| 4650 |
|
|
[(set_attr "op_type" "RRE,RXY")
|
| 4651 |
|
|
(set_attr "type" "idiv")])
|
| 4652 |
|
|
|
| 4653 |
|
|
;
|
| 4654 |
|
|
; divmodsi4 instruction pattern(s).
|
| 4655 |
|
|
;
|
| 4656 |
|
|
|
| 4657 |
|
|
(define_expand "divmodsi4"
|
| 4658 |
|
|
[(parallel [(set (match_operand:SI 0 "general_operand" "")
|
| 4659 |
|
|
(div:SI (match_operand:SI 1 "general_operand" "")
|
| 4660 |
|
|
(match_operand:SI 2 "nonimmediate_operand" "")))
|
| 4661 |
|
|
(set (match_operand:SI 3 "general_operand" "")
|
| 4662 |
|
|
(mod:SI (match_dup 1) (match_dup 2)))])
|
| 4663 |
|
|
(clobber (match_dup 4))]
|
| 4664 |
|
|
"!TARGET_64BIT"
|
| 4665 |
|
|
{
|
| 4666 |
|
|
rtx insn, div_equal, mod_equal, equal;
|
| 4667 |
|
|
|
| 4668 |
|
|
div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
|
| 4669 |
|
|
mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
|
| 4670 |
|
|
equal = gen_rtx_IOR (DImode,
|
| 4671 |
|
|
gen_rtx_ASHIFT (DImode,
|
| 4672 |
|
|
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
|
| 4673 |
|
|
GEN_INT (32)),
|
| 4674 |
|
|
gen_rtx_ZERO_EXTEND (DImode, div_equal));
|
| 4675 |
|
|
|
| 4676 |
|
|
operands[4] = gen_reg_rtx(DImode);
|
| 4677 |
|
|
emit_insn (gen_extendsidi2 (operands[4], operands[1]));
|
| 4678 |
|
|
insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
|
| 4679 |
|
|
REG_NOTES (insn) =
|
| 4680 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
|
| 4681 |
|
|
|
| 4682 |
|
|
insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
|
| 4683 |
|
|
REG_NOTES (insn) =
|
| 4684 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
|
| 4685 |
|
|
|
| 4686 |
|
|
insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
|
| 4687 |
|
|
REG_NOTES (insn) =
|
| 4688 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
|
| 4689 |
|
|
|
| 4690 |
|
|
DONE;
|
| 4691 |
|
|
})
|
| 4692 |
|
|
|
| 4693 |
|
|
(define_insn "divmoddisi3"
|
| 4694 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 4695 |
|
|
(ior:DI
|
| 4696 |
|
|
(ashift:DI
|
| 4697 |
|
|
(zero_extend:DI
|
| 4698 |
|
|
(truncate:SI
|
| 4699 |
|
|
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
|
| 4700 |
|
|
(sign_extend:DI
|
| 4701 |
|
|
(match_operand:SI 2 "nonimmediate_operand" "d,R")))))
|
| 4702 |
|
|
(const_int 32))
|
| 4703 |
|
|
(zero_extend:DI
|
| 4704 |
|
|
(truncate:SI
|
| 4705 |
|
|
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
|
| 4706 |
|
|
"!TARGET_64BIT"
|
| 4707 |
|
|
"@
|
| 4708 |
|
|
dr\t%0,%2
|
| 4709 |
|
|
d\t%0,%2"
|
| 4710 |
|
|
[(set_attr "op_type" "RR,RX")
|
| 4711 |
|
|
(set_attr "type" "idiv")])
|
| 4712 |
|
|
|
| 4713 |
|
|
;
|
| 4714 |
|
|
; udivsi3 and umodsi3 instruction pattern(s).
|
| 4715 |
|
|
;
|
| 4716 |
|
|
|
| 4717 |
|
|
(define_expand "udivmodsi4"
|
| 4718 |
|
|
[(parallel [(set (match_operand:SI 0 "general_operand" "")
|
| 4719 |
|
|
(udiv:SI (match_operand:SI 1 "general_operand" "")
|
| 4720 |
|
|
(match_operand:SI 2 "nonimmediate_operand" "")))
|
| 4721 |
|
|
(set (match_operand:SI 3 "general_operand" "")
|
| 4722 |
|
|
(umod:SI (match_dup 1) (match_dup 2)))])
|
| 4723 |
|
|
(clobber (match_dup 4))]
|
| 4724 |
|
|
"!TARGET_64BIT && TARGET_CPU_ZARCH"
|
| 4725 |
|
|
{
|
| 4726 |
|
|
rtx insn, div_equal, mod_equal, equal;
|
| 4727 |
|
|
|
| 4728 |
|
|
div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
|
| 4729 |
|
|
mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
|
| 4730 |
|
|
equal = gen_rtx_IOR (DImode,
|
| 4731 |
|
|
gen_rtx_ASHIFT (DImode,
|
| 4732 |
|
|
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
|
| 4733 |
|
|
GEN_INT (32)),
|
| 4734 |
|
|
gen_rtx_ZERO_EXTEND (DImode, div_equal));
|
| 4735 |
|
|
|
| 4736 |
|
|
operands[4] = gen_reg_rtx(DImode);
|
| 4737 |
|
|
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
|
| 4738 |
|
|
emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
|
| 4739 |
|
|
emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
|
| 4740 |
|
|
insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
|
| 4741 |
|
|
REG_NOTES (insn) =
|
| 4742 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
|
| 4743 |
|
|
|
| 4744 |
|
|
insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
|
| 4745 |
|
|
REG_NOTES (insn) =
|
| 4746 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
|
| 4747 |
|
|
|
| 4748 |
|
|
insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
|
| 4749 |
|
|
REG_NOTES (insn) =
|
| 4750 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
|
| 4751 |
|
|
|
| 4752 |
|
|
DONE;
|
| 4753 |
|
|
})
|
| 4754 |
|
|
|
| 4755 |
|
|
(define_insn "udivmoddisi3"
|
| 4756 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 4757 |
|
|
(ior:DI
|
| 4758 |
|
|
(ashift:DI
|
| 4759 |
|
|
(zero_extend:DI
|
| 4760 |
|
|
(truncate:SI
|
| 4761 |
|
|
(umod:DI (match_operand:DI 1 "register_operand" "0,0")
|
| 4762 |
|
|
(zero_extend:DI
|
| 4763 |
|
|
(match_operand:SI 2 "nonimmediate_operand" "d,m")))))
|
| 4764 |
|
|
(const_int 32))
|
| 4765 |
|
|
(zero_extend:DI
|
| 4766 |
|
|
(truncate:SI
|
| 4767 |
|
|
(udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
|
| 4768 |
|
|
"!TARGET_64BIT && TARGET_CPU_ZARCH"
|
| 4769 |
|
|
"@
|
| 4770 |
|
|
dlr\t%0,%2
|
| 4771 |
|
|
dl\t%0,%2"
|
| 4772 |
|
|
[(set_attr "op_type" "RRE,RXY")
|
| 4773 |
|
|
(set_attr "type" "idiv")])
|
| 4774 |
|
|
|
| 4775 |
|
|
(define_expand "udivsi3"
|
| 4776 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 4777 |
|
|
(udiv:SI (match_operand:SI 1 "general_operand" "")
|
| 4778 |
|
|
(match_operand:SI 2 "general_operand" "")))
|
| 4779 |
|
|
(clobber (match_dup 3))]
|
| 4780 |
|
|
"!TARGET_64BIT && !TARGET_CPU_ZARCH"
|
| 4781 |
|
|
{
|
| 4782 |
|
|
rtx insn, udiv_equal, umod_equal, equal;
|
| 4783 |
|
|
|
| 4784 |
|
|
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
|
| 4785 |
|
|
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
|
| 4786 |
|
|
equal = gen_rtx_IOR (DImode,
|
| 4787 |
|
|
gen_rtx_ASHIFT (DImode,
|
| 4788 |
|
|
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
|
| 4789 |
|
|
GEN_INT (32)),
|
| 4790 |
|
|
gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
|
| 4791 |
|
|
|
| 4792 |
|
|
operands[3] = gen_reg_rtx (DImode);
|
| 4793 |
|
|
|
| 4794 |
|
|
if (CONSTANT_P (operands[2]))
|
| 4795 |
|
|
{
|
| 4796 |
|
|
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
|
| 4797 |
|
|
{
|
| 4798 |
|
|
rtx label1 = gen_label_rtx ();
|
| 4799 |
|
|
|
| 4800 |
|
|
operands[1] = make_safe_from (operands[1], operands[0]);
|
| 4801 |
|
|
emit_move_insn (operands[0], const0_rtx);
|
| 4802 |
|
|
emit_insn (gen_cmpsi (operands[1], operands[2]));
|
| 4803 |
|
|
emit_jump_insn (gen_bltu (label1));
|
| 4804 |
|
|
emit_move_insn (operands[0], const1_rtx);
|
| 4805 |
|
|
emit_label (label1);
|
| 4806 |
|
|
}
|
| 4807 |
|
|
else
|
| 4808 |
|
|
{
|
| 4809 |
|
|
operands[2] = force_reg (SImode, operands[2]);
|
| 4810 |
|
|
operands[2] = make_safe_from (operands[2], operands[0]);
|
| 4811 |
|
|
|
| 4812 |
|
|
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
|
| 4813 |
|
|
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
|
| 4814 |
|
|
operands[2]));
|
| 4815 |
|
|
REG_NOTES (insn) =
|
| 4816 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
|
| 4817 |
|
|
|
| 4818 |
|
|
insn = emit_move_insn (operands[0],
|
| 4819 |
|
|
gen_lowpart (SImode, operands[3]));
|
| 4820 |
|
|
REG_NOTES (insn) =
|
| 4821 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL,
|
| 4822 |
|
|
udiv_equal, REG_NOTES (insn));
|
| 4823 |
|
|
}
|
| 4824 |
|
|
}
|
| 4825 |
|
|
else
|
| 4826 |
|
|
{
|
| 4827 |
|
|
rtx label1 = gen_label_rtx ();
|
| 4828 |
|
|
rtx label2 = gen_label_rtx ();
|
| 4829 |
|
|
rtx label3 = gen_label_rtx ();
|
| 4830 |
|
|
|
| 4831 |
|
|
operands[1] = force_reg (SImode, operands[1]);
|
| 4832 |
|
|
operands[1] = make_safe_from (operands[1], operands[0]);
|
| 4833 |
|
|
operands[2] = force_reg (SImode, operands[2]);
|
| 4834 |
|
|
operands[2] = make_safe_from (operands[2], operands[0]);
|
| 4835 |
|
|
|
| 4836 |
|
|
emit_move_insn (operands[0], const0_rtx);
|
| 4837 |
|
|
emit_insn (gen_cmpsi (operands[2], operands[1]));
|
| 4838 |
|
|
emit_jump_insn (gen_bgtu (label3));
|
| 4839 |
|
|
emit_insn (gen_cmpsi (operands[2], const0_rtx));
|
| 4840 |
|
|
emit_jump_insn (gen_blt (label2));
|
| 4841 |
|
|
emit_insn (gen_cmpsi (operands[2], const1_rtx));
|
| 4842 |
|
|
emit_jump_insn (gen_beq (label1));
|
| 4843 |
|
|
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
|
| 4844 |
|
|
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
|
| 4845 |
|
|
operands[2]));
|
| 4846 |
|
|
REG_NOTES (insn) =
|
| 4847 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
|
| 4848 |
|
|
|
| 4849 |
|
|
insn = emit_move_insn (operands[0],
|
| 4850 |
|
|
gen_lowpart (SImode, operands[3]));
|
| 4851 |
|
|
REG_NOTES (insn) =
|
| 4852 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL,
|
| 4853 |
|
|
udiv_equal, REG_NOTES (insn));
|
| 4854 |
|
|
emit_jump (label3);
|
| 4855 |
|
|
emit_label (label1);
|
| 4856 |
|
|
emit_move_insn (operands[0], operands[1]);
|
| 4857 |
|
|
emit_jump (label3);
|
| 4858 |
|
|
emit_label (label2);
|
| 4859 |
|
|
emit_move_insn (operands[0], const1_rtx);
|
| 4860 |
|
|
emit_label (label3);
|
| 4861 |
|
|
}
|
| 4862 |
|
|
emit_move_insn (operands[0], operands[0]);
|
| 4863 |
|
|
DONE;
|
| 4864 |
|
|
})
|
| 4865 |
|
|
|
| 4866 |
|
|
(define_expand "umodsi3"
|
| 4867 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
| 4868 |
|
|
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
|
| 4869 |
|
|
(match_operand:SI 2 "nonimmediate_operand" "")))
|
| 4870 |
|
|
(clobber (match_dup 3))]
|
| 4871 |
|
|
"!TARGET_64BIT && !TARGET_CPU_ZARCH"
|
| 4872 |
|
|
{
|
| 4873 |
|
|
rtx insn, udiv_equal, umod_equal, equal;
|
| 4874 |
|
|
|
| 4875 |
|
|
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
|
| 4876 |
|
|
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
|
| 4877 |
|
|
equal = gen_rtx_IOR (DImode,
|
| 4878 |
|
|
gen_rtx_ASHIFT (DImode,
|
| 4879 |
|
|
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
|
| 4880 |
|
|
GEN_INT (32)),
|
| 4881 |
|
|
gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
|
| 4882 |
|
|
|
| 4883 |
|
|
operands[3] = gen_reg_rtx (DImode);
|
| 4884 |
|
|
|
| 4885 |
|
|
if (CONSTANT_P (operands[2]))
|
| 4886 |
|
|
{
|
| 4887 |
|
|
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
|
| 4888 |
|
|
{
|
| 4889 |
|
|
rtx label1 = gen_label_rtx ();
|
| 4890 |
|
|
|
| 4891 |
|
|
operands[1] = make_safe_from (operands[1], operands[0]);
|
| 4892 |
|
|
emit_move_insn (operands[0], operands[1]);
|
| 4893 |
|
|
emit_insn (gen_cmpsi (operands[0], operands[2]));
|
| 4894 |
|
|
emit_jump_insn (gen_bltu (label1));
|
| 4895 |
|
|
emit_insn (gen_abssi2 (operands[0], operands[2]));
|
| 4896 |
|
|
emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
|
| 4897 |
|
|
emit_label (label1);
|
| 4898 |
|
|
}
|
| 4899 |
|
|
else
|
| 4900 |
|
|
{
|
| 4901 |
|
|
operands[2] = force_reg (SImode, operands[2]);
|
| 4902 |
|
|
operands[2] = make_safe_from (operands[2], operands[0]);
|
| 4903 |
|
|
|
| 4904 |
|
|
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
|
| 4905 |
|
|
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
|
| 4906 |
|
|
operands[2]));
|
| 4907 |
|
|
REG_NOTES (insn) =
|
| 4908 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
|
| 4909 |
|
|
|
| 4910 |
|
|
insn = emit_move_insn (operands[0],
|
| 4911 |
|
|
gen_highpart (SImode, operands[3]));
|
| 4912 |
|
|
REG_NOTES (insn) =
|
| 4913 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL,
|
| 4914 |
|
|
umod_equal, REG_NOTES (insn));
|
| 4915 |
|
|
}
|
| 4916 |
|
|
}
|
| 4917 |
|
|
else
|
| 4918 |
|
|
{
|
| 4919 |
|
|
rtx label1 = gen_label_rtx ();
|
| 4920 |
|
|
rtx label2 = gen_label_rtx ();
|
| 4921 |
|
|
rtx label3 = gen_label_rtx ();
|
| 4922 |
|
|
|
| 4923 |
|
|
operands[1] = force_reg (SImode, operands[1]);
|
| 4924 |
|
|
operands[1] = make_safe_from (operands[1], operands[0]);
|
| 4925 |
|
|
operands[2] = force_reg (SImode, operands[2]);
|
| 4926 |
|
|
operands[2] = make_safe_from (operands[2], operands[0]);
|
| 4927 |
|
|
|
| 4928 |
|
|
emit_move_insn(operands[0], operands[1]);
|
| 4929 |
|
|
emit_insn (gen_cmpsi (operands[2], operands[1]));
|
| 4930 |
|
|
emit_jump_insn (gen_bgtu (label3));
|
| 4931 |
|
|
emit_insn (gen_cmpsi (operands[2], const0_rtx));
|
| 4932 |
|
|
emit_jump_insn (gen_blt (label2));
|
| 4933 |
|
|
emit_insn (gen_cmpsi (operands[2], const1_rtx));
|
| 4934 |
|
|
emit_jump_insn (gen_beq (label1));
|
| 4935 |
|
|
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
|
| 4936 |
|
|
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
|
| 4937 |
|
|
operands[2]));
|
| 4938 |
|
|
REG_NOTES (insn) =
|
| 4939 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
|
| 4940 |
|
|
|
| 4941 |
|
|
insn = emit_move_insn (operands[0],
|
| 4942 |
|
|
gen_highpart (SImode, operands[3]));
|
| 4943 |
|
|
REG_NOTES (insn) =
|
| 4944 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL,
|
| 4945 |
|
|
umod_equal, REG_NOTES (insn));
|
| 4946 |
|
|
emit_jump (label3);
|
| 4947 |
|
|
emit_label (label1);
|
| 4948 |
|
|
emit_move_insn (operands[0], const0_rtx);
|
| 4949 |
|
|
emit_jump (label3);
|
| 4950 |
|
|
emit_label (label2);
|
| 4951 |
|
|
emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
|
| 4952 |
|
|
emit_label (label3);
|
| 4953 |
|
|
}
|
| 4954 |
|
|
DONE;
|
| 4955 |
|
|
})
|
| 4956 |
|
|
|
| 4957 |
|
|
;
|
| 4958 |
|
|
; div(df|sf)3 instruction pattern(s).
|
| 4959 |
|
|
;
|
| 4960 |
|
|
|
| 4961 |
|
|
(define_expand "div3"
|
| 4962 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4963 |
|
|
(div:FPR (match_operand:FPR 1 "register_operand" "0,0")
|
| 4964 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))]
|
| 4965 |
|
|
"TARGET_HARD_FLOAT"
|
| 4966 |
|
|
"")
|
| 4967 |
|
|
|
| 4968 |
|
|
; dxbr, ddbr, debr, dxb, ddb, deb
|
| 4969 |
|
|
(define_insn "*div3"
|
| 4970 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4971 |
|
|
(div:FPR (match_operand:FPR 1 "register_operand" "0,0")
|
| 4972 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))]
|
| 4973 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 4974 |
|
|
"@
|
| 4975 |
|
|
dbr\t%0,%2
|
| 4976 |
|
|
db\t%0,%2"
|
| 4977 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 4978 |
|
|
(set_attr "type" "fdiv")])
|
| 4979 |
|
|
|
| 4980 |
|
|
; dxr, ddr, der, dx, dd, de
|
| 4981 |
|
|
(define_insn "*div3_ibm"
|
| 4982 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 4983 |
|
|
(div:FPR (match_operand:FPR 1 "register_operand" "0,0")
|
| 4984 |
|
|
(match_operand:FPR 2 "general_operand" "f,")))]
|
| 4985 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 4986 |
|
|
"@
|
| 4987 |
|
|
dr\t%0,%2
|
| 4988 |
|
|
d\t%0,%2"
|
| 4989 |
|
|
[(set_attr "op_type" ",")
|
| 4990 |
|
|
(set_attr "type" "fdiv")])
|
| 4991 |
|
|
|
| 4992 |
|
|
|
| 4993 |
|
|
;;
|
| 4994 |
|
|
;;- And instructions.
|
| 4995 |
|
|
;;
|
| 4996 |
|
|
|
| 4997 |
|
|
(define_expand "and3"
|
| 4998 |
|
|
[(set (match_operand:INT 0 "nonimmediate_operand" "")
|
| 4999 |
|
|
(and:INT (match_operand:INT 1 "nonimmediate_operand" "")
|
| 5000 |
|
|
(match_operand:INT 2 "general_operand" "")))
|
| 5001 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5002 |
|
|
""
|
| 5003 |
|
|
"s390_expand_logical_operator (AND, mode, operands); DONE;")
|
| 5004 |
|
|
|
| 5005 |
|
|
;
|
| 5006 |
|
|
; anddi3 instruction pattern(s).
|
| 5007 |
|
|
;
|
| 5008 |
|
|
|
| 5009 |
|
|
(define_insn "*anddi3_cc"
|
| 5010 |
|
|
[(set (reg CC_REGNUM)
|
| 5011 |
|
|
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
|
| 5012 |
|
|
(match_operand:DI 2 "general_operand" "d,m"))
|
| 5013 |
|
|
(const_int 0)))
|
| 5014 |
|
|
(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 5015 |
|
|
(and:DI (match_dup 1) (match_dup 2)))]
|
| 5016 |
|
|
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
|
| 5017 |
|
|
"@
|
| 5018 |
|
|
ngr\t%0,%2
|
| 5019 |
|
|
ng\t%0,%2"
|
| 5020 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 5021 |
|
|
|
| 5022 |
|
|
(define_insn "*anddi3_cconly"
|
| 5023 |
|
|
[(set (reg CC_REGNUM)
|
| 5024 |
|
|
(compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
|
| 5025 |
|
|
(match_operand:DI 2 "general_operand" "d,m"))
|
| 5026 |
|
|
(const_int 0)))
|
| 5027 |
|
|
(clobber (match_scratch:DI 0 "=d,d"))]
|
| 5028 |
|
|
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
|
| 5029 |
|
|
/* Do not steal TM patterns. */
|
| 5030 |
|
|
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
|
| 5031 |
|
|
"@
|
| 5032 |
|
|
ngr\t%0,%2
|
| 5033 |
|
|
ng\t%0,%2"
|
| 5034 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 5035 |
|
|
|
| 5036 |
|
|
(define_insn "*anddi3_extimm"
|
| 5037 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
|
| 5038 |
|
|
(and:DI (match_operand:DI 1 "nonimmediate_operand"
|
| 5039 |
|
|
"%d,o,0,0,0,0,0,0,0,0,0,0")
|
| 5040 |
|
|
(match_operand:DI 2 "general_operand"
|
| 5041 |
|
|
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
|
| 5042 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5043 |
|
|
"TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
|
| 5044 |
|
|
"@
|
| 5045 |
|
|
#
|
| 5046 |
|
|
#
|
| 5047 |
|
|
nihh\t%0,%j2
|
| 5048 |
|
|
nihl\t%0,%j2
|
| 5049 |
|
|
nilh\t%0,%j2
|
| 5050 |
|
|
nill\t%0,%j2
|
| 5051 |
|
|
nihf\t%0,%m2
|
| 5052 |
|
|
nilf\t%0,%m2
|
| 5053 |
|
|
ngr\t%0,%2
|
| 5054 |
|
|
ng\t%0,%2
|
| 5055 |
|
|
#
|
| 5056 |
|
|
#"
|
| 5057 |
|
|
[(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
|
| 5058 |
|
|
|
| 5059 |
|
|
(define_insn "*anddi3"
|
| 5060 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
|
| 5061 |
|
|
(and:DI (match_operand:DI 1 "nonimmediate_operand"
|
| 5062 |
|
|
"%d,o,0,0,0,0,0,0,0,0")
|
| 5063 |
|
|
(match_operand:DI 2 "general_operand"
|
| 5064 |
|
|
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
|
| 5065 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5066 |
|
|
"TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
|
| 5067 |
|
|
"@
|
| 5068 |
|
|
#
|
| 5069 |
|
|
#
|
| 5070 |
|
|
nihh\t%0,%j2
|
| 5071 |
|
|
nihl\t%0,%j2
|
| 5072 |
|
|
nilh\t%0,%j2
|
| 5073 |
|
|
nill\t%0,%j2
|
| 5074 |
|
|
ngr\t%0,%2
|
| 5075 |
|
|
ng\t%0,%2
|
| 5076 |
|
|
#
|
| 5077 |
|
|
#"
|
| 5078 |
|
|
[(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
|
| 5079 |
|
|
|
| 5080 |
|
|
(define_split
|
| 5081 |
|
|
[(set (match_operand:DI 0 "s_operand" "")
|
| 5082 |
|
|
(and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
|
| 5083 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5084 |
|
|
"reload_completed"
|
| 5085 |
|
|
[(parallel
|
| 5086 |
|
|
[(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
|
| 5087 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5088 |
|
|
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
|
| 5089 |
|
|
|
| 5090 |
|
|
|
| 5091 |
|
|
;
|
| 5092 |
|
|
; andsi3 instruction pattern(s).
|
| 5093 |
|
|
;
|
| 5094 |
|
|
|
| 5095 |
|
|
(define_insn "*andsi3_cc"
|
| 5096 |
|
|
[(set (reg CC_REGNUM)
|
| 5097 |
|
|
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5098 |
|
|
(match_operand:SI 2 "general_operand" "Os,d,R,T"))
|
| 5099 |
|
|
(const_int 0)))
|
| 5100 |
|
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
| 5101 |
|
|
(and:SI (match_dup 1) (match_dup 2)))]
|
| 5102 |
|
|
"s390_match_ccmode(insn, CCTmode)"
|
| 5103 |
|
|
"@
|
| 5104 |
|
|
nilf\t%0,%o2
|
| 5105 |
|
|
nr\t%0,%2
|
| 5106 |
|
|
n\t%0,%2
|
| 5107 |
|
|
ny\t%0,%2"
|
| 5108 |
|
|
[(set_attr "op_type" "RIL,RR,RX,RXY")])
|
| 5109 |
|
|
|
| 5110 |
|
|
(define_insn "*andsi3_cconly"
|
| 5111 |
|
|
[(set (reg CC_REGNUM)
|
| 5112 |
|
|
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5113 |
|
|
(match_operand:SI 2 "general_operand" "Os,d,R,T"))
|
| 5114 |
|
|
(const_int 0)))
|
| 5115 |
|
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
| 5116 |
|
|
"s390_match_ccmode(insn, CCTmode)
|
| 5117 |
|
|
/* Do not steal TM patterns. */
|
| 5118 |
|
|
&& s390_single_part (operands[2], SImode, HImode, 0) < 0"
|
| 5119 |
|
|
"@
|
| 5120 |
|
|
nilf\t%0,%o2
|
| 5121 |
|
|
nr\t%0,%2
|
| 5122 |
|
|
n\t%0,%2
|
| 5123 |
|
|
ny\t%0,%2"
|
| 5124 |
|
|
[(set_attr "op_type" "RIL,RR,RX,RXY")])
|
| 5125 |
|
|
|
| 5126 |
|
|
(define_insn "*andsi3_zarch"
|
| 5127 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
|
| 5128 |
|
|
(and:SI (match_operand:SI 1 "nonimmediate_operand"
|
| 5129 |
|
|
"%d,o,0,0,0,0,0,0,0,0")
|
| 5130 |
|
|
(match_operand:SI 2 "general_operand"
|
| 5131 |
|
|
"M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
|
| 5132 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5133 |
|
|
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5134 |
|
|
"@
|
| 5135 |
|
|
#
|
| 5136 |
|
|
#
|
| 5137 |
|
|
nilh\t%0,%j2
|
| 5138 |
|
|
nill\t%0,%j2
|
| 5139 |
|
|
nilf\t%0,%o2
|
| 5140 |
|
|
nr\t%0,%2
|
| 5141 |
|
|
n\t%0,%2
|
| 5142 |
|
|
ny\t%0,%2
|
| 5143 |
|
|
#
|
| 5144 |
|
|
#"
|
| 5145 |
|
|
[(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
|
| 5146 |
|
|
|
| 5147 |
|
|
(define_insn "*andsi3_esa"
|
| 5148 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
|
| 5149 |
|
|
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5150 |
|
|
(match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
|
| 5151 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5152 |
|
|
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5153 |
|
|
"@
|
| 5154 |
|
|
nr\t%0,%2
|
| 5155 |
|
|
n\t%0,%2
|
| 5156 |
|
|
#
|
| 5157 |
|
|
#"
|
| 5158 |
|
|
[(set_attr "op_type" "RR,RX,SI,SS")])
|
| 5159 |
|
|
|
| 5160 |
|
|
(define_split
|
| 5161 |
|
|
[(set (match_operand:SI 0 "s_operand" "")
|
| 5162 |
|
|
(and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
|
| 5163 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5164 |
|
|
"reload_completed"
|
| 5165 |
|
|
[(parallel
|
| 5166 |
|
|
[(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
|
| 5167 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5168 |
|
|
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
|
| 5169 |
|
|
|
| 5170 |
|
|
;
|
| 5171 |
|
|
; andhi3 instruction pattern(s).
|
| 5172 |
|
|
;
|
| 5173 |
|
|
|
| 5174 |
|
|
(define_insn "*andhi3_zarch"
|
| 5175 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
|
| 5176 |
|
|
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5177 |
|
|
(match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
|
| 5178 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5179 |
|
|
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5180 |
|
|
"@
|
| 5181 |
|
|
nr\t%0,%2
|
| 5182 |
|
|
nill\t%0,%x2
|
| 5183 |
|
|
#
|
| 5184 |
|
|
#"
|
| 5185 |
|
|
[(set_attr "op_type" "RR,RI,SI,SS")])
|
| 5186 |
|
|
|
| 5187 |
|
|
(define_insn "*andhi3_esa"
|
| 5188 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
|
| 5189 |
|
|
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
|
| 5190 |
|
|
(match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
|
| 5191 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5192 |
|
|
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5193 |
|
|
"@
|
| 5194 |
|
|
nr\t%0,%2
|
| 5195 |
|
|
#
|
| 5196 |
|
|
#"
|
| 5197 |
|
|
[(set_attr "op_type" "RR,SI,SS")])
|
| 5198 |
|
|
|
| 5199 |
|
|
(define_split
|
| 5200 |
|
|
[(set (match_operand:HI 0 "s_operand" "")
|
| 5201 |
|
|
(and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
|
| 5202 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5203 |
|
|
"reload_completed"
|
| 5204 |
|
|
[(parallel
|
| 5205 |
|
|
[(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
|
| 5206 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5207 |
|
|
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
|
| 5208 |
|
|
|
| 5209 |
|
|
;
|
| 5210 |
|
|
; andqi3 instruction pattern(s).
|
| 5211 |
|
|
;
|
| 5212 |
|
|
|
| 5213 |
|
|
(define_insn "*andqi3_zarch"
|
| 5214 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
|
| 5215 |
|
|
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
|
| 5216 |
|
|
(match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
|
| 5217 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5218 |
|
|
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5219 |
|
|
"@
|
| 5220 |
|
|
nr\t%0,%2
|
| 5221 |
|
|
nill\t%0,%b2
|
| 5222 |
|
|
ni\t%S0,%b2
|
| 5223 |
|
|
niy\t%S0,%b2
|
| 5224 |
|
|
#"
|
| 5225 |
|
|
[(set_attr "op_type" "RR,RI,SI,SIY,SS")])
|
| 5226 |
|
|
|
| 5227 |
|
|
(define_insn "*andqi3_esa"
|
| 5228 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
|
| 5229 |
|
|
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
|
| 5230 |
|
|
(match_operand:QI 2 "general_operand" "d,n,Q")))
|
| 5231 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5232 |
|
|
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5233 |
|
|
"@
|
| 5234 |
|
|
nr\t%0,%2
|
| 5235 |
|
|
ni\t%S0,%b2
|
| 5236 |
|
|
#"
|
| 5237 |
|
|
[(set_attr "op_type" "RR,SI,SS")])
|
| 5238 |
|
|
|
| 5239 |
|
|
;
|
| 5240 |
|
|
; Block and (NC) patterns.
|
| 5241 |
|
|
;
|
| 5242 |
|
|
|
| 5243 |
|
|
(define_insn "*nc"
|
| 5244 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "=Q")
|
| 5245 |
|
|
(and:BLK (match_dup 0)
|
| 5246 |
|
|
(match_operand:BLK 1 "memory_operand" "Q")))
|
| 5247 |
|
|
(use (match_operand 2 "const_int_operand" "n"))
|
| 5248 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5249 |
|
|
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
|
| 5250 |
|
|
"nc\t%O0(%2,%R0),%S1"
|
| 5251 |
|
|
[(set_attr "op_type" "SS")])
|
| 5252 |
|
|
|
| 5253 |
|
|
(define_split
|
| 5254 |
|
|
[(set (match_operand 0 "memory_operand" "")
|
| 5255 |
|
|
(and (match_dup 0)
|
| 5256 |
|
|
(match_operand 1 "memory_operand" "")))
|
| 5257 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5258 |
|
|
"reload_completed
|
| 5259 |
|
|
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
|
| 5260 |
|
|
&& GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
|
| 5261 |
|
|
[(parallel
|
| 5262 |
|
|
[(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
|
| 5263 |
|
|
(use (match_dup 2))
|
| 5264 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5265 |
|
|
{
|
| 5266 |
|
|
operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
|
| 5267 |
|
|
operands[0] = adjust_address (operands[0], BLKmode, 0);
|
| 5268 |
|
|
operands[1] = adjust_address (operands[1], BLKmode, 0);
|
| 5269 |
|
|
})
|
| 5270 |
|
|
|
| 5271 |
|
|
(define_peephole2
|
| 5272 |
|
|
[(parallel
|
| 5273 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 5274 |
|
|
(and:BLK (match_dup 0)
|
| 5275 |
|
|
(match_operand:BLK 1 "memory_operand" "")))
|
| 5276 |
|
|
(use (match_operand 2 "const_int_operand" ""))
|
| 5277 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 5278 |
|
|
(parallel
|
| 5279 |
|
|
[(set (match_operand:BLK 3 "memory_operand" "")
|
| 5280 |
|
|
(and:BLK (match_dup 3)
|
| 5281 |
|
|
(match_operand:BLK 4 "memory_operand" "")))
|
| 5282 |
|
|
(use (match_operand 5 "const_int_operand" ""))
|
| 5283 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5284 |
|
|
"s390_offset_p (operands[0], operands[3], operands[2])
|
| 5285 |
|
|
&& s390_offset_p (operands[1], operands[4], operands[2])
|
| 5286 |
|
|
&& !s390_overlap_p (operands[0], operands[1],
|
| 5287 |
|
|
INTVAL (operands[2]) + INTVAL (operands[5]))
|
| 5288 |
|
|
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
|
| 5289 |
|
|
[(parallel
|
| 5290 |
|
|
[(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
|
| 5291 |
|
|
(use (match_dup 8))
|
| 5292 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5293 |
|
|
"operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
|
| 5294 |
|
|
operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
|
| 5295 |
|
|
operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
|
| 5296 |
|
|
|
| 5297 |
|
|
|
| 5298 |
|
|
;;
|
| 5299 |
|
|
;;- Bit set (inclusive or) instructions.
|
| 5300 |
|
|
;;
|
| 5301 |
|
|
|
| 5302 |
|
|
(define_expand "ior3"
|
| 5303 |
|
|
[(set (match_operand:INT 0 "nonimmediate_operand" "")
|
| 5304 |
|
|
(ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
|
| 5305 |
|
|
(match_operand:INT 2 "general_operand" "")))
|
| 5306 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5307 |
|
|
""
|
| 5308 |
|
|
"s390_expand_logical_operator (IOR, mode, operands); DONE;")
|
| 5309 |
|
|
|
| 5310 |
|
|
;
|
| 5311 |
|
|
; iordi3 instruction pattern(s).
|
| 5312 |
|
|
;
|
| 5313 |
|
|
|
| 5314 |
|
|
(define_insn "*iordi3_cc"
|
| 5315 |
|
|
[(set (reg CC_REGNUM)
|
| 5316 |
|
|
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
|
| 5317 |
|
|
(match_operand:DI 2 "general_operand" "d,m"))
|
| 5318 |
|
|
(const_int 0)))
|
| 5319 |
|
|
(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 5320 |
|
|
(ior:DI (match_dup 1) (match_dup 2)))]
|
| 5321 |
|
|
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
|
| 5322 |
|
|
"@
|
| 5323 |
|
|
ogr\t%0,%2
|
| 5324 |
|
|
og\t%0,%2"
|
| 5325 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 5326 |
|
|
|
| 5327 |
|
|
(define_insn "*iordi3_cconly"
|
| 5328 |
|
|
[(set (reg CC_REGNUM)
|
| 5329 |
|
|
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
|
| 5330 |
|
|
(match_operand:DI 2 "general_operand" "d,m"))
|
| 5331 |
|
|
(const_int 0)))
|
| 5332 |
|
|
(clobber (match_scratch:DI 0 "=d,d"))]
|
| 5333 |
|
|
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
|
| 5334 |
|
|
"@
|
| 5335 |
|
|
ogr\t%0,%2
|
| 5336 |
|
|
og\t%0,%2"
|
| 5337 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 5338 |
|
|
|
| 5339 |
|
|
(define_insn "*iordi3_extimm"
|
| 5340 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
|
| 5341 |
|
|
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
|
| 5342 |
|
|
(match_operand:DI 2 "general_operand"
|
| 5343 |
|
|
"N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
|
| 5344 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5345 |
|
|
"TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
|
| 5346 |
|
|
"@
|
| 5347 |
|
|
oihh\t%0,%i2
|
| 5348 |
|
|
oihl\t%0,%i2
|
| 5349 |
|
|
oilh\t%0,%i2
|
| 5350 |
|
|
oill\t%0,%i2
|
| 5351 |
|
|
oihf\t%0,%k2
|
| 5352 |
|
|
oilf\t%0,%k2
|
| 5353 |
|
|
ogr\t%0,%2
|
| 5354 |
|
|
og\t%0,%2
|
| 5355 |
|
|
#
|
| 5356 |
|
|
#"
|
| 5357 |
|
|
[(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
|
| 5358 |
|
|
|
| 5359 |
|
|
(define_insn "*iordi3"
|
| 5360 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
|
| 5361 |
|
|
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
|
| 5362 |
|
|
(match_operand:DI 2 "general_operand"
|
| 5363 |
|
|
"N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
|
| 5364 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5365 |
|
|
"TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
|
| 5366 |
|
|
"@
|
| 5367 |
|
|
oihh\t%0,%i2
|
| 5368 |
|
|
oihl\t%0,%i2
|
| 5369 |
|
|
oilh\t%0,%i2
|
| 5370 |
|
|
oill\t%0,%i2
|
| 5371 |
|
|
ogr\t%0,%2
|
| 5372 |
|
|
og\t%0,%2
|
| 5373 |
|
|
#
|
| 5374 |
|
|
#"
|
| 5375 |
|
|
[(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
|
| 5376 |
|
|
|
| 5377 |
|
|
(define_split
|
| 5378 |
|
|
[(set (match_operand:DI 0 "s_operand" "")
|
| 5379 |
|
|
(ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
|
| 5380 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5381 |
|
|
"reload_completed"
|
| 5382 |
|
|
[(parallel
|
| 5383 |
|
|
[(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
|
| 5384 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5385 |
|
|
"s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
|
| 5386 |
|
|
|
| 5387 |
|
|
;
|
| 5388 |
|
|
; iorsi3 instruction pattern(s).
|
| 5389 |
|
|
;
|
| 5390 |
|
|
|
| 5391 |
|
|
(define_insn "*iorsi3_cc"
|
| 5392 |
|
|
[(set (reg CC_REGNUM)
|
| 5393 |
|
|
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5394 |
|
|
(match_operand:SI 2 "general_operand" "Os,d,R,T"))
|
| 5395 |
|
|
(const_int 0)))
|
| 5396 |
|
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
| 5397 |
|
|
(ior:SI (match_dup 1) (match_dup 2)))]
|
| 5398 |
|
|
"s390_match_ccmode(insn, CCTmode)"
|
| 5399 |
|
|
"@
|
| 5400 |
|
|
oilf\t%0,%o2
|
| 5401 |
|
|
or\t%0,%2
|
| 5402 |
|
|
o\t%0,%2
|
| 5403 |
|
|
oy\t%0,%2"
|
| 5404 |
|
|
[(set_attr "op_type" "RIL,RR,RX,RXY")])
|
| 5405 |
|
|
|
| 5406 |
|
|
(define_insn "*iorsi3_cconly"
|
| 5407 |
|
|
[(set (reg CC_REGNUM)
|
| 5408 |
|
|
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5409 |
|
|
(match_operand:SI 2 "general_operand" "Os,d,R,T"))
|
| 5410 |
|
|
(const_int 0)))
|
| 5411 |
|
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
| 5412 |
|
|
"s390_match_ccmode(insn, CCTmode)"
|
| 5413 |
|
|
"@
|
| 5414 |
|
|
oilf\t%0,%o2
|
| 5415 |
|
|
or\t%0,%2
|
| 5416 |
|
|
o\t%0,%2
|
| 5417 |
|
|
oy\t%0,%2"
|
| 5418 |
|
|
[(set_attr "op_type" "RIL,RR,RX,RXY")])
|
| 5419 |
|
|
|
| 5420 |
|
|
(define_insn "*iorsi3_zarch"
|
| 5421 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
|
| 5422 |
|
|
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
|
| 5423 |
|
|
(match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
|
| 5424 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5425 |
|
|
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5426 |
|
|
"@
|
| 5427 |
|
|
oilh\t%0,%i2
|
| 5428 |
|
|
oill\t%0,%i2
|
| 5429 |
|
|
oilf\t%0,%o2
|
| 5430 |
|
|
or\t%0,%2
|
| 5431 |
|
|
o\t%0,%2
|
| 5432 |
|
|
oy\t%0,%2
|
| 5433 |
|
|
#
|
| 5434 |
|
|
#"
|
| 5435 |
|
|
[(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
|
| 5436 |
|
|
|
| 5437 |
|
|
(define_insn "*iorsi3_esa"
|
| 5438 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
|
| 5439 |
|
|
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5440 |
|
|
(match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
|
| 5441 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5442 |
|
|
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5443 |
|
|
"@
|
| 5444 |
|
|
or\t%0,%2
|
| 5445 |
|
|
o\t%0,%2
|
| 5446 |
|
|
#
|
| 5447 |
|
|
#"
|
| 5448 |
|
|
[(set_attr "op_type" "RR,RX,SI,SS")])
|
| 5449 |
|
|
|
| 5450 |
|
|
(define_split
|
| 5451 |
|
|
[(set (match_operand:SI 0 "s_operand" "")
|
| 5452 |
|
|
(ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
|
| 5453 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5454 |
|
|
"reload_completed"
|
| 5455 |
|
|
[(parallel
|
| 5456 |
|
|
[(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
|
| 5457 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5458 |
|
|
"s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
|
| 5459 |
|
|
|
| 5460 |
|
|
;
|
| 5461 |
|
|
; iorhi3 instruction pattern(s).
|
| 5462 |
|
|
;
|
| 5463 |
|
|
|
| 5464 |
|
|
(define_insn "*iorhi3_zarch"
|
| 5465 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
|
| 5466 |
|
|
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5467 |
|
|
(match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
|
| 5468 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5469 |
|
|
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5470 |
|
|
"@
|
| 5471 |
|
|
or\t%0,%2
|
| 5472 |
|
|
oill\t%0,%x2
|
| 5473 |
|
|
#
|
| 5474 |
|
|
#"
|
| 5475 |
|
|
[(set_attr "op_type" "RR,RI,SI,SS")])
|
| 5476 |
|
|
|
| 5477 |
|
|
(define_insn "*iorhi3_esa"
|
| 5478 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
|
| 5479 |
|
|
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
|
| 5480 |
|
|
(match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
|
| 5481 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5482 |
|
|
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5483 |
|
|
"@
|
| 5484 |
|
|
or\t%0,%2
|
| 5485 |
|
|
#
|
| 5486 |
|
|
#"
|
| 5487 |
|
|
[(set_attr "op_type" "RR,SI,SS")])
|
| 5488 |
|
|
|
| 5489 |
|
|
(define_split
|
| 5490 |
|
|
[(set (match_operand:HI 0 "s_operand" "")
|
| 5491 |
|
|
(ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
|
| 5492 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5493 |
|
|
"reload_completed"
|
| 5494 |
|
|
[(parallel
|
| 5495 |
|
|
[(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
|
| 5496 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5497 |
|
|
"s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
|
| 5498 |
|
|
|
| 5499 |
|
|
;
|
| 5500 |
|
|
; iorqi3 instruction pattern(s).
|
| 5501 |
|
|
;
|
| 5502 |
|
|
|
| 5503 |
|
|
(define_insn "*iorqi3_zarch"
|
| 5504 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
|
| 5505 |
|
|
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
|
| 5506 |
|
|
(match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
|
| 5507 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5508 |
|
|
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5509 |
|
|
"@
|
| 5510 |
|
|
or\t%0,%2
|
| 5511 |
|
|
oill\t%0,%b2
|
| 5512 |
|
|
oi\t%S0,%b2
|
| 5513 |
|
|
oiy\t%S0,%b2
|
| 5514 |
|
|
#"
|
| 5515 |
|
|
[(set_attr "op_type" "RR,RI,SI,SIY,SS")])
|
| 5516 |
|
|
|
| 5517 |
|
|
(define_insn "*iorqi3_esa"
|
| 5518 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
|
| 5519 |
|
|
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
|
| 5520 |
|
|
(match_operand:QI 2 "general_operand" "d,n,Q")))
|
| 5521 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5522 |
|
|
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
|
| 5523 |
|
|
"@
|
| 5524 |
|
|
or\t%0,%2
|
| 5525 |
|
|
oi\t%S0,%b2
|
| 5526 |
|
|
#"
|
| 5527 |
|
|
[(set_attr "op_type" "RR,SI,SS")])
|
| 5528 |
|
|
|
| 5529 |
|
|
;
|
| 5530 |
|
|
; Block inclusive or (OC) patterns.
|
| 5531 |
|
|
;
|
| 5532 |
|
|
|
| 5533 |
|
|
(define_insn "*oc"
|
| 5534 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "=Q")
|
| 5535 |
|
|
(ior:BLK (match_dup 0)
|
| 5536 |
|
|
(match_operand:BLK 1 "memory_operand" "Q")))
|
| 5537 |
|
|
(use (match_operand 2 "const_int_operand" "n"))
|
| 5538 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5539 |
|
|
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
|
| 5540 |
|
|
"oc\t%O0(%2,%R0),%S1"
|
| 5541 |
|
|
[(set_attr "op_type" "SS")])
|
| 5542 |
|
|
|
| 5543 |
|
|
(define_split
|
| 5544 |
|
|
[(set (match_operand 0 "memory_operand" "")
|
| 5545 |
|
|
(ior (match_dup 0)
|
| 5546 |
|
|
(match_operand 1 "memory_operand" "")))
|
| 5547 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5548 |
|
|
"reload_completed
|
| 5549 |
|
|
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
|
| 5550 |
|
|
&& GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
|
| 5551 |
|
|
[(parallel
|
| 5552 |
|
|
[(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
|
| 5553 |
|
|
(use (match_dup 2))
|
| 5554 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5555 |
|
|
{
|
| 5556 |
|
|
operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
|
| 5557 |
|
|
operands[0] = adjust_address (operands[0], BLKmode, 0);
|
| 5558 |
|
|
operands[1] = adjust_address (operands[1], BLKmode, 0);
|
| 5559 |
|
|
})
|
| 5560 |
|
|
|
| 5561 |
|
|
(define_peephole2
|
| 5562 |
|
|
[(parallel
|
| 5563 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 5564 |
|
|
(ior:BLK (match_dup 0)
|
| 5565 |
|
|
(match_operand:BLK 1 "memory_operand" "")))
|
| 5566 |
|
|
(use (match_operand 2 "const_int_operand" ""))
|
| 5567 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 5568 |
|
|
(parallel
|
| 5569 |
|
|
[(set (match_operand:BLK 3 "memory_operand" "")
|
| 5570 |
|
|
(ior:BLK (match_dup 3)
|
| 5571 |
|
|
(match_operand:BLK 4 "memory_operand" "")))
|
| 5572 |
|
|
(use (match_operand 5 "const_int_operand" ""))
|
| 5573 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5574 |
|
|
"s390_offset_p (operands[0], operands[3], operands[2])
|
| 5575 |
|
|
&& s390_offset_p (operands[1], operands[4], operands[2])
|
| 5576 |
|
|
&& !s390_overlap_p (operands[0], operands[1],
|
| 5577 |
|
|
INTVAL (operands[2]) + INTVAL (operands[5]))
|
| 5578 |
|
|
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
|
| 5579 |
|
|
[(parallel
|
| 5580 |
|
|
[(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
|
| 5581 |
|
|
(use (match_dup 8))
|
| 5582 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5583 |
|
|
"operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
|
| 5584 |
|
|
operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
|
| 5585 |
|
|
operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
|
| 5586 |
|
|
|
| 5587 |
|
|
|
| 5588 |
|
|
;;
|
| 5589 |
|
|
;;- Xor instructions.
|
| 5590 |
|
|
;;
|
| 5591 |
|
|
|
| 5592 |
|
|
(define_expand "xor3"
|
| 5593 |
|
|
[(set (match_operand:INT 0 "nonimmediate_operand" "")
|
| 5594 |
|
|
(xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
|
| 5595 |
|
|
(match_operand:INT 2 "general_operand" "")))
|
| 5596 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5597 |
|
|
""
|
| 5598 |
|
|
"s390_expand_logical_operator (XOR, mode, operands); DONE;")
|
| 5599 |
|
|
|
| 5600 |
|
|
;
|
| 5601 |
|
|
; xordi3 instruction pattern(s).
|
| 5602 |
|
|
;
|
| 5603 |
|
|
|
| 5604 |
|
|
(define_insn "*xordi3_cc"
|
| 5605 |
|
|
[(set (reg CC_REGNUM)
|
| 5606 |
|
|
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
|
| 5607 |
|
|
(match_operand:DI 2 "general_operand" "d,m"))
|
| 5608 |
|
|
(const_int 0)))
|
| 5609 |
|
|
(set (match_operand:DI 0 "register_operand" "=d,d")
|
| 5610 |
|
|
(xor:DI (match_dup 1) (match_dup 2)))]
|
| 5611 |
|
|
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
|
| 5612 |
|
|
"@
|
| 5613 |
|
|
xgr\t%0,%2
|
| 5614 |
|
|
xg\t%0,%2"
|
| 5615 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 5616 |
|
|
|
| 5617 |
|
|
(define_insn "*xordi3_cconly"
|
| 5618 |
|
|
[(set (reg CC_REGNUM)
|
| 5619 |
|
|
(compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
|
| 5620 |
|
|
(match_operand:DI 2 "general_operand" "d,m"))
|
| 5621 |
|
|
(const_int 0)))
|
| 5622 |
|
|
(clobber (match_scratch:DI 0 "=d,d"))]
|
| 5623 |
|
|
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
|
| 5624 |
|
|
"@
|
| 5625 |
|
|
xgr\t%0,%2
|
| 5626 |
|
|
xg\t%0,%2"
|
| 5627 |
|
|
[(set_attr "op_type" "RRE,RXY")])
|
| 5628 |
|
|
|
| 5629 |
|
|
(define_insn "*xordi3_extimm"
|
| 5630 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
|
| 5631 |
|
|
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
|
| 5632 |
|
|
(match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
|
| 5633 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5634 |
|
|
"TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
|
| 5635 |
|
|
"@
|
| 5636 |
|
|
xihf\t%0,%k2
|
| 5637 |
|
|
xilf\t%0,%k2
|
| 5638 |
|
|
xgr\t%0,%2
|
| 5639 |
|
|
xg\t%0,%2
|
| 5640 |
|
|
#
|
| 5641 |
|
|
#"
|
| 5642 |
|
|
[(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
|
| 5643 |
|
|
|
| 5644 |
|
|
(define_insn "*xordi3"
|
| 5645 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
|
| 5646 |
|
|
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5647 |
|
|
(match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
|
| 5648 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5649 |
|
|
"TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
|
| 5650 |
|
|
"@
|
| 5651 |
|
|
xgr\t%0,%2
|
| 5652 |
|
|
xg\t%0,%2
|
| 5653 |
|
|
#
|
| 5654 |
|
|
#"
|
| 5655 |
|
|
[(set_attr "op_type" "RRE,RXY,SI,SS")])
|
| 5656 |
|
|
|
| 5657 |
|
|
(define_split
|
| 5658 |
|
|
[(set (match_operand:DI 0 "s_operand" "")
|
| 5659 |
|
|
(xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
|
| 5660 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5661 |
|
|
"reload_completed"
|
| 5662 |
|
|
[(parallel
|
| 5663 |
|
|
[(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
|
| 5664 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5665 |
|
|
"s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
|
| 5666 |
|
|
|
| 5667 |
|
|
;
|
| 5668 |
|
|
; xorsi3 instruction pattern(s).
|
| 5669 |
|
|
;
|
| 5670 |
|
|
|
| 5671 |
|
|
(define_insn "*xorsi3_cc"
|
| 5672 |
|
|
[(set (reg CC_REGNUM)
|
| 5673 |
|
|
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5674 |
|
|
(match_operand:SI 2 "general_operand" "Os,d,R,T"))
|
| 5675 |
|
|
(const_int 0)))
|
| 5676 |
|
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
| 5677 |
|
|
(xor:SI (match_dup 1) (match_dup 2)))]
|
| 5678 |
|
|
"s390_match_ccmode(insn, CCTmode)"
|
| 5679 |
|
|
"@
|
| 5680 |
|
|
xilf\t%0,%o2
|
| 5681 |
|
|
xr\t%0,%2
|
| 5682 |
|
|
x\t%0,%2
|
| 5683 |
|
|
xy\t%0,%2"
|
| 5684 |
|
|
[(set_attr "op_type" "RIL,RR,RX,RXY")])
|
| 5685 |
|
|
|
| 5686 |
|
|
(define_insn "*xorsi3_cconly"
|
| 5687 |
|
|
[(set (reg CC_REGNUM)
|
| 5688 |
|
|
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5689 |
|
|
(match_operand:SI 2 "general_operand" "Os,d,R,T"))
|
| 5690 |
|
|
(const_int 0)))
|
| 5691 |
|
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
| 5692 |
|
|
"s390_match_ccmode(insn, CCTmode)"
|
| 5693 |
|
|
"@
|
| 5694 |
|
|
xilf\t%0,%o2
|
| 5695 |
|
|
xr\t%0,%2
|
| 5696 |
|
|
x\t%0,%2
|
| 5697 |
|
|
xy\t%0,%2"
|
| 5698 |
|
|
[(set_attr "op_type" "RIL,RR,RX,RXY")])
|
| 5699 |
|
|
|
| 5700 |
|
|
(define_insn "*xorsi3"
|
| 5701 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
|
| 5702 |
|
|
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
|
| 5703 |
|
|
(match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
|
| 5704 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5705 |
|
|
"s390_logical_operator_ok_p (operands)"
|
| 5706 |
|
|
"@
|
| 5707 |
|
|
xilf\t%0,%o2
|
| 5708 |
|
|
xr\t%0,%2
|
| 5709 |
|
|
x\t%0,%2
|
| 5710 |
|
|
xy\t%0,%2
|
| 5711 |
|
|
#
|
| 5712 |
|
|
#"
|
| 5713 |
|
|
[(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
|
| 5714 |
|
|
|
| 5715 |
|
|
(define_split
|
| 5716 |
|
|
[(set (match_operand:SI 0 "s_operand" "")
|
| 5717 |
|
|
(xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
|
| 5718 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5719 |
|
|
"reload_completed"
|
| 5720 |
|
|
[(parallel
|
| 5721 |
|
|
[(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
|
| 5722 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5723 |
|
|
"s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
|
| 5724 |
|
|
|
| 5725 |
|
|
;
|
| 5726 |
|
|
; xorhi3 instruction pattern(s).
|
| 5727 |
|
|
;
|
| 5728 |
|
|
|
| 5729 |
|
|
(define_insn "*xorhi3"
|
| 5730 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
|
| 5731 |
|
|
(xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
|
| 5732 |
|
|
(match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
|
| 5733 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5734 |
|
|
"s390_logical_operator_ok_p (operands)"
|
| 5735 |
|
|
"@
|
| 5736 |
|
|
xilf\t%0,%x2
|
| 5737 |
|
|
xr\t%0,%2
|
| 5738 |
|
|
#
|
| 5739 |
|
|
#"
|
| 5740 |
|
|
[(set_attr "op_type" "RIL,RR,SI,SS")])
|
| 5741 |
|
|
|
| 5742 |
|
|
(define_split
|
| 5743 |
|
|
[(set (match_operand:HI 0 "s_operand" "")
|
| 5744 |
|
|
(xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
|
| 5745 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5746 |
|
|
"reload_completed"
|
| 5747 |
|
|
[(parallel
|
| 5748 |
|
|
[(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
|
| 5749 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5750 |
|
|
"s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
|
| 5751 |
|
|
|
| 5752 |
|
|
;
|
| 5753 |
|
|
; xorqi3 instruction pattern(s).
|
| 5754 |
|
|
;
|
| 5755 |
|
|
|
| 5756 |
|
|
(define_insn "*xorqi3"
|
| 5757 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
|
| 5758 |
|
|
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
|
| 5759 |
|
|
(match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
|
| 5760 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5761 |
|
|
"s390_logical_operator_ok_p (operands)"
|
| 5762 |
|
|
"@
|
| 5763 |
|
|
xilf\t%0,%b2
|
| 5764 |
|
|
xr\t%0,%2
|
| 5765 |
|
|
xi\t%S0,%b2
|
| 5766 |
|
|
xiy\t%S0,%b2
|
| 5767 |
|
|
#"
|
| 5768 |
|
|
[(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
|
| 5769 |
|
|
|
| 5770 |
|
|
;
|
| 5771 |
|
|
; Block exclusive or (XC) patterns.
|
| 5772 |
|
|
;
|
| 5773 |
|
|
|
| 5774 |
|
|
(define_insn "*xc"
|
| 5775 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "=Q")
|
| 5776 |
|
|
(xor:BLK (match_dup 0)
|
| 5777 |
|
|
(match_operand:BLK 1 "memory_operand" "Q")))
|
| 5778 |
|
|
(use (match_operand 2 "const_int_operand" "n"))
|
| 5779 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5780 |
|
|
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
|
| 5781 |
|
|
"xc\t%O0(%2,%R0),%S1"
|
| 5782 |
|
|
[(set_attr "op_type" "SS")])
|
| 5783 |
|
|
|
| 5784 |
|
|
(define_split
|
| 5785 |
|
|
[(set (match_operand 0 "memory_operand" "")
|
| 5786 |
|
|
(xor (match_dup 0)
|
| 5787 |
|
|
(match_operand 1 "memory_operand" "")))
|
| 5788 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5789 |
|
|
"reload_completed
|
| 5790 |
|
|
&& GET_MODE (operands[0]) == GET_MODE (operands[1])
|
| 5791 |
|
|
&& GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
|
| 5792 |
|
|
[(parallel
|
| 5793 |
|
|
[(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
|
| 5794 |
|
|
(use (match_dup 2))
|
| 5795 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5796 |
|
|
{
|
| 5797 |
|
|
operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
|
| 5798 |
|
|
operands[0] = adjust_address (operands[0], BLKmode, 0);
|
| 5799 |
|
|
operands[1] = adjust_address (operands[1], BLKmode, 0);
|
| 5800 |
|
|
})
|
| 5801 |
|
|
|
| 5802 |
|
|
(define_peephole2
|
| 5803 |
|
|
[(parallel
|
| 5804 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 5805 |
|
|
(xor:BLK (match_dup 0)
|
| 5806 |
|
|
(match_operand:BLK 1 "memory_operand" "")))
|
| 5807 |
|
|
(use (match_operand 2 "const_int_operand" ""))
|
| 5808 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 5809 |
|
|
(parallel
|
| 5810 |
|
|
[(set (match_operand:BLK 3 "memory_operand" "")
|
| 5811 |
|
|
(xor:BLK (match_dup 3)
|
| 5812 |
|
|
(match_operand:BLK 4 "memory_operand" "")))
|
| 5813 |
|
|
(use (match_operand 5 "const_int_operand" ""))
|
| 5814 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5815 |
|
|
"s390_offset_p (operands[0], operands[3], operands[2])
|
| 5816 |
|
|
&& s390_offset_p (operands[1], operands[4], operands[2])
|
| 5817 |
|
|
&& !s390_overlap_p (operands[0], operands[1],
|
| 5818 |
|
|
INTVAL (operands[2]) + INTVAL (operands[5]))
|
| 5819 |
|
|
&& INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
|
| 5820 |
|
|
[(parallel
|
| 5821 |
|
|
[(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
|
| 5822 |
|
|
(use (match_dup 8))
|
| 5823 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5824 |
|
|
"operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
|
| 5825 |
|
|
operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
|
| 5826 |
|
|
operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
|
| 5827 |
|
|
|
| 5828 |
|
|
;
|
| 5829 |
|
|
; Block xor (XC) patterns with src == dest.
|
| 5830 |
|
|
;
|
| 5831 |
|
|
|
| 5832 |
|
|
(define_insn "*xc_zero"
|
| 5833 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "=Q")
|
| 5834 |
|
|
(const_int 0))
|
| 5835 |
|
|
(use (match_operand 1 "const_int_operand" "n"))
|
| 5836 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5837 |
|
|
"INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
|
| 5838 |
|
|
"xc\t%O0(%1,%R0),%S0"
|
| 5839 |
|
|
[(set_attr "op_type" "SS")])
|
| 5840 |
|
|
|
| 5841 |
|
|
(define_peephole2
|
| 5842 |
|
|
[(parallel
|
| 5843 |
|
|
[(set (match_operand:BLK 0 "memory_operand" "")
|
| 5844 |
|
|
(const_int 0))
|
| 5845 |
|
|
(use (match_operand 1 "const_int_operand" ""))
|
| 5846 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 5847 |
|
|
(parallel
|
| 5848 |
|
|
[(set (match_operand:BLK 2 "memory_operand" "")
|
| 5849 |
|
|
(const_int 0))
|
| 5850 |
|
|
(use (match_operand 3 "const_int_operand" ""))
|
| 5851 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5852 |
|
|
"s390_offset_p (operands[0], operands[2], operands[1])
|
| 5853 |
|
|
&& INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
|
| 5854 |
|
|
[(parallel
|
| 5855 |
|
|
[(set (match_dup 4) (const_int 0))
|
| 5856 |
|
|
(use (match_dup 5))
|
| 5857 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5858 |
|
|
"operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
|
| 5859 |
|
|
operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
|
| 5860 |
|
|
|
| 5861 |
|
|
|
| 5862 |
|
|
;;
|
| 5863 |
|
|
;;- Negate instructions.
|
| 5864 |
|
|
;;
|
| 5865 |
|
|
|
| 5866 |
|
|
;
|
| 5867 |
|
|
; neg(di|si)2 instruction pattern(s).
|
| 5868 |
|
|
;
|
| 5869 |
|
|
|
| 5870 |
|
|
(define_expand "neg2"
|
| 5871 |
|
|
[(parallel
|
| 5872 |
|
|
[(set (match_operand:DSI 0 "register_operand" "=d")
|
| 5873 |
|
|
(neg:DSI (match_operand:DSI 1 "register_operand" "d")))
|
| 5874 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5875 |
|
|
""
|
| 5876 |
|
|
"")
|
| 5877 |
|
|
|
| 5878 |
|
|
(define_insn "*negdi2_sign_cc"
|
| 5879 |
|
|
[(set (reg CC_REGNUM)
|
| 5880 |
|
|
(compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
|
| 5881 |
|
|
(match_operand:SI 1 "register_operand" "d") 0)
|
| 5882 |
|
|
(const_int 32)) (const_int 32)))
|
| 5883 |
|
|
(const_int 0)))
|
| 5884 |
|
|
(set (match_operand:DI 0 "register_operand" "=d")
|
| 5885 |
|
|
(neg:DI (sign_extend:DI (match_dup 1))))]
|
| 5886 |
|
|
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
|
| 5887 |
|
|
"lcgfr\t%0,%1"
|
| 5888 |
|
|
[(set_attr "op_type" "RRE")])
|
| 5889 |
|
|
|
| 5890 |
|
|
(define_insn "*negdi2_sign"
|
| 5891 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 5892 |
|
|
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
|
| 5893 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5894 |
|
|
"TARGET_64BIT"
|
| 5895 |
|
|
"lcgfr\t%0,%1"
|
| 5896 |
|
|
[(set_attr "op_type" "RRE")])
|
| 5897 |
|
|
|
| 5898 |
|
|
; lcr, lcgr
|
| 5899 |
|
|
(define_insn "*neg2_cc"
|
| 5900 |
|
|
[(set (reg CC_REGNUM)
|
| 5901 |
|
|
(compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
|
| 5902 |
|
|
(const_int 0)))
|
| 5903 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d")
|
| 5904 |
|
|
(neg:GPR (match_dup 1)))]
|
| 5905 |
|
|
"s390_match_ccmode (insn, CCAmode)"
|
| 5906 |
|
|
"lcr\t%0,%1"
|
| 5907 |
|
|
[(set_attr "op_type" "RR")])
|
| 5908 |
|
|
|
| 5909 |
|
|
; lcr, lcgr
|
| 5910 |
|
|
(define_insn "*neg2_cconly"
|
| 5911 |
|
|
[(set (reg CC_REGNUM)
|
| 5912 |
|
|
(compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
|
| 5913 |
|
|
(const_int 0)))
|
| 5914 |
|
|
(clobber (match_scratch:GPR 0 "=d"))]
|
| 5915 |
|
|
"s390_match_ccmode (insn, CCAmode)"
|
| 5916 |
|
|
"lcr\t%0,%1"
|
| 5917 |
|
|
[(set_attr "op_type" "RR")])
|
| 5918 |
|
|
|
| 5919 |
|
|
; lcr, lcgr
|
| 5920 |
|
|
(define_insn "*neg2"
|
| 5921 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 5922 |
|
|
(neg:GPR (match_operand:GPR 1 "register_operand" "d")))
|
| 5923 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5924 |
|
|
""
|
| 5925 |
|
|
"lcr\t%0,%1"
|
| 5926 |
|
|
[(set_attr "op_type" "RR")])
|
| 5927 |
|
|
|
| 5928 |
|
|
(define_insn_and_split "*negdi2_31"
|
| 5929 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 5930 |
|
|
(neg:DI (match_operand:DI 1 "register_operand" "d")))
|
| 5931 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5932 |
|
|
"!TARGET_64BIT"
|
| 5933 |
|
|
"#"
|
| 5934 |
|
|
"&& reload_completed"
|
| 5935 |
|
|
[(parallel
|
| 5936 |
|
|
[(set (match_dup 2) (neg:SI (match_dup 3)))
|
| 5937 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 5938 |
|
|
(parallel
|
| 5939 |
|
|
[(set (reg:CCAP CC_REGNUM)
|
| 5940 |
|
|
(compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
|
| 5941 |
|
|
(set (match_dup 4) (neg:SI (match_dup 5)))])
|
| 5942 |
|
|
(set (pc)
|
| 5943 |
|
|
(if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
|
| 5944 |
|
|
(pc)
|
| 5945 |
|
|
(label_ref (match_dup 6))))
|
| 5946 |
|
|
(parallel
|
| 5947 |
|
|
[(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
|
| 5948 |
|
|
(clobber (reg:CC CC_REGNUM))])
|
| 5949 |
|
|
(match_dup 6)]
|
| 5950 |
|
|
"operands[2] = operand_subword (operands[0], 0, 0, DImode);
|
| 5951 |
|
|
operands[3] = operand_subword (operands[1], 0, 0, DImode);
|
| 5952 |
|
|
operands[4] = operand_subword (operands[0], 1, 0, DImode);
|
| 5953 |
|
|
operands[5] = operand_subword (operands[1], 1, 0, DImode);
|
| 5954 |
|
|
operands[6] = gen_label_rtx ();")
|
| 5955 |
|
|
|
| 5956 |
|
|
;
|
| 5957 |
|
|
; neg(df|sf)2 instruction pattern(s).
|
| 5958 |
|
|
;
|
| 5959 |
|
|
|
| 5960 |
|
|
(define_expand "neg2"
|
| 5961 |
|
|
[(parallel
|
| 5962 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 5963 |
|
|
(neg:FPR (match_operand:FPR 1 "register_operand" "f")))
|
| 5964 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 5965 |
|
|
"TARGET_HARD_FLOAT"
|
| 5966 |
|
|
"")
|
| 5967 |
|
|
|
| 5968 |
|
|
; lcxbr, lcdbr, lcebr
|
| 5969 |
|
|
(define_insn "*neg2_cc"
|
| 5970 |
|
|
[(set (reg CC_REGNUM)
|
| 5971 |
|
|
(compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
|
| 5972 |
|
|
(match_operand:FPR 2 "const0_operand" "")))
|
| 5973 |
|
|
(set (match_operand:FPR 0 "register_operand" "=f")
|
| 5974 |
|
|
(neg:FPR (match_dup 1)))]
|
| 5975 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 5976 |
|
|
"lcbr\t%0,%1"
|
| 5977 |
|
|
[(set_attr "op_type" "RRE")
|
| 5978 |
|
|
(set_attr "type" "fsimp")])
|
| 5979 |
|
|
|
| 5980 |
|
|
; lcxbr, lcdbr, lcebr
|
| 5981 |
|
|
(define_insn "*neg2_cconly"
|
| 5982 |
|
|
[(set (reg CC_REGNUM)
|
| 5983 |
|
|
(compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
|
| 5984 |
|
|
(match_operand:FPR 2 "const0_operand" "")))
|
| 5985 |
|
|
(clobber (match_scratch:FPR 0 "=f"))]
|
| 5986 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 5987 |
|
|
"lcbr\t%0,%1"
|
| 5988 |
|
|
[(set_attr "op_type" "RRE")
|
| 5989 |
|
|
(set_attr "type" "fsimp")])
|
| 5990 |
|
|
|
| 5991 |
|
|
; lcxbr, lcdbr, lcebr
|
| 5992 |
|
|
(define_insn "*neg2"
|
| 5993 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 5994 |
|
|
(neg:FPR (match_operand:FPR 1 "register_operand" "f")))
|
| 5995 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 5996 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 5997 |
|
|
"lcbr\t%0,%1"
|
| 5998 |
|
|
[(set_attr "op_type" "RRE")
|
| 5999 |
|
|
(set_attr "type" "fsimp")])
|
| 6000 |
|
|
|
| 6001 |
|
|
; lcxr, lcdr, lcer
|
| 6002 |
|
|
(define_insn "*neg2_ibm"
|
| 6003 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 6004 |
|
|
(neg:FPR (match_operand:FPR 1 "register_operand" "f")))
|
| 6005 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6006 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 6007 |
|
|
"lcr\t%0,%1"
|
| 6008 |
|
|
[(set_attr "op_type" "")
|
| 6009 |
|
|
(set_attr "type" "fsimp")])
|
| 6010 |
|
|
|
| 6011 |
|
|
|
| 6012 |
|
|
;;
|
| 6013 |
|
|
;;- Absolute value instructions.
|
| 6014 |
|
|
;;
|
| 6015 |
|
|
|
| 6016 |
|
|
;
|
| 6017 |
|
|
; abs(di|si)2 instruction pattern(s).
|
| 6018 |
|
|
;
|
| 6019 |
|
|
|
| 6020 |
|
|
(define_insn "*absdi2_sign_cc"
|
| 6021 |
|
|
[(set (reg CC_REGNUM)
|
| 6022 |
|
|
(compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
|
| 6023 |
|
|
(match_operand:SI 1 "register_operand" "d") 0)
|
| 6024 |
|
|
(const_int 32)) (const_int 32)))
|
| 6025 |
|
|
(const_int 0)))
|
| 6026 |
|
|
(set (match_operand:DI 0 "register_operand" "=d")
|
| 6027 |
|
|
(abs:DI (sign_extend:DI (match_dup 1))))]
|
| 6028 |
|
|
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
|
| 6029 |
|
|
"lpgfr\t%0,%1"
|
| 6030 |
|
|
[(set_attr "op_type" "RRE")])
|
| 6031 |
|
|
|
| 6032 |
|
|
(define_insn "*absdi2_sign"
|
| 6033 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 6034 |
|
|
(abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
|
| 6035 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6036 |
|
|
"TARGET_64BIT"
|
| 6037 |
|
|
"lpgfr\t%0,%1"
|
| 6038 |
|
|
[(set_attr "op_type" "RRE")])
|
| 6039 |
|
|
|
| 6040 |
|
|
; lpr, lpgr
|
| 6041 |
|
|
(define_insn "*abs2_cc"
|
| 6042 |
|
|
[(set (reg CC_REGNUM)
|
| 6043 |
|
|
(compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
|
| 6044 |
|
|
(const_int 0)))
|
| 6045 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6046 |
|
|
(abs:GPR (match_dup 1)))]
|
| 6047 |
|
|
"s390_match_ccmode (insn, CCAmode)"
|
| 6048 |
|
|
"lpr\t%0,%1"
|
| 6049 |
|
|
[(set_attr "op_type" "RR")])
|
| 6050 |
|
|
|
| 6051 |
|
|
; lpr, lpgr
|
| 6052 |
|
|
(define_insn "*abs2_cconly"
|
| 6053 |
|
|
[(set (reg CC_REGNUM)
|
| 6054 |
|
|
(compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
|
| 6055 |
|
|
(const_int 0)))
|
| 6056 |
|
|
(clobber (match_scratch:GPR 0 "=d"))]
|
| 6057 |
|
|
"s390_match_ccmode (insn, CCAmode)"
|
| 6058 |
|
|
"lpr\t%0,%1"
|
| 6059 |
|
|
[(set_attr "op_type" "RR")])
|
| 6060 |
|
|
|
| 6061 |
|
|
; lpr, lpgr
|
| 6062 |
|
|
(define_insn "abs2"
|
| 6063 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6064 |
|
|
(abs:GPR (match_operand:GPR 1 "register_operand" "d")))
|
| 6065 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6066 |
|
|
""
|
| 6067 |
|
|
"lpr\t%0,%1"
|
| 6068 |
|
|
[(set_attr "op_type" "RR")])
|
| 6069 |
|
|
|
| 6070 |
|
|
;
|
| 6071 |
|
|
; abs(df|sf)2 instruction pattern(s).
|
| 6072 |
|
|
;
|
| 6073 |
|
|
|
| 6074 |
|
|
(define_expand "abs2"
|
| 6075 |
|
|
[(parallel
|
| 6076 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 6077 |
|
|
(abs:FPR (match_operand:FPR 1 "register_operand" "f")))
|
| 6078 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 6079 |
|
|
"TARGET_HARD_FLOAT"
|
| 6080 |
|
|
"")
|
| 6081 |
|
|
|
| 6082 |
|
|
; lpxbr, lpdbr, lpebr
|
| 6083 |
|
|
(define_insn "*abs2_cc"
|
| 6084 |
|
|
[(set (reg CC_REGNUM)
|
| 6085 |
|
|
(compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
|
| 6086 |
|
|
(match_operand:FPR 2 "const0_operand" "")))
|
| 6087 |
|
|
(set (match_operand:FPR 0 "register_operand" "=f")
|
| 6088 |
|
|
(abs:FPR (match_dup 1)))]
|
| 6089 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 6090 |
|
|
"lpbr\t%0,%1"
|
| 6091 |
|
|
[(set_attr "op_type" "RRE")
|
| 6092 |
|
|
(set_attr "type" "fsimp")])
|
| 6093 |
|
|
|
| 6094 |
|
|
; lpxbr, lpdbr, lpebr
|
| 6095 |
|
|
(define_insn "*abs2_cconly"
|
| 6096 |
|
|
[(set (reg CC_REGNUM)
|
| 6097 |
|
|
(compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
|
| 6098 |
|
|
(match_operand:FPR 2 "const0_operand" "")))
|
| 6099 |
|
|
(clobber (match_scratch:FPR 0 "=f"))]
|
| 6100 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 6101 |
|
|
"lpbr\t%0,%1"
|
| 6102 |
|
|
[(set_attr "op_type" "RRE")
|
| 6103 |
|
|
(set_attr "type" "fsimp")])
|
| 6104 |
|
|
|
| 6105 |
|
|
; lpxbr, lpdbr, lpebr
|
| 6106 |
|
|
(define_insn "*abs2"
|
| 6107 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 6108 |
|
|
(abs:FPR (match_operand:FPR 1 "register_operand" "f")))
|
| 6109 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6110 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 6111 |
|
|
"lpbr\t%0,%1"
|
| 6112 |
|
|
[(set_attr "op_type" "RRE")
|
| 6113 |
|
|
(set_attr "type" "fsimp")])
|
| 6114 |
|
|
|
| 6115 |
|
|
; lpxr, lpdr, lper
|
| 6116 |
|
|
(define_insn "*abs2_ibm"
|
| 6117 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 6118 |
|
|
(abs:FPR (match_operand:FPR 1 "register_operand" "f")))
|
| 6119 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6120 |
|
|
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
|
| 6121 |
|
|
"lpr\t%0,%1"
|
| 6122 |
|
|
[(set_attr "op_type" "")
|
| 6123 |
|
|
(set_attr "type" "fsimp")])
|
| 6124 |
|
|
|
| 6125 |
|
|
;;
|
| 6126 |
|
|
;;- Negated absolute value instructions
|
| 6127 |
|
|
;;
|
| 6128 |
|
|
|
| 6129 |
|
|
;
|
| 6130 |
|
|
; Integer
|
| 6131 |
|
|
;
|
| 6132 |
|
|
|
| 6133 |
|
|
(define_insn "*negabsdi2_sign_cc"
|
| 6134 |
|
|
[(set (reg CC_REGNUM)
|
| 6135 |
|
|
(compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
|
| 6136 |
|
|
(match_operand:SI 1 "register_operand" "d") 0)
|
| 6137 |
|
|
(const_int 32)) (const_int 32))))
|
| 6138 |
|
|
(const_int 0)))
|
| 6139 |
|
|
(set (match_operand:DI 0 "register_operand" "=d")
|
| 6140 |
|
|
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
|
| 6141 |
|
|
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
|
| 6142 |
|
|
"lngfr\t%0,%1"
|
| 6143 |
|
|
[(set_attr "op_type" "RRE")])
|
| 6144 |
|
|
|
| 6145 |
|
|
(define_insn "*negabsdi2_sign"
|
| 6146 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 6147 |
|
|
(neg:DI (abs:DI (sign_extend:DI
|
| 6148 |
|
|
(match_operand:SI 1 "register_operand" "d")))))
|
| 6149 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6150 |
|
|
"TARGET_64BIT"
|
| 6151 |
|
|
"lngfr\t%0,%1"
|
| 6152 |
|
|
[(set_attr "op_type" "RRE")])
|
| 6153 |
|
|
|
| 6154 |
|
|
; lnr, lngr
|
| 6155 |
|
|
(define_insn "*negabs2_cc"
|
| 6156 |
|
|
[(set (reg CC_REGNUM)
|
| 6157 |
|
|
(compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
|
| 6158 |
|
|
(const_int 0)))
|
| 6159 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6160 |
|
|
(neg:GPR (abs:GPR (match_dup 1))))]
|
| 6161 |
|
|
"s390_match_ccmode (insn, CCAmode)"
|
| 6162 |
|
|
"lnr\t%0,%1"
|
| 6163 |
|
|
[(set_attr "op_type" "RR")])
|
| 6164 |
|
|
|
| 6165 |
|
|
; lnr, lngr
|
| 6166 |
|
|
(define_insn "*negabs2_cconly"
|
| 6167 |
|
|
[(set (reg CC_REGNUM)
|
| 6168 |
|
|
(compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
|
| 6169 |
|
|
(const_int 0)))
|
| 6170 |
|
|
(clobber (match_scratch:GPR 0 "=d"))]
|
| 6171 |
|
|
"s390_match_ccmode (insn, CCAmode)"
|
| 6172 |
|
|
"lnr\t%0,%1"
|
| 6173 |
|
|
[(set_attr "op_type" "RR")])
|
| 6174 |
|
|
|
| 6175 |
|
|
; lnr, lngr
|
| 6176 |
|
|
(define_insn "*negabs2"
|
| 6177 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6178 |
|
|
(neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
|
| 6179 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6180 |
|
|
""
|
| 6181 |
|
|
"lnr\t%0,%1"
|
| 6182 |
|
|
[(set_attr "op_type" "RR")])
|
| 6183 |
|
|
|
| 6184 |
|
|
;
|
| 6185 |
|
|
; Floating point
|
| 6186 |
|
|
;
|
| 6187 |
|
|
|
| 6188 |
|
|
; lnxbr, lndbr, lnebr
|
| 6189 |
|
|
(define_insn "*negabs2_cc"
|
| 6190 |
|
|
[(set (reg CC_REGNUM)
|
| 6191 |
|
|
(compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
|
| 6192 |
|
|
(match_operand:FPR 2 "const0_operand" "")))
|
| 6193 |
|
|
(set (match_operand:FPR 0 "register_operand" "=f")
|
| 6194 |
|
|
(neg:FPR (abs:FPR (match_dup 1))))]
|
| 6195 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 6196 |
|
|
"lnbr\t%0,%1"
|
| 6197 |
|
|
[(set_attr "op_type" "RRE")
|
| 6198 |
|
|
(set_attr "type" "fsimp")])
|
| 6199 |
|
|
|
| 6200 |
|
|
; lnxbr, lndbr, lnebr
|
| 6201 |
|
|
(define_insn "*negabs2_cconly"
|
| 6202 |
|
|
[(set (reg CC_REGNUM)
|
| 6203 |
|
|
(compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
|
| 6204 |
|
|
(match_operand:FPR 2 "const0_operand" "")))
|
| 6205 |
|
|
(clobber (match_scratch:FPR 0 "=f"))]
|
| 6206 |
|
|
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 6207 |
|
|
"lnbr\t%0,%1"
|
| 6208 |
|
|
[(set_attr "op_type" "RRE")
|
| 6209 |
|
|
(set_attr "type" "fsimp")])
|
| 6210 |
|
|
|
| 6211 |
|
|
; lnxbr, lndbr, lnebr
|
| 6212 |
|
|
(define_insn "*negabs2"
|
| 6213 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f")
|
| 6214 |
|
|
(neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
|
| 6215 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6216 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 6217 |
|
|
"lnbr\t%0,%1"
|
| 6218 |
|
|
[(set_attr "op_type" "RRE")
|
| 6219 |
|
|
(set_attr "type" "fsimp")])
|
| 6220 |
|
|
|
| 6221 |
|
|
;;
|
| 6222 |
|
|
;;- Square root instructions.
|
| 6223 |
|
|
;;
|
| 6224 |
|
|
|
| 6225 |
|
|
;
|
| 6226 |
|
|
; sqrt(df|sf)2 instruction pattern(s).
|
| 6227 |
|
|
;
|
| 6228 |
|
|
|
| 6229 |
|
|
; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
|
| 6230 |
|
|
(define_insn "sqrt2"
|
| 6231 |
|
|
[(set (match_operand:FPR 0 "register_operand" "=f,f")
|
| 6232 |
|
|
(sqrt:FPR (match_operand:FPR 1 "general_operand" "f,")))]
|
| 6233 |
|
|
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
|
| 6234 |
|
|
"@
|
| 6235 |
|
|
sqbr\t%0,%1
|
| 6236 |
|
|
sqb\t%0,%1"
|
| 6237 |
|
|
[(set_attr "op_type" "RRE,RXE")
|
| 6238 |
|
|
(set_attr "type" "fsqrt")])
|
| 6239 |
|
|
|
| 6240 |
|
|
|
| 6241 |
|
|
;;
|
| 6242 |
|
|
;;- One complement instructions.
|
| 6243 |
|
|
;;
|
| 6244 |
|
|
|
| 6245 |
|
|
;
|
| 6246 |
|
|
; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
|
| 6247 |
|
|
;
|
| 6248 |
|
|
|
| 6249 |
|
|
(define_expand "one_cmpl2"
|
| 6250 |
|
|
[(parallel
|
| 6251 |
|
|
[(set (match_operand:INT 0 "register_operand" "")
|
| 6252 |
|
|
(xor:INT (match_operand:INT 1 "register_operand" "")
|
| 6253 |
|
|
(const_int -1)))
|
| 6254 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 6255 |
|
|
""
|
| 6256 |
|
|
"")
|
| 6257 |
|
|
|
| 6258 |
|
|
|
| 6259 |
|
|
;;
|
| 6260 |
|
|
;; Find leftmost bit instructions.
|
| 6261 |
|
|
;;
|
| 6262 |
|
|
|
| 6263 |
|
|
(define_expand "clzdi2"
|
| 6264 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 6265 |
|
|
(clz:DI (match_operand:DI 1 "register_operand" "d")))]
|
| 6266 |
|
|
"TARGET_EXTIMM && TARGET_64BIT"
|
| 6267 |
|
|
{
|
| 6268 |
|
|
rtx insn, clz_equal;
|
| 6269 |
|
|
rtx wide_reg = gen_reg_rtx (TImode);
|
| 6270 |
|
|
rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
|
| 6271 |
|
|
|
| 6272 |
|
|
clz_equal = gen_rtx_CLZ (DImode, operands[1]);
|
| 6273 |
|
|
|
| 6274 |
|
|
emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
|
| 6275 |
|
|
|
| 6276 |
|
|
insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
|
| 6277 |
|
|
REG_NOTES (insn) =
|
| 6278 |
|
|
gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
|
| 6279 |
|
|
|
| 6280 |
|
|
DONE;
|
| 6281 |
|
|
})
|
| 6282 |
|
|
|
| 6283 |
|
|
(define_insn "clztidi2"
|
| 6284 |
|
|
[(set (match_operand:TI 0 "register_operand" "=d")
|
| 6285 |
|
|
(ior:TI
|
| 6286 |
|
|
(ashift:TI
|
| 6287 |
|
|
(zero_extend:TI
|
| 6288 |
|
|
(xor:DI (match_operand:DI 1 "register_operand" "d")
|
| 6289 |
|
|
(lshiftrt (match_operand:DI 2 "const_int_operand" "")
|
| 6290 |
|
|
(subreg:SI (clz:DI (match_dup 1)) 4))))
|
| 6291 |
|
|
|
| 6292 |
|
|
(const_int 64))
|
| 6293 |
|
|
(zero_extend:TI (clz:DI (match_dup 1)))))
|
| 6294 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6295 |
|
|
"(unsigned HOST_WIDE_INT) INTVAL (operands[2])
|
| 6296 |
|
|
== (unsigned HOST_WIDE_INT) 1 << 63
|
| 6297 |
|
|
&& TARGET_EXTIMM && TARGET_64BIT"
|
| 6298 |
|
|
"flogr\t%0,%1"
|
| 6299 |
|
|
[(set_attr "op_type" "RRE")])
|
| 6300 |
|
|
|
| 6301 |
|
|
|
| 6302 |
|
|
;;
|
| 6303 |
|
|
;;- Rotate instructions.
|
| 6304 |
|
|
;;
|
| 6305 |
|
|
|
| 6306 |
|
|
;
|
| 6307 |
|
|
; rotl(di|si)3 instruction pattern(s).
|
| 6308 |
|
|
;
|
| 6309 |
|
|
|
| 6310 |
|
|
; rll, rllg
|
| 6311 |
|
|
(define_insn "rotl3"
|
| 6312 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6313 |
|
|
(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
|
| 6314 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
|
| 6315 |
|
|
"TARGET_CPU_ZARCH"
|
| 6316 |
|
|
"rll\t%0,%1,%Y2"
|
| 6317 |
|
|
[(set_attr "op_type" "RSE")
|
| 6318 |
|
|
(set_attr "atype" "reg")])
|
| 6319 |
|
|
|
| 6320 |
|
|
; rll, rllg
|
| 6321 |
|
|
(define_insn "*rotl3_and"
|
| 6322 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6323 |
|
|
(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
|
| 6324 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6325 |
|
|
(match_operand:SI 3 "const_int_operand" "n"))))]
|
| 6326 |
|
|
"TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
|
| 6327 |
|
|
"rll\t%0,%1,%Y2"
|
| 6328 |
|
|
[(set_attr "op_type" "RSE")
|
| 6329 |
|
|
(set_attr "atype" "reg")])
|
| 6330 |
|
|
|
| 6331 |
|
|
|
| 6332 |
|
|
;;
|
| 6333 |
|
|
;;- Shift instructions.
|
| 6334 |
|
|
;;
|
| 6335 |
|
|
|
| 6336 |
|
|
;
|
| 6337 |
|
|
; (ashl|lshr)(di|si)3 instruction pattern(s).
|
| 6338 |
|
|
;
|
| 6339 |
|
|
|
| 6340 |
|
|
(define_expand "3"
|
| 6341 |
|
|
[(set (match_operand:DSI 0 "register_operand" "")
|
| 6342 |
|
|
(SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
|
| 6343 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
|
| 6344 |
|
|
""
|
| 6345 |
|
|
"")
|
| 6346 |
|
|
|
| 6347 |
|
|
; sldl, srdl
|
| 6348 |
|
|
(define_insn "*di3_31"
|
| 6349 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 6350 |
|
|
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
|
| 6351 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
|
| 6352 |
|
|
"!TARGET_64BIT"
|
| 6353 |
|
|
"sdl\t%0,%Y2"
|
| 6354 |
|
|
[(set_attr "op_type" "RS")
|
| 6355 |
|
|
(set_attr "atype" "reg")])
|
| 6356 |
|
|
|
| 6357 |
|
|
; sll, srl, sllg, srlg
|
| 6358 |
|
|
(define_insn "*3"
|
| 6359 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6360 |
|
|
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "")
|
| 6361 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
|
| 6362 |
|
|
""
|
| 6363 |
|
|
"sl\t%0,<1>%Y2"
|
| 6364 |
|
|
[(set_attr "op_type" "RS")
|
| 6365 |
|
|
(set_attr "atype" "reg")])
|
| 6366 |
|
|
|
| 6367 |
|
|
; sldl, srdl
|
| 6368 |
|
|
(define_insn "*di3_31_and"
|
| 6369 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 6370 |
|
|
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
|
| 6371 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6372 |
|
|
(match_operand:SI 3 "const_int_operand" "n"))))]
|
| 6373 |
|
|
"!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
|
| 6374 |
|
|
"sdl\t%0,%Y2"
|
| 6375 |
|
|
[(set_attr "op_type" "RS")
|
| 6376 |
|
|
(set_attr "atype" "reg")])
|
| 6377 |
|
|
|
| 6378 |
|
|
; sll, srl, sllg, srlg
|
| 6379 |
|
|
(define_insn "*3_and"
|
| 6380 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6381 |
|
|
(SHIFT:GPR (match_operand:GPR 1 "register_operand" "")
|
| 6382 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6383 |
|
|
(match_operand:SI 3 "const_int_operand" "n"))))]
|
| 6384 |
|
|
"(INTVAL (operands[3]) & 63) == 63"
|
| 6385 |
|
|
"sl\t%0,<1>%Y2"
|
| 6386 |
|
|
[(set_attr "op_type" "RS")
|
| 6387 |
|
|
(set_attr "atype" "reg")])
|
| 6388 |
|
|
|
| 6389 |
|
|
;
|
| 6390 |
|
|
; ashr(di|si)3 instruction pattern(s).
|
| 6391 |
|
|
;
|
| 6392 |
|
|
|
| 6393 |
|
|
(define_expand "ashr3"
|
| 6394 |
|
|
[(parallel
|
| 6395 |
|
|
[(set (match_operand:DSI 0 "register_operand" "")
|
| 6396 |
|
|
(ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
|
| 6397 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "")))
|
| 6398 |
|
|
(clobber (reg:CC CC_REGNUM))])]
|
| 6399 |
|
|
""
|
| 6400 |
|
|
"")
|
| 6401 |
|
|
|
| 6402 |
|
|
(define_insn "*ashrdi3_cc_31"
|
| 6403 |
|
|
[(set (reg CC_REGNUM)
|
| 6404 |
|
|
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
|
| 6405 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
|
| 6406 |
|
|
(const_int 0)))
|
| 6407 |
|
|
(set (match_operand:DI 0 "register_operand" "=d")
|
| 6408 |
|
|
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
|
| 6409 |
|
|
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
|
| 6410 |
|
|
"srda\t%0,%Y2"
|
| 6411 |
|
|
[(set_attr "op_type" "RS")
|
| 6412 |
|
|
(set_attr "atype" "reg")])
|
| 6413 |
|
|
|
| 6414 |
|
|
(define_insn "*ashrdi3_cconly_31"
|
| 6415 |
|
|
[(set (reg CC_REGNUM)
|
| 6416 |
|
|
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
|
| 6417 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
|
| 6418 |
|
|
(const_int 0)))
|
| 6419 |
|
|
(clobber (match_scratch:DI 0 "=d"))]
|
| 6420 |
|
|
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
|
| 6421 |
|
|
"srda\t%0,%Y2"
|
| 6422 |
|
|
[(set_attr "op_type" "RS")
|
| 6423 |
|
|
(set_attr "atype" "reg")])
|
| 6424 |
|
|
|
| 6425 |
|
|
(define_insn "*ashrdi3_31"
|
| 6426 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 6427 |
|
|
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
|
| 6428 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
|
| 6429 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6430 |
|
|
"!TARGET_64BIT"
|
| 6431 |
|
|
"srda\t%0,%Y2"
|
| 6432 |
|
|
[(set_attr "op_type" "RS")
|
| 6433 |
|
|
(set_attr "atype" "reg")])
|
| 6434 |
|
|
|
| 6435 |
|
|
; sra, srag
|
| 6436 |
|
|
(define_insn "*ashr3_cc"
|
| 6437 |
|
|
[(set (reg CC_REGNUM)
|
| 6438 |
|
|
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "")
|
| 6439 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
|
| 6440 |
|
|
(const_int 0)))
|
| 6441 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6442 |
|
|
(ashiftrt:GPR (match_dup 1) (match_dup 2)))]
|
| 6443 |
|
|
"s390_match_ccmode(insn, CCSmode)"
|
| 6444 |
|
|
"sra\t%0,<1>%Y2"
|
| 6445 |
|
|
[(set_attr "op_type" "RS")
|
| 6446 |
|
|
(set_attr "atype" "reg")])
|
| 6447 |
|
|
|
| 6448 |
|
|
; sra, srag
|
| 6449 |
|
|
(define_insn "*ashr3_cconly"
|
| 6450 |
|
|
[(set (reg CC_REGNUM)
|
| 6451 |
|
|
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "")
|
| 6452 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
|
| 6453 |
|
|
(const_int 0)))
|
| 6454 |
|
|
(clobber (match_scratch:GPR 0 "=d"))]
|
| 6455 |
|
|
"s390_match_ccmode(insn, CCSmode)"
|
| 6456 |
|
|
"sra\t%0,<1>%Y2"
|
| 6457 |
|
|
[(set_attr "op_type" "RS")
|
| 6458 |
|
|
(set_attr "atype" "reg")])
|
| 6459 |
|
|
|
| 6460 |
|
|
; sra, srag
|
| 6461 |
|
|
(define_insn "*ashr3"
|
| 6462 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6463 |
|
|
(ashiftrt:GPR (match_operand:GPR 1 "register_operand" "")
|
| 6464 |
|
|
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
|
| 6465 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6466 |
|
|
""
|
| 6467 |
|
|
"sra\t%0,<1>%Y2"
|
| 6468 |
|
|
[(set_attr "op_type" "RS")
|
| 6469 |
|
|
(set_attr "atype" "reg")])
|
| 6470 |
|
|
|
| 6471 |
|
|
|
| 6472 |
|
|
; shift pattern with implicit ANDs
|
| 6473 |
|
|
|
| 6474 |
|
|
(define_insn "*ashrdi3_cc_31_and"
|
| 6475 |
|
|
[(set (reg CC_REGNUM)
|
| 6476 |
|
|
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
|
| 6477 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6478 |
|
|
(match_operand:SI 3 "const_int_operand" "n")))
|
| 6479 |
|
|
(const_int 0)))
|
| 6480 |
|
|
(set (match_operand:DI 0 "register_operand" "=d")
|
| 6481 |
|
|
(ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
|
| 6482 |
|
|
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
|
| 6483 |
|
|
&& (INTVAL (operands[3]) & 63) == 63"
|
| 6484 |
|
|
"srda\t%0,%Y2"
|
| 6485 |
|
|
[(set_attr "op_type" "RS")
|
| 6486 |
|
|
(set_attr "atype" "reg")])
|
| 6487 |
|
|
|
| 6488 |
|
|
(define_insn "*ashrdi3_cconly_31_and"
|
| 6489 |
|
|
[(set (reg CC_REGNUM)
|
| 6490 |
|
|
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
|
| 6491 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6492 |
|
|
(match_operand:SI 3 "const_int_operand" "n")))
|
| 6493 |
|
|
(const_int 0)))
|
| 6494 |
|
|
(clobber (match_scratch:DI 0 "=d"))]
|
| 6495 |
|
|
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
|
| 6496 |
|
|
&& (INTVAL (operands[3]) & 63) == 63"
|
| 6497 |
|
|
"srda\t%0,%Y2"
|
| 6498 |
|
|
[(set_attr "op_type" "RS")
|
| 6499 |
|
|
(set_attr "atype" "reg")])
|
| 6500 |
|
|
|
| 6501 |
|
|
(define_insn "*ashrdi3_31_and"
|
| 6502 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 6503 |
|
|
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
|
| 6504 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6505 |
|
|
(match_operand:SI 3 "const_int_operand" "n"))))
|
| 6506 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6507 |
|
|
"!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
|
| 6508 |
|
|
"srda\t%0,%Y2"
|
| 6509 |
|
|
[(set_attr "op_type" "RS")
|
| 6510 |
|
|
(set_attr "atype" "reg")])
|
| 6511 |
|
|
|
| 6512 |
|
|
; sra, srag
|
| 6513 |
|
|
(define_insn "*ashr3_cc_and"
|
| 6514 |
|
|
[(set (reg CC_REGNUM)
|
| 6515 |
|
|
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "")
|
| 6516 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6517 |
|
|
(match_operand:SI 3 "const_int_operand" "n")))
|
| 6518 |
|
|
(const_int 0)))
|
| 6519 |
|
|
(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6520 |
|
|
(ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
|
| 6521 |
|
|
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
|
| 6522 |
|
|
"sra\t%0,<1>%Y2"
|
| 6523 |
|
|
[(set_attr "op_type" "RS")
|
| 6524 |
|
|
(set_attr "atype" "reg")])
|
| 6525 |
|
|
|
| 6526 |
|
|
; sra, srag
|
| 6527 |
|
|
(define_insn "*ashr3_cconly_and"
|
| 6528 |
|
|
[(set (reg CC_REGNUM)
|
| 6529 |
|
|
(compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "")
|
| 6530 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6531 |
|
|
(match_operand:SI 3 "const_int_operand" "n")))
|
| 6532 |
|
|
(const_int 0)))
|
| 6533 |
|
|
(clobber (match_scratch:GPR 0 "=d"))]
|
| 6534 |
|
|
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
|
| 6535 |
|
|
"sra\t%0,<1>%Y2"
|
| 6536 |
|
|
[(set_attr "op_type" "RS")
|
| 6537 |
|
|
(set_attr "atype" "reg")])
|
| 6538 |
|
|
|
| 6539 |
|
|
; sra, srag
|
| 6540 |
|
|
(define_insn "*ashr3_and"
|
| 6541 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=d")
|
| 6542 |
|
|
(ashiftrt:GPR (match_operand:GPR 1 "register_operand" "")
|
| 6543 |
|
|
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
|
| 6544 |
|
|
(match_operand:SI 3 "const_int_operand" "n"))))
|
| 6545 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6546 |
|
|
"(INTVAL (operands[3]) & 63) == 63"
|
| 6547 |
|
|
"sra\t%0,<1>%Y2"
|
| 6548 |
|
|
[(set_attr "op_type" "RS")
|
| 6549 |
|
|
(set_attr "atype" "reg")])
|
| 6550 |
|
|
|
| 6551 |
|
|
|
| 6552 |
|
|
;;
|
| 6553 |
|
|
;; Branch instruction patterns.
|
| 6554 |
|
|
;;
|
| 6555 |
|
|
|
| 6556 |
|
|
(define_expand "b"
|
| 6557 |
|
|
[(set (pc)
|
| 6558 |
|
|
(if_then_else (COMPARE (match_operand 0 "" "")
|
| 6559 |
|
|
(const_int 0))
|
| 6560 |
|
|
(match_dup 0)
|
| 6561 |
|
|
(pc)))]
|
| 6562 |
|
|
""
|
| 6563 |
|
|
"s390_emit_jump (operands[0],
|
| 6564 |
|
|
s390_emit_compare (, s390_compare_op0, s390_compare_op1)); DONE;")
|
| 6565 |
|
|
|
| 6566 |
|
|
|
| 6567 |
|
|
;;
|
| 6568 |
|
|
;;- Conditional jump instructions.
|
| 6569 |
|
|
;;
|
| 6570 |
|
|
|
| 6571 |
|
|
(define_insn "*cjump_64"
|
| 6572 |
|
|
[(set (pc)
|
| 6573 |
|
|
(if_then_else
|
| 6574 |
|
|
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
| 6575 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 6576 |
|
|
(pc)))]
|
| 6577 |
|
|
"TARGET_CPU_ZARCH"
|
| 6578 |
|
|
{
|
| 6579 |
|
|
if (get_attr_length (insn) == 4)
|
| 6580 |
|
|
return "j%C1\t%l0";
|
| 6581 |
|
|
else
|
| 6582 |
|
|
return "jg%C1\t%l0";
|
| 6583 |
|
|
}
|
| 6584 |
|
|
[(set_attr "op_type" "RI")
|
| 6585 |
|
|
(set_attr "type" "branch")
|
| 6586 |
|
|
(set (attr "length")
|
| 6587 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6588 |
|
|
(const_int 4) (const_int 6)))])
|
| 6589 |
|
|
|
| 6590 |
|
|
(define_insn "*cjump_31"
|
| 6591 |
|
|
[(set (pc)
|
| 6592 |
|
|
(if_then_else
|
| 6593 |
|
|
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
| 6594 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 6595 |
|
|
(pc)))]
|
| 6596 |
|
|
"!TARGET_CPU_ZARCH"
|
| 6597 |
|
|
{
|
| 6598 |
|
|
gcc_assert (get_attr_length (insn) == 4);
|
| 6599 |
|
|
return "j%C1\t%l0";
|
| 6600 |
|
|
}
|
| 6601 |
|
|
[(set_attr "op_type" "RI")
|
| 6602 |
|
|
(set_attr "type" "branch")
|
| 6603 |
|
|
(set (attr "length")
|
| 6604 |
|
|
(if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
|
| 6605 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6606 |
|
|
(const_int 4) (const_int 6))
|
| 6607 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6608 |
|
|
(const_int 4) (const_int 8))))])
|
| 6609 |
|
|
|
| 6610 |
|
|
(define_insn "*cjump_long"
|
| 6611 |
|
|
[(set (pc)
|
| 6612 |
|
|
(if_then_else
|
| 6613 |
|
|
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
| 6614 |
|
|
(match_operand 0 "address_operand" "U")
|
| 6615 |
|
|
(pc)))]
|
| 6616 |
|
|
""
|
| 6617 |
|
|
{
|
| 6618 |
|
|
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
| 6619 |
|
|
return "b%C1r\t%0";
|
| 6620 |
|
|
else
|
| 6621 |
|
|
return "b%C1\t%a0";
|
| 6622 |
|
|
}
|
| 6623 |
|
|
[(set (attr "op_type")
|
| 6624 |
|
|
(if_then_else (match_operand 0 "register_operand" "")
|
| 6625 |
|
|
(const_string "RR") (const_string "RX")))
|
| 6626 |
|
|
(set_attr "type" "branch")
|
| 6627 |
|
|
(set_attr "atype" "agen")])
|
| 6628 |
|
|
|
| 6629 |
|
|
|
| 6630 |
|
|
;;
|
| 6631 |
|
|
;;- Negated conditional jump instructions.
|
| 6632 |
|
|
;;
|
| 6633 |
|
|
|
| 6634 |
|
|
(define_insn "*icjump_64"
|
| 6635 |
|
|
[(set (pc)
|
| 6636 |
|
|
(if_then_else
|
| 6637 |
|
|
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
| 6638 |
|
|
(pc)
|
| 6639 |
|
|
(label_ref (match_operand 0 "" ""))))]
|
| 6640 |
|
|
"TARGET_CPU_ZARCH"
|
| 6641 |
|
|
{
|
| 6642 |
|
|
if (get_attr_length (insn) == 4)
|
| 6643 |
|
|
return "j%D1\t%l0";
|
| 6644 |
|
|
else
|
| 6645 |
|
|
return "jg%D1\t%l0";
|
| 6646 |
|
|
}
|
| 6647 |
|
|
[(set_attr "op_type" "RI")
|
| 6648 |
|
|
(set_attr "type" "branch")
|
| 6649 |
|
|
(set (attr "length")
|
| 6650 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6651 |
|
|
(const_int 4) (const_int 6)))])
|
| 6652 |
|
|
|
| 6653 |
|
|
(define_insn "*icjump_31"
|
| 6654 |
|
|
[(set (pc)
|
| 6655 |
|
|
(if_then_else
|
| 6656 |
|
|
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
| 6657 |
|
|
(pc)
|
| 6658 |
|
|
(label_ref (match_operand 0 "" ""))))]
|
| 6659 |
|
|
"!TARGET_CPU_ZARCH"
|
| 6660 |
|
|
{
|
| 6661 |
|
|
gcc_assert (get_attr_length (insn) == 4);
|
| 6662 |
|
|
return "j%D1\t%l0";
|
| 6663 |
|
|
}
|
| 6664 |
|
|
[(set_attr "op_type" "RI")
|
| 6665 |
|
|
(set_attr "type" "branch")
|
| 6666 |
|
|
(set (attr "length")
|
| 6667 |
|
|
(if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
|
| 6668 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6669 |
|
|
(const_int 4) (const_int 6))
|
| 6670 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6671 |
|
|
(const_int 4) (const_int 8))))])
|
| 6672 |
|
|
|
| 6673 |
|
|
(define_insn "*icjump_long"
|
| 6674 |
|
|
[(set (pc)
|
| 6675 |
|
|
(if_then_else
|
| 6676 |
|
|
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
| 6677 |
|
|
(pc)
|
| 6678 |
|
|
(match_operand 0 "address_operand" "U")))]
|
| 6679 |
|
|
""
|
| 6680 |
|
|
{
|
| 6681 |
|
|
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
| 6682 |
|
|
return "b%D1r\t%0";
|
| 6683 |
|
|
else
|
| 6684 |
|
|
return "b%D1\t%a0";
|
| 6685 |
|
|
}
|
| 6686 |
|
|
[(set (attr "op_type")
|
| 6687 |
|
|
(if_then_else (match_operand 0 "register_operand" "")
|
| 6688 |
|
|
(const_string "RR") (const_string "RX")))
|
| 6689 |
|
|
(set_attr "type" "branch")
|
| 6690 |
|
|
(set_attr "atype" "agen")])
|
| 6691 |
|
|
|
| 6692 |
|
|
;;
|
| 6693 |
|
|
;;- Trap instructions.
|
| 6694 |
|
|
;;
|
| 6695 |
|
|
|
| 6696 |
|
|
(define_insn "trap"
|
| 6697 |
|
|
[(trap_if (const_int 1) (const_int 0))]
|
| 6698 |
|
|
""
|
| 6699 |
|
|
"j\t.+2"
|
| 6700 |
|
|
[(set_attr "op_type" "RI")
|
| 6701 |
|
|
(set_attr "type" "branch")])
|
| 6702 |
|
|
|
| 6703 |
|
|
(define_expand "conditional_trap"
|
| 6704 |
|
|
[(trap_if (match_operand 0 "comparison_operator" "")
|
| 6705 |
|
|
(match_operand 1 "general_operand" ""))]
|
| 6706 |
|
|
""
|
| 6707 |
|
|
{
|
| 6708 |
|
|
if (operands[1] != const0_rtx) FAIL;
|
| 6709 |
|
|
operands[0] = s390_emit_compare (GET_CODE (operands[0]),
|
| 6710 |
|
|
s390_compare_op0, s390_compare_op1);
|
| 6711 |
|
|
})
|
| 6712 |
|
|
|
| 6713 |
|
|
(define_insn "*trap"
|
| 6714 |
|
|
[(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
|
| 6715 |
|
|
(const_int 0))]
|
| 6716 |
|
|
""
|
| 6717 |
|
|
"j%C0\t.+2";
|
| 6718 |
|
|
[(set_attr "op_type" "RI")
|
| 6719 |
|
|
(set_attr "type" "branch")])
|
| 6720 |
|
|
|
| 6721 |
|
|
;;
|
| 6722 |
|
|
;;- Loop instructions.
|
| 6723 |
|
|
;;
|
| 6724 |
|
|
;; This is all complicated by the fact that since this is a jump insn
|
| 6725 |
|
|
;; we must handle our own output reloads.
|
| 6726 |
|
|
|
| 6727 |
|
|
(define_expand "doloop_end"
|
| 6728 |
|
|
[(use (match_operand 0 "" "")) ; loop pseudo
|
| 6729 |
|
|
(use (match_operand 1 "" "")) ; iterations; zero if unknown
|
| 6730 |
|
|
(use (match_operand 2 "" "")) ; max iterations
|
| 6731 |
|
|
(use (match_operand 3 "" "")) ; loop level
|
| 6732 |
|
|
(use (match_operand 4 "" ""))] ; label
|
| 6733 |
|
|
""
|
| 6734 |
|
|
{
|
| 6735 |
|
|
if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
|
| 6736 |
|
|
emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
|
| 6737 |
|
|
else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
|
| 6738 |
|
|
emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
|
| 6739 |
|
|
else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
|
| 6740 |
|
|
emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
|
| 6741 |
|
|
else
|
| 6742 |
|
|
FAIL;
|
| 6743 |
|
|
|
| 6744 |
|
|
DONE;
|
| 6745 |
|
|
})
|
| 6746 |
|
|
|
| 6747 |
|
|
(define_insn_and_split "doloop_si64"
|
| 6748 |
|
|
[(set (pc)
|
| 6749 |
|
|
(if_then_else
|
| 6750 |
|
|
(ne (match_operand:SI 1 "register_operand" "d,d,d")
|
| 6751 |
|
|
(const_int 1))
|
| 6752 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 6753 |
|
|
(pc)))
|
| 6754 |
|
|
(set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
|
| 6755 |
|
|
(plus:SI (match_dup 1) (const_int -1)))
|
| 6756 |
|
|
(clobber (match_scratch:SI 3 "=X,&1,&?d"))
|
| 6757 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6758 |
|
|
"TARGET_CPU_ZARCH"
|
| 6759 |
|
|
{
|
| 6760 |
|
|
if (which_alternative != 0)
|
| 6761 |
|
|
return "#";
|
| 6762 |
|
|
else if (get_attr_length (insn) == 4)
|
| 6763 |
|
|
return "brct\t%1,%l0";
|
| 6764 |
|
|
else
|
| 6765 |
|
|
return "ahi\t%1,-1\;jgne\t%l0";
|
| 6766 |
|
|
}
|
| 6767 |
|
|
"&& reload_completed
|
| 6768 |
|
|
&& (! REG_P (operands[2])
|
| 6769 |
|
|
|| ! rtx_equal_p (operands[1], operands[2]))"
|
| 6770 |
|
|
[(set (match_dup 3) (match_dup 1))
|
| 6771 |
|
|
(parallel [(set (reg:CCAN CC_REGNUM)
|
| 6772 |
|
|
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
|
| 6773 |
|
|
(const_int 0)))
|
| 6774 |
|
|
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
|
| 6775 |
|
|
(set (match_dup 2) (match_dup 3))
|
| 6776 |
|
|
(set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
|
| 6777 |
|
|
(label_ref (match_dup 0))
|
| 6778 |
|
|
(pc)))]
|
| 6779 |
|
|
""
|
| 6780 |
|
|
[(set_attr "op_type" "RI")
|
| 6781 |
|
|
(set_attr "type" "branch")
|
| 6782 |
|
|
(set (attr "length")
|
| 6783 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6784 |
|
|
(const_int 4) (const_int 10)))])
|
| 6785 |
|
|
|
| 6786 |
|
|
(define_insn_and_split "doloop_si31"
|
| 6787 |
|
|
[(set (pc)
|
| 6788 |
|
|
(if_then_else
|
| 6789 |
|
|
(ne (match_operand:SI 1 "register_operand" "d,d,d")
|
| 6790 |
|
|
(const_int 1))
|
| 6791 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 6792 |
|
|
(pc)))
|
| 6793 |
|
|
(set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
|
| 6794 |
|
|
(plus:SI (match_dup 1) (const_int -1)))
|
| 6795 |
|
|
(clobber (match_scratch:SI 3 "=X,&1,&?d"))
|
| 6796 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6797 |
|
|
"!TARGET_CPU_ZARCH"
|
| 6798 |
|
|
{
|
| 6799 |
|
|
if (which_alternative != 0)
|
| 6800 |
|
|
return "#";
|
| 6801 |
|
|
else if (get_attr_length (insn) == 4)
|
| 6802 |
|
|
return "brct\t%1,%l0";
|
| 6803 |
|
|
else
|
| 6804 |
|
|
gcc_unreachable ();
|
| 6805 |
|
|
}
|
| 6806 |
|
|
"&& reload_completed
|
| 6807 |
|
|
&& (! REG_P (operands[2])
|
| 6808 |
|
|
|| ! rtx_equal_p (operands[1], operands[2]))"
|
| 6809 |
|
|
[(set (match_dup 3) (match_dup 1))
|
| 6810 |
|
|
(parallel [(set (reg:CCAN CC_REGNUM)
|
| 6811 |
|
|
(compare:CCAN (plus:SI (match_dup 3) (const_int -1))
|
| 6812 |
|
|
(const_int 0)))
|
| 6813 |
|
|
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
|
| 6814 |
|
|
(set (match_dup 2) (match_dup 3))
|
| 6815 |
|
|
(set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
|
| 6816 |
|
|
(label_ref (match_dup 0))
|
| 6817 |
|
|
(pc)))]
|
| 6818 |
|
|
""
|
| 6819 |
|
|
[(set_attr "op_type" "RI")
|
| 6820 |
|
|
(set_attr "type" "branch")
|
| 6821 |
|
|
(set (attr "length")
|
| 6822 |
|
|
(if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
|
| 6823 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6824 |
|
|
(const_int 4) (const_int 6))
|
| 6825 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6826 |
|
|
(const_int 4) (const_int 8))))])
|
| 6827 |
|
|
|
| 6828 |
|
|
(define_insn "*doloop_si_long"
|
| 6829 |
|
|
[(set (pc)
|
| 6830 |
|
|
(if_then_else
|
| 6831 |
|
|
(ne (match_operand:SI 1 "register_operand" "d")
|
| 6832 |
|
|
(const_int 1))
|
| 6833 |
|
|
(match_operand 0 "address_operand" "U")
|
| 6834 |
|
|
(pc)))
|
| 6835 |
|
|
(set (match_operand:SI 2 "register_operand" "=1")
|
| 6836 |
|
|
(plus:SI (match_dup 1) (const_int -1)))
|
| 6837 |
|
|
(clobber (match_scratch:SI 3 "=X"))
|
| 6838 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6839 |
|
|
"!TARGET_CPU_ZARCH"
|
| 6840 |
|
|
{
|
| 6841 |
|
|
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
| 6842 |
|
|
return "bctr\t%1,%0";
|
| 6843 |
|
|
else
|
| 6844 |
|
|
return "bct\t%1,%a0";
|
| 6845 |
|
|
}
|
| 6846 |
|
|
[(set (attr "op_type")
|
| 6847 |
|
|
(if_then_else (match_operand 0 "register_operand" "")
|
| 6848 |
|
|
(const_string "RR") (const_string "RX")))
|
| 6849 |
|
|
(set_attr "type" "branch")
|
| 6850 |
|
|
(set_attr "atype" "agen")])
|
| 6851 |
|
|
|
| 6852 |
|
|
(define_insn_and_split "doloop_di"
|
| 6853 |
|
|
[(set (pc)
|
| 6854 |
|
|
(if_then_else
|
| 6855 |
|
|
(ne (match_operand:DI 1 "register_operand" "d,d,d")
|
| 6856 |
|
|
(const_int 1))
|
| 6857 |
|
|
(label_ref (match_operand 0 "" ""))
|
| 6858 |
|
|
(pc)))
|
| 6859 |
|
|
(set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
|
| 6860 |
|
|
(plus:DI (match_dup 1) (const_int -1)))
|
| 6861 |
|
|
(clobber (match_scratch:DI 3 "=X,&1,&?d"))
|
| 6862 |
|
|
(clobber (reg:CC CC_REGNUM))]
|
| 6863 |
|
|
"TARGET_64BIT"
|
| 6864 |
|
|
{
|
| 6865 |
|
|
if (which_alternative != 0)
|
| 6866 |
|
|
return "#";
|
| 6867 |
|
|
else if (get_attr_length (insn) == 4)
|
| 6868 |
|
|
return "brctg\t%1,%l0";
|
| 6869 |
|
|
else
|
| 6870 |
|
|
return "aghi\t%1,-1\;jgne\t%l0";
|
| 6871 |
|
|
}
|
| 6872 |
|
|
"&& reload_completed
|
| 6873 |
|
|
&& (! REG_P (operands[2])
|
| 6874 |
|
|
|| ! rtx_equal_p (operands[1], operands[2]))"
|
| 6875 |
|
|
[(set (match_dup 3) (match_dup 1))
|
| 6876 |
|
|
(parallel [(set (reg:CCAN CC_REGNUM)
|
| 6877 |
|
|
(compare:CCAN (plus:DI (match_dup 3) (const_int -1))
|
| 6878 |
|
|
(const_int 0)))
|
| 6879 |
|
|
(set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
|
| 6880 |
|
|
(set (match_dup 2) (match_dup 3))
|
| 6881 |
|
|
(set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
|
| 6882 |
|
|
(label_ref (match_dup 0))
|
| 6883 |
|
|
(pc)))]
|
| 6884 |
|
|
""
|
| 6885 |
|
|
[(set_attr "op_type" "RI")
|
| 6886 |
|
|
(set_attr "type" "branch")
|
| 6887 |
|
|
(set (attr "length")
|
| 6888 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6889 |
|
|
(const_int 4) (const_int 10)))])
|
| 6890 |
|
|
|
| 6891 |
|
|
;;
|
| 6892 |
|
|
;;- Unconditional jump instructions.
|
| 6893 |
|
|
;;
|
| 6894 |
|
|
|
| 6895 |
|
|
;
|
| 6896 |
|
|
; jump instruction pattern(s).
|
| 6897 |
|
|
;
|
| 6898 |
|
|
|
| 6899 |
|
|
(define_expand "jump"
|
| 6900 |
|
|
[(match_operand 0 "" "")]
|
| 6901 |
|
|
""
|
| 6902 |
|
|
"s390_emit_jump (operands[0], NULL_RTX); DONE;")
|
| 6903 |
|
|
|
| 6904 |
|
|
(define_insn "*jump64"
|
| 6905 |
|
|
[(set (pc) (label_ref (match_operand 0 "" "")))]
|
| 6906 |
|
|
"TARGET_CPU_ZARCH"
|
| 6907 |
|
|
{
|
| 6908 |
|
|
if (get_attr_length (insn) == 4)
|
| 6909 |
|
|
return "j\t%l0";
|
| 6910 |
|
|
else
|
| 6911 |
|
|
return "jg\t%l0";
|
| 6912 |
|
|
}
|
| 6913 |
|
|
[(set_attr "op_type" "RI")
|
| 6914 |
|
|
(set_attr "type" "branch")
|
| 6915 |
|
|
(set (attr "length")
|
| 6916 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6917 |
|
|
(const_int 4) (const_int 6)))])
|
| 6918 |
|
|
|
| 6919 |
|
|
(define_insn "*jump31"
|
| 6920 |
|
|
[(set (pc) (label_ref (match_operand 0 "" "")))]
|
| 6921 |
|
|
"!TARGET_CPU_ZARCH"
|
| 6922 |
|
|
{
|
| 6923 |
|
|
gcc_assert (get_attr_length (insn) == 4);
|
| 6924 |
|
|
return "j\t%l0";
|
| 6925 |
|
|
}
|
| 6926 |
|
|
[(set_attr "op_type" "RI")
|
| 6927 |
|
|
(set_attr "type" "branch")
|
| 6928 |
|
|
(set (attr "length")
|
| 6929 |
|
|
(if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
|
| 6930 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6931 |
|
|
(const_int 4) (const_int 6))
|
| 6932 |
|
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
|
| 6933 |
|
|
(const_int 4) (const_int 8))))])
|
| 6934 |
|
|
|
| 6935 |
|
|
;
|
| 6936 |
|
|
; indirect-jump instruction pattern(s).
|
| 6937 |
|
|
;
|
| 6938 |
|
|
|
| 6939 |
|
|
(define_insn "indirect_jump"
|
| 6940 |
|
|
[(set (pc) (match_operand 0 "address_operand" "U"))]
|
| 6941 |
|
|
""
|
| 6942 |
|
|
{
|
| 6943 |
|
|
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
| 6944 |
|
|
return "br\t%0";
|
| 6945 |
|
|
else
|
| 6946 |
|
|
return "b\t%a0";
|
| 6947 |
|
|
}
|
| 6948 |
|
|
[(set (attr "op_type")
|
| 6949 |
|
|
(if_then_else (match_operand 0 "register_operand" "")
|
| 6950 |
|
|
(const_string "RR") (const_string "RX")))
|
| 6951 |
|
|
(set_attr "type" "branch")
|
| 6952 |
|
|
(set_attr "atype" "agen")])
|
| 6953 |
|
|
|
| 6954 |
|
|
;
|
| 6955 |
|
|
; casesi instruction pattern(s).
|
| 6956 |
|
|
;
|
| 6957 |
|
|
|
| 6958 |
|
|
(define_insn "casesi_jump"
|
| 6959 |
|
|
[(set (pc) (match_operand 0 "address_operand" "U"))
|
| 6960 |
|
|
(use (label_ref (match_operand 1 "" "")))]
|
| 6961 |
|
|
""
|
| 6962 |
|
|
{
|
| 6963 |
|
|
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
| 6964 |
|
|
return "br\t%0";
|
| 6965 |
|
|
else
|
| 6966 |
|
|
return "b\t%a0";
|
| 6967 |
|
|
}
|
| 6968 |
|
|
[(set (attr "op_type")
|
| 6969 |
|
|
(if_then_else (match_operand 0 "register_operand" "")
|
| 6970 |
|
|
(const_string "RR") (const_string "RX")))
|
| 6971 |
|
|
(set_attr "type" "branch")
|
| 6972 |
|
|
(set_attr "atype" "agen")])
|
| 6973 |
|
|
|
| 6974 |
|
|
(define_expand "casesi"
|
| 6975 |
|
|
[(match_operand:SI 0 "general_operand" "")
|
| 6976 |
|
|
(match_operand:SI 1 "general_operand" "")
|
| 6977 |
|
|
(match_operand:SI 2 "general_operand" "")
|
| 6978 |
|
|
(label_ref (match_operand 3 "" ""))
|
| 6979 |
|
|
(label_ref (match_operand 4 "" ""))]
|
| 6980 |
|
|
""
|
| 6981 |
|
|
{
|
| 6982 |
|
|
rtx index = gen_reg_rtx (SImode);
|
| 6983 |
|
|
rtx base = gen_reg_rtx (Pmode);
|
| 6984 |
|
|
rtx target = gen_reg_rtx (Pmode);
|
| 6985 |
|
|
|
| 6986 |
|
|
emit_move_insn (index, operands[0]);
|
| 6987 |
|
|
emit_insn (gen_subsi3 (index, index, operands[1]));
|
| 6988 |
|
|
emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
|
| 6989 |
|
|
operands[4]);
|
| 6990 |
|
|
|
| 6991 |
|
|
if (Pmode != SImode)
|
| 6992 |
|
|
index = convert_to_mode (Pmode, index, 1);
|
| 6993 |
|
|
if (GET_CODE (index) != REG)
|
| 6994 |
|
|
index = copy_to_mode_reg (Pmode, index);
|
| 6995 |
|
|
|
| 6996 |
|
|
if (TARGET_64BIT)
|
| 6997 |
|
|
emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
|
| 6998 |
|
|
else
|
| 6999 |
|
|
emit_insn (gen_ashlsi3 (index, index, const2_rtx));
|
| 7000 |
|
|
|
| 7001 |
|
|
emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
|
| 7002 |
|
|
|
| 7003 |
|
|
index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
|
| 7004 |
|
|
emit_move_insn (target, index);
|
| 7005 |
|
|
|
| 7006 |
|
|
if (flag_pic)
|
| 7007 |
|
|
target = gen_rtx_PLUS (Pmode, base, target);
|
| 7008 |
|
|
emit_jump_insn (gen_casesi_jump (target, operands[3]));
|
| 7009 |
|
|
|
| 7010 |
|
|
DONE;
|
| 7011 |
|
|
})
|
| 7012 |
|
|
|
| 7013 |
|
|
|
| 7014 |
|
|
;;
|
| 7015 |
|
|
;;- Jump to subroutine.
|
| 7016 |
|
|
;;
|
| 7017 |
|
|
;;
|
| 7018 |
|
|
|
| 7019 |
|
|
;
|
| 7020 |
|
|
; untyped call instruction pattern(s).
|
| 7021 |
|
|
;
|
| 7022 |
|
|
|
| 7023 |
|
|
;; Call subroutine returning any type.
|
| 7024 |
|
|
(define_expand "untyped_call"
|
| 7025 |
|
|
[(parallel [(call (match_operand 0 "" "")
|
| 7026 |
|
|
(const_int 0))
|
| 7027 |
|
|
(match_operand 1 "" "")
|
| 7028 |
|
|
(match_operand 2 "" "")])]
|
| 7029 |
|
|
""
|
| 7030 |
|
|
{
|
| 7031 |
|
|
int i;
|
| 7032 |
|
|
|
| 7033 |
|
|
emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
|
| 7034 |
|
|
|
| 7035 |
|
|
for (i = 0; i < XVECLEN (operands[2], 0); i++)
|
| 7036 |
|
|
{
|
| 7037 |
|
|
rtx set = XVECEXP (operands[2], 0, i);
|
| 7038 |
|
|
emit_move_insn (SET_DEST (set), SET_SRC (set));
|
| 7039 |
|
|
}
|
| 7040 |
|
|
|
| 7041 |
|
|
/* The optimizer does not know that the call sets the function value
|
| 7042 |
|
|
registers we stored in the result block. We avoid problems by
|
| 7043 |
|
|
claiming that all hard registers are used and clobbered at this
|
| 7044 |
|
|
point. */
|
| 7045 |
|
|
emit_insn (gen_blockage ());
|
| 7046 |
|
|
|
| 7047 |
|
|
DONE;
|
| 7048 |
|
|
})
|
| 7049 |
|
|
|
| 7050 |
|
|
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
|
| 7051 |
|
|
;; all of memory. This blocks insns from being moved across this point.
|
| 7052 |
|
|
|
| 7053 |
|
|
(define_insn "blockage"
|
| 7054 |
|
|
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
|
| 7055 |
|
|
""
|
| 7056 |
|
|
""
|
| 7057 |
|
|
[(set_attr "type" "none")
|
| 7058 |
|
|
(set_attr "length" "0")])
|
| 7059 |
|
|
|
| 7060 |
|
|
;
|
| 7061 |
|
|
; sibcall patterns
|
| 7062 |
|
|
;
|
| 7063 |
|
|
|
| 7064 |
|
|
(define_expand "sibcall"
|
| 7065 |
|
|
[(call (match_operand 0 "" "")
|
| 7066 |
|
|
(match_operand 1 "" ""))]
|
| 7067 |
|
|
""
|
| 7068 |
|
|
{
|
| 7069 |
|
|
s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
|
| 7070 |
|
|
DONE;
|
| 7071 |
|
|
})
|
| 7072 |
|
|
|
| 7073 |
|
|
(define_insn "*sibcall_br"
|
| 7074 |
|
|
[(call (mem:QI (reg SIBCALL_REGNUM))
|
| 7075 |
|
|
(match_operand 0 "const_int_operand" "n"))]
|
| 7076 |
|
|
"SIBLING_CALL_P (insn)
|
| 7077 |
|
|
&& GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
|
| 7078 |
|
|
"br\t%%r1"
|
| 7079 |
|
|
[(set_attr "op_type" "RR")
|
| 7080 |
|
|
(set_attr "type" "branch")
|
| 7081 |
|
|
(set_attr "atype" "agen")])
|
| 7082 |
|
|
|
| 7083 |
|
|
(define_insn "*sibcall_brc"
|
| 7084 |
|
|
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
|
| 7085 |
|
|
(match_operand 1 "const_int_operand" "n"))]
|
| 7086 |
|
|
"SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
|
| 7087 |
|
|
"j\t%0"
|
| 7088 |
|
|
[(set_attr "op_type" "RI")
|
| 7089 |
|
|
(set_attr "type" "branch")])
|
| 7090 |
|
|
|
| 7091 |
|
|
(define_insn "*sibcall_brcl"
|
| 7092 |
|
|
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
|
| 7093 |
|
|
(match_operand 1 "const_int_operand" "n"))]
|
| 7094 |
|
|
"SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
|
| 7095 |
|
|
"jg\t%0"
|
| 7096 |
|
|
[(set_attr "op_type" "RIL")
|
| 7097 |
|
|
(set_attr "type" "branch")])
|
| 7098 |
|
|
|
| 7099 |
|
|
;
|
| 7100 |
|
|
; sibcall_value patterns
|
| 7101 |
|
|
;
|
| 7102 |
|
|
|
| 7103 |
|
|
(define_expand "sibcall_value"
|
| 7104 |
|
|
[(set (match_operand 0 "" "")
|
| 7105 |
|
|
(call (match_operand 1 "" "")
|
| 7106 |
|
|
(match_operand 2 "" "")))]
|
| 7107 |
|
|
""
|
| 7108 |
|
|
{
|
| 7109 |
|
|
s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
|
| 7110 |
|
|
DONE;
|
| 7111 |
|
|
})
|
| 7112 |
|
|
|
| 7113 |
|
|
(define_insn "*sibcall_value_br"
|
| 7114 |
|
|
[(set (match_operand 0 "" "")
|
| 7115 |
|
|
(call (mem:QI (reg SIBCALL_REGNUM))
|
| 7116 |
|
|
(match_operand 1 "const_int_operand" "n")))]
|
| 7117 |
|
|
"SIBLING_CALL_P (insn)
|
| 7118 |
|
|
&& GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
|
| 7119 |
|
|
"br\t%%r1"
|
| 7120 |
|
|
[(set_attr "op_type" "RR")
|
| 7121 |
|
|
(set_attr "type" "branch")
|
| 7122 |
|
|
(set_attr "atype" "agen")])
|
| 7123 |
|
|
|
| 7124 |
|
|
(define_insn "*sibcall_value_brc"
|
| 7125 |
|
|
[(set (match_operand 0 "" "")
|
| 7126 |
|
|
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
|
| 7127 |
|
|
(match_operand 2 "const_int_operand" "n")))]
|
| 7128 |
|
|
"SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
|
| 7129 |
|
|
"j\t%1"
|
| 7130 |
|
|
[(set_attr "op_type" "RI")
|
| 7131 |
|
|
(set_attr "type" "branch")])
|
| 7132 |
|
|
|
| 7133 |
|
|
(define_insn "*sibcall_value_brcl"
|
| 7134 |
|
|
[(set (match_operand 0 "" "")
|
| 7135 |
|
|
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
|
| 7136 |
|
|
(match_operand 2 "const_int_operand" "n")))]
|
| 7137 |
|
|
"SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
|
| 7138 |
|
|
"jg\t%1"
|
| 7139 |
|
|
[(set_attr "op_type" "RIL")
|
| 7140 |
|
|
(set_attr "type" "branch")])
|
| 7141 |
|
|
|
| 7142 |
|
|
|
| 7143 |
|
|
;
|
| 7144 |
|
|
; call instruction pattern(s).
|
| 7145 |
|
|
;
|
| 7146 |
|
|
|
| 7147 |
|
|
(define_expand "call"
|
| 7148 |
|
|
[(call (match_operand 0 "" "")
|
| 7149 |
|
|
(match_operand 1 "" ""))
|
| 7150 |
|
|
(use (match_operand 2 "" ""))]
|
| 7151 |
|
|
""
|
| 7152 |
|
|
{
|
| 7153 |
|
|
s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
|
| 7154 |
|
|
gen_rtx_REG (Pmode, RETURN_REGNUM));
|
| 7155 |
|
|
DONE;
|
| 7156 |
|
|
})
|
| 7157 |
|
|
|
| 7158 |
|
|
(define_insn "*bras"
|
| 7159 |
|
|
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
|
| 7160 |
|
|
(match_operand 1 "const_int_operand" "n"))
|
| 7161 |
|
|
(clobber (match_operand 2 "register_operand" "=r"))]
|
| 7162 |
|
|
"!SIBLING_CALL_P (insn)
|
| 7163 |
|
|
&& TARGET_SMALL_EXEC
|
| 7164 |
|
|
&& GET_MODE (operands[2]) == Pmode"
|
| 7165 |
|
|
"bras\t%2,%0"
|
| 7166 |
|
|
[(set_attr "op_type" "RI")
|
| 7167 |
|
|
(set_attr "type" "jsr")])
|
| 7168 |
|
|
|
| 7169 |
|
|
(define_insn "*brasl"
|
| 7170 |
|
|
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
|
| 7171 |
|
|
(match_operand 1 "const_int_operand" "n"))
|
| 7172 |
|
|
(clobber (match_operand 2 "register_operand" "=r"))]
|
| 7173 |
|
|
"!SIBLING_CALL_P (insn)
|
| 7174 |
|
|
&& TARGET_CPU_ZARCH
|
| 7175 |
|
|
&& GET_MODE (operands[2]) == Pmode"
|
| 7176 |
|
|
"brasl\t%2,%0"
|
| 7177 |
|
|
[(set_attr "op_type" "RIL")
|
| 7178 |
|
|
(set_attr "type" "jsr")])
|
| 7179 |
|
|
|
| 7180 |
|
|
(define_insn "*basr"
|
| 7181 |
|
|
[(call (mem:QI (match_operand 0 "address_operand" "U"))
|
| 7182 |
|
|
(match_operand 1 "const_int_operand" "n"))
|
| 7183 |
|
|
(clobber (match_operand 2 "register_operand" "=r"))]
|
| 7184 |
|
|
"!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
|
| 7185 |
|
|
{
|
| 7186 |
|
|
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
| 7187 |
|
|
return "basr\t%2,%0";
|
| 7188 |
|
|
else
|
| 7189 |
|
|
return "bas\t%2,%a0";
|
| 7190 |
|
|
}
|
| 7191 |
|
|
[(set (attr "op_type")
|
| 7192 |
|
|
(if_then_else (match_operand 0 "register_operand" "")
|
| 7193 |
|
|
(const_string "RR") (const_string "RX")))
|
| 7194 |
|
|
(set_attr "type" "jsr")
|
| 7195 |
|
|
(set_attr "atype" "agen")])
|
| 7196 |
|
|
|
| 7197 |
|
|
;
|
| 7198 |
|
|
; call_value instruction pattern(s).
|
| 7199 |
|
|
;
|
| 7200 |
|
|
|
| 7201 |
|
|
(define_expand "call_value"
|
| 7202 |
|
|
[(set (match_operand 0 "" "")
|
| 7203 |
|
|
(call (match_operand 1 "" "")
|
| 7204 |
|
|
(match_operand 2 "" "")))
|
| 7205 |
|
|
(use (match_operand 3 "" ""))]
|
| 7206 |
|
|
""
|
| 7207 |
|
|
{
|
| 7208 |
|
|
s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
|
| 7209 |
|
|
gen_rtx_REG (Pmode, RETURN_REGNUM));
|
| 7210 |
|
|
DONE;
|
| 7211 |
|
|
})
|
| 7212 |
|
|
|
| 7213 |
|
|
(define_insn "*bras_r"
|
| 7214 |
|
|
[(set (match_operand 0 "" "")
|
| 7215 |
|
|
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
|
| 7216 |
|
|
(match_operand:SI 2 "const_int_operand" "n")))
|
| 7217 |
|
|
(clobber (match_operand 3 "register_operand" "=r"))]
|
| 7218 |
|
|
"!SIBLING_CALL_P (insn)
|
| 7219 |
|
|
&& TARGET_SMALL_EXEC
|
| 7220 |
|
|
&& GET_MODE (operands[3]) == Pmode"
|
| 7221 |
|
|
"bras\t%3,%1"
|
| 7222 |
|
|
[(set_attr "op_type" "RI")
|
| 7223 |
|
|
(set_attr "type" "jsr")])
|
| 7224 |
|
|
|
| 7225 |
|
|
(define_insn "*brasl_r"
|
| 7226 |
|
|
[(set (match_operand 0 "" "")
|
| 7227 |
|
|
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
|
| 7228 |
|
|
(match_operand 2 "const_int_operand" "n")))
|
| 7229 |
|
|
(clobber (match_operand 3 "register_operand" "=r"))]
|
| 7230 |
|
|
"!SIBLING_CALL_P (insn)
|
| 7231 |
|
|
&& TARGET_CPU_ZARCH
|
| 7232 |
|
|
&& GET_MODE (operands[3]) == Pmode"
|
| 7233 |
|
|
"brasl\t%3,%1"
|
| 7234 |
|
|
[(set_attr "op_type" "RIL")
|
| 7235 |
|
|
(set_attr "type" "jsr")])
|
| 7236 |
|
|
|
| 7237 |
|
|
(define_insn "*basr_r"
|
| 7238 |
|
|
[(set (match_operand 0 "" "")
|
| 7239 |
|
|
(call (mem:QI (match_operand 1 "address_operand" "U"))
|
| 7240 |
|
|
(match_operand 2 "const_int_operand" "n")))
|
| 7241 |
|
|
(clobber (match_operand 3 "register_operand" "=r"))]
|
| 7242 |
|
|
"!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
|
| 7243 |
|
|
{
|
| 7244 |
|
|
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
| 7245 |
|
|
return "basr\t%3,%1";
|
| 7246 |
|
|
else
|
| 7247 |
|
|
return "bas\t%3,%a1";
|
| 7248 |
|
|
}
|
| 7249 |
|
|
[(set (attr "op_type")
|
| 7250 |
|
|
(if_then_else (match_operand 1 "register_operand" "")
|
| 7251 |
|
|
(const_string "RR") (const_string "RX")))
|
| 7252 |
|
|
(set_attr "type" "jsr")
|
| 7253 |
|
|
(set_attr "atype" "agen")])
|
| 7254 |
|
|
|
| 7255 |
|
|
;;
|
| 7256 |
|
|
;;- Thread-local storage support.
|
| 7257 |
|
|
;;
|
| 7258 |
|
|
|
| 7259 |
|
|
(define_expand "get_tp_64"
|
| 7260 |
|
|
[(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
|
| 7261 |
|
|
"TARGET_64BIT"
|
| 7262 |
|
|
"")
|
| 7263 |
|
|
|
| 7264 |
|
|
(define_expand "get_tp_31"
|
| 7265 |
|
|
[(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
|
| 7266 |
|
|
"!TARGET_64BIT"
|
| 7267 |
|
|
"")
|
| 7268 |
|
|
|
| 7269 |
|
|
(define_expand "set_tp_64"
|
| 7270 |
|
|
[(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
|
| 7271 |
|
|
(set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
|
| 7272 |
|
|
"TARGET_64BIT"
|
| 7273 |
|
|
"")
|
| 7274 |
|
|
|
| 7275 |
|
|
(define_expand "set_tp_31"
|
| 7276 |
|
|
[(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
|
| 7277 |
|
|
(set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
|
| 7278 |
|
|
"!TARGET_64BIT"
|
| 7279 |
|
|
"")
|
| 7280 |
|
|
|
| 7281 |
|
|
(define_insn "*set_tp"
|
| 7282 |
|
|
[(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
|
| 7283 |
|
|
""
|
| 7284 |
|
|
""
|
| 7285 |
|
|
[(set_attr "type" "none")
|
| 7286 |
|
|
(set_attr "length" "0")])
|
| 7287 |
|
|
|
| 7288 |
|
|
(define_insn "*tls_load_64"
|
| 7289 |
|
|
[(set (match_operand:DI 0 "register_operand" "=d")
|
| 7290 |
|
|
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
| 7291 |
|
|
(match_operand:DI 2 "" "")]
|
| 7292 |
|
|
UNSPEC_TLS_LOAD))]
|
| 7293 |
|
|
"TARGET_64BIT"
|
| 7294 |
|
|
"lg\t%0,%1%J2"
|
| 7295 |
|
|
[(set_attr "op_type" "RXE")])
|
| 7296 |
|
|
|
| 7297 |
|
|
(define_insn "*tls_load_31"
|
| 7298 |
|
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
| 7299 |
|
|
(unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
|
| 7300 |
|
|
(match_operand:SI 2 "" "")]
|
| 7301 |
|
|
UNSPEC_TLS_LOAD))]
|
| 7302 |
|
|
"!TARGET_64BIT"
|
| 7303 |
|
|
"@
|
| 7304 |
|
|
l\t%0,%1%J2
|
| 7305 |
|
|
ly\t%0,%1%J2"
|
| 7306 |
|
|
[(set_attr "op_type" "RX,RXY")])
|
| 7307 |
|
|
|
| 7308 |
|
|
(define_insn "*bras_tls"
|
| 7309 |
|
|
[(set (match_operand 0 "" "")
|
| 7310 |
|
|
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
|
| 7311 |
|
|
(match_operand 2 "const_int_operand" "n")))
|
| 7312 |
|
|
(clobber (match_operand 3 "register_operand" "=r"))
|
| 7313 |
|
|
(use (match_operand 4 "" ""))]
|
| 7314 |
|
|
"!SIBLING_CALL_P (insn)
|
| 7315 |
|
|
&& TARGET_SMALL_EXEC
|
| 7316 |
|
|
&& GET_MODE (operands[3]) == Pmode"
|
| 7317 |
|
|
"bras\t%3,%1%J4"
|
| 7318 |
|
|
[(set_attr "op_type" "RI")
|
| 7319 |
|
|
(set_attr "type" "jsr")])
|
| 7320 |
|
|
|
| 7321 |
|
|
(define_insn "*brasl_tls"
|
| 7322 |
|
|
[(set (match_operand 0 "" "")
|
| 7323 |
|
|
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
|
| 7324 |
|
|
(match_operand 2 "const_int_operand" "n")))
|
| 7325 |
|
|
(clobber (match_operand 3 "register_operand" "=r"))
|
| 7326 |
|
|
(use (match_operand 4 "" ""))]
|
| 7327 |
|
|
"!SIBLING_CALL_P (insn)
|
| 7328 |
|
|
&& TARGET_CPU_ZARCH
|
| 7329 |
|
|
&& GET_MODE (operands[3]) == Pmode"
|
| 7330 |
|
|
"brasl\t%3,%1%J4"
|
| 7331 |
|
|
[(set_attr "op_type" "RIL")
|
| 7332 |
|
|
(set_attr "type" "jsr")])
|
| 7333 |
|
|
|
| 7334 |
|
|
(define_insn "*basr_tls"
|
| 7335 |
|
|
[(set (match_operand 0 "" "")
|
| 7336 |
|
|
(call (mem:QI (match_operand 1 "address_operand" "U"))
|
| 7337 |
|
|
(match_operand 2 "const_int_operand" "n")))
|
| 7338 |
|
|
(clobber (match_operand 3 "register_operand" "=r"))
|
| 7339 |
|
|
(use (match_operand 4 "" ""))]
|
| 7340 |
|
|
"!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
|
| 7341 |
|
|
{
|
| 7342 |
|
|
if (get_attr_op_type (insn) == OP_TYPE_RR)
|
| 7343 |
|
|
return "basr\t%3,%1%J4";
|
| 7344 |
|
|
else
|
| 7345 |
|
|
return "bas\t%3,%a1%J4";
|
| 7346 |
|
|
}
|
| 7347 |
|
|
[(set (attr "op_type")
|
| 7348 |
|
|
(if_then_else (match_operand 1 "register_operand" "")
|
| 7349 |
|
|
(const_string "RR") (const_string "RX")))
|
| 7350 |
|
|
(set_attr "type" "jsr")
|
| 7351 |
|
|
(set_attr "atype" "agen")])
|
| 7352 |
|
|
|
| 7353 |
|
|
;;
|
| 7354 |
|
|
;;- Atomic operations
|
| 7355 |
|
|
;;
|
| 7356 |
|
|
|
| 7357 |
|
|
;
|
| 7358 |
|
|
; memory barrier pattern.
|
| 7359 |
|
|
;
|
| 7360 |
|
|
|
| 7361 |
|
|
(define_expand "memory_barrier"
|
| 7362 |
|
|
[(set (mem:BLK (match_dup 0))
|
| 7363 |
|
|
(unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
|
| 7364 |
|
|
""
|
| 7365 |
|
|
{
|
| 7366 |
|
|
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
|
| 7367 |
|
|
MEM_VOLATILE_P (operands[0]) = 1;
|
| 7368 |
|
|
})
|
| 7369 |
|
|
|
| 7370 |
|
|
(define_insn "*memory_barrier"
|
| 7371 |
|
|
[(set (match_operand:BLK 0 "" "")
|
| 7372 |
|
|
(unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
|
| 7373 |
|
|
""
|
| 7374 |
|
|
"bcr\t15,0"
|
| 7375 |
|
|
[(set_attr "op_type" "RR")])
|
| 7376 |
|
|
|
| 7377 |
|
|
;
|
| 7378 |
|
|
; compare and swap patterns.
|
| 7379 |
|
|
;
|
| 7380 |
|
|
|
| 7381 |
|
|
(define_expand "sync_compare_and_swap"
|
| 7382 |
|
|
[(parallel
|
| 7383 |
|
|
[(set (match_operand:TDSI 0 "register_operand" "")
|
| 7384 |
|
|
(match_operand:TDSI 1 "memory_operand" ""))
|
| 7385 |
|
|
(set (match_dup 1)
|
| 7386 |
|
|
(unspec_volatile:TDSI
|
| 7387 |
|
|
[(match_dup 1)
|
| 7388 |
|
|
(match_operand:TDSI 2 "register_operand" "")
|
| 7389 |
|
|
(match_operand:TDSI 3 "register_operand" "")]
|
| 7390 |
|
|
UNSPECV_CAS))
|
| 7391 |
|
|
(set (reg:CCZ1 CC_REGNUM)
|
| 7392 |
|
|
(compare:CCZ1 (match_dup 1) (match_dup 2)))])]
|
| 7393 |
|
|
"")
|
| 7394 |
|
|
|
| 7395 |
|
|
(define_expand "sync_compare_and_swap"
|
| 7396 |
|
|
[(parallel
|
| 7397 |
|
|
[(set (match_operand:HQI 0 "register_operand" "")
|
| 7398 |
|
|
(match_operand:HQI 1 "memory_operand" ""))
|
| 7399 |
|
|
(set (match_dup 1)
|
| 7400 |
|
|
(unspec_volatile:HQI
|
| 7401 |
|
|
[(match_dup 1)
|
| 7402 |
|
|
(match_operand:HQI 2 "general_operand" "")
|
| 7403 |
|
|
(match_operand:HQI 3 "general_operand" "")]
|
| 7404 |
|
|
UNSPECV_CAS))
|
| 7405 |
|
|
(set (reg:CCZ1 CC_REGNUM)
|
| 7406 |
|
|
(compare:CCZ1 (match_dup 1) (match_dup 2)))])]
|
| 7407 |
|
|
""
|
| 7408 |
|
|
"s390_expand_cs_hqi (mode, operands[0], operands[1],
|
| 7409 |
|
|
operands[2], operands[3]); DONE;")
|
| 7410 |
|
|
|
| 7411 |
|
|
(define_expand "sync_compare_and_swap_cc"
|
| 7412 |
|
|
[(parallel
|
| 7413 |
|
|
[(set (match_operand:TDSI 0 "register_operand" "")
|
| 7414 |
|
|
(match_operand:TDSI 1 "memory_operand" ""))
|
| 7415 |
|
|
(set (match_dup 1)
|
| 7416 |
|
|
(unspec_volatile:TDSI
|
| 7417 |
|
|
[(match_dup 1)
|
| 7418 |
|
|
(match_operand:TDSI 2 "register_operand" "")
|
| 7419 |
|
|
(match_operand:TDSI 3 "register_operand" "")]
|
| 7420 |
|
|
UNSPECV_CAS))
|
| 7421 |
|
|
(set (match_dup 4)
|
| 7422 |
|
|
(compare:CCZ1 (match_dup 1) (match_dup 2)))])]
|
| 7423 |
|
|
""
|
| 7424 |
|
|
{
|
| 7425 |
|
|
/* Emulate compare. */
|
| 7426 |
|
|
operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
|
| 7427 |
|
|
s390_compare_op0 = operands[1];
|
| 7428 |
|
|
s390_compare_op1 = operands[2];
|
| 7429 |
|
|
s390_compare_emitted = operands[4];
|
| 7430 |
|
|
})
|
| 7431 |
|
|
|
| 7432 |
|
|
; cds, cdsg
|
| 7433 |
|
|
(define_insn "*sync_compare_and_swap"
|
| 7434 |
|
|
[(set (match_operand:DP 0 "register_operand" "=r")
|
| 7435 |
|
|
(match_operand:DP 1 "memory_operand" "+Q"))
|
| 7436 |
|
|
(set (match_dup 1)
|
| 7437 |
|
|
(unspec_volatile:DP
|
| 7438 |
|
|
[(match_dup 1)
|
| 7439 |
|
|
(match_operand:DP 2 "register_operand" "0")
|
| 7440 |
|
|
(match_operand:DP 3 "register_operand" "r")]
|
| 7441 |
|
|
UNSPECV_CAS))
|
| 7442 |
|
|
(set (reg:CCZ1 CC_REGNUM)
|
| 7443 |
|
|
(compare:CCZ1 (match_dup 1) (match_dup 2)))]
|
| 7444 |
|
|
""
|
| 7445 |
|
|
"cds\t%0,%3,%S1"
|
| 7446 |
|
|
[(set_attr "op_type" "RS")
|
| 7447 |
|
|
(set_attr "type" "sem")])
|
| 7448 |
|
|
|
| 7449 |
|
|
; cs, csg
|
| 7450 |
|
|
(define_insn "*sync_compare_and_swap"
|
| 7451 |
|
|
[(set (match_operand:GPR 0 "register_operand" "=r")
|
| 7452 |
|
|
(match_operand:GPR 1 "memory_operand" "+Q"))
|
| 7453 |
|
|
(set (match_dup 1)
|
| 7454 |
|
|
(unspec_volatile:GPR
|
| 7455 |
|
|
[(match_dup 1)
|
| 7456 |
|
|
(match_operand:GPR 2 "register_operand" "0")
|
| 7457 |
|
|
(match_operand:GPR 3 "register_operand" "r")]
|
| 7458 |
|
|
UNSPECV_CAS))
|
| 7459 |
|
|
(set (reg:CCZ1 CC_REGNUM)
|
| 7460 |
|
|
(compare:CCZ1 (match_dup 1) (match_dup 2)))]
|
| 7461 |
|
|
""
|
| 7462 |
|
|
"cs\t%0,%3,%S1"
|
| 7463 |
|
|
[(set_attr "op_type" "RS")
|
| 7464 |
|
|
(set_attr "type" "sem")])
|
| 7465 |
|
|
|
| 7466 |
|
|
|
| 7467 |
|
|
;
|
| 7468 |
|
|
; Other atomic instruction patterns.
|
| 7469 |
|
|
;
|
| 7470 |
|
|
|
| 7471 |
|
|
(define_expand "sync_lock_test_and_set"
|
| 7472 |
|
|
[(match_operand:HQI 0 "register_operand")
|
| 7473 |
|
|
(match_operand:HQI 1 "memory_operand")
|
| 7474 |
|
|
(match_operand:HQI 2 "general_operand")]
|
| 7475 |
|
|
""
|
| 7476 |
|
|
"s390_expand_atomic (mode, SET, operands[0], operands[1],
|
| 7477 |
|
|
operands[2], false); DONE;")
|
| 7478 |
|
|
|
| 7479 |
|
|
(define_expand "sync_"
|
| 7480 |
|
|
[(set (match_operand:HQI 0 "memory_operand")
|
| 7481 |
|
|
(ATOMIC:HQI (match_dup 0)
|
| 7482 |
|
|
(match_operand:HQI 1 "general_operand")))]
|
| 7483 |
|
|
""
|
| 7484 |
|
|
"s390_expand_atomic (mode, , NULL_RTX, operands[0],
|
| 7485 |
|
|
operands[1], false); DONE;")
|
| 7486 |
|
|
|
| 7487 |
|
|
(define_expand "sync_old_"
|
| 7488 |
|
|
[(set (match_operand:HQI 0 "register_operand")
|
| 7489 |
|
|
(match_operand:HQI 1 "memory_operand"))
|
| 7490 |
|
|
(set (match_dup 1)
|
| 7491 |
|
|
(ATOMIC:HQI (match_dup 1)
|
| 7492 |
|
|
(match_operand:HQI 2 "general_operand")))]
|
| 7493 |
|
|
""
|
| 7494 |
|
|
"s390_expand_atomic (mode, , operands[0], operands[1],
|
| 7495 |
|
|
operands[2], false); DONE;")
|
| 7496 |
|
|
|
| 7497 |
|
|
(define_expand "sync_new_"
|
| 7498 |
|
|
[(set (match_operand:HQI 0 "register_operand")
|
| 7499 |
|
|
(ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
|
| 7500 |
|
|
(match_operand:HQI 2 "general_operand")))
|
| 7501 |
|
|
(set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
|
| 7502 |
|
|
""
|
| 7503 |
|
|
"s390_expand_atomic (mode, , operands[0], operands[1],
|
| 7504 |
|
|
operands[2], true); DONE;")
|
| 7505 |
|
|
|
| 7506 |
|
|
;;
|
| 7507 |
|
|
;;- Miscellaneous instructions.
|
| 7508 |
|
|
;;
|
| 7509 |
|
|
|
| 7510 |
|
|
;
|
| 7511 |
|
|
; allocate stack instruction pattern(s).
|
| 7512 |
|
|
;
|
| 7513 |
|
|
|
| 7514 |
|
|
(define_expand "allocate_stack"
|
| 7515 |
|
|
[(match_operand 0 "general_operand" "")
|
| 7516 |
|
|
(match_operand 1 "general_operand" "")]
|
| 7517 |
|
|
"TARGET_BACKCHAIN"
|
| 7518 |
|
|
{
|
| 7519 |
|
|
rtx temp = gen_reg_rtx (Pmode);
|
| 7520 |
|
|
|
| 7521 |
|
|
emit_move_insn (temp, s390_back_chain_rtx ());
|
| 7522 |
|
|
anti_adjust_stack (operands[1]);
|
| 7523 |
|
|
emit_move_insn (s390_back_chain_rtx (), temp);
|
| 7524 |
|
|
|
| 7525 |
|
|
emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
|
| 7526 |
|
|
DONE;
|
| 7527 |
|
|
})
|
| 7528 |
|
|
|
| 7529 |
|
|
|
| 7530 |
|
|
;
|
| 7531 |
|
|
; setjmp instruction pattern.
|
| 7532 |
|
|
;
|
| 7533 |
|
|
|
| 7534 |
|
|
(define_expand "builtin_setjmp_receiver"
|
| 7535 |
|
|
[(match_operand 0 "" "")]
|
| 7536 |
|
|
"flag_pic"
|
| 7537 |
|
|
{
|
| 7538 |
|
|
emit_insn (s390_load_got ());
|
| 7539 |
|
|
emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
|
| 7540 |
|
|
DONE;
|
| 7541 |
|
|
})
|
| 7542 |
|
|
|
| 7543 |
|
|
;; These patterns say how to save and restore the stack pointer. We need not
|
| 7544 |
|
|
;; save the stack pointer at function level since we are careful to
|
| 7545 |
|
|
;; preserve the backchain. At block level, we have to restore the backchain
|
| 7546 |
|
|
;; when we restore the stack pointer.
|
| 7547 |
|
|
;;
|
| 7548 |
|
|
;; For nonlocal gotos, we must save both the stack pointer and its
|
| 7549 |
|
|
;; backchain and restore both. Note that in the nonlocal case, the
|
| 7550 |
|
|
;; save area is a memory location.
|
| 7551 |
|
|
|
| 7552 |
|
|
(define_expand "save_stack_function"
|
| 7553 |
|
|
[(match_operand 0 "general_operand" "")
|
| 7554 |
|
|
(match_operand 1 "general_operand" "")]
|
| 7555 |
|
|
""
|
| 7556 |
|
|
"DONE;")
|
| 7557 |
|
|
|
| 7558 |
|
|
(define_expand "restore_stack_function"
|
| 7559 |
|
|
[(match_operand 0 "general_operand" "")
|
| 7560 |
|
|
(match_operand 1 "general_operand" "")]
|
| 7561 |
|
|
""
|
| 7562 |
|
|
"DONE;")
|
| 7563 |
|
|
|
| 7564 |
|
|
(define_expand "restore_stack_block"
|
| 7565 |
|
|
[(match_operand 0 "register_operand" "")
|
| 7566 |
|
|
(match_operand 1 "register_operand" "")]
|
| 7567 |
|
|
"TARGET_BACKCHAIN"
|
| 7568 |
|
|
{
|
| 7569 |
|
|
rtx temp = gen_reg_rtx (Pmode);
|
| 7570 |
|
|
|
| 7571 |
|
|
emit_move_insn (temp, s390_back_chain_rtx ());
|
| 7572 |
|
|
emit_move_insn (operands[0], operands[1]);
|
| 7573 |
|
|
emit_move_insn (s390_back_chain_rtx (), temp);
|
| 7574 |
|
|
|
| 7575 |
|
|
DONE;
|
| 7576 |
|
|
})
|
| 7577 |
|
|
|
| 7578 |
|
|
(define_expand "save_stack_nonlocal"
|
| 7579 |
|
|
[(match_operand 0 "memory_operand" "")
|
| 7580 |
|
|
(match_operand 1 "register_operand" "")]
|
| 7581 |
|
|
""
|
| 7582 |
|
|
{
|
| 7583 |
|
|
enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
|
| 7584 |
|
|
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
|
| 7585 |
|
|
|
| 7586 |
|
|
/* Copy the backchain to the first word, sp to the second and the
|
| 7587 |
|
|
literal pool base to the third. */
|
| 7588 |
|
|
|
| 7589 |
|
|
if (TARGET_BACKCHAIN)
|
| 7590 |
|
|
{
|
| 7591 |
|
|
rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
|
| 7592 |
|
|
emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
|
| 7593 |
|
|
}
|
| 7594 |
|
|
|
| 7595 |
|
|
emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
|
| 7596 |
|
|
emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
|
| 7597 |
|
|
|
| 7598 |
|
|
DONE;
|
| 7599 |
|
|
})
|
| 7600 |
|
|
|
| 7601 |
|
|
(define_expand "restore_stack_nonlocal"
|
| 7602 |
|
|
[(match_operand 0 "register_operand" "")
|
| 7603 |
|
|
(match_operand 1 "memory_operand" "")]
|
| 7604 |
|
|
""
|
| 7605 |
|
|
{
|
| 7606 |
|
|
enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
|
| 7607 |
|
|
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
|
| 7608 |
|
|
rtx temp = NULL_RTX;
|
| 7609 |
|
|
|
| 7610 |
|
|
/* Restore the backchain from the first word, sp from the second and the
|
| 7611 |
|
|
literal pool base from the third. */
|
| 7612 |
|
|
|
| 7613 |
|
|
if (TARGET_BACKCHAIN)
|
| 7614 |
|
|
temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
|
| 7615 |
|
|
|
| 7616 |
|
|
emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
|
| 7617 |
|
|
emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
|
| 7618 |
|
|
|
| 7619 |
|
|
if (temp)
|
| 7620 |
|
|
emit_move_insn (s390_back_chain_rtx (), temp);
|
| 7621 |
|
|
|
| 7622 |
|
|
emit_insn (gen_rtx_USE (VOIDmode, base));
|
| 7623 |
|
|
DONE;
|
| 7624 |
|
|
})
|
| 7625 |
|
|
|
| 7626 |
|
|
(define_expand "exception_receiver"
|
| 7627 |
|
|
[(const_int 0)]
|
| 7628 |
|
|
""
|
| 7629 |
|
|
{
|
| 7630 |
|
|
s390_set_has_landing_pad_p (true);
|
| 7631 |
|
|
DONE;
|
| 7632 |
|
|
})
|
| 7633 |
|
|
|
| 7634 |
|
|
;
|
| 7635 |
|
|
; nop instruction pattern(s).
|
| 7636 |
|
|
;
|
| 7637 |
|
|
|
| 7638 |
|
|
(define_insn "nop"
|
| 7639 |
|
|
[(const_int 0)]
|
| 7640 |
|
|
""
|
| 7641 |
|
|
"lr\t0,0"
|
| 7642 |
|
|
[(set_attr "op_type" "RR")])
|
| 7643 |
|
|
|
| 7644 |
|
|
|
| 7645 |
|
|
;
|
| 7646 |
|
|
; Special literal pool access instruction pattern(s).
|
| 7647 |
|
|
;
|
| 7648 |
|
|
|
| 7649 |
|
|
(define_insn "*pool_entry"
|
| 7650 |
|
|
[(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
|
| 7651 |
|
|
UNSPECV_POOL_ENTRY)]
|
| 7652 |
|
|
""
|
| 7653 |
|
|
{
|
| 7654 |
|
|
enum machine_mode mode = GET_MODE (PATTERN (insn));
|
| 7655 |
|
|
unsigned int align = GET_MODE_BITSIZE (mode);
|
| 7656 |
|
|
s390_output_pool_entry (operands[0], mode, align);
|
| 7657 |
|
|
return "";
|
| 7658 |
|
|
}
|
| 7659 |
|
|
[(set (attr "length")
|
| 7660 |
|
|
(symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
|
| 7661 |
|
|
|
| 7662 |
|
|
(define_insn "pool_align"
|
| 7663 |
|
|
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
|
| 7664 |
|
|
UNSPECV_POOL_ALIGN)]
|
| 7665 |
|
|
""
|
| 7666 |
|
|
".align\t%0"
|
| 7667 |
|
|
[(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
|
| 7668 |
|
|
|
| 7669 |
|
|
(define_insn "pool_section_start"
|
| 7670 |
|
|
[(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
|
| 7671 |
|
|
""
|
| 7672 |
|
|
".section\t.rodata"
|
| 7673 |
|
|
[(set_attr "length" "0")])
|
| 7674 |
|
|
|
| 7675 |
|
|
(define_insn "pool_section_end"
|
| 7676 |
|
|
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
|
| 7677 |
|
|
""
|
| 7678 |
|
|
".previous"
|
| 7679 |
|
|
[(set_attr "length" "0")])
|
| 7680 |
|
|
|
| 7681 |
|
|
(define_insn "main_base_31_small"
|
| 7682 |
|
|
[(set (match_operand 0 "register_operand" "=a")
|
| 7683 |
|
|
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
|
| 7684 |
|
|
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
| 7685 |
|
|
"basr\t%0,0"
|
| 7686 |
|
|
[(set_attr "op_type" "RR")
|
| 7687 |
|
|
(set_attr "type" "la")])
|
| 7688 |
|
|
|
| 7689 |
|
|
(define_insn "main_base_31_large"
|
| 7690 |
|
|
[(set (match_operand 0 "register_operand" "=a")
|
| 7691 |
|
|
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
|
| 7692 |
|
|
(set (pc) (label_ref (match_operand 2 "" "")))]
|
| 7693 |
|
|
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
| 7694 |
|
|
"bras\t%0,%2"
|
| 7695 |
|
|
[(set_attr "op_type" "RI")])
|
| 7696 |
|
|
|
| 7697 |
|
|
(define_insn "main_base_64"
|
| 7698 |
|
|
[(set (match_operand 0 "register_operand" "=a")
|
| 7699 |
|
|
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
|
| 7700 |
|
|
"TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
| 7701 |
|
|
"larl\t%0,%1"
|
| 7702 |
|
|
[(set_attr "op_type" "RIL")
|
| 7703 |
|
|
(set_attr "type" "larl")])
|
| 7704 |
|
|
|
| 7705 |
|
|
(define_insn "main_pool"
|
| 7706 |
|
|
[(set (match_operand 0 "register_operand" "=a")
|
| 7707 |
|
|
(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
|
| 7708 |
|
|
"GET_MODE (operands[0]) == Pmode"
|
| 7709 |
|
|
{
|
| 7710 |
|
|
gcc_unreachable ();
|
| 7711 |
|
|
}
|
| 7712 |
|
|
[(set (attr "type")
|
| 7713 |
|
|
(if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
|
| 7714 |
|
|
(const_string "larl") (const_string "la")))])
|
| 7715 |
|
|
|
| 7716 |
|
|
(define_insn "reload_base_31"
|
| 7717 |
|
|
[(set (match_operand 0 "register_operand" "=a")
|
| 7718 |
|
|
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
|
| 7719 |
|
|
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
| 7720 |
|
|
"basr\t%0,0\;la\t%0,%1-.(%0)"
|
| 7721 |
|
|
[(set_attr "length" "6")
|
| 7722 |
|
|
(set_attr "type" "la")])
|
| 7723 |
|
|
|
| 7724 |
|
|
(define_insn "reload_base_64"
|
| 7725 |
|
|
[(set (match_operand 0 "register_operand" "=a")
|
| 7726 |
|
|
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
|
| 7727 |
|
|
"TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
| 7728 |
|
|
"larl\t%0,%1"
|
| 7729 |
|
|
[(set_attr "op_type" "RIL")
|
| 7730 |
|
|
(set_attr "type" "larl")])
|
| 7731 |
|
|
|
| 7732 |
|
|
(define_insn "pool"
|
| 7733 |
|
|
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
|
| 7734 |
|
|
""
|
| 7735 |
|
|
{
|
| 7736 |
|
|
gcc_unreachable ();
|
| 7737 |
|
|
}
|
| 7738 |
|
|
[(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
|
| 7739 |
|
|
|
| 7740 |
|
|
;;
|
| 7741 |
|
|
;; Insns related to generating the function prologue and epilogue.
|
| 7742 |
|
|
;;
|
| 7743 |
|
|
|
| 7744 |
|
|
|
| 7745 |
|
|
(define_expand "prologue"
|
| 7746 |
|
|
[(use (const_int 0))]
|
| 7747 |
|
|
""
|
| 7748 |
|
|
"s390_emit_prologue (); DONE;")
|
| 7749 |
|
|
|
| 7750 |
|
|
(define_expand "epilogue"
|
| 7751 |
|
|
[(use (const_int 1))]
|
| 7752 |
|
|
""
|
| 7753 |
|
|
"s390_emit_epilogue (false); DONE;")
|
| 7754 |
|
|
|
| 7755 |
|
|
(define_expand "sibcall_epilogue"
|
| 7756 |
|
|
[(use (const_int 0))]
|
| 7757 |
|
|
""
|
| 7758 |
|
|
"s390_emit_epilogue (true); DONE;")
|
| 7759 |
|
|
|
| 7760 |
|
|
(define_insn "*return"
|
| 7761 |
|
|
[(return)
|
| 7762 |
|
|
(use (match_operand 0 "register_operand" "a"))]
|
| 7763 |
|
|
"GET_MODE (operands[0]) == Pmode"
|
| 7764 |
|
|
"br\t%0"
|
| 7765 |
|
|
[(set_attr "op_type" "RR")
|
| 7766 |
|
|
(set_attr "type" "jsr")
|
| 7767 |
|
|
(set_attr "atype" "agen")])
|
| 7768 |
|
|
|
| 7769 |
|
|
|
| 7770 |
|
|
;; Instruction definition to extend a 31-bit pointer into a 64-bit
|
| 7771 |
|
|
;; pointer. This is used for compatibility.
|
| 7772 |
|
|
|
| 7773 |
|
|
(define_expand "ptr_extend"
|
| 7774 |
|
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
| 7775 |
|
|
(match_operand:SI 1 "register_operand" "r"))]
|
| 7776 |
|
|
"TARGET_64BIT"
|
| 7777 |
|
|
{
|
| 7778 |
|
|
emit_insn (gen_anddi3 (operands[0],
|
| 7779 |
|
|
gen_lowpart (DImode, operands[1]),
|
| 7780 |
|
|
GEN_INT (0x7fffffff)));
|
| 7781 |
|
|
DONE;
|
| 7782 |
|
|
})
|
| 7783 |
|
|
|
| 7784 |
|
|
;; Instruction definition to expand eh_return macro to support
|
| 7785 |
|
|
;; swapping in special linkage return addresses.
|
| 7786 |
|
|
|
| 7787 |
|
|
(define_expand "eh_return"
|
| 7788 |
|
|
[(use (match_operand 0 "register_operand" ""))]
|
| 7789 |
|
|
"TARGET_TPF"
|
| 7790 |
|
|
{
|
| 7791 |
|
|
s390_emit_tpf_eh_return (operands[0]);
|
| 7792 |
|
|
DONE;
|
| 7793 |
|
|
})
|
| 7794 |
|
|
|
| 7795 |
|
|
;
|
| 7796 |
|
|
; Stack Protector Patterns
|
| 7797 |
|
|
;
|
| 7798 |
|
|
|
| 7799 |
|
|
(define_expand "stack_protect_set"
|
| 7800 |
|
|
[(set (match_operand 0 "memory_operand" "")
|
| 7801 |
|
|
(match_operand 1 "memory_operand" ""))]
|
| 7802 |
|
|
""
|
| 7803 |
|
|
{
|
| 7804 |
|
|
#ifdef TARGET_THREAD_SSP_OFFSET
|
| 7805 |
|
|
operands[1]
|
| 7806 |
|
|
= gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
|
| 7807 |
|
|
GEN_INT (TARGET_THREAD_SSP_OFFSET)));
|
| 7808 |
|
|
#endif
|
| 7809 |
|
|
if (TARGET_64BIT)
|
| 7810 |
|
|
emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
|
| 7811 |
|
|
else
|
| 7812 |
|
|
emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
|
| 7813 |
|
|
|
| 7814 |
|
|
DONE;
|
| 7815 |
|
|
})
|
| 7816 |
|
|
|
| 7817 |
|
|
(define_insn "stack_protect_set"
|
| 7818 |
|
|
[(set (match_operand:DSI 0 "memory_operand" "=Q")
|
| 7819 |
|
|
(unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
|
| 7820 |
|
|
""
|
| 7821 |
|
|
"mvc\t%O0(%G0,%R0),%S1"
|
| 7822 |
|
|
[(set_attr "op_type" "SS")])
|
| 7823 |
|
|
|
| 7824 |
|
|
(define_expand "stack_protect_test"
|
| 7825 |
|
|
[(set (reg:CC CC_REGNUM)
|
| 7826 |
|
|
(compare (match_operand 0 "memory_operand" "")
|
| 7827 |
|
|
(match_operand 1 "memory_operand" "")))
|
| 7828 |
|
|
(match_operand 2 "" "")]
|
| 7829 |
|
|
""
|
| 7830 |
|
|
{
|
| 7831 |
|
|
#ifdef TARGET_THREAD_SSP_OFFSET
|
| 7832 |
|
|
operands[1]
|
| 7833 |
|
|
= gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
|
| 7834 |
|
|
GEN_INT (TARGET_THREAD_SSP_OFFSET)));
|
| 7835 |
|
|
#endif
|
| 7836 |
|
|
s390_compare_op0 = operands[0];
|
| 7837 |
|
|
s390_compare_op1 = operands[1];
|
| 7838 |
|
|
s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
|
| 7839 |
|
|
|
| 7840 |
|
|
if (TARGET_64BIT)
|
| 7841 |
|
|
emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
|
| 7842 |
|
|
else
|
| 7843 |
|
|
emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
|
| 7844 |
|
|
|
| 7845 |
|
|
emit_jump_insn (gen_beq (operands[2]));
|
| 7846 |
|
|
|
| 7847 |
|
|
DONE;
|
| 7848 |
|
|
})
|
| 7849 |
|
|
|
| 7850 |
|
|
(define_insn "stack_protect_test"
|
| 7851 |
|
|
[(set (reg:CCZ CC_REGNUM)
|
| 7852 |
|
|
(unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
|
| 7853 |
|
|
(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
|
| 7854 |
|
|
""
|
| 7855 |
|
|
"clc\t%O0(%G0,%R0),%S1"
|
| 7856 |
|
|
[(set_attr "op_type" "SS")])
|
