OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [score/] [mac.md] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
;;  Machine description for Sunplus S+CORE
2 
;;  Copyright (C) 2005, 2007
3 
;;  Free Software Foundation, Inc.
4 
;;  Contributed by Sunnorth.
5 
 
6 
;; This file is part of GCC.
7 
 
8 
;; GCC is free software; you can redistribute it and/or modify
9 
;; it under the terms of the GNU General Public License as published by
10 
;; the Free Software Foundation; either version 3, or (at your option)
11 
;; any later version.
12 
 
13 
;; GCC is distributed in the hope that it will be useful,
14 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
;; GNU General Public License for more details.
17 
 
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .
21 
 
22 
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 
 
24 
(define_insn "smaxsi3"
25 
  [(set (match_operand:SI 0 "register_operand" "=d")
26 
        (smax:SI (match_operand:SI 1 "register_operand" "d")
27 
                 (match_operand:SI 2 "register_operand" "d")))]
28 
  "TARGET_MAC || TARGET_SCORE7D"
29 
  "max     %0, %1, %2"
30 
  [(set_attr "type" "arith")
31 
   (set_attr "mode" "SI")])
32 
 
33 
(define_insn "sminsi3"
34 
  [(set (match_operand:SI 0 "register_operand" "=d")
35 
        (smin:SI (match_operand:SI 1 "register_operand" "d")
36 
                 (match_operand:SI 2 "register_operand" "d")))]
37 
  "TARGET_MAC || TARGET_SCORE7D"
38 
  "min     %0, %1, %2"
39 
  [(set_attr "type" "arith")
40 
   (set_attr "mode" "SI")])
41 
 
42 
(define_insn "abssi2"
43 
  [(set (match_operand:SI 0 "register_operand" "=d")
44 
        (abs:SI (match_operand:SI 1 "register_operand" "d")))]
45 
  "TARGET_MAC || TARGET_SCORE7D"
46 
  "abs     %0, %1"
47 
  [(set_attr "type" "arith")
48 
   (set_attr "mode" "SI")])
49 
 
50 
(define_insn "clzsi2"
51 
  [(set (match_operand:SI 0 "register_operand" "=d")
52 
        (clz:SI (match_operand:SI 1 "register_operand" "d")))]
53 
  "TARGET_MAC || TARGET_SCORE7D"
54 
  "clz     %0, %1"
55 
  [(set_attr "type" "arith")
56 
   (set_attr "mode" "SI")])
57 
 
58 
(define_insn "sffs"
59 
  [(set (match_operand:SI 0 "register_operand" "=d")
60 
        (unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))]
61 
  "TARGET_MAC || TARGET_SCORE7D"
62 
  "bitrev  %0, %1, r0\;clz     %0, %0\;addi    %0, 0x1"
63 
  [(set_attr "type" "arith")
64 
   (set_attr "mode" "SI")])
65 
 
66 
(define_expand "ffssi2"
67 
  [(set (match_operand:SI 0 "register_operand")
68 
        (ffs:SI (match_operand:SI 1 "register_operand")))]
69 
  "TARGET_MAC || TARGET_SCORE7D"
70 
{
71 
  emit_insn (gen_sffs (operands[0], operands[1]));
72 
  emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM),
73 
                          gen_rtx_COMPARE (CC_NZmode, operands[0],
74 
                                           GEN_INT (33))));
75 
  emit_insn (gen_movsicc_internal (operands[0],
76 
             gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
77 
             GEN_INT (0),
78 
             operands[0]));
79 
  DONE;
80 
})
81 
 
82 
(define_peephole2
83 
  [(set (match_operand:SI 0 "loreg_operand" "")
84 
        (match_operand:SI 1 "register_operand" ""))
85 
   (set (match_operand:SI 2 "hireg_operand" "")
86 
        (match_operand:SI 3 "register_operand" ""))]
87 
  "TARGET_MAC || TARGET_SCORE7D"
88 
  [(parallel
89 
       [(set (match_dup 0) (match_dup 1))
90 
        (set (match_dup 2) (match_dup 3))])])
91 
 
92 
(define_peephole2
93 
  [(set (match_operand:SI 0 "hireg_operand" "")
94 
        (match_operand:SI 1 "register_operand" ""))
95 
   (set (match_operand:SI 2 "loreg_operand" "")
96 
        (match_operand:SI 3 "register_operand" ""))]
97 
  "TARGET_MAC || TARGET_SCORE7D"
98 
  [(parallel
99 
       [(set (match_dup 2) (match_dup 3))
100 
        (set (match_dup 0) (match_dup 1))])])
101 
 
102 
(define_insn "movtohilo"
103 
  [(parallel
104 
       [(set (match_operand:SI 0 "loreg_operand" "=l")
105 
             (match_operand:SI 1 "register_operand" "d"))
106 
        (set (match_operand:SI 2 "hireg_operand" "=h")
107 
             (match_operand:SI 3 "register_operand" "d"))])]
108 
  "TARGET_MAC || TARGET_SCORE7D"
109 
  "mtcehl  %3, %1"
110 
  [(set_attr "type" "fce")
111 
   (set_attr "mode" "SI")])
112 
 
113 
(define_insn "mulsi3addsi"
114 
  [(set (match_operand:SI 0 "register_operand" "=l,l,d")
115 
        (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
116 
                          (match_operand:SI 3 "register_operand" "d,d,d"))
117 
                 (match_operand:SI 1 "register_operand" "0,d,l")))
118 
   (clobber (reg:SI HI_REGNUM))]
119 
  "TARGET_MAC || TARGET_SCORE7D"
120 
  "@
121 
   mad     %2, %3
122 
   mtcel%S1 %1\;mad     %2, %3
123 
   mad      %2, %3\;mfcel%S0 %0"
124 
  [(set_attr "mode" "SI")])
125 
 
126 
(define_insn "mulsi3subsi"
127 
  [(set (match_operand:SI 0 "register_operand" "=l,l,d")
128 
        (minus:SI (match_operand:SI 1 "register_operand" "0,d,l")
129 
                  (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
130 
                           (match_operand:SI 3 "register_operand" "d,d,d"))))
131 
   (clobber (reg:SI HI_REGNUM))]
132 
  "TARGET_MAC || TARGET_SCORE7D"
133 
  "@
134 
   msb     %2, %3
135 
   mtcel%S1 %1\;msb     %2, %3
136 
   msb     %2, %3\;mfcel%S0 %0"
137 
  [(set_attr "mode" "SI")])
138 
 
139 
(define_insn "mulsidi3adddi"
140 
  [(set (match_operand:DI 0 "register_operand" "=x")
141 
        (plus:DI (mult:DI
142 
                  (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
143 
                  (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))
144 
                 (match_operand:DI 1 "register_operand" "0")))]
145 
  "TARGET_MAC || TARGET_SCORE7D"
146 
  "mad     %2, %3"
147 
  [(set_attr "mode" "DI")])
148 
 
149 
(define_insn "umulsidi3adddi"
150 
  [(set (match_operand:DI 0 "register_operand" "=x")
151 
        (plus:DI (mult:DI
152 
                  (zero_extend:DI (match_operand:SI 2 "register_operand" "%d"))
153 
                  (zero_extend:DI (match_operand:SI 3 "register_operand" "d")))
154 
                 (match_operand:DI 1 "register_operand" "0")))]
155 
  "TARGET_MAC || TARGET_SCORE7D"
156 
  "madu    %2, %3"
157 
  [(set_attr "mode" "DI")])
158 
 
159 
(define_insn "mulsidi3subdi"
160 
  [(set (match_operand:DI 0 "register_operand" "=x")
161 
        (minus:DI
162 
         (match_operand:DI 1 "register_operand" "0")
163 
         (mult:DI
164 
          (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
165 
          (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))]
166 
  "TARGET_MAC || TARGET_SCORE7D"
167 
  "msb     %2, %3"
168 
  [(set_attr "mode" "DI")])
169 
 
170 
(define_insn "umulsidi3subdi"
171 
  [(set (match_operand:DI 0 "register_operand" "=x")
172 
        (minus:DI
173 
         (match_operand:DI 1 "register_operand" "0")
174 
         (mult:DI (zero_extend:DI
175 
                   (match_operand:SI 2 "register_operand" "%d"))
176 
                  (zero_extend:DI
177 
                   (match_operand:SI 3 "register_operand" "d")))))]
178 
  "TARGET_MAC || TARGET_SCORE7D"
179 
  "msbu    %2, %3"
180 
  [(set_attr "mode" "DI")])

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.