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julius |
;; Machine description for Sunplus S+CORE
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;; Copyright (C) 2005, 2007
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;; Free Software Foundation, Inc.
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;; Contributed by Sunnorth.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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(define_insn "smaxsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(smax:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "d")))]
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"TARGET_MAC || TARGET_SCORE7D"
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"max %0, %1, %2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "sminsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(smin:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "d")))]
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"TARGET_MAC || TARGET_SCORE7D"
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"min %0, %1, %2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "abssi2"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(abs:SI (match_operand:SI 1 "register_operand" "d")))]
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"TARGET_MAC || TARGET_SCORE7D"
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"abs %0, %1"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "clzsi2"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(clz:SI (match_operand:SI 1 "register_operand" "d")))]
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"TARGET_MAC || TARGET_SCORE7D"
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"clz %0, %1"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "sffs"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))]
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"TARGET_MAC || TARGET_SCORE7D"
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"bitrev %0, %1, r0\;clz %0, %0\;addi %0, 0x1"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_expand "ffssi2"
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[(set (match_operand:SI 0 "register_operand")
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(ffs:SI (match_operand:SI 1 "register_operand")))]
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"TARGET_MAC || TARGET_SCORE7D"
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{
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emit_insn (gen_sffs (operands[0], operands[1]));
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emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM),
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gen_rtx_COMPARE (CC_NZmode, operands[0],
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GEN_INT (33))));
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emit_insn (gen_movsicc_internal (operands[0],
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gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
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GEN_INT (0),
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operands[0]));
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DONE;
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})
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(define_peephole2
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[(set (match_operand:SI 0 "loreg_operand" "")
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(match_operand:SI 1 "register_operand" ""))
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(set (match_operand:SI 2 "hireg_operand" "")
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(match_operand:SI 3 "register_operand" ""))]
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"TARGET_MAC || TARGET_SCORE7D"
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[(parallel
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[(set (match_dup 0) (match_dup 1))
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(set (match_dup 2) (match_dup 3))])])
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(define_peephole2
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[(set (match_operand:SI 0 "hireg_operand" "")
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(match_operand:SI 1 "register_operand" ""))
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(set (match_operand:SI 2 "loreg_operand" "")
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(match_operand:SI 3 "register_operand" ""))]
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"TARGET_MAC || TARGET_SCORE7D"
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[(parallel
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[(set (match_dup 2) (match_dup 3))
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(set (match_dup 0) (match_dup 1))])])
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(define_insn "movtohilo"
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[(parallel
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[(set (match_operand:SI 0 "loreg_operand" "=l")
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(match_operand:SI 1 "register_operand" "d"))
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(set (match_operand:SI 2 "hireg_operand" "=h")
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(match_operand:SI 3 "register_operand" "d"))])]
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"TARGET_MAC || TARGET_SCORE7D"
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"mtcehl %3, %1"
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[(set_attr "type" "fce")
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(set_attr "mode" "SI")])
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(define_insn "mulsi3addsi"
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[(set (match_operand:SI 0 "register_operand" "=l,l,d")
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(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
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(match_operand:SI 3 "register_operand" "d,d,d"))
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(match_operand:SI 1 "register_operand" "0,d,l")))
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(clobber (reg:SI HI_REGNUM))]
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"TARGET_MAC || TARGET_SCORE7D"
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"@
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mad %2, %3
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mtcel%S1 %1\;mad %2, %3
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mad %2, %3\;mfcel%S0 %0"
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[(set_attr "mode" "SI")])
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(define_insn "mulsi3subsi"
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[(set (match_operand:SI 0 "register_operand" "=l,l,d")
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(minus:SI (match_operand:SI 1 "register_operand" "0,d,l")
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(mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
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(match_operand:SI 3 "register_operand" "d,d,d"))))
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(clobber (reg:SI HI_REGNUM))]
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"TARGET_MAC || TARGET_SCORE7D"
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"@
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msb %2, %3
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mtcel%S1 %1\;msb %2, %3
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msb %2, %3\;mfcel%S0 %0"
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[(set_attr "mode" "SI")])
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(define_insn "mulsidi3adddi"
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[(set (match_operand:DI 0 "register_operand" "=x")
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(plus:DI (mult:DI
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(sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
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(sign_extend:DI (match_operand:SI 3 "register_operand" "d")))
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(match_operand:DI 1 "register_operand" "0")))]
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"TARGET_MAC || TARGET_SCORE7D"
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"mad %2, %3"
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[(set_attr "mode" "DI")])
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(define_insn "umulsidi3adddi"
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[(set (match_operand:DI 0 "register_operand" "=x")
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(plus:DI (mult:DI
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(zero_extend:DI (match_operand:SI 2 "register_operand" "%d"))
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(zero_extend:DI (match_operand:SI 3 "register_operand" "d")))
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(match_operand:DI 1 "register_operand" "0")))]
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"TARGET_MAC || TARGET_SCORE7D"
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"madu %2, %3"
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[(set_attr "mode" "DI")])
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(define_insn "mulsidi3subdi"
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[(set (match_operand:DI 0 "register_operand" "=x")
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(minus:DI
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(match_operand:DI 1 "register_operand" "0")
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(mult:DI
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(sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
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(sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))]
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"TARGET_MAC || TARGET_SCORE7D"
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"msb %2, %3"
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[(set_attr "mode" "DI")])
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(define_insn "umulsidi3subdi"
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[(set (match_operand:DI 0 "register_operand" "=x")
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(minus:DI
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(match_operand:DI 1 "register_operand" "0")
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(mult:DI (zero_extend:DI
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(match_operand:SI 2 "register_operand" "%d"))
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(zero_extend:DI
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(match_operand:SI 3 "register_operand" "d")))))]
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"TARGET_MAC || TARGET_SCORE7D"
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"msbu %2, %3"
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[(set_attr "mode" "DI")])
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