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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [score/] [misc.md] - Blame information for rev 816

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1 38 julius 
;;  Machine description for Sunplus S+CORE
2 
;;  Copyright (C) 2005, 2007
3 
;;  Free Software Foundation, Inc.
4 
;;  Contributed by Sunnorth.
5 
 
6 
;; This file is part of GCC.
7 
 
8 
;; GCC is free software; you can redistribute it and/or modify
9 
;; it under the terms of the GNU General Public License as published by
10 
;; the Free Software Foundation; either version 3, or (at your option)
11 
;; any later version.
12 
 
13 
;; GCC is distributed in the hope that it will be useful,
14 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
;; GNU General Public License for more details.
17 
 
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .
21 
 
22 
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 
 
24 
(define_insn "pushsi"
25 
  [(set (match_operand:SI 0 "push_operand" "=<")
26 
        (match_operand:SI 1 "register_operand" "d"))]
27 
  ""
28 
  "push!   %1, [r0]"
29 
  [(set_attr "type" "store")
30 
   (set_attr "mode" "SI")])
31 
 
32 
(define_insn "popsi"
33 
  [(set (match_operand:SI 0 "register_operand" "=d")
34 
        (match_operand:SI 1 "pop_operand" ">"))]
35 
  ""
36 
  "pop!    %0, [r0]"
37 
  [(set_attr "type" "store")
38 
   (set_attr "mode" "SI")])
39 
 
40 
(define_peephole2
41 
  [(set (match_operand:SI 0 "g32reg_operand" "")
42 
        (match_operand:SI 1 "loreg_operand" ""))
43 
   (set (match_operand:SI 2 "g32reg_operand" "")
44 
        (match_operand:SI 3 "hireg_operand" ""))]
45 
  ""
46 
  [(parallel
47 
       [(set (match_dup 0) (match_dup 1))
48 
        (set (match_dup 2) (match_dup 3))])])
49 
 
50 
(define_peephole2
51 
  [(set (match_operand:SI 0 "g32reg_operand" "")
52 
        (match_operand:SI 1 "hireg_operand" ""))
53 
   (set (match_operand:SI 2 "g32reg_operand" "")
54 
        (match_operand:SI 3 "loreg_operand" ""))]
55 
  ""
56 
  [(parallel
57 
       [(set (match_dup 2) (match_dup 3))
58 
        (set (match_dup 0) (match_dup 1))])])
59 
 
60 
(define_insn "movhilo"
61 
  [(parallel
62 
       [(set (match_operand:SI 0 "register_operand" "=d")
63 
             (match_operand:SI 1 "loreg_operand" ""))
64 
        (set (match_operand:SI 2 "register_operand" "=d")
65 
             (match_operand:SI 3 "hireg_operand" ""))])]
66 
  ""
67 
  "mfcehl  %2, %0"
68 
  [(set_attr "type" "fce")
69 
   (set_attr "mode" "SI")])
70 
 
71 
(define_expand "movsicc"
72 
  [(set (match_operand:SI 0 "register_operand" "")
73 
        (if_then_else:SI (match_operator 1 "comparison_operator"
74 
                          [(reg:CC CC_REGNUM) (const_int 0)])
75 
                         (match_operand:SI 2 "register_operand" "")
76 
                         (match_operand:SI 3 "register_operand" "")))]
77 
  ""
78 
{
79 
  mdx_movsicc (operands);
80 
})
81 
 
82 
(define_insn "movsicc_internal"
83 
  [(set (match_operand:SI 0 "register_operand" "=d")
84 
        (if_then_else:SI (match_operator 1 "comparison_operator"
85 
                          [(reg:CC CC_REGNUM) (const_int 0)])
86 
                         (match_operand:SI 2 "arith_operand" "d")
87 
                         (match_operand:SI 3 "arith_operand" "0")))]
88 
  ""
89 
  "mv%C1   %0, %2"
90 
  [(set_attr "type" "cndmv")
91 
   (set_attr "mode" "SI")])
92 
 
93 
(define_insn "zero_extract_bittst"
94 
  [(set (reg:CC_NZ CC_REGNUM)
95 
        (compare:CC_NZ (unspec:SI
96 
                        [(match_operand:SI 0 "register_operand" "*e,d")
97 
                         (match_operand:SI 1 "const_uimm5" "")]
98 
                        BITTST)
99 
                       (const_int 0)))]
100 
  ""
101 
  "@
102 
   bittst!  %0, %c1
103 
   bittst.c %0, %c1"
104 
  [(set_attr "type" "arith")
105 
   (set_attr "up_c" "yes")
106 
   (set_attr "mode" "SI")])
107 
 
108 
(define_expand "extzv"
109 
  [(set (match_operand:SI 0 "register_operand" "")
110 
        (zero_extract (match_operand:SI 1 "memory_operand" "")
111 
                      (match_operand:SI 2 "immediate_operand" "")
112 
                      (match_operand:SI 3 "immediate_operand" "")))]
113 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
114 
{
115 
  if (mdx_unaligned_load (operands))
116 
    DONE;
117 
  else
118 
    FAIL;
119 
})
120 
 
121 
(define_expand "insv"
122 
  [(set (zero_extract (match_operand:SI 0 "memory_operand" "")
123 
                      (match_operand:SI 1 "immediate_operand" "")
124 
                      (match_operand:SI 2 "immediate_operand" ""))
125 
        (match_operand:SI 3 "register_operand" ""))]
126 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
127 
{
128 
  if (mdx_unaligned_store (operands))
129 
    DONE;
130 
  else
131 
    FAIL;
132 
})
133 
 
134 
(define_expand "extv"
135 
  [(set (match_operand:SI 0 "register_operand" "")
136 
        (sign_extract (match_operand:SI 1 "memory_operand" "")
137 
                      (match_operand:SI 2 "immediate_operand" "")
138 
                      (match_operand:SI 3 "immediate_operand" "")))]
139 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
140 
{
141 
  if (mdx_unaligned_load (operands))
142 
    DONE;
143 
  else
144 
    FAIL;
145 
})
146 
 
147 
(define_expand "movmemsi"
148 
  [(parallel [(set (match_operand:BLK 0 "general_operand")
149 
                   (match_operand:BLK 1 "general_operand"))
150 
              (use (match_operand:SI 2 ""))
151 
              (use (match_operand:SI 3 "const_int_operand"))])]
152 
  "!TARGET_SCORE5U && TARGET_ULS"
153 
{
154 
  if (mdx_block_move (operands))
155 
    DONE;
156 
  else
157 
    FAIL;
158 
})
159 
 
160 
(define_insn "move_lbu_a"
161 
  [(set (match_operand:SI 0 "register_operand" "=d")
162 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
163 
                 (match_operand:SI 2 "const_simm12" "")))
164 
   (set (match_operand:QI 3 "register_operand" "=d")
165 
        (mem:QI (match_dup 1)))]
166 
  ""
167 
  "lbu     %3, [%1]+, %2"
168 
  [(set_attr "type" "load")
169 
   (set_attr "mode" "QI")])
170 
 
171 
(define_insn "move_lhu_a"
172 
  [(set (match_operand:SI 0 "register_operand" "=d")
173 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
174 
                 (match_operand:SI 2 "const_simm12" "")))
175 
   (set (match_operand:HI 3 "register_operand" "=d")
176 
        (mem:HI (match_dup 1)))]
177 
  ""
178 
  "lhu     %3, [%1]+, %2"
179 
  [(set_attr "type" "load")
180 
   (set_attr "mode" "HI")])
181 
 
182 
(define_insn "move_lw_a"
183 
  [(set (match_operand:SI 0 "register_operand" "=d")
184 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
185 
                 (match_operand:SI 2 "const_simm12" "")))
186 
   (set (match_operand:SI 3 "register_operand" "=d")
187 
        (mem:SI (match_dup 1)))]
188 
  ""
189 
  "lw      %3, [%1]+, %2"
190 
  [(set_attr "type" "load")
191 
   (set_attr "mode" "SI")])
192 
 
193 
(define_insn "move_sb_a"
194 
  [(set (match_operand:SI 0 "register_operand" "=d")
195 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
196 
                 (match_operand:SI 2 "const_simm12" "")))
197 
   (set (mem:QI (match_dup 1))
198 
        (match_operand:QI 3 "register_operand" "d"))]
199 
  ""
200 
  "sb      %3, [%1]+, %2"
201 
  [(set_attr "type" "store")
202 
   (set_attr "mode" "QI")])
203 
 
204 
(define_insn "move_sh_a"
205 
  [(set (match_operand:SI 0 "register_operand" "=d")
206 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
207 
                 (match_operand:SI 2 "const_simm12" "")))
208 
   (set (mem:HI (match_dup 1))
209 
        (match_operand:HI 3 "register_operand" "d"))]
210 
  ""
211 
  "sh      %3, [%1]+, %2"
212 
  [(set_attr "type" "store")
213 
   (set_attr "mode" "HI")])
214 
 
215 
(define_insn "move_sw_a"
216 
  [(set (match_operand:SI 0 "register_operand" "=d")
217 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
218 
                 (match_operand:SI 2 "const_simm12" "")))
219 
   (set (mem:SI (match_dup 1))
220 
        (match_operand:SI 3 "register_operand" "d"))]
221 
  ""
222 
  "sw      %3, [%1]+, %2"
223 
  [(set_attr "type" "store")
224 
   (set_attr "mode" "SI")])
225 
 
226 
(define_insn "move_lbu_b"
227 
  [(set (match_operand:SI 0 "register_operand" "=d")
228 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
229 
                 (match_operand:SI 2 "const_simm12" "")))
230 
   (set (match_operand:QI 3 "register_operand" "=d")
231 
        (mem:QI (plus:SI (match_dup 1)
232 
                         (match_dup 2))))]
233 
  ""
234 
  "lbu     %3, [%1, %2]+"
235 
  [(set_attr "type" "load")
236 
   (set_attr "mode" "QI")])
237 
 
238 
(define_insn "move_lhu_b"
239 
  [(set (match_operand:SI 0 "register_operand" "=d")
240 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
241 
                 (match_operand:SI 2 "const_simm12" "")))
242 
   (set (match_operand:HI 3 "register_operand" "=d")
243 
        (mem:HI (plus:SI (match_dup 1)
244 
                         (match_dup 2))))]
245 
  ""
246 
  "lhu     %3, [%1, %2]+"
247 
  [(set_attr "type" "load")
248 
   (set_attr "mode" "HI")])
249 
 
250 
(define_insn "move_lw_b"
251 
  [(set (match_operand:SI 0 "register_operand" "=d")
252 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
253 
                 (match_operand:SI 2 "const_simm12" "")))
254 
   (set (match_operand:SI 3 "register_operand" "=d")
255 
        (mem:SI (plus:SI (match_dup 1)
256 
                         (match_dup 2))))]
257 
  ""
258 
  "lw      %3, [%1, %2]+"
259 
  [(set_attr "type" "load")
260 
   (set_attr "mode" "SI")])
261 
 
262 
(define_insn "move_sb_b"
263 
  [(set (match_operand:SI 0 "register_operand" "=d")
264 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
265 
                 (match_operand:SI 2 "const_simm12" "")))
266 
   (set (mem:QI (plus:SI (match_dup 1)
267 
                         (match_dup 2)))
268 
        (match_operand:QI 3 "register_operand" "d"))]
269 
  ""
270 
  "sb      %3, [%1, %2]+"
271 
  [(set_attr "type" "store")
272 
   (set_attr "mode" "QI")])
273 
 
274 
(define_insn "move_sh_b"
275 
  [(set (match_operand:SI 0 "register_operand" "=d")
276 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
277 
                 (match_operand:SI 2 "const_simm12" "")))
278 
   (set (mem:HI (plus:SI (match_dup 1)
279 
                         (match_dup 2)))
280 
        (match_operand:HI 3 "register_operand" "d"))]
281 
  ""
282 
  "sh      %3, [%1, %2]+"
283 
  [(set_attr "type" "store")
284 
   (set_attr "mode" "HI")])
285 
 
286 
(define_insn "move_sw_b"
287 
  [(set (match_operand:SI 0 "register_operand" "=d")
288 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
289 
                 (match_operand:SI 2 "const_simm12" "")))
290 
   (set (mem:SI (plus:SI (match_dup 1)
291 
                         (match_dup 2)))
292 
        (match_operand:SI 3 "register_operand" "d"))]
293 
  ""
294 
  "sw      %3, [%1, %2]+"
295 
  [(set_attr "type" "store")
296 
   (set_attr "mode" "SI")])
297 
 
298 
(define_insn "move_lcb"
299 
  [(set (match_operand:SI 0 "register_operand" "=d")
300 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
301 
                 (const_int 4)))
302 
   (set (reg:SI LC_REGNUM)
303 
        (unspec:SI [(mem:BLK (match_dup 1))] LCB))]
304 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
305 
  "lcb     [%1]+"
306 
  [(set_attr "type" "load")
307 
   (set_attr "mode" "SI")])
308 
 
309 
(define_insn "move_lcw"
310 
  [(set (match_operand:SI 0 "register_operand" "=d")
311 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
312 
                 (const_int 4)))
313 
   (set (match_operand:SI 2 "register_operand" "=d")
314 
        (unspec:SI [(mem:BLK (match_dup 1))
315 
                    (reg:SI LC_REGNUM)] LCW))
316 
   (set (reg:SI LC_REGNUM)
317 
        (unspec:SI [(mem:BLK (match_dup 1))] LCB))]
318 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
319 
  "lcw     %2, [%1]+"
320 
  [(set_attr "type" "load")
321 
   (set_attr "mode" "SI")])
322 
 
323 
(define_insn "move_lce"
324 
  [(set (match_operand:SI 0 "register_operand" "=d")
325 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
326 
                 (const_int 4)))
327 
   (set (match_operand:SI 2 "register_operand" "=d")
328 
        (unspec:SI [(mem:BLK (match_dup 1))
329 
                    (reg:SI LC_REGNUM)] LCE))]
330 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
331 
  "lce     %2, [%1]+"
332 
  [(set_attr "type" "load")
333 
   (set_attr "mode" "SI")])
334 
 
335 
(define_insn "move_scb"
336 
  [(set (match_operand:SI 0 "register_operand" "=d")
337 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
338 
                 (const_int 4)))
339 
   (set (mem:BLK (match_dup 1))
340 
        (unspec:BLK [(match_operand:SI 2 "register_operand" "d")] SCB))
341 
   (set (reg:SI SC_REGNUM)
342 
        (unspec:SI [(match_dup 2)] SCLC))]
343 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
344 
  "scb     %2, [%1]+"
345 
  [(set_attr "type" "store")
346 
   (set_attr "mode" "SI")])
347 
 
348 
(define_insn "move_scw"
349 
  [(set (match_operand:SI 0 "register_operand" "=d")
350 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
351 
                 (const_int 4)))
352 
   (set (mem:BLK (match_dup 1))
353 
        (unspec:BLK [(match_operand:SI 2 "register_operand" "d")
354 
                     (reg:SI SC_REGNUM)] SCW))
355 
   (set (reg:SI SC_REGNUM)
356 
        (unspec:SI [(match_dup 2)] SCLC))]
357 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
358 
  "scw     %2, [%1]+"
359 
  [(set_attr "type" "store")
360 
   (set_attr "mode" "SI")])
361 
 
362 
(define_insn "move_sce"
363 
  [(set (match_operand:SI 0 "register_operand" "=d")
364 
        (plus:SI (match_operand:SI 1 "register_operand" "0")
365 
                 (const_int 4)))
366 
   (set (mem:BLK (match_dup 1))
367 
        (unspec:BLK [(reg:SI SC_REGNUM)] SCE))]
368 
  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
369 
  "sce     [%1]+"
370 
  [(set_attr "type" "store")
371 
   (set_attr "mode" "SI")])
372 
 
373 
(define_insn "andsi3_extzh"
374 
  [(set (match_operand:SI 0 "register_operand" "=d")
375 
        (and:SI (match_operand:SI 1 "register_operand" "d")
376 
                (const_int 65535)))]
377 
  ""
378 
  "extzh   %0, %1"
379 
  [(set_attr "type" "arith")
380 
   (set_attr "mode" "SI")])
381 
 

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