OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [sh/] [sh.opt] - Blame information for rev 816

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
; Options for the SH port of the compiler.
2
 
3
; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
4
;
5
; This file is part of GCC.
6
;
7
; GCC is free software; you can redistribute it and/or modify it under
8
; the terms of the GNU General Public License as published by the Free
9
; Software Foundation; either version 3, or (at your option) any later
10
; version.
11
;
12
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15
; for more details.
16
;
17
; You should have received a copy of the GNU General Public License
18
; along with GCC; see the file COPYING3.  If not see
19
; .
20
 
21
;; Used for various architecture options.
22
Mask(SH_E)
23
 
24
;; Set if the default precision of th FPU is single.
25
Mask(FPU_SINGLE)
26
 
27
;; Set if we should generate code using type 2A insns.
28
Mask(HARD_SH2A)
29
 
30
;; Set if we should generate code using type 2A DF insns.
31
Mask(HARD_SH2A_DOUBLE)
32
 
33
;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
34
Mask(HARD_SH4)
35
 
36
;; Set if we should generate code for a SH5 CPU (either ISA).
37
Mask(SH5)
38
 
39
;; Set if we should save all target registers.
40
Mask(SAVE_ALL_TARGET_REGS)
41
 
42
m1
43
Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
44
Generate SH1 code
45
 
46
m2
47
Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
48
Generate SH2 code
49
 
50
m2a
51
Target RejectNegative Condition(SUPPORT_SH2A)
52
Generate SH2a code
53
 
54
m2a-nofpu
55
Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
56
Generate SH2a FPU-less code
57
 
58
m2a-single
59
Target RejectNegative Condition (SUPPORT_SH2A_SINGLE)
60
Generate default single-precision SH2a code
61
 
62
m2a-single-only
63
Target RejectNegative Condition (SUPPORT_SH2A_SINGLE_ONLY)
64
Generate only single-precision SH2a code
65
 
66
m2e
67
Target RejectNegative Condition(SUPPORT_SH2E)
68
Generate SH2e code
69
 
70
m3
71
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
72
Generate SH3 code
73
 
74
m3e
75
Target RejectNegative Condition(SUPPORT_SH3E)
76
Generate SH3e code
77
 
78
m4
79
Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
80
Generate SH4 code
81
 
82
m4-100
83
Target RejectNegative Condition(SUPPORT_SH4)
84
Generate SH4-100 code
85
 
86
m4-200
87
Target RejectNegative Condition(SUPPORT_SH4)
88
Generate SH4-200 code
89
 
90
m4-nofpu
91
Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
92
Generate SH4 FPU-less code
93
 
94
m4-400
95
Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
96
Generate code for SH4 400 series (MMU/FPU-less)
97
;; passes -isa=sh4-nommu-nofpu to the assembler.
98
 
99
m4-500
100
Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
101
Generate code for SH4 500 series (FPU-less).
102
;; passes -isa=sh4-nofpu to the assembler.
103
 
104
m4-single
105
Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
106
Generate default single-precision SH4 code
107
 
108
m4-100-single
109
Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
110
Generate default single-precision SH4-100 code
111
 
112
m4-200-single
113
Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
114
Generate default single-precision SH4-200 code
115
 
116
m4-single-only
117
Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
118
Generate only single-precision SH4 code
119
 
120
m4-100-single-only
121
Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
122
Generate only single-precision SH4-100 code
123
 
124
m4-200-single-only
125
Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
126
Generate only single-precision SH4-200 code
127
 
128
m4a
129
Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
130
Generate SH4a code
131
 
132
m4a-nofpu
133
Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
134
Generate SH4a FPU-less code
135
 
136
m4a-single
137
Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
138
Generate default single-precision SH4a code
139
 
140
m4a-single-only
141
Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
142
Generate only single-precision SH4a code
143
 
144
m4al
145
Target RejectNegative Condition(SUPPORT_SH4AL)
146
Generate SH4al-dsp code
147
 
148
m5-32media
149
Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
150
Generate 32-bit SHmedia code
151
 
152
m5-32media-nofpu
153
Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
154
Generate 32-bit FPU-less SHmedia code
155
 
156
m5-64media
157
Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
158
Generate 64-bit SHmedia code
159
 
160
m5-64media-nofpu
161
Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
162
Generate 64-bit FPU-less SHmedia code
163
 
164
m5-compact
165
Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
166
Generate SHcompact code
167
 
168
m5-compact-nofpu
169
Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
170
Generate FPU-less SHcompact code
171
 
172
madjust-unroll
173
Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
174
Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
175
 
176
mb
177
Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
178
Generate code in big endian mode
179
 
180
mbigtable
181
Target Report RejectNegative Mask(BIGTABLE)
182
Generate 32-bit offsets in switch tables
183
 
184
mcut2-workaround
185
Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
186
Enable SH5 cut2 workaround
187
 
188
mdalign
189
Target Report RejectNegative Mask(ALIGN_DOUBLE)
190
Align doubles at 64-bit boundaries
191
 
192
mdiv=
193
Target RejectNegative Joined Var(sh_div_str) Init("")
194
Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp call-div1 call-fp call-table
195
 
196
mdivsi3_libfunc=
197
Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
198
Specify name for 32 bit signed division function
199
 
200
mfmovd
201
Target RejectNegative Mask(FMOVD) Undocumented
202
 
203
mgettrcost=
204
Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
205
Cost to assume for gettr insn
206
 
207
mhitachi
208
Target Report RejectNegative Mask(HITACHI)
209
Follow Renesas (formerly Hitachi) / SuperH calling conventions
210
 
211
mieee
212
Target Report Mask(IEEE)
213
Increase the IEEE compliance for floating-point code
214
 
215
mindexed-addressing
216
Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
217
Enable the use of the indexed addressing mode for SHmedia32/SHcompact
218
 
219
minvalid-symbols
220
Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
221
Assume symbols might be invalid
222
 
223
misize
224
Target Report RejectNegative Mask(DUMPISIZE)
225
Annotate assembler instructions with estimated addresses
226
 
227
ml
228
Target Report RejectNegative Mask(LITTLE_ENDIAN)
229
Generate code in little endian mode
230
 
231
mnomacsave
232
Target Report RejectNegative Mask(NOMACSAVE)
233
Mark MAC register as call-clobbered
234
 
235
;; ??? This option is not useful, but is retained in case there are people
236
;; who are still relying on it.  It may be deleted in the future.
237
mpadstruct
238
Target Report RejectNegative Mask(PADSTRUCT)
239
Make structs a multiple of 4 bytes (warning: ABI altered)
240
 
241
mprefergot
242
Target Report RejectNegative Mask(PREFERGOT)
243
Emit function-calls using global offset table when generating PIC
244
 
245
mpt-fixed
246
Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
247
Assume pt* instructions won't trap
248
 
249
mrelax
250
Target Report RejectNegative Mask(RELAX)
251
Shorten address references during linking
252
 
253
mrenesas
254
Target Mask(HITACHI) MaskExists
255
Follow Renesas (formerly Hitachi) / SuperH calling conventions
256
 
257
mspace
258
Target Report RejectNegative Mask(SMALLCODE)
259
Deprecated. Use -Os instead
260
 
261
multcost=
262
Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
263
Cost to assume for a multiply insn
264
 
265
musermode
266
Target Report RejectNegative Mask(USERMODE)
267
Generate library function call to invalidate instruction cache entries after fixing trampoline
268
 
269
;; We might want to enable this by default for TARGET_HARD_SH4, because
270
;; zero-offset branches have zero latency.  Needs some benchmarking.
271
mpretend-cmove
272
Target Var(TARGET_PRETEND_CMOVE)
273
Pretend a branch-around-a-move is a conditional move.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.