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julius |
;; DFA scheduling description for Renesas / SuperH SH.
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;; Copyright (C) 2004, 2007 Free Software Foundation, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; Load and store instructions save a cycle if they are aligned on a
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;; four byte boundary. Using a function unit for stores encourages
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;; gcc to separate load and store instructions by one instruction,
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;; which makes it more likely that the linker will be able to word
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;; align them when relaxing.
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;; SH-1 scheduling. This is just a conversion of the old scheduling
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;; model, using define_function_unit.
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(define_automaton "sh1")
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(define_cpu_unit "sh1memory,sh1int,sh1mpy,sh1fp" "sh1")
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;; Loads have a latency of two.
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;; However, call insns can have a delay slot, so that we want one more
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;; insn to be scheduled between the load of the function address and the call.
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;; This is equivalent to a latency of three.
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;; ADJUST_COST can only properly handle reductions of the cost, so we
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;; use a latency of three here.
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;; We only do this for SImode loads of general registers, to make the work
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;; for ADJUST_COST easier.
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(define_insn_reservation "sh1_load_si" 3
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "load_si,pcload_si"))
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"sh1memory*2")
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(define_insn_reservation "sh1_load_store" 2
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "load,pcload,pload,store,pstore"))
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"sh1memory*2")
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(define_insn_reservation "sh1_arith3" 3
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "arith3,arith3b"))
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"sh1int*3")
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(define_insn_reservation "sh1_dyn_shift" 2
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "dyn_shift"))
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"sh1int*2")
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(define_insn_reservation "sh1_int" 1
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "!arith3,arith3b,dyn_shift"))
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"sh1int")
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;; ??? These are approximations.
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(define_insn_reservation "sh1_smpy" 2
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "smpy"))
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"sh1mpy*2")
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(define_insn_reservation "sh1_dmpy" 3
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "dmpy"))
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"sh1mpy*3")
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(define_insn_reservation "sh1_fp" 2
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "fp,fmove"))
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"sh1fp")
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(define_insn_reservation "sh1_fdiv" 13
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(and (eq_attr "pipe_model" "sh1")
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(eq_attr "type" "fdiv"))
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"sh1fp*12")
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