OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [config/] [sparc/] [sparc-protos.h] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/* Prototypes of target machine for SPARC.
2
   Copyright (C) 1999, 2000, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
3
   Contributed by Michael Tiemann (tiemann@cygnus.com).
4
   64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
5
   at Cygnus Support.
6
 
7
This file is part of GCC.
8
 
9
GCC is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 3, or (at your option)
12
any later version.
13
 
14
GCC is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with GCC; see the file COPYING3.  If not see
21
<http://www.gnu.org/licenses/>.  */
22
 
23
#ifndef __SPARC_PROTOS_H__
24
#define __SPARC_PROTOS_H__
25
 
26
#ifdef TREE_CODE
27
extern struct rtx_def *function_value (tree, enum machine_mode, int);
28
extern void function_arg_advance (CUMULATIVE_ARGS *,
29
                                  enum machine_mode, tree, int);
30
extern struct rtx_def *function_arg (const CUMULATIVE_ARGS *,
31
                                     enum machine_mode, tree, int, int);
32
#ifdef RTX_CODE
33
extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
34
extern void sparc_va_start (tree, rtx);
35
#endif
36
extern unsigned long sparc_type_code (tree);
37
#ifdef ARGS_SIZE_RTX
38
/* expr.h defines ARGS_SIZE_RTX and `enum direction' */
39
extern enum direction function_arg_padding (enum machine_mode, tree);
40
#endif /* ARGS_SIZE_RTX */
41
#endif /* TREE_CODE */
42
 
43
extern void order_regs_for_local_alloc (void);
44
extern HOST_WIDE_INT sparc_compute_frame_size (HOST_WIDE_INT, int);
45
extern void sparc_expand_prologue (void);
46
extern void sparc_expand_epilogue (void);
47
extern bool sparc_can_use_return_insn_p (void);
48
extern int check_pic (int);
49
extern int short_branch (int, int);
50
extern void sparc_profile_hook (int);
51
extern void sparc_override_options (void);
52
extern void sparc_output_scratch_registers (FILE *);
53
 
54
#ifdef RTX_CODE
55
extern enum machine_mode select_cc_mode (enum rtx_code, rtx, rtx);
56
/* Define the function that build the compare insn for scc and bcc.  */
57
extern rtx gen_compare_reg (enum rtx_code code);
58
extern void sparc_emit_float_lib_cmp (rtx, rtx, enum rtx_code);
59
extern void sparc_emit_floatunsdi (rtx [2], enum machine_mode);
60
extern void sparc_emit_fixunsdi (rtx [2], enum machine_mode);
61
extern void emit_tfmode_binop (enum rtx_code, rtx *);
62
extern void emit_tfmode_unop (enum rtx_code, rtx *);
63
extern void emit_tfmode_cvt (enum rtx_code, rtx *);
64
/* This function handles all v9 scc insns */
65
extern int gen_v9_scc (enum rtx_code, rtx *);
66
extern void sparc_initialize_trampoline (rtx, rtx, rtx);
67
extern void sparc64_initialize_trampoline (rtx, rtx, rtx);
68
extern bool legitimate_constant_p (rtx);
69
extern bool constant_address_p (rtx);
70
extern bool legitimate_pic_operand_p (rtx);
71
extern int legitimate_address_p (enum machine_mode, rtx, int);
72
extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
73
extern rtx legitimize_tls_address (rtx);
74
extern rtx legitimize_address (rtx, rtx, enum machine_mode);
75
extern void sparc_defer_case_vector (rtx, rtx, int);
76
extern bool sparc_expand_move (enum machine_mode, rtx *);
77
extern void sparc_emit_set_const32 (rtx, rtx);
78
extern void sparc_emit_set_const64 (rtx, rtx);
79
extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx);
80
extern int sparc_splitdi_legitimate (rtx, rtx);
81
extern int sparc_absnegfloat_split_legitimate (rtx, rtx);
82
extern const char *output_ubranch (rtx, int, rtx);
83
extern const char *output_cbranch (rtx, rtx, int, int, int, rtx);
84
extern const char *output_return (rtx);
85
extern const char *output_sibcall (rtx, rtx);
86
extern const char *output_v8plus_shift (rtx *, rtx, const char *);
87
extern const char *output_v9branch (rtx, rtx, int, int, int, int, rtx);
88
extern void emit_v9_brxx_insn (enum rtx_code, rtx, rtx);
89
extern void print_operand (FILE *, rtx, int);
90
extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);
91
extern int arith_double_4096_operand (rtx, enum machine_mode);
92
extern int arith_4096_operand (rtx, enum machine_mode);
93
extern int zero_operand (rtx, enum machine_mode);
94
extern int fp_zero_operand (rtx, enum machine_mode);
95
extern int reg_or_0_operand (rtx, enum machine_mode);
96
extern int empty_delay_slot (rtx);
97
extern int eligible_for_return_delay (rtx);
98
extern int eligible_for_sibcall_delay (rtx);
99
extern int tls_call_delay (rtx);
100
extern int emit_move_sequence (rtx, enum machine_mode);
101
extern int fp_sethi_p (rtx);
102
extern int fp_mov_p (rtx);
103
extern int fp_high_losum_p (rtx);
104
extern bool sparc_tls_referenced_p (rtx);
105
extern int mem_min_alignment (rtx, int);
106
extern int pic_address_needs_scratch (rtx);
107
extern int reg_unused_after (rtx, rtx);
108
extern int register_ok_for_ldd (rtx);
109
extern int registers_ok_for_ldd_peep (rtx, rtx);
110
extern int v9_regcmp_p (enum rtx_code);
111
/* Function used for V8+ code generation.  Returns 1 if the high
112
   32 bits of REG are 0 before INSN.  */
113
extern int sparc_check_64 (rtx, rtx);
114
extern rtx gen_df_reg (rtx, int);
115
extern int sparc_extra_constraint_check (rtx, int, int);
116
extern void sparc_expand_compare_and_swap_12 (rtx, rtx, rtx, rtx);
117
#endif /* RTX_CODE */
118
 
119
#endif /* __SPARC_PROTOS_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.