OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.c-torture/] [execute/] [pr15296.c] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* PR optimization/15296.  The delayed-branch scheduler caused code that
2
   SEGV:d for CRIS; a register was set to -1 in a delay-slot for the
3
   fall-through code, while that register held a pointer used in code at
4
   the branch target.  */
5
 
6
typedef int __attribute__ ((mode (__pointer__))) intptr_t;
7
typedef intptr_t W;
8
union u0
9
{
10
  union u0 *r;
11
  W i;
12
};
13
struct s1
14
{
15
  union u0 **m0;
16
  union u0 m1[4];
17
};
18
 
19
void f (void *, struct s1 *, const union u0 *, W, W, W)
20
     __attribute__ ((__noinline__));
21
void g (void *, char *) __attribute__ ((__noinline__));
22
 
23
void
24
f (void *a, struct s1 *b, const union u0 *h, W v0, W v1, W v4)
25
{
26
  union u0 *e = 0;
27
  union u0 *k = 0;
28
  union u0 **v5 = b->m0;
29
  union u0 *c = b->m1;
30
  union u0 **d = &v5[0];
31
l0:;
32
  if (v0 < v1)
33
    goto l0;
34
  if (v0 == 0)
35
    goto l3;
36
  v0 = v4;
37
  if (v0 != 0)
38
    goto l3;
39
  c[0].r = *d;
40
  v1 = -1;
41
  e = c[0].r;
42
  if (e != 0)
43
    g (a, "");
44
  k = e + 3;
45
  k->i = v1;
46
  goto l4;
47
l3:;
48
  c[0].i = v0;
49
  e = c[1].r;
50
  if (e != 0)
51
    g (a, "");
52
  e = c[0].r;
53
  if (e == 0)
54
    g (a, "");
55
  k = e + 2;
56
  k->r = c[1].r;
57
l4:;
58
}
59
 
60
void g (void *a, char *b) { abort (); }
61
 
62
int
63
main ()
64
{
65
  union u0 uv[] = {{ .i = 111 }, { .i = 222 }, { .i = 333 }, { .i = 444 }};
66
  struct s1 s = { 0, {{ .i = 555 }, { .i = 0 }, { .i = 999 }, { .i = 777 }}};
67
  f (0, &s, 0, 20000, 10000, (W) uv);
68
  if (s.m1[0].i != (W) uv || s.m1[1].i != 0 || s.m1[2].i != 999
69
      || s.m1[3].i != 777 || uv[0].i != 111 || uv[1].i != 222
70
      || uv[2].i != 0 || uv[3].i != 444)
71
    abort ();
72
  exit (0);
73
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.