OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [i386/] [20020523-1.c] - Blame information for rev 816

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* PR target/6753
2
   This testcase was miscompiled because sse_mov?fcc_const0*
3
   patterns were missing earlyclobber.  */
4
/* { dg-do run { target i?86-*-* x86_64-*-* } } */
5
/* { dg-skip-if "" { ilp32 } { "-fpic" "-fPIC" } { "" } } */
6
/* { dg-skip-if "PIC default" { *-*-darwin* } { "*" } { "" } } */
7
/* { dg-require-effective-target ilp32 } */
8
/* { dg-options "-march=pentium3 -msse -ffast-math -O2" } */
9
 
10
extern void abort (void);
11
extern void exit (int);
12
 
13
float one = 1.f;
14
 
15
void bar (float f)
16
{
17
  if (__builtin_memcmp (&one, &f, sizeof (float)))
18
    abort ();
19
}
20
 
21
float foo (void)
22
{
23
  return 1.f;
24
}
25
 
26
typedef struct
27
{
28
  float t;
29
} T;
30
 
31
void bail_if_no_sse (void)
32
{
33
  int fl1, fl2;
34
 
35
  /* See if we can use cpuid.  */
36
  __asm__ ("pushfl; pushfl; popl %0; movl %0,%1; xorl %2,%0;"
37
           "pushl %0; popfl; pushfl; popl %0; popfl"
38
           : "=&r" (fl1), "=&r" (fl2)
39
           : "i" (0x00200000));
40
  if (((fl1 ^ fl2) & 0x00200000) == 0)
41
    exit (0);
42
 
43
  /* See if cpuid gives capabilities.  */
44
  __asm__ ("cpuid" : "=a" (fl1) : "0" (0) : "ebx", "ecx", "edx", "cc");
45
  if (fl1 == 0)
46
    exit (0);
47
 
48
  /* See if capabilities include SSE (25th bit; 26 for SSE2).  */
49
  __asm__ ("cpuid" : "=a" (fl1), "=d" (fl2) : "0" (1) : "ebx", "ecx", "cc");
50
  if ((fl2 & (1 << 25)) == 0)
51
    exit (0);
52
}
53
 
54
int main (void)
55
{
56
  int i;
57
  T x[1];
58
 
59
  bail_if_no_sse ();
60
  for (i = 0; i < 1; i++)
61
    {
62
      x[i].t = foo ();
63
      x[i].t = 0.f > x[i].t ? 0.f : x[i].t;
64
      bar (x[i].t);
65
    }
66
 
67
  exit (0);
68
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.