OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [i386/] [20020729-1.c] - Blame information for rev 154

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
2
/* { dg-require-effective-target ilp32 } */
3
/* { dg-options "-O2 -march=k6" } */
4
 
5
static inline void *
6
baz (void *s, unsigned long c, unsigned int count)
7
{
8
  int d0, d1;
9
  __asm__ __volatile__ (""
10
                        : "=&c" (d0), "=&D" (d1)
11
                        :"a" (c), "q" (count), "0" (count / 4), "1" ((long) s)
12
                        :"memory");
13
  return s;
14
}
15
 
16
struct A
17
{
18
  unsigned long *a;
19
};
20
 
21
inline static void *
22
bar (struct A *x, int y)
23
{
24
  char *ptr;
25
 
26
  ptr = (void *) x->a[y >> 12];
27
  ptr += y % (1UL << 12);
28
  return (void *) ptr;
29
}
30
 
31
int
32
foo (struct A *x, unsigned int *y, int z, int u)
33
{
34
  int a, b, c, d, e;
35
 
36
  z += *y;
37
  c = z + u;
38
  a = (z >> 12) + 1;
39
  do
40
    {
41
      b = (a << 12);
42
      d = b - z;
43
      e = c - z;
44
      if (e < d)
45
        d = e;
46
      baz (bar (x, z), 0, d);
47
      z = b;
48
      a++;
49
    }
50
  while (z < c);
51
  return 0;
52
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.