OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pic-1.c] - Blame information for rev 816

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* PR target/8340 */
2
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
3
/* { dg-require-effective-target ilp32 } */
4
/* { dg-options "-fPIC" } */
5
 
6
int foo ()
7
{
8
  static int a;
9
 
10
  __asm__ __volatile__ (  /* { dg-error "PIC register" } */
11
    "xorl %%ebx, %%ebx\n"
12
    "movl %%ebx, %0\n"
13
    : "=m" (a)
14
    :
15
    : "%ebx"
16
  );
17
 
18
  return a;
19
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.