OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [mips/] [branch-1.c] - Blame information for rev 844

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* We should implement these "if" statements using an "andi" instruction
2
   followed by a branch on zero.  */
3
/* { dg-mips-options "-O2 -mno-mips16" } */
4
void bar (void);
5
void f1 (int x) { if (x & 4) bar (); }
6
void f2 (int x) { if ((x >> 2) & 1) bar (); }
7
void f3 (unsigned int x) { if (x & 0x10) bar (); }
8
void f4 (unsigned int x) { if ((x >> 4) & 1) bar (); }
9
/* { dg-final { scan-assembler "\tandi\t.*\tandi\t.*\tandi\t.*\tandi\t" } } */
10
/* { dg-final { scan-assembler-not "\tsrl\t" } } */
11
/* { dg-final { scan-assembler-not "\tsra\t" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.