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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-consts.c] - Blame information for rev 867

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Line No. Rev Author Line
1 149 jeremybenn
/* { dg-do run { target powerpc*-*-* } } */
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/* { dg-require-effective-target powerpc_altivec_ok } */
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/* { dg-options "-maltivec -mabi=altivec -O2" } */
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/* Check that "easy" AltiVec constants are correctly synthesized.  */
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#include "altivec_check.h"
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extern void abort (void);
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typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
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typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
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typedef __attribute__ ((vector_size (16))) unsigned int v4si;
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char w[16] __attribute__((aligned(16)));
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/* Emulate the vspltis? instructions on a 16-byte array of chars.  */
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void vspltisb (char *v, int val)
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{
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  int i;
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  for (i = 0; i < 16; i++)
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    v[i] = val;
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}
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void vspltish (char *v, int val)
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{
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  int i;
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  for (i = 0; i < 16; i += 2)
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    v[i] = val >> 7, v[i + 1] = val;
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}
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void vspltisw (char *v, int val)
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{
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  int i;
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  for (i = 0; i < 16; i += 4)
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    v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val;
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}
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/* Use three different check functions for each mode-instruction pair.
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   The callers have no typecasting and no addressable vectors, to make
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   the test more robust.  */
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void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
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{
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  if (memcmp (&v1, v2, 16))
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    abort ();
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}
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void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2)
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{
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  if (memcmp (&v1, v2, 16))
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    abort ();
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}
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void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2)
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{
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  if (memcmp (&v1, v2, 16))
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    abort ();
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}
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/* V16QI tests.  */
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void v16qi_vspltisb ()
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{
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  v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 };
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  vspltisb (w, 15);
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  check_v16qi (v, w);
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}
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void v16qi_vspltisb_neg ()
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{
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  v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 };
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  vspltisb (w, -5);
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  check_v16qi (v, w);
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}
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void v16qi_vspltisb_addself ()
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{
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  v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 };
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  vspltisb (w, 30);
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  check_v16qi (v, w);
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}
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void v16qi_vspltisb_neg_addself ()
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{
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  v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 };
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  vspltisb (w, -24);
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  check_v16qi (v, w);
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}
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void v16qi_vspltish ()
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{
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  v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 };
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  vspltish (w, 15);
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  check_v16qi (v, w);
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}
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void v16qi_vspltish_addself ()
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{
104
  v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 };
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  vspltish (w, 30);
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  check_v16qi (v, w);
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}
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void v16qi_vspltish_neg ()
110
{
111
  v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 };
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  vspltish (w, -5);
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  check_v16qi (v, w);
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}
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116
void v16qi_vspltisw ()
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{
118
  v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 };
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  vspltisw (w, 15);
120
  check_v16qi (v, w);
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}
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123
void v16qi_vspltisw_addself ()
124
{
125
  v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 };
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  vspltisw (w, 30);
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  check_v16qi (v, w);
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}
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130
void v16qi_vspltisw_neg ()
131
{
132
  v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 };
133
  vspltisw (w, -5);
134
  check_v16qi (v, w);
135
}
136
 
137
 
138
/* V8HI tests. */
139
 
140
void v8hi_vspltisb ()
141
{
142
  v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F };
143
  vspltisb (w, 15);
144
  check_v8hi (v, w);
145
}
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147
void v8hi_vspltisb_addself ()
148
{
149
  v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E };
150
  vspltisb (w, 30);
151
  check_v8hi (v, w);
152
}
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154
void v8hi_vspltisb_neg ()
155
{
156
  v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB };
157
  vspltisb (w, -5);
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  check_v8hi (v, w);
159
}
160
 
161
void v8hi_vspltish ()
162
{
163
  v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 };
164
  vspltish (w, 15);
165
  check_v8hi (v, w);
166
}
167
 
168
void v8hi_vspltish_neg ()
169
{
170
  v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 };
171
  vspltish (w, -5);
172
  check_v8hi (v, w);
173
}
174
 
175
void v8hi_vspltish_addself ()
176
{
177
  v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 };
178
  vspltish (w, 30);
179
  check_v8hi (v, w);
180
}
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182
void v8hi_vspltish_neg_addself ()
183
{
184
  v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 };
185
  vspltish (w, -24);
186
  check_v8hi (v, w);
187
}
188
 
189
void v8hi_vspltisw ()
190
{
191
  v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 };
192
  vspltisw (w, 15);
193
  check_v8hi (v, w);
194
}
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196
void v8hi_vspltisw_addself ()
197
{
198
  v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 };
199
  vspltisw (w, 30);
200
  check_v8hi (v, w);
201
}
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203
void v8hi_vspltisw_neg ()
204
{
205
  v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 };
206
  vspltisw (w, -5);
207
  check_v8hi (v, w);
208
}
209
 
210
/* V4SI tests. */
211
 
212
void v4si_vspltisb ()
213
{
214
  v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F };
215
  vspltisb (w, 15);
216
  check_v4si (v, w);
217
}
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219
void v4si_vspltisb_addself ()
220
{
221
  v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E };
222
  vspltisb (w, 30);
223
  check_v4si (v, w);
224
}
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226
void v4si_vspltisb_neg ()
227
{
228
  v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB };
229
  vspltisb (w, -5);
230
  check_v4si (v, w);
231
}
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233
void v4si_vspltish ()
234
{
235
  v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F };
236
  vspltish (w, 15);
237
  check_v4si (v, w);
238
}
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240
void v4si_vspltish_addself ()
241
{
242
  v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E };
243
  vspltish (w, 30);
244
  check_v4si (v, w);
245
}
246
 
247
void v4si_vspltish_neg ()
248
{
249
  v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB };
250
  vspltish (w, -5);
251
  check_v4si (v, w);
252
}
253
 
254
void v4si_vspltisw ()
255
{
256
  v4si v = { 15, 15, 15, 15 };
257
  vspltisw (w, 15);
258
  check_v4si (v, w);
259
}
260
 
261
void v4si_vspltisw_neg ()
262
{
263
  v4si v = { -5, -5, -5, -5 };
264
  vspltisw (w, -5);
265
  check_v4si (v, w);
266
}
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268
void v4si_vspltisw_addself ()
269
{
270
  v4si v = { 30, 30, 30, 30 };
271
  vspltisw (w, 30);
272
  check_v4si (v, w);
273
}
274
 
275
void v4si_vspltisw_neg_addself ()
276
{
277
  v4si v = { -24, -24, -24, -24 };
278
  vspltisw (w, -24);
279
  check_v4si (v, w);
280
}
281
 
282
 
283
 
284
int main ()
285
{
286
  altivec_check ();   /* Exit if hardware doesn't support AltiVec.  */
287
 
288
  v16qi_vspltisb ();
289
  v16qi_vspltisb_neg ();
290
  v16qi_vspltisb_addself ();
291
  v16qi_vspltisb_neg_addself ();
292
  v16qi_vspltish ();
293
  v16qi_vspltish_addself ();
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  v16qi_vspltish_neg ();
295
  v16qi_vspltisw ();
296
  v16qi_vspltisw_addself ();
297
  v16qi_vspltisw_neg ();
298
 
299
  v8hi_vspltisb ();
300
  v8hi_vspltisb_addself ();
301
  v8hi_vspltisb_neg ();
302
  v8hi_vspltish ();
303
  v8hi_vspltish_neg ();
304
  v8hi_vspltish_addself ();
305
  v8hi_vspltish_neg_addself ();
306
  v8hi_vspltisw ();
307
  v8hi_vspltisw_addself ();
308
  v8hi_vspltisw_neg ();
309
 
310
  v4si_vspltisb ();
311
  v4si_vspltisb_addself ();
312
  v4si_vspltisb_neg ();
313
  v4si_vspltish ();
314
  v4si_vspltish_addself ();
315
  v4si_vspltish_neg ();
316
  v4si_vspltisw ();
317
  v4si_vspltisw_neg ();
318
  v4si_vspltisw_addself ();
319
  v4si_vspltisw_neg_addself ();
320
  return 0;
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}

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