OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-splat.c] - Blame information for rev 823

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn 
/* { dg-do compile { target powerpc*-*-* } } */
2 
/* { dg-require-effective-target powerpc_altivec_ok } */
3 
/* { dg-options "-maltivec -mabi=altivec -O2" } */
4 
 
5 
/* Testcase by Richard Guenther and Steven Bosscher.
6 
   Check that "easy" AltiVec constants are correctly synthesized
7 
   if they need to be reloaded.  */
8 
 
9 
typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
10 
typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
11 
typedef __attribute__ ((vector_size (16))) unsigned int v4si;
12 
 
13 
#define REGLIST                                                         \
14 
  "77",  "78",  "79",  "80",  "81",  "82",  "83",  "84",  "85",  "86",  \
15 
  "87",  "88",  "89",  "90",  "91",  "92",  "93",  "94",  "95",  "96",  \
16 
  "97",  "98",  "99", "100", "101", "102", "103", "104", "105", "106",  \
17 
 "107", "108"
18 
 
19 
 
20 
#define TEST(a, result, b)                              \
21 
  void a##_##b (int h)                                  \
22 
  {                                                     \
23 
    volatile a tmp;                                     \
24 
    while (h-- > 0)                                      \
25 
      {                                                 \
26 
        asm ("" : : : REGLIST);                         \
27 
        tmp = (a) (result) __builtin_altivec_##b (5);   \
28 
      }                                                 \
29 
  }                                                     \
30 
                                                        \
31 
  void a##_##b##_neg (int h)                            \
32 
  {                                                     \
33 
    volatile a tmp;                                     \
34 
    while (h-- > 0)                                      \
35 
      {                                                 \
36 
        asm ("" : : : REGLIST);                         \
37 
        tmp = (a) (result) __builtin_altivec_##b (-5);  \
38 
      }                                                 \
39 
  }
40 
 
41 
TEST(v16qi, v16qi, vspltisb)
42 
TEST(v16qi, v8hi, vspltish)
43 
TEST(v16qi, v4si, vspltisw)
44 
TEST(v8hi, v16qi, vspltisb)
45 
TEST(v8hi, v8hi, vspltish)
46 
TEST(v8hi, v4si, vspltisw)
47 
TEST(v4si, v16qi, vspltisb)
48 
TEST(v4si, v8hi, vspltish)
49 
TEST(v4si, v4si, vspltisw)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.