OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [ppc-bitfield1.c] - Blame information for rev 867

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
2
/* { dg-options "-O2" } */
3
 
4
/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,1,31"  } } */
5
/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,0xffffffff" } } */
6
 
7
/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
8
 
9
/* PR 17104 many sign extends added.  */
10
 
11
struct {
12
 int f1 : 1;
13
 int f2 : 1;
14
 int f3 : 1;
15
 int f4 : 1;
16
 int f5 : 1;
17
 int f6 : 1;
18
 int f7 : 1;
19
 int f8 : 1;
20
 int f9 : 1;
21
 int f10 : 1;
22
 int f11 : 1;
23
 int f12 : 1;
24
 int f13 : 1;
25
 int f14 : 1;
26
 int f15 : 1;
27
 int f16 : 1;
28
 int f17 : 2;
29
 int f18 : 2;
30
 int f19 : 2;
31
 int f20 : 2;
32
 int f21 : 2;
33
 int f22 : 2;
34
 int f23 : 2;
35
 int f24 : 2;
36
 } s;
37
 
38
void foo ()
39
{
40
 
41
    s.f1 = 0;
42
    s.f2 = 0;
43
    s.f3 = 0;
44
    s.f4 = 0;
45
    s.f5 = 0;
46
    s.f6 = 0;
47
    s.f7 = 0;
48
    s.f8 = 0;
49
    s.f9 = 0;
50
    s.f10 = 0;
51
    s.f11 = 0;
52
    s.f12 = 0;
53
    s.f13 = 0;
54
    s.f14 = 0;
55
    s.f15 = 0;
56
    s.f16 = 0;
57
    s.f17 = 0;
58
    s.f18 = 0;
59
    s.f19 = 0;
60
    s.f20 = 0;
61
    s.f21 = 0;
62
    s.f22 = 0;
63
    s.f23 = 0;
64
    s.f24 = 0;
65
 
66
}
67
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.