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[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [rs6000-power2-1.c] - Blame information for rev 816

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Line No. Rev Author Line
1 149 jeremybenn
/* { dg-do compile { target { ilp32 } } } */
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/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
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/* This used to ICE as the peephole was not checking to see
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   if the register is a floating point one (I think this cannot
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   happen in real life except in this example).  */
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register volatile double t1 __asm__("r14");
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register volatile double t2 __asm__("r15");
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register volatile double t3 __asm__("r16"), t4 __asm__("r17");
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void t(double *a, double *b)
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{
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        t1 = a[-1];
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        t2 = a[0];
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        t3 = a[1];
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        t4 = a[2];
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        b[-1] = t1;
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        b[0] = t2;
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        b[1] = t3;
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        b[2] = t4;
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}
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