OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [fpmul.c] - Blame information for rev 816

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 149 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-mcpu=ultrasparc -mvis" } */
3
typedef int vec32 __attribute__((vector_size(8)));
4
typedef short vec16 __attribute__((vector_size(8)));
5
typedef unsigned char pixel __attribute__((vector_size(4)));
6
typedef short pixel16 __attribute__((vector_size(4)));
7
typedef unsigned char vec8 __attribute__((vector_size(8)));
8
 
9
vec16 foo1 (pixel a, vec16 b) {
10
  return __builtin_vis_fmul8x16 (a, b);
11
}
12
 
13
vec16 foo2 (pixel a, pixel16 b) {
14
  return __builtin_vis_fmul8x16au (a, b);
15
}
16
 
17
vec16 foo3 (pixel a, pixel16 b) {
18
  return __builtin_vis_fmul8x16al (a, b);
19
}
20
 
21
vec16 foo4 (vec8 a, vec16 b) {
22
  return __builtin_vis_fmul8sux16 (a, b);
23
}
24
 
25
vec16 foo5 (vec8 a, vec16 b) {
26
  return __builtin_vis_fmul8ulx16 (a, b);
27
}
28
 
29
vec32 foo6 (pixel a, pixel16 b) {
30
  return __builtin_vis_fmuld8sux16 (a, b);
31
}
32
 
33
vec32 foo7 (pixel a, pixel16 b) {
34
  return __builtin_vis_fmuld8ulx16 (a, b);
35
}
36
 
37
/* { dg-final { scan-assembler "fmul8x16\t%" } } */
38
/* { dg-final { scan-assembler "fmul8x16au\t%" } } */
39
/* { dg-final { scan-assembler "fmul8x16al\t%" } } */
40
/* { dg-final { scan-assembler "fmul8sux16\t%" } } */
41
/* { dg-final { scan-assembler "fmul8ulx16\t%" } } */
42
/* { dg-final { scan-assembler "fmuld8sux16\t%" } } */
43
/* { dg-final { scan-assembler "fmuld8ulx16\t%" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.