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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [gdb/] [cris-tdep.c] - Blame information for rev 827

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1 24 jeremybenn
/* Target dependent code for CRIS, for GDB, the GNU debugger.
2
 
3
   Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4
   Free Software Foundation, Inc.
5
 
6
   Contributed by Axis Communications AB.
7
   Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8
 
9
   This file is part of GDB.
10
 
11
   This program is free software; you can redistribute it and/or modify
12
   it under the terms of the GNU General Public License as published by
13
   the Free Software Foundation; either version 3 of the License, or
14
   (at your option) any later version.
15
 
16
   This program is distributed in the hope that it will be useful,
17
   but WITHOUT ANY WARRANTY; without even the implied warranty of
18
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
   GNU General Public License for more details.
20
 
21
   You should have received a copy of the GNU General Public License
22
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
23
 
24
#include "defs.h"
25
#include "frame.h"
26
#include "frame-unwind.h"
27
#include "frame-base.h"
28
#include "trad-frame.h"
29
#include "dwarf2-frame.h"
30
#include "symtab.h"
31
#include "inferior.h"
32
#include "gdbtypes.h"
33
#include "gdbcore.h"
34
#include "gdbcmd.h"
35
#include "target.h"
36
#include "value.h"
37
#include "opcode/cris.h"
38
#include "arch-utils.h"
39
#include "regcache.h"
40
#include "gdb_assert.h"
41
 
42
/* To get entry_point_address.  */
43
#include "objfiles.h"
44
 
45
#include "solib.h"              /* Support for shared libraries.  */
46
#include "solib-svr4.h"
47
#include "gdb_string.h"
48
#include "dis-asm.h"
49
 
50
enum cris_num_regs
51
{
52
  /* There are no floating point registers.  Used in gdbserver low-linux.c.  */
53
  NUM_FREGS = 0,
54
 
55
  /* There are 16 general registers.  */
56
  NUM_GENREGS = 16,
57
 
58
  /* There are 16 special registers.  */
59
  NUM_SPECREGS = 16,
60
 
61
  /* CRISv32 has a pseudo PC register, not noted here.  */
62
 
63
  /* CRISv32 has 16 support registers.  */
64
  NUM_SUPPREGS = 16
65
};
66
 
67
/* Register numbers of various important registers.
68
   CRIS_FP_REGNUM   Contains address of executing stack frame.
69
   STR_REGNUM  Contains the address of structure return values.
70
   RET_REGNUM  Contains the return value when shorter than or equal to 32 bits
71
   ARG1_REGNUM Contains the first parameter to a function.
72
   ARG2_REGNUM Contains the second parameter to a function.
73
   ARG3_REGNUM Contains the third parameter to a function.
74
   ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
75
   gdbarch_sp_regnum Contains address of top of stack.
76
   gdbarch_pc_regnum Contains address of next instruction.
77
   SRP_REGNUM  Subroutine return pointer register.
78
   BRP_REGNUM  Breakpoint return pointer register.  */
79
 
80
enum cris_regnums
81
{
82
  /* Enums with respect to the general registers, valid for all
83
     CRIS versions.  The frame pointer is always in R8.  */
84
  CRIS_FP_REGNUM = 8,
85
  /* ABI related registers.  */
86
  STR_REGNUM  = 9,
87
  RET_REGNUM  = 10,
88
  ARG1_REGNUM = 10,
89
  ARG2_REGNUM = 11,
90
  ARG3_REGNUM = 12,
91
  ARG4_REGNUM = 13,
92
 
93
  /* Registers which happen to be common.  */
94
  VR_REGNUM   = 17,
95
  MOF_REGNUM  = 23,
96
  SRP_REGNUM  = 27,
97
 
98
  /* CRISv10 et. al. specific registers.  */
99
  P0_REGNUM   = 16,
100
  P4_REGNUM   = 20,
101
  CCR_REGNUM  = 21,
102
  P8_REGNUM   = 24,
103
  IBR_REGNUM  = 25,
104
  IRP_REGNUM  = 26,
105
  BAR_REGNUM  = 28,
106
  DCCR_REGNUM = 29,
107
  BRP_REGNUM  = 30,
108
  USP_REGNUM  = 31,
109
 
110
  /* CRISv32 specific registers.  */
111
  ACR_REGNUM  = 15,
112
  BZ_REGNUM   = 16,
113
  PID_REGNUM  = 18,
114
  SRS_REGNUM  = 19,
115
  WZ_REGNUM   = 20,
116
  EXS_REGNUM  = 21,
117
  EDA_REGNUM  = 22,
118
  DZ_REGNUM   = 24,
119
  EBP_REGNUM  = 25,
120
  ERP_REGNUM  = 26,
121
  NRP_REGNUM  = 28,
122
  CCS_REGNUM  = 29,
123
  CRISV32USP_REGNUM  = 30, /* Shares name but not number with CRISv10.  */
124
  SPC_REGNUM  = 31,
125
  CRISV32PC_REGNUM   = 32, /* Shares name but not number with CRISv10.  */
126
 
127
  S0_REGNUM = 33,
128
  S1_REGNUM = 34,
129
  S2_REGNUM = 35,
130
  S3_REGNUM = 36,
131
  S4_REGNUM = 37,
132
  S5_REGNUM = 38,
133
  S6_REGNUM = 39,
134
  S7_REGNUM = 40,
135
  S8_REGNUM = 41,
136
  S9_REGNUM = 42,
137
  S10_REGNUM = 43,
138
  S11_REGNUM = 44,
139
  S12_REGNUM = 45,
140
  S13_REGNUM = 46,
141
  S14_REGNUM = 47,
142
  S15_REGNUM = 48,
143
};
144
 
145
extern const struct cris_spec_reg cris_spec_regs[];
146
 
147
/* CRIS version, set via the user command 'set cris-version'.  Affects
148
   register names and sizes.  */
149
static int usr_cmd_cris_version;
150
 
151
/* Indicates whether to trust the above variable.  */
152
static int usr_cmd_cris_version_valid = 0;
153
 
154
static const char cris_mode_normal[] = "normal";
155
static const char cris_mode_guru[] = "guru";
156
static const char *cris_modes[] = {
157
  cris_mode_normal,
158
  cris_mode_guru,
159
 
160
};
161
 
162
/* CRIS mode, set via the user command 'set cris-mode'.  Affects
163
   type of break instruction among other things.  */
164
static const char *usr_cmd_cris_mode = cris_mode_normal;
165
 
166
/* Whether to make use of Dwarf-2 CFI (default on).  */
167
static int usr_cmd_cris_dwarf2_cfi = 1;
168
 
169
/* CRIS architecture specific information.  */
170
struct gdbarch_tdep
171
{
172
  int cris_version;
173
  const char *cris_mode;
174
  int cris_dwarf2_cfi;
175
};
176
 
177
/* Functions for accessing target dependent data.  */
178
 
179
static int
180
cris_version (void)
181
{
182
  return (gdbarch_tdep (current_gdbarch)->cris_version);
183
}
184
 
185
static const char *
186
cris_mode (void)
187
{
188
  return (gdbarch_tdep (current_gdbarch)->cris_mode);
189
}
190
 
191
/* Sigtramp identification code copied from i386-linux-tdep.c.  */
192
 
193
#define SIGTRAMP_INSN0    0x9c5f  /* movu.w 0xXX, $r9 */
194
#define SIGTRAMP_OFFSET0  0
195
#define SIGTRAMP_INSN1    0xe93d  /* break 13 */
196
#define SIGTRAMP_OFFSET1  4
197
 
198
static const unsigned short sigtramp_code[] =
199
{
200
  SIGTRAMP_INSN0, 0x0077,  /* movu.w $0x77, $r9 */
201
  SIGTRAMP_INSN1           /* break 13 */
202
};
203
 
204
#define SIGTRAMP_LEN (sizeof sigtramp_code)
205
 
206
/* Note: same length as normal sigtramp code.  */
207
 
208
static const unsigned short rt_sigtramp_code[] =
209
{
210
  SIGTRAMP_INSN0, 0x00ad,  /* movu.w $0xad, $r9 */
211
  SIGTRAMP_INSN1           /* break 13 */
212
};
213
 
214
/* If PC is in a sigtramp routine, return the address of the start of
215
   the routine.  Otherwise, return 0.  */
216
 
217
static CORE_ADDR
218
cris_sigtramp_start (struct frame_info *next_frame)
219
{
220
  CORE_ADDR pc = frame_pc_unwind (next_frame);
221
  gdb_byte buf[SIGTRAMP_LEN];
222
 
223
  if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
224
    return 0;
225
 
226
  if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
227
    {
228
      if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
229
        return 0;
230
 
231
      pc -= SIGTRAMP_OFFSET1;
232
      if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
233
        return 0;
234
    }
235
 
236
  if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
237
    return 0;
238
 
239
  return pc;
240
}
241
 
242
/* If PC is in a RT sigtramp routine, return the address of the start of
243
   the routine.  Otherwise, return 0.  */
244
 
245
static CORE_ADDR
246
cris_rt_sigtramp_start (struct frame_info *next_frame)
247
{
248
  CORE_ADDR pc = frame_pc_unwind (next_frame);
249
  gdb_byte buf[SIGTRAMP_LEN];
250
 
251
  if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
252
    return 0;
253
 
254
  if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
255
    {
256
      if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
257
        return 0;
258
 
259
      pc -= SIGTRAMP_OFFSET1;
260
      if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN))
261
        return 0;
262
    }
263
 
264
  if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
265
    return 0;
266
 
267
  return pc;
268
}
269
 
270
/* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
271
   routine, return the address of the associated sigcontext structure.  */
272
 
273
static CORE_ADDR
274
cris_sigcontext_addr (struct frame_info *next_frame)
275
{
276
  CORE_ADDR pc;
277
  CORE_ADDR sp;
278
  char buf[4];
279
 
280
  frame_unwind_register (next_frame,
281
                         gdbarch_sp_regnum (get_frame_arch (next_frame)), buf);
282
  sp = extract_unsigned_integer (buf, 4);
283
 
284
  /* Look for normal sigtramp frame first.  */
285
  pc = cris_sigtramp_start (next_frame);
286
  if (pc)
287
    {
288
      /* struct signal_frame (arch/cris/kernel/signal.c) contains
289
         struct sigcontext as its first member, meaning the SP points to
290
         it already.  */
291
      return sp;
292
    }
293
 
294
  pc = cris_rt_sigtramp_start (next_frame);
295
  if (pc)
296
    {
297
      /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
298
         a struct ucontext, which in turn contains a struct sigcontext.
299
         Magic digging:
300
         4 + 4 + 128 to struct ucontext, then
301
         4 + 4 + 12 to struct sigcontext.  */
302
      return (sp + 156);
303
    }
304
 
305
  error (_("Couldn't recognize signal trampoline."));
306
  return 0;
307
}
308
 
309
struct cris_unwind_cache
310
{
311
  /* The previous frame's inner most stack address.  Used as this
312
     frame ID's stack_addr.  */
313
  CORE_ADDR prev_sp;
314
  /* The frame's base, optionally used by the high-level debug info.  */
315
  CORE_ADDR base;
316
  int size;
317
  /* How far the SP and r8 (FP) have been offset from the start of
318
     the stack frame (as defined by the previous frame's stack
319
     pointer).  */
320
  LONGEST sp_offset;
321
  LONGEST r8_offset;
322
  int uses_frame;
323
 
324
  /* From old frame_extra_info struct.  */
325
  CORE_ADDR return_pc;
326
  int leaf_function;
327
 
328
  /* Table indicating the location of each and every register.  */
329
  struct trad_frame_saved_reg *saved_regs;
330
};
331
 
332
static struct cris_unwind_cache *
333
cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame,
334
                                  void **this_cache)
335
{
336
  struct gdbarch *gdbarch = get_frame_arch (next_frame);
337
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
338
  struct cris_unwind_cache *info;
339
  CORE_ADDR pc;
340
  CORE_ADDR sp;
341
  CORE_ADDR addr;
342
  char buf[4];
343
  int i;
344
 
345
  if ((*this_cache))
346
    return (*this_cache);
347
 
348
  info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
349
  (*this_cache) = info;
350
  info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
351
 
352
  /* Zero all fields.  */
353
  info->prev_sp = 0;
354
  info->base = 0;
355
  info->size = 0;
356
  info->sp_offset = 0;
357
  info->r8_offset = 0;
358
  info->uses_frame = 0;
359
  info->return_pc = 0;
360
  info->leaf_function = 0;
361
 
362
  frame_unwind_register (next_frame, gdbarch_sp_regnum (gdbarch), buf);
363
  info->base = extract_unsigned_integer (buf, 4);
364
 
365
  addr = cris_sigcontext_addr (next_frame);
366
 
367
  /* Layout of the sigcontext struct:
368
     struct sigcontext {
369
        struct pt_regs regs;
370
        unsigned long oldmask;
371
        unsigned long usp;
372
     }; */
373
 
374
  if (tdep->cris_version == 10)
375
    {
376
      /* R0 to R13 are stored in reverse order at offset (2 * 4) in
377
         struct pt_regs.  */
378
      for (i = 0; i <= 13; i++)
379
        info->saved_regs[i].addr = addr + ((15 - i) * 4);
380
 
381
      info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
382
      info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
383
      info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
384
      /* Note: IRP is off by 2 at this point.  There's no point in correcting
385
         it though since that will mean that the backtrace will show a PC
386
         different from what is shown when stopped.  */
387
      info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
388
      info->saved_regs[gdbarch_pc_regnum (gdbarch)]
389
        = info->saved_regs[IRP_REGNUM];
390
      info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
391
    }
392
  else
393
    {
394
      /* CRISv32.  */
395
      /* R0 to R13 are stored in order at offset (1 * 4) in
396
         struct pt_regs.  */
397
      for (i = 0; i <= 13; i++)
398
        info->saved_regs[i].addr = addr + ((i + 1) * 4);
399
 
400
      info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
401
      info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
402
      info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
403
      info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
404
      info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
405
      info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
406
      info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
407
      info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
408
      info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
409
 
410
      /* FIXME: If ERP is in a delay slot at this point then the PC will
411
         be wrong at this point.  This problem manifests itself in the
412
         sigaltstack.exp test case, which occasionally generates FAILs when
413
         the signal is received while in a delay slot.
414
 
415
         This could be solved by a couple of read_memory_unsigned_integer and a
416
         trad_frame_set_value.  */
417
      info->saved_regs[gdbarch_pc_regnum (gdbarch)]
418
        = info->saved_regs[ERP_REGNUM];
419
 
420
      info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
421
        = addr + (25 * 4);
422
    }
423
 
424
  return info;
425
}
426
 
427
static void
428
cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
429
                             struct frame_id *this_id)
430
{
431
  struct cris_unwind_cache *cache =
432
    cris_sigtramp_frame_unwind_cache (next_frame, this_cache);
433
  (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame));
434
}
435
 
436
/* Forward declaration.  */
437
 
438
static void cris_frame_prev_register (struct frame_info *next_frame,
439
                                      void **this_prologue_cache,
440
                                      int regnum, int *optimizedp,
441
                                      enum lval_type *lvalp, CORE_ADDR *addrp,
442
                                      int *realnump, gdb_byte *bufferp);
443
static void
444
cris_sigtramp_frame_prev_register (struct frame_info *next_frame,
445
                                   void **this_cache,
446
                                   int regnum, int *optimizedp,
447
                                   enum lval_type *lvalp, CORE_ADDR *addrp,
448
                                   int *realnump, gdb_byte *valuep)
449
{
450
  /* Make sure we've initialized the cache.  */
451
  cris_sigtramp_frame_unwind_cache (next_frame, this_cache);
452
  cris_frame_prev_register (next_frame, this_cache, regnum,
453
                            optimizedp, lvalp, addrp, realnump, valuep);
454
}
455
 
456
static const struct frame_unwind cris_sigtramp_frame_unwind =
457
{
458
  SIGTRAMP_FRAME,
459
  cris_sigtramp_frame_this_id,
460
  cris_sigtramp_frame_prev_register
461
};
462
 
463
static const struct frame_unwind *
464
cris_sigtramp_frame_sniffer (struct frame_info *next_frame)
465
{
466
  if (cris_sigtramp_start (next_frame)
467
      || cris_rt_sigtramp_start (next_frame))
468
    return &cris_sigtramp_frame_unwind;
469
 
470
  return NULL;
471
}
472
 
473
int
474
crisv32_single_step_through_delay (struct gdbarch *gdbarch,
475
                                   struct frame_info *this_frame)
476
{
477
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
478
  ULONGEST erp;
479
  int ret = 0;
480
  char buf[4];
481
 
482
  if (cris_mode () == cris_mode_guru)
483
    {
484
      frame_unwind_register (this_frame, NRP_REGNUM, buf);
485
    }
486
  else
487
    {
488
      frame_unwind_register (this_frame, ERP_REGNUM, buf);
489
    }
490
 
491
  erp = extract_unsigned_integer (buf, 4);
492
 
493
  if (erp & 0x1)
494
    {
495
      /* In delay slot - check if there's a breakpoint at the preceding
496
         instruction.  */
497
      if (breakpoint_here_p (erp & ~0x1))
498
        ret = 1;
499
    }
500
  return ret;
501
}
502
 
503
/* Hardware watchpoint support.  */
504
 
505
/* We support 6 hardware data watchpoints, but cannot trigger on execute
506
   (any combination of read/write is fine).  */
507
 
508
int
509
cris_can_use_hardware_watchpoint (int type, int count, int other)
510
{
511
  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
512
 
513
  /* No bookkeeping is done here; it is handled by the remote debug agent.  */
514
 
515
  if (tdep->cris_version != 32)
516
    return 0;
517
  else
518
    /* CRISv32: Six data watchpoints, one for instructions.  */
519
    return (((type == bp_read_watchpoint || type == bp_access_watchpoint
520
             || type == bp_hardware_watchpoint) && count <= 6)
521
            || (type == bp_hardware_breakpoint && count <= 1));
522
}
523
 
524
/* The CRISv32 hardware data watchpoints work by specifying ranges,
525
   which have no alignment or length restrictions.  */
526
 
527
int
528
cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
529
{
530
  return 1;
531
}
532
 
533
/* If the inferior has some watchpoint that triggered, return the
534
   address associated with that watchpoint.  Otherwise, return
535
   zero.  */
536
 
537
CORE_ADDR
538
cris_stopped_data_address (void)
539
{
540
  CORE_ADDR eda;
541
  eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM);
542
  return eda;
543
}
544
 
545
/* The instruction environment needed to find single-step breakpoints.  */
546
 
547
typedef
548
struct instruction_environment
549
{
550
  unsigned long reg[NUM_GENREGS];
551
  unsigned long preg[NUM_SPECREGS];
552
  unsigned long branch_break_address;
553
  unsigned long delay_slot_pc;
554
  unsigned long prefix_value;
555
  int   branch_found;
556
  int   prefix_found;
557
  int   invalid;
558
  int   slot_needed;
559
  int   delay_slot_pc_active;
560
  int   xflag_found;
561
  int   disable_interrupt;
562
} inst_env_type;
563
 
564
/* Machine-dependencies in CRIS for opcodes.  */
565
 
566
/* Instruction sizes.  */
567
enum cris_instruction_sizes
568
{
569
  INST_BYTE_SIZE  = 0,
570
  INST_WORD_SIZE  = 1,
571
  INST_DWORD_SIZE = 2
572
};
573
 
574
/* Addressing modes.  */
575
enum cris_addressing_modes
576
{
577
  REGISTER_MODE = 1,
578
  INDIRECT_MODE = 2,
579
  AUTOINC_MODE  = 3
580
};
581
 
582
/* Prefix addressing modes.  */
583
enum cris_prefix_addressing_modes
584
{
585
  PREFIX_INDEX_MODE  = 2,
586
  PREFIX_ASSIGN_MODE = 3,
587
 
588
  /* Handle immediate byte offset addressing mode prefix format.  */
589
  PREFIX_OFFSET_MODE = 2
590
};
591
 
592
/* Masks for opcodes.  */
593
enum cris_opcode_masks
594
{
595
  BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
596
  SIGNED_EXTEND_BIT_MASK          = 0x2,
597
  SIGNED_BYTE_MASK                = 0x80,
598
  SIGNED_BYTE_EXTEND_MASK         = 0xFFFFFF00,
599
  SIGNED_WORD_MASK                = 0x8000,
600
  SIGNED_WORD_EXTEND_MASK         = 0xFFFF0000,
601
  SIGNED_DWORD_MASK               = 0x80000000,
602
  SIGNED_QUICK_VALUE_MASK         = 0x20,
603
  SIGNED_QUICK_VALUE_EXTEND_MASK  = 0xFFFFFFC0
604
};
605
 
606
/* Functions for opcodes.  The general form of the ETRAX 16-bit instruction:
607
   Bit 15 - 12   Operand2
608
       11 - 10   Mode
609
        9 -  6   Opcode
610
        5 -  4   Size
611
        3 -  0   Operand1  */
612
 
613
static int
614
cris_get_operand2 (unsigned short insn)
615
{
616
  return ((insn & 0xF000) >> 12);
617
}
618
 
619
static int
620
cris_get_mode (unsigned short insn)
621
{
622
  return ((insn & 0x0C00) >> 10);
623
}
624
 
625
static int
626
cris_get_opcode (unsigned short insn)
627
{
628
  return ((insn & 0x03C0) >> 6);
629
}
630
 
631
static int
632
cris_get_size (unsigned short insn)
633
{
634
  return ((insn & 0x0030) >> 4);
635
}
636
 
637
static int
638
cris_get_operand1 (unsigned short insn)
639
{
640
  return (insn & 0x000F);
641
}
642
 
643
/* Additional functions in order to handle opcodes.  */
644
 
645
static int
646
cris_get_quick_value (unsigned short insn)
647
{
648
  return (insn & 0x003F);
649
}
650
 
651
static int
652
cris_get_bdap_quick_offset (unsigned short insn)
653
{
654
  return (insn & 0x00FF);
655
}
656
 
657
static int
658
cris_get_branch_short_offset (unsigned short insn)
659
{
660
  return (insn & 0x00FF);
661
}
662
 
663
static int
664
cris_get_asr_shift_steps (unsigned long value)
665
{
666
  return (value & 0x3F);
667
}
668
 
669
static int
670
cris_get_clear_size (unsigned short insn)
671
{
672
  return ((insn) & 0xC000);
673
}
674
 
675
static int
676
cris_is_signed_extend_bit_on (unsigned short insn)
677
{
678
  return (((insn) & 0x20) == 0x20);
679
}
680
 
681
static int
682
cris_is_xflag_bit_on (unsigned short insn)
683
{
684
  return (((insn) & 0x1000) == 0x1000);
685
}
686
 
687
static void
688
cris_set_size_to_dword (unsigned short *insn)
689
{
690
  *insn &= 0xFFCF;
691
  *insn |= 0x20;
692
}
693
 
694
static signed char
695
cris_get_signed_offset (unsigned short insn)
696
{
697
  return ((signed char) (insn & 0x00FF));
698
}
699
 
700
/* Calls an op function given the op-type, working on the insn and the
701
   inst_env.  */
702
static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
703
                           inst_env_type *);
704
 
705
static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
706
                                          struct gdbarch_list *);
707
 
708
static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
709
 
710
static void set_cris_version (char *ignore_args, int from_tty,
711
                              struct cmd_list_element *c);
712
 
713
static void set_cris_mode (char *ignore_args, int from_tty,
714
                           struct cmd_list_element *c);
715
 
716
static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
717
                                 struct cmd_list_element *c);
718
 
719
static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
720
                                     struct frame_info *next_frame,
721
                                     struct cris_unwind_cache *info);
722
 
723
static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
724
                                        struct frame_info *next_frame,
725
                                        struct cris_unwind_cache *info);
726
 
727
static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
728
                                 struct frame_info *next_frame);
729
 
730
static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
731
                                 struct frame_info *next_frame);
732
 
733
/* When arguments must be pushed onto the stack, they go on in reverse
734
   order.  The below implements a FILO (stack) to do this.
735
   Copied from d10v-tdep.c.  */
736
 
737
struct stack_item
738
{
739
  int len;
740
  struct stack_item *prev;
741
  void *data;
742
};
743
 
744
static struct stack_item *
745
push_stack_item (struct stack_item *prev, void *contents, int len)
746
{
747
  struct stack_item *si;
748
  si = xmalloc (sizeof (struct stack_item));
749
  si->data = xmalloc (len);
750
  si->len = len;
751
  si->prev = prev;
752
  memcpy (si->data, contents, len);
753
  return si;
754
}
755
 
756
static struct stack_item *
757
pop_stack_item (struct stack_item *si)
758
{
759
  struct stack_item *dead = si;
760
  si = si->prev;
761
  xfree (dead->data);
762
  xfree (dead);
763
  return si;
764
}
765
 
766
/* Put here the code to store, into fi->saved_regs, the addresses of
767
   the saved registers of frame described by FRAME_INFO.  This
768
   includes special registers such as pc and fp saved in special ways
769
   in the stack frame.  sp is even more special: the address we return
770
   for it IS the sp for the next frame.  */
771
 
772
struct cris_unwind_cache *
773
cris_frame_unwind_cache (struct frame_info *next_frame,
774
                         void **this_prologue_cache)
775
{
776
  CORE_ADDR pc;
777
  struct cris_unwind_cache *info;
778
  int i;
779
 
780
  if ((*this_prologue_cache))
781
    return (*this_prologue_cache);
782
 
783
  info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
784
  (*this_prologue_cache) = info;
785
  info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
786
 
787
  /* Zero all fields.  */
788
  info->prev_sp = 0;
789
  info->base = 0;
790
  info->size = 0;
791
  info->sp_offset = 0;
792
  info->r8_offset = 0;
793
  info->uses_frame = 0;
794
  info->return_pc = 0;
795
  info->leaf_function = 0;
796
 
797
  /* Prologue analysis does the rest...  */
798
  if (cris_version () == 32)
799
    crisv32_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME),
800
                           next_frame, info);
801
  else
802
    cris_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME),
803
                        next_frame, info);
804
 
805
  return info;
806
}
807
 
808
/* Given a GDB frame, determine the address of the calling function's
809
   frame.  This will be used to create a new GDB frame struct.  */
810
 
811
static void
812
cris_frame_this_id (struct frame_info *next_frame,
813
                    void **this_prologue_cache,
814
                    struct frame_id *this_id)
815
{
816
  struct cris_unwind_cache *info
817
    = cris_frame_unwind_cache (next_frame, this_prologue_cache);
818
  CORE_ADDR base;
819
  CORE_ADDR func;
820
  struct frame_id id;
821
 
822
  /* The FUNC is easy.  */
823
  func = frame_func_unwind (next_frame, NORMAL_FRAME);
824
 
825
  /* Hopefully the prologue analysis either correctly determined the
826
     frame's base (which is the SP from the previous frame), or set
827
     that base to "NULL".  */
828
  base = info->prev_sp;
829
  if (base == 0)
830
    return;
831
 
832
  id = frame_id_build (base, func);
833
 
834
  (*this_id) = id;
835
}
836
 
837
static void
838
cris_frame_prev_register (struct frame_info *next_frame,
839
                          void **this_prologue_cache,
840
                          int regnum, int *optimizedp,
841
                          enum lval_type *lvalp, CORE_ADDR *addrp,
842
                          int *realnump, gdb_byte *bufferp)
843
{
844
  struct cris_unwind_cache *info
845
    = cris_frame_unwind_cache (next_frame, this_prologue_cache);
846
  trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
847
                                optimizedp, lvalp, addrp, realnump, bufferp);
848
}
849
 
850
/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
851
   dummy frame.  The frame ID's base needs to match the TOS value
852
   saved by save_dummy_frame_tos(), and the PC match the dummy frame's
853
   breakpoint.  */
854
 
855
static struct frame_id
856
cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
857
{
858
  return frame_id_build (cris_unwind_sp (gdbarch, next_frame),
859
                         frame_pc_unwind (next_frame));
860
}
861
 
862
static CORE_ADDR
863
cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
864
{
865
  /* Align to the size of an instruction (so that they can safely be
866
     pushed onto the stack).  */
867
  return sp & ~3;
868
}
869
 
870
static CORE_ADDR
871
cris_push_dummy_code (struct gdbarch *gdbarch,
872
                      CORE_ADDR sp, CORE_ADDR funaddr,
873
                      struct value **args, int nargs,
874
                      struct type *value_type,
875
                      CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
876
                      struct regcache *regcache)
877
{
878
  /* Allocate space sufficient for a breakpoint.  */
879
  sp = (sp - 4) & ~3;
880
  /* Store the address of that breakpoint */
881
  *bp_addr = sp;
882
  /* CRIS always starts the call at the callee's entry point.  */
883
  *real_pc = funaddr;
884
  return sp;
885
}
886
 
887
static CORE_ADDR
888
cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
889
                      struct regcache *regcache, CORE_ADDR bp_addr,
890
                      int nargs, struct value **args, CORE_ADDR sp,
891
                      int struct_return, CORE_ADDR struct_addr)
892
{
893
  int stack_alloc;
894
  int stack_offset;
895
  int argreg;
896
  int argnum;
897
 
898
  CORE_ADDR regval;
899
 
900
  /* The function's arguments and memory allocated by gdb for the arguments to
901
     point at reside in separate areas on the stack.
902
     Both frame pointers grow toward higher addresses.  */
903
  CORE_ADDR fp_arg;
904
  CORE_ADDR fp_mem;
905
 
906
  struct stack_item *si = NULL;
907
 
908
  /* Push the return address.  */
909
  regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
910
 
911
  /* Are we returning a value using a structure return or a normal value
912
     return?  struct_addr is the address of the reserved space for the return
913
     structure to be written on the stack.  */
914
  if (struct_return)
915
    {
916
      regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
917
    }
918
 
919
  /* Now load as many as possible of the first arguments into registers,
920
     and push the rest onto the stack.  */
921
  argreg = ARG1_REGNUM;
922
  stack_offset = 0;
923
 
924
  for (argnum = 0; argnum < nargs; argnum++)
925
    {
926
      int len;
927
      char *val;
928
      int reg_demand;
929
      int i;
930
 
931
      len = TYPE_LENGTH (value_type (args[argnum]));
932
      val = (char *) value_contents (args[argnum]);
933
 
934
      /* How may registers worth of storage do we need for this argument?  */
935
      reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
936
 
937
      if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
938
        {
939
          /* Data passed by value.  Fits in available register(s).  */
940
          for (i = 0; i < reg_demand; i++)
941
            {
942
              regcache_cooked_write (regcache, argreg, val);
943
              argreg++;
944
              val += 4;
945
            }
946
        }
947
      else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
948
        {
949
          /* Data passed by value. Does not fit in available register(s).
950
             Use the register(s) first, then the stack.  */
951
          for (i = 0; i < reg_demand; i++)
952
            {
953
              if (argreg <= ARG4_REGNUM)
954
                {
955
                  regcache_cooked_write (regcache, argreg, val);
956
                  argreg++;
957
                  val += 4;
958
                }
959
              else
960
                {
961
                  /* Push item for later so that pushed arguments
962
                     come in the right order.  */
963
                  si = push_stack_item (si, val, 4);
964
                  val += 4;
965
                }
966
            }
967
        }
968
      else if (len > (2 * 4))
969
        {
970
          /* Data passed by reference.  Push copy of data onto stack
971
             and pass pointer to this copy as argument.  */
972
          sp = (sp - len) & ~3;
973
          write_memory (sp, val, len);
974
 
975
          if (argreg <= ARG4_REGNUM)
976
            {
977
              regcache_cooked_write_unsigned (regcache, argreg, sp);
978
              argreg++;
979
            }
980
          else
981
            {
982
              gdb_byte buf[4];
983
              store_unsigned_integer (buf, 4, sp);
984
              si = push_stack_item (si, buf, 4);
985
            }
986
        }
987
      else
988
        {
989
          /* Data passed by value.  No available registers.  Put it on
990
             the stack.  */
991
           si = push_stack_item (si, val, len);
992
        }
993
    }
994
 
995
  while (si)
996
    {
997
      /* fp_arg must be word-aligned (i.e., don't += len) to match
998
         the function prologue.  */
999
      sp = (sp - si->len) & ~3;
1000
      write_memory (sp, si->data, si->len);
1001
      si = pop_stack_item (si);
1002
    }
1003
 
1004
  /* Finally, update the SP register.  */
1005
  regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
1006
 
1007
  return sp;
1008
}
1009
 
1010
static const struct frame_unwind cris_frame_unwind =
1011
{
1012
  NORMAL_FRAME,
1013
  cris_frame_this_id,
1014
  cris_frame_prev_register
1015
};
1016
 
1017
const struct frame_unwind *
1018
cris_frame_sniffer (struct frame_info *next_frame)
1019
{
1020
  return &cris_frame_unwind;
1021
}
1022
 
1023
static CORE_ADDR
1024
cris_frame_base_address (struct frame_info *next_frame, void **this_cache)
1025
{
1026
  struct cris_unwind_cache *info
1027
    = cris_frame_unwind_cache (next_frame, this_cache);
1028
  return info->base;
1029
}
1030
 
1031
static const struct frame_base cris_frame_base =
1032
{
1033
  &cris_frame_unwind,
1034
  cris_frame_base_address,
1035
  cris_frame_base_address,
1036
  cris_frame_base_address
1037
};
1038
 
1039
/* Frames information. The definition of the struct frame_info is
1040
 
1041
   CORE_ADDR frame
1042
   CORE_ADDR pc
1043
   enum frame_type type;
1044
   CORE_ADDR return_pc
1045
   int leaf_function
1046
 
1047
   If the compilation option -fno-omit-frame-pointer is present the
1048
   variable frame will be set to the content of R8 which is the frame
1049
   pointer register.
1050
 
1051
   The variable pc contains the address where execution is performed
1052
   in the present frame.  The innermost frame contains the current content
1053
   of the register PC.  All other frames contain the content of the
1054
   register PC in the next frame.
1055
 
1056
   The variable `type' indicates the frame's type: normal, SIGTRAMP
1057
   (associated with a signal handler), dummy (associated with a dummy
1058
   frame).
1059
 
1060
   The variable return_pc contains the address where execution should be
1061
   resumed when the present frame has finished, the return address.
1062
 
1063
   The variable leaf_function is 1 if the return address is in the register
1064
   SRP, and 0 if it is on the stack.
1065
 
1066
   Prologue instructions C-code.
1067
   The prologue may consist of (-fno-omit-frame-pointer)
1068
   1)                2)
1069
   push   srp
1070
   push   r8         push   r8
1071
   move.d sp,r8      move.d sp,r8
1072
   subq   X,sp       subq   X,sp
1073
   movem  rY,[sp]    movem  rY,[sp]
1074
   move.S rZ,[r8-U]  move.S rZ,[r8-U]
1075
 
1076
   where 1 is a non-terminal function, and 2 is a leaf-function.
1077
 
1078
   Note that this assumption is extremely brittle, and will break at the
1079
   slightest change in GCC's prologue.
1080
 
1081
   If local variables are declared or register contents are saved on stack
1082
   the subq-instruction will be present with X as the number of bytes
1083
   needed for storage.  The reshuffle with respect to r8 may be performed
1084
   with any size S (b, w, d) and any of the general registers Z={0..13}.
1085
   The offset U should be representable by a signed 8-bit value in all cases.
1086
   Thus, the prefix word is assumed to be immediate byte offset mode followed
1087
   by another word containing the instruction.
1088
 
1089
   Degenerate cases:
1090
   3)
1091
   push   r8
1092
   move.d sp,r8
1093
   move.d r8,sp
1094
   pop    r8
1095
 
1096
   Prologue instructions C++-code.
1097
   Case 1) and 2) in the C-code may be followed by
1098
 
1099
   move.d r10,rS    ; this
1100
   move.d r11,rT    ; P1
1101
   move.d r12,rU    ; P2
1102
   move.d r13,rV    ; P3
1103
   move.S [r8+U],rZ ; P4
1104
 
1105
   if any of the call parameters are stored. The host expects these
1106
   instructions to be executed in order to get the call parameters right.  */
1107
 
1108
/* Examine the prologue of a function.  The variable ip is the address of
1109
   the first instruction of the prologue.  The variable limit is the address
1110
   of the first instruction after the prologue.  The variable fi contains the
1111
   information in struct frame_info.  The variable frameless_p controls whether
1112
   the entire prologue is examined (0) or just enough instructions to
1113
   determine that it is a prologue (1).  */
1114
 
1115
static CORE_ADDR
1116
cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
1117
                    struct cris_unwind_cache *info)
1118
{
1119
  struct gdbarch *gdbarch = get_frame_arch (next_frame);
1120
  /* Present instruction.  */
1121
  unsigned short insn;
1122
 
1123
  /* Next instruction, lookahead.  */
1124
  unsigned short insn_next;
1125
  int regno;
1126
 
1127
  /* Is there a push fp?  */
1128
  int have_fp;
1129
 
1130
  /* Number of byte on stack used for local variables and movem.  */
1131
  int val;
1132
 
1133
  /* Highest register number in a movem.  */
1134
  int regsave;
1135
 
1136
  /* move.d r<source_register>,rS */
1137
  short source_register;
1138
 
1139
  /* Scan limit.  */
1140
  int limit;
1141
 
1142
  /* This frame is with respect to a leaf until a push srp is found.  */
1143
  if (info)
1144
    {
1145
      info->leaf_function = 1;
1146
    }
1147
 
1148
  /* Assume nothing on stack.  */
1149
  val = 0;
1150
  regsave = -1;
1151
 
1152
  /* If we were called without a next_frame, that means we were called
1153
     from cris_skip_prologue which already tried to find the end of the
1154
     prologue through the symbol information.  64 instructions past current
1155
     pc is arbitrarily chosen, but at least it means we'll stop eventually.  */
1156
  limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64;
1157
 
1158
  /* Find the prologue instructions.  */
1159
  while (pc > 0 && pc < limit)
1160
    {
1161
      insn = read_memory_unsigned_integer (pc, 2);
1162
      pc += 2;
1163
      if (insn == 0xE1FC)
1164
        {
1165
          /* push <reg> 32 bit instruction */
1166
          insn_next = read_memory_unsigned_integer (pc, 2);
1167
          pc += 2;
1168
          regno = cris_get_operand2 (insn_next);
1169
          if (info)
1170
            {
1171
              info->sp_offset += 4;
1172
            }
1173
          /* This check, meant to recognize srp, used to be regno ==
1174
             (SRP_REGNUM - NUM_GENREGS), but that covers r11 also.  */
1175
          if (insn_next == 0xBE7E)
1176
            {
1177
              if (info)
1178
                {
1179
                  info->leaf_function = 0;
1180
                }
1181
            }
1182
          else if (insn_next == 0x8FEE)
1183
            {
1184
              /* push $r8 */
1185
              if (info)
1186
                {
1187
                  info->r8_offset = info->sp_offset;
1188
                }
1189
            }
1190
        }
1191
      else if (insn == 0x866E)
1192
        {
1193
          /* move.d sp,r8 */
1194
          if (info)
1195
            {
1196
              info->uses_frame = 1;
1197
            }
1198
          continue;
1199
        }
1200
      else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1201
               && cris_get_mode (insn) == 0x0000
1202
               && cris_get_opcode (insn) == 0x000A)
1203
        {
1204
          /* subq <val>,sp */
1205
          if (info)
1206
            {
1207
              info->sp_offset += cris_get_quick_value (insn);
1208
            }
1209
        }
1210
      else if (cris_get_mode (insn) == 0x0002
1211
               && cris_get_opcode (insn) == 0x000F
1212
               && cris_get_size (insn) == 0x0003
1213
               && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1214
        {
1215
          /* movem r<regsave>,[sp] */
1216
          regsave = cris_get_operand2 (insn);
1217
        }
1218
      else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1219
               && ((insn & 0x0F00) >> 8) == 0x0001
1220
               && (cris_get_signed_offset (insn) < 0))
1221
        {
1222
          /* Immediate byte offset addressing prefix word with sp as base
1223
             register.  Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1224
             is between 64 and 128.
1225
             movem r<regsave>,[sp=sp-<val>] */
1226
          if (info)
1227
            {
1228
              info->sp_offset += -cris_get_signed_offset (insn);
1229
            }
1230
          insn_next = read_memory_unsigned_integer (pc, 2);
1231
          pc += 2;
1232
          if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1233
              && cris_get_opcode (insn_next) == 0x000F
1234
              && cris_get_size (insn_next) == 0x0003
1235
              && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1236
                                                  (gdbarch))
1237
            {
1238
              regsave = cris_get_operand2 (insn_next);
1239
            }
1240
          else
1241
            {
1242
              /* The prologue ended before the limit was reached.  */
1243
              pc -= 4;
1244
              break;
1245
            }
1246
        }
1247
      else if (cris_get_mode (insn) == 0x0001
1248
               && cris_get_opcode (insn) == 0x0009
1249
               && cris_get_size (insn) == 0x0002)
1250
        {
1251
          /* move.d r<10..13>,r<0..15> */
1252
          source_register = cris_get_operand1 (insn);
1253
 
1254
          /* FIXME?  In the glibc solibs, the prologue might contain something
1255
             like (this example taken from relocate_doit):
1256
             move.d $pc,$r0
1257
             sub.d 0xfffef426,$r0
1258
             which isn't covered by the source_register check below.  Question
1259
             is whether to add a check for this combo, or make better use of
1260
             the limit variable instead.  */
1261
          if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1262
            {
1263
              /* The prologue ended before the limit was reached.  */
1264
              pc -= 2;
1265
              break;
1266
            }
1267
        }
1268
      else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1269
               /* The size is a fixed-size.  */
1270
               && ((insn & 0x0F00) >> 8) == 0x0001
1271
               /* A negative offset.  */
1272
               && (cris_get_signed_offset (insn) < 0))
1273
        {
1274
          /* move.S rZ,[r8-U] (?) */
1275
          insn_next = read_memory_unsigned_integer (pc, 2);
1276
          pc += 2;
1277
          regno = cris_get_operand2 (insn_next);
1278
          if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1279
              && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1280
              && cris_get_opcode (insn_next) == 0x000F)
1281
            {
1282
              /* move.S rZ,[r8-U] */
1283
              continue;
1284
            }
1285
          else
1286
            {
1287
              /* The prologue ended before the limit was reached.  */
1288
              pc -= 4;
1289
              break;
1290
            }
1291
        }
1292
      else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1293
               /* The size is a fixed-size.  */
1294
               && ((insn & 0x0F00) >> 8) == 0x0001
1295
               /* A positive offset.  */
1296
               && (cris_get_signed_offset (insn) > 0))
1297
        {
1298
          /* move.S [r8+U],rZ (?) */
1299
          insn_next = read_memory_unsigned_integer (pc, 2);
1300
          pc += 2;
1301
          regno = cris_get_operand2 (insn_next);
1302
          if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1303
              && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1304
              && cris_get_opcode (insn_next) == 0x0009
1305
              && cris_get_operand1 (insn_next) == regno)
1306
            {
1307
              /* move.S [r8+U],rZ */
1308
              continue;
1309
            }
1310
          else
1311
            {
1312
              /* The prologue ended before the limit was reached.  */
1313
              pc -= 4;
1314
              break;
1315
            }
1316
        }
1317
      else
1318
        {
1319
          /* The prologue ended before the limit was reached.  */
1320
          pc -= 2;
1321
          break;
1322
        }
1323
    }
1324
 
1325
  /* We only want to know the end of the prologue when next_frame and info
1326
     are NULL (called from cris_skip_prologue i.e.).  */
1327
  if (next_frame == NULL && info == NULL)
1328
    {
1329
      return pc;
1330
    }
1331
 
1332
  info->size = info->sp_offset;
1333
 
1334
  /* Compute the previous frame's stack pointer (which is also the
1335
     frame's ID's stack address), and this frame's base pointer.  */
1336
  if (info->uses_frame)
1337
    {
1338
      ULONGEST this_base;
1339
      /* The SP was moved to the FP.  This indicates that a new frame
1340
         was created.  Get THIS frame's FP value by unwinding it from
1341
         the next frame.  */
1342
      this_base = frame_unwind_register_unsigned (next_frame, CRIS_FP_REGNUM);
1343
      info->base = this_base;
1344
      info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1345
 
1346
      /* The FP points at the last saved register.  Adjust the FP back
1347
         to before the first saved register giving the SP.  */
1348
      info->prev_sp = info->base + info->r8_offset;
1349
    }
1350
  else
1351
    {
1352
      ULONGEST this_base;
1353
      /* Assume that the FP is this frame's SP but with that pushed
1354
         stack space added back.  */
1355
      this_base = frame_unwind_register_unsigned (next_frame,
1356
                                                  gdbarch_sp_regnum (gdbarch));
1357
      info->base = this_base;
1358
      info->prev_sp = info->base + info->size;
1359
    }
1360
 
1361
  /* Calculate the addresses for the saved registers on the stack.  */
1362
  /* FIXME: The address calculation should really be done on the fly while
1363
     we're analyzing the prologue (we only hold one regsave value as it is
1364
     now).  */
1365
  val = info->sp_offset;
1366
 
1367
  for (regno = regsave; regno >= 0; regno--)
1368
    {
1369
      info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1370
      val -= 4;
1371
    }
1372
 
1373
  /* The previous frame's SP needed to be computed.  Save the computed
1374
     value.  */
1375
  trad_frame_set_value (info->saved_regs,
1376
                        gdbarch_sp_regnum (gdbarch), info->prev_sp);
1377
 
1378
  if (!info->leaf_function)
1379
    {
1380
      /* SRP saved on the stack.  But where?  */
1381
      if (info->r8_offset == 0)
1382
        {
1383
          /* R8 not pushed yet.  */
1384
          info->saved_regs[SRP_REGNUM].addr = info->base;
1385
        }
1386
      else
1387
        {
1388
          /* R8 pushed, but SP may or may not be moved to R8 yet.  */
1389
          info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1390
        }
1391
    }
1392
 
1393
  /* The PC is found in SRP (the actual register or located on the stack).  */
1394
  info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1395
    = info->saved_regs[SRP_REGNUM];
1396
 
1397
  return pc;
1398
}
1399
 
1400
static CORE_ADDR
1401
crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
1402
                    struct cris_unwind_cache *info)
1403
{
1404
  struct gdbarch *gdbarch = get_frame_arch (next_frame);
1405
  ULONGEST this_base;
1406
 
1407
  /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1408
     meant to be a full-fledged prologue scanner.  It is only needed for
1409
     the cases where we end up in code always lacking DWARF-2 CFI, notably:
1410
 
1411
       * PLT stubs (library calls)
1412
       * call dummys
1413
       * signal trampolines
1414
 
1415
     For those cases, it is assumed that there is no actual prologue; that
1416
     the stack pointer is not adjusted, and (as a consequence) the return
1417
     address is not pushed onto the stack.  */
1418
 
1419
  /* We only want to know the end of the prologue when next_frame and info
1420
     are NULL (called from cris_skip_prologue i.e.).  */
1421
  if (next_frame == NULL && info == NULL)
1422
    {
1423
      return pc;
1424
    }
1425
 
1426
  /* The SP is assumed to be unaltered.  */
1427
  this_base = frame_unwind_register_unsigned (next_frame,
1428
                                              gdbarch_sp_regnum (gdbarch));
1429
  info->base = this_base;
1430
  info->prev_sp = this_base;
1431
 
1432
  /* The PC is assumed to be found in SRP.  */
1433
  info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1434
    = info->saved_regs[SRP_REGNUM];
1435
 
1436
  return pc;
1437
}
1438
 
1439
/* Advance pc beyond any function entry prologue instructions at pc
1440
   to reach some "real" code.  */
1441
 
1442
/* Given a PC value corresponding to the start of a function, return the PC
1443
   of the first instruction after the function prologue.  */
1444
 
1445
static CORE_ADDR
1446
cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1447
{
1448
  CORE_ADDR func_addr, func_end;
1449
  struct symtab_and_line sal;
1450
  CORE_ADDR pc_after_prologue;
1451
 
1452
  /* If we have line debugging information, then the end of the prologue
1453
     should the first assembly instruction of the first source line.  */
1454
  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1455
    {
1456
      sal = find_pc_line (func_addr, 0);
1457
      if (sal.end > 0 && sal.end < func_end)
1458
        return sal.end;
1459
    }
1460
 
1461
  if (cris_version () == 32)
1462
    pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1463
  else
1464
    pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1465
 
1466
  return pc_after_prologue;
1467
}
1468
 
1469
static CORE_ADDR
1470
cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1471
{
1472
  ULONGEST pc;
1473
  pc = frame_unwind_register_unsigned (next_frame,
1474
                                       gdbarch_pc_regnum (gdbarch));
1475
  return pc;
1476
}
1477
 
1478
static CORE_ADDR
1479
cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1480
{
1481
  ULONGEST sp;
1482
  sp = frame_unwind_register_unsigned (next_frame,
1483
                                       gdbarch_sp_regnum (gdbarch));
1484
  return sp;
1485
}
1486
 
1487
/* Use the program counter to determine the contents and size of a breakpoint
1488
   instruction.  It returns a pointer to a string of bytes that encode a
1489
   breakpoint instruction, stores the length of the string to *lenptr, and
1490
   adjusts pcptr (if necessary) to point to the actual memory location where
1491
   the breakpoint should be inserted.  */
1492
 
1493
static const unsigned char *
1494
cris_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
1495
{
1496
  static unsigned char break8_insn[] = {0x38, 0xe9};
1497
  static unsigned char break15_insn[] = {0x3f, 0xe9};
1498
  *lenptr = 2;
1499
 
1500
  if (cris_mode () == cris_mode_guru)
1501
    return break15_insn;
1502
  else
1503
    return break8_insn;
1504
}
1505
 
1506
/* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1507
 
1508
 
1509
static int
1510
cris_spec_reg_applicable (struct cris_spec_reg spec_reg)
1511
{
1512
  int version = cris_version ();
1513
 
1514
  switch (spec_reg.applicable_version)
1515
    {
1516
    case cris_ver_version_all:
1517
      return 1;
1518
    case cris_ver_warning:
1519
      /* Indeterminate/obsolete.  */
1520
      return 0;
1521
    case cris_ver_v0_3:
1522
      return (version >= 0 && version <= 3);
1523
    case cris_ver_v3p:
1524
      return (version >= 3);
1525
    case cris_ver_v8:
1526
      return (version == 8 || version == 9);
1527
    case cris_ver_v8p:
1528
      return (version >= 8);
1529
    case cris_ver_v0_10:
1530
      return (version >= 0 && version <= 10);
1531
    case cris_ver_v3_10:
1532
      return (version >= 3 && version <= 10);
1533
    case cris_ver_v8_10:
1534
      return (version >= 8 && version <= 10);
1535
    case cris_ver_v10:
1536
      return (version == 10);
1537
    case cris_ver_v10p:
1538
      return (version >= 10);
1539
    case cris_ver_v32p:
1540
      return (version >= 32);
1541
    default:
1542
      /* Invalid cris version.  */
1543
      return 0;
1544
    }
1545
}
1546
 
1547
/* Returns the register size in unit byte.  Returns 0 for an unimplemented
1548
   register, -1 for an invalid register.  */
1549
 
1550
static int
1551
cris_register_size (struct gdbarch *gdbarch, int regno)
1552
{
1553
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1554
  int i;
1555
  int spec_regno;
1556
 
1557
  if (regno >= 0 && regno < NUM_GENREGS)
1558
    {
1559
      /* General registers (R0 - R15) are 32 bits.  */
1560
      return 4;
1561
    }
1562
  else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1563
    {
1564
      /* Special register (R16 - R31).  cris_spec_regs is zero-based.
1565
         Adjust regno accordingly.  */
1566
      spec_regno = regno - NUM_GENREGS;
1567
 
1568
      for (i = 0; cris_spec_regs[i].name != NULL; i++)
1569
        {
1570
          if (cris_spec_regs[i].number == spec_regno
1571
              && cris_spec_reg_applicable (cris_spec_regs[i]))
1572
            /* Go with the first applicable register.  */
1573
            return cris_spec_regs[i].reg_size;
1574
        }
1575
      /* Special register not applicable to this CRIS version.  */
1576
      return 0;
1577
    }
1578
  else if (regno >= gdbarch_pc_regnum (gdbarch)
1579
           && regno < gdbarch_num_regs (gdbarch))
1580
    {
1581
      /* This will apply to CRISv32 only where there are additional registers
1582
         after the special registers (pseudo PC and support registers).  */
1583
      return 4;
1584
    }
1585
 
1586
 
1587
  return -1;
1588
}
1589
 
1590
/* Nonzero if regno should not be fetched from the target.  This is the case
1591
   for unimplemented (size 0) and non-existant registers.  */
1592
 
1593
static int
1594
cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1595
{
1596
  return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1597
          || (cris_register_size (gdbarch, regno) == 0));
1598
}
1599
 
1600
/* Nonzero if regno should not be written to the target, for various
1601
   reasons.  */
1602
 
1603
static int
1604
cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1605
{
1606
  /* There are three kinds of registers we refuse to write to.
1607
     1. Those that not implemented.
1608
     2. Those that are read-only (depends on the processor mode).
1609
     3. Those registers to which a write has no effect.
1610
  */
1611
 
1612
  if (regno < 0
1613
      || regno >= gdbarch_num_regs (gdbarch)
1614
      || cris_register_size (gdbarch, regno) == 0)
1615
    /* Not implemented.  */
1616
    return 1;
1617
 
1618
  else if  (regno == VR_REGNUM)
1619
    /* Read-only.  */
1620
    return 1;
1621
 
1622
  else if  (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1623
    /* Writing has no effect.  */
1624
    return 1;
1625
 
1626
  /* IBR, BAR, BRP and IRP are read-only in user mode.  Let the debug
1627
     agent decide whether they are writable.  */
1628
 
1629
  return 0;
1630
}
1631
 
1632
/* Nonzero if regno should not be fetched from the target.  This is the case
1633
   for unimplemented (size 0) and non-existant registers.  */
1634
 
1635
static int
1636
crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1637
{
1638
  return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1639
          || (cris_register_size (gdbarch, regno) == 0));
1640
}
1641
 
1642
/* Nonzero if regno should not be written to the target, for various
1643
   reasons.  */
1644
 
1645
static int
1646
crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1647
{
1648
  /* There are three kinds of registers we refuse to write to.
1649
     1. Those that not implemented.
1650
     2. Those that are read-only (depends on the processor mode).
1651
     3. Those registers to which a write has no effect.
1652
  */
1653
 
1654
  if (regno < 0
1655
      || regno >= gdbarch_num_regs (gdbarch)
1656
      || cris_register_size (gdbarch, regno) == 0)
1657
    /* Not implemented.  */
1658
    return 1;
1659
 
1660
  else if  (regno == VR_REGNUM)
1661
    /* Read-only.  */
1662
    return 1;
1663
 
1664
  else if  (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1665
    /* Writing has no effect.  */
1666
    return 1;
1667
 
1668
  /* Many special registers are read-only in user mode.  Let the debug
1669
     agent decide whether they are writable.  */
1670
 
1671
  return 0;
1672
}
1673
 
1674
/* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1675
   of data in register regno.  */
1676
 
1677
static struct type *
1678
cris_register_type (struct gdbarch *gdbarch, int regno)
1679
{
1680
  if (regno == gdbarch_pc_regnum (gdbarch))
1681
    return builtin_type_void_func_ptr;
1682
  else if (regno == gdbarch_sp_regnum (gdbarch)
1683
           || regno == CRIS_FP_REGNUM)
1684
    return builtin_type_void_data_ptr;
1685
  else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1686
           || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1687
    /* Note: R8 taken care of previous clause.  */
1688
    return builtin_type_uint32;
1689
  else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1690
      return builtin_type_uint16;
1691
  else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1692
      return builtin_type_uint8;
1693
  else
1694
      /* Invalid (unimplemented) register.  */
1695
      return builtin_type_int0;
1696
}
1697
 
1698
static struct type *
1699
crisv32_register_type (struct gdbarch *gdbarch, int regno)
1700
{
1701
  if (regno == gdbarch_pc_regnum (gdbarch))
1702
    return builtin_type_void_func_ptr;
1703
  else if (regno == gdbarch_sp_regnum (gdbarch)
1704
           || regno == CRIS_FP_REGNUM)
1705
    return builtin_type_void_data_ptr;
1706
  else if ((regno >= 0 && regno <= ACR_REGNUM)
1707
           || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1708
           || (regno == PID_REGNUM)
1709
           || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1710
    /* Note: R8 and SP taken care of by previous clause.  */
1711
    return builtin_type_uint32;
1712
  else if (regno == WZ_REGNUM)
1713
      return builtin_type_uint16;
1714
  else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1715
      return builtin_type_uint8;
1716
  else
1717
    {
1718
      /* Invalid (unimplemented) register.  Should not happen as there are
1719
         no unimplemented CRISv32 registers.  */
1720
      warning (_("crisv32_register_type: unknown regno %d"), regno);
1721
      return builtin_type_int0;
1722
    }
1723
}
1724
 
1725
/* Stores a function return value of type type, where valbuf is the address
1726
   of the value to be stored.  */
1727
 
1728
/* In the CRIS ABI, R10 and R11 are used to store return values.  */
1729
 
1730
static void
1731
cris_store_return_value (struct type *type, struct regcache *regcache,
1732
                         const void *valbuf)
1733
{
1734
  ULONGEST val;
1735
  int len = TYPE_LENGTH (type);
1736
 
1737
  if (len <= 4)
1738
    {
1739
      /* Put the return value in R10.  */
1740
      val = extract_unsigned_integer (valbuf, len);
1741
      regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1742
    }
1743
  else if (len <= 8)
1744
    {
1745
      /* Put the return value in R10 and R11.  */
1746
      val = extract_unsigned_integer (valbuf, 4);
1747
      regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1748
      val = extract_unsigned_integer ((char *)valbuf + 4, len - 4);
1749
      regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1750
    }
1751
  else
1752
    error (_("cris_store_return_value: type length too large."));
1753
}
1754
 
1755
/* Return the name of register regno as a string. Return NULL for an invalid or
1756
   unimplemented register.  */
1757
 
1758
static const char *
1759
cris_special_register_name (int regno)
1760
{
1761
  int spec_regno;
1762
  int i;
1763
 
1764
  /* Special register (R16 - R31).  cris_spec_regs is zero-based.
1765
     Adjust regno accordingly.  */
1766
  spec_regno = regno - NUM_GENREGS;
1767
 
1768
  /* Assume nothing about the layout of the cris_spec_regs struct
1769
     when searching.  */
1770
  for (i = 0; cris_spec_regs[i].name != NULL; i++)
1771
    {
1772
      if (cris_spec_regs[i].number == spec_regno
1773
          && cris_spec_reg_applicable (cris_spec_regs[i]))
1774
        /* Go with the first applicable register.  */
1775
        return cris_spec_regs[i].name;
1776
    }
1777
  /* Special register not applicable to this CRIS version.  */
1778
  return NULL;
1779
}
1780
 
1781
static const char *
1782
cris_register_name (struct gdbarch *gdbarch, int regno)
1783
{
1784
  static char *cris_genreg_names[] =
1785
  { "r0",  "r1",  "r2",  "r3", \
1786
    "r4",  "r5",  "r6",  "r7", \
1787
    "r8",  "r9",  "r10", "r11", \
1788
    "r12", "r13", "sp",  "pc" };
1789
 
1790
  if (regno >= 0 && regno < NUM_GENREGS)
1791
    {
1792
      /* General register.  */
1793
      return cris_genreg_names[regno];
1794
    }
1795
  else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1796
    {
1797
      return cris_special_register_name (regno);
1798
    }
1799
  else
1800
    {
1801
      /* Invalid register.  */
1802
      return NULL;
1803
    }
1804
}
1805
 
1806
static const char *
1807
crisv32_register_name (struct gdbarch *gdbarch, int regno)
1808
{
1809
  static char *crisv32_genreg_names[] =
1810
    { "r0",  "r1",  "r2",  "r3", \
1811
      "r4",  "r5",  "r6",  "r7", \
1812
      "r8",  "r9",  "r10", "r11", \
1813
      "r12", "r13", "sp",  "acr"
1814
    };
1815
 
1816
  static char *crisv32_sreg_names[] =
1817
    { "s0",  "s1",  "s2",  "s3", \
1818
      "s4",  "s5",  "s6",  "s7", \
1819
      "s8",  "s9",  "s10", "s11", \
1820
      "s12", "s13", "s14",  "s15"
1821
    };
1822
 
1823
  if (regno >= 0 && regno < NUM_GENREGS)
1824
    {
1825
      /* General register.  */
1826
      return crisv32_genreg_names[regno];
1827
    }
1828
  else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1829
    {
1830
      return cris_special_register_name (regno);
1831
    }
1832
  else if (regno == gdbarch_pc_regnum (gdbarch))
1833
    {
1834
      return "pc";
1835
    }
1836
  else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1837
    {
1838
      return crisv32_sreg_names[regno - S0_REGNUM];
1839
    }
1840
  else
1841
    {
1842
      /* Invalid register.  */
1843
      return NULL;
1844
    }
1845
}
1846
 
1847
/* Convert DWARF register number REG to the appropriate register
1848
   number used by GDB.  */
1849
 
1850
static int
1851
cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1852
{
1853
  /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1854
     numbering, MOF is 18).
1855
     Adapted from gcc/config/cris/cris.h.  */
1856
  static int cris_dwarf_regmap[] = {
1857
    0,  1,  2,  3,
1858
    4,  5,  6,  7,
1859
    8,  9,  10, 11,
1860
    12, 13, 14, 15,
1861
    27, -1, -1, -1,
1862
    -1, -1, -1, 23,
1863
    -1, -1, -1, 27,
1864
    -1, -1, -1, -1
1865
  };
1866
  int regnum = -1;
1867
 
1868
  if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1869
    regnum = cris_dwarf_regmap[reg];
1870
 
1871
  if (regnum == -1)
1872
    warning (_("Unmapped DWARF Register #%d encountered."), reg);
1873
 
1874
  return regnum;
1875
}
1876
 
1877
/* DWARF-2 frame support.  */
1878
 
1879
static void
1880
cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1881
                            struct dwarf2_frame_state_reg *reg,
1882
                            struct frame_info *next_frame)
1883
{
1884
  /* The return address column.  */
1885
  if (regnum == gdbarch_pc_regnum (gdbarch))
1886
    reg->how = DWARF2_FRAME_REG_RA;
1887
 
1888
  /* The call frame address.  */
1889
  else if (regnum == gdbarch_sp_regnum (gdbarch))
1890
    reg->how = DWARF2_FRAME_REG_CFA;
1891
}
1892
 
1893
/* Extract from an array regbuf containing the raw register state a function
1894
   return value of type type, and copy that, in virtual format, into
1895
   valbuf.  */
1896
 
1897
/* In the CRIS ABI, R10 and R11 are used to store return values.  */
1898
 
1899
static void
1900
cris_extract_return_value (struct type *type, struct regcache *regcache,
1901
                           void *valbuf)
1902
{
1903
  ULONGEST val;
1904
  int len = TYPE_LENGTH (type);
1905
 
1906
  if (len <= 4)
1907
    {
1908
      /* Get the return value from R10.  */
1909
      regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1910
      store_unsigned_integer (valbuf, len, val);
1911
    }
1912
  else if (len <= 8)
1913
    {
1914
      /* Get the return value from R10 and R11.  */
1915
      regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1916
      store_unsigned_integer (valbuf, 4, val);
1917
      regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1918
      store_unsigned_integer ((char *)valbuf + 4, len - 4, val);
1919
    }
1920
  else
1921
    error (_("cris_extract_return_value: type length too large"));
1922
}
1923
 
1924
/* Handle the CRIS return value convention.  */
1925
 
1926
static enum return_value_convention
1927
cris_return_value (struct gdbarch *gdbarch, struct type *type,
1928
                   struct regcache *regcache, gdb_byte *readbuf,
1929
                   const gdb_byte *writebuf)
1930
{
1931
  if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1932
      || TYPE_CODE (type) == TYPE_CODE_UNION
1933
      || TYPE_LENGTH (type) > 8)
1934
    /* Structs, unions, and anything larger than 8 bytes (2 registers)
1935
       goes on the stack.  */
1936
    return RETURN_VALUE_STRUCT_CONVENTION;
1937
 
1938
  if (readbuf)
1939
    cris_extract_return_value (type, regcache, readbuf);
1940
  if (writebuf)
1941
    cris_store_return_value (type, regcache, writebuf);
1942
 
1943
  return RETURN_VALUE_REGISTER_CONVENTION;
1944
}
1945
 
1946
/* Calculates a value that measures how good inst_args constraints an
1947
   instruction.  It stems from cris_constraint, found in cris-dis.c.  */
1948
 
1949
static int
1950
constraint (unsigned int insn, const signed char *inst_args,
1951
            inst_env_type *inst_env)
1952
{
1953
  int retval = 0;
1954
  int tmp, i;
1955
 
1956
  const char *s = inst_args;
1957
 
1958
  for (; *s; s++)
1959
    switch (*s)
1960
      {
1961
      case 'm':
1962
        if ((insn & 0x30) == 0x30)
1963
          return -1;
1964
        break;
1965
 
1966
      case 'S':
1967
        /* A prefix operand.  */
1968
        if (inst_env->prefix_found)
1969
          break;
1970
        else
1971
          return -1;
1972
 
1973
      case 'B':
1974
        /* A "push" prefix.  (This check was REMOVED by san 970921.)  Check for
1975
           valid "push" size.  In case of special register, it may be != 4.  */
1976
        if (inst_env->prefix_found)
1977
          break;
1978
        else
1979
          return -1;
1980
 
1981
      case 'D':
1982
        retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1983
        if (!retval)
1984
          return -1;
1985
        else
1986
          retval += 4;
1987
        break;
1988
 
1989
      case 'P':
1990
        tmp = (insn >> 0xC) & 0xF;
1991
 
1992
        for (i = 0; cris_spec_regs[i].name != NULL; i++)
1993
          {
1994
            /* Since we match four bits, we will give a value of
1995
               4 - 1 = 3 in a match.  If there is a corresponding
1996
               exact match of a special register in another pattern, it
1997
               will get a value of 4, which will be higher.  This should
1998
               be correct in that an exact pattern would match better that
1999
               a general pattern.
2000
               Note that there is a reason for not returning zero; the
2001
               pattern for "clear" is partly  matched in the bit-pattern
2002
               (the two lower bits must be zero), while the bit-pattern
2003
               for a move from a special register is matched in the
2004
               register constraint.
2005
               This also means we will will have a race condition if
2006
               there is a partly match in three bits in the bit pattern.  */
2007
            if (tmp == cris_spec_regs[i].number)
2008
              {
2009
                retval += 3;
2010
                break;
2011
              }
2012
          }
2013
 
2014
        if (cris_spec_regs[i].name == NULL)
2015
          return -1;
2016
        break;
2017
      }
2018
  return retval;
2019
}
2020
 
2021
/* Returns the number of bits set in the variable value.  */
2022
 
2023
static int
2024
number_of_bits (unsigned int value)
2025
{
2026
  int number_of_bits = 0;
2027
 
2028
  while (value != 0)
2029
    {
2030
      number_of_bits += 1;
2031
      value &= (value - 1);
2032
    }
2033
  return number_of_bits;
2034
}
2035
 
2036
/* Finds the address that should contain the single step breakpoint(s).
2037
   It stems from code in cris-dis.c.  */
2038
 
2039
static int
2040
find_cris_op (unsigned short insn, inst_env_type *inst_env)
2041
{
2042
  int i;
2043
  int max_level_of_match = -1;
2044
  int max_matched = -1;
2045
  int level_of_match;
2046
 
2047
  for (i = 0; cris_opcodes[i].name != NULL; i++)
2048
    {
2049
      if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
2050
          && ((cris_opcodes[i].lose & insn) == 0)
2051
          /* Only CRISv10 instructions, please.  */
2052
          && (cris_opcodes[i].applicable_version != cris_ver_v32p))
2053
        {
2054
          level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
2055
          if (level_of_match >= 0)
2056
            {
2057
              level_of_match +=
2058
                number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
2059
              if (level_of_match > max_level_of_match)
2060
                {
2061
                  max_matched = i;
2062
                  max_level_of_match = level_of_match;
2063
                  if (level_of_match == 16)
2064
                    {
2065
                      /* All bits matched, cannot find better.  */
2066
                      break;
2067
                    }
2068
                }
2069
            }
2070
        }
2071
    }
2072
  return max_matched;
2073
}
2074
 
2075
/* Attempts to find single-step breakpoints.  Returns -1 on failure which is
2076
   actually an internal error.  */
2077
 
2078
static int
2079
find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2080
{
2081
  int i;
2082
  int offset;
2083
  unsigned short insn;
2084
  struct gdbarch *gdbarch = get_frame_arch (frame);
2085
 
2086
  /* Create a local register image and set the initial state.  */
2087
  for (i = 0; i < NUM_GENREGS; i++)
2088
    {
2089
      inst_env->reg[i] =
2090
        (unsigned long) get_frame_register_unsigned (frame, i);
2091
    }
2092
  offset = NUM_GENREGS;
2093
  for (i = 0; i < NUM_SPECREGS; i++)
2094
    {
2095
      inst_env->preg[i] =
2096
        (unsigned long) get_frame_register_unsigned (frame, offset + i);
2097
    }
2098
  inst_env->branch_found = 0;
2099
  inst_env->slot_needed = 0;
2100
  inst_env->delay_slot_pc_active = 0;
2101
  inst_env->prefix_found = 0;
2102
  inst_env->invalid = 0;
2103
  inst_env->xflag_found = 0;
2104
  inst_env->disable_interrupt = 0;
2105
 
2106
  /* Look for a step target.  */
2107
  do
2108
    {
2109
      /* Read an instruction from the client.  */
2110
      insn = read_memory_unsigned_integer
2111
             (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2);
2112
 
2113
      /* If the instruction is not in a delay slot the new content of the
2114
         PC is [PC] + 2.  If the instruction is in a delay slot it is not
2115
         that simple.  Since a instruction in a delay slot cannot change
2116
         the content of the PC, it does not matter what value PC will have.
2117
         Just make sure it is a valid instruction.  */
2118
      if (!inst_env->delay_slot_pc_active)
2119
        {
2120
          inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2121
        }
2122
      else
2123
        {
2124
          inst_env->delay_slot_pc_active = 0;
2125
          inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2126
            = inst_env->delay_slot_pc;
2127
        }
2128
      /* Analyse the present instruction.  */
2129
      i = find_cris_op (insn, inst_env);
2130
      if (i == -1)
2131
        {
2132
          inst_env->invalid = 1;
2133
        }
2134
      else
2135
        {
2136
          cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2137
        }
2138
    } while (!inst_env->invalid
2139
             && (inst_env->prefix_found || inst_env->xflag_found
2140
                 || inst_env->slot_needed));
2141
  return i;
2142
}
2143
 
2144
/* There is no hardware single-step support.  The function find_step_target
2145
   digs through the opcodes in order to find all possible targets.
2146
   Either one ordinary target or two targets for branches may be found.  */
2147
 
2148
static int
2149
cris_software_single_step (struct frame_info *frame)
2150
{
2151
  inst_env_type inst_env;
2152
 
2153
  /* Analyse the present instruction environment and insert
2154
     breakpoints.  */
2155
  int status = find_step_target (frame, &inst_env);
2156
  if (status == -1)
2157
    {
2158
      /* Could not find a target.  Things are likely to go downhill
2159
         from here.  */
2160
      warning (_("CRIS software single step could not find a step target."));
2161
    }
2162
  else
2163
    {
2164
      /* Insert at most two breakpoints.  One for the next PC content
2165
         and possibly another one for a branch, jump, etc.  */
2166
      CORE_ADDR next_pc =
2167
        (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (get_frame_arch (frame))];
2168
      insert_single_step_breakpoint (next_pc);
2169
      if (inst_env.branch_found
2170
          && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2171
        {
2172
          CORE_ADDR branch_target_address
2173
                = (CORE_ADDR) inst_env.branch_break_address;
2174
          insert_single_step_breakpoint (branch_target_address);
2175
        }
2176
    }
2177
 
2178
  return 1;
2179
}
2180
 
2181
/* Calculates the prefix value for quick offset addressing mode.  */
2182
 
2183
static void
2184
quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2185
{
2186
  /* It's invalid to be in a delay slot.  You can't have a prefix to this
2187
     instruction (not 100% sure).  */
2188
  if (inst_env->slot_needed || inst_env->prefix_found)
2189
    {
2190
      inst_env->invalid = 1;
2191
      return;
2192
    }
2193
 
2194
  inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2195
  inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2196
 
2197
  /* A prefix doesn't change the xflag_found.  But the rest of the flags
2198
     need updating.  */
2199
  inst_env->slot_needed = 0;
2200
  inst_env->prefix_found = 1;
2201
}
2202
 
2203
/* Updates the autoincrement register.  The size of the increment is derived
2204
   from the size of the operation.  The PC is always kept aligned on even
2205
   word addresses.  */
2206
 
2207
static void
2208
process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2209
{
2210
  if (size == INST_BYTE_SIZE)
2211
    {
2212
      inst_env->reg[cris_get_operand1 (inst)] += 1;
2213
 
2214
      /* The PC must be word aligned, so increase the PC with one
2215
         word even if the size is byte.  */
2216
      if (cris_get_operand1 (inst) == REG_PC)
2217
        {
2218
          inst_env->reg[REG_PC] += 1;
2219
        }
2220
    }
2221
  else if (size == INST_WORD_SIZE)
2222
    {
2223
      inst_env->reg[cris_get_operand1 (inst)] += 2;
2224
    }
2225
  else if (size == INST_DWORD_SIZE)
2226
    {
2227
      inst_env->reg[cris_get_operand1 (inst)] += 4;
2228
    }
2229
  else
2230
    {
2231
      /* Invalid size.  */
2232
      inst_env->invalid = 1;
2233
    }
2234
}
2235
 
2236
/* Just a forward declaration.  */
2237
 
2238
static unsigned long get_data_from_address (unsigned short *inst,
2239
                                            CORE_ADDR address);
2240
 
2241
/* Calculates the prefix value for the general case of offset addressing
2242
   mode.  */
2243
 
2244
static void
2245
bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2246
{
2247
 
2248
  long offset;
2249
 
2250
  /* It's invalid to be in a delay slot.  */
2251
  if (inst_env->slot_needed || inst_env->prefix_found)
2252
    {
2253
      inst_env->invalid = 1;
2254
      return;
2255
    }
2256
 
2257
  /* The calculation of prefix_value used to be after process_autoincrement,
2258
     but that fails for an instruction such as jsr [$r0+12] which is encoded
2259
     as 5f0d 0c00 30b9 when compiled with -fpic.  Since PC is operand1 it
2260
     mustn't be incremented until we have read it and what it points at.  */
2261
  inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2262
 
2263
  /* The offset is an indirection of the contents of the operand1 register.  */
2264
  inst_env->prefix_value +=
2265
    get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]);
2266
 
2267
  if (cris_get_mode (inst) == AUTOINC_MODE)
2268
    {
2269
      process_autoincrement (cris_get_size (inst), inst, inst_env);
2270
    }
2271
 
2272
  /* A prefix doesn't change the xflag_found.  But the rest of the flags
2273
     need updating.  */
2274
  inst_env->slot_needed = 0;
2275
  inst_env->prefix_found = 1;
2276
}
2277
 
2278
/* Calculates the prefix value for the index addressing mode.  */
2279
 
2280
static void
2281
biap_prefix (unsigned short inst, inst_env_type *inst_env)
2282
{
2283
  /* It's invalid to be in a delay slot.  I can't see that it's possible to
2284
     have a prefix to this instruction.  So I will treat this as invalid.  */
2285
  if (inst_env->slot_needed || inst_env->prefix_found)
2286
    {
2287
      inst_env->invalid = 1;
2288
      return;
2289
    }
2290
 
2291
  inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2292
 
2293
  /* The offset is the operand2 value shifted the size of the instruction
2294
     to the left.  */
2295
  inst_env->prefix_value +=
2296
    inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2297
 
2298
  /* If the PC is operand1 (base) the address used is the address after
2299
     the main instruction, i.e. address + 2 (the PC is already compensated
2300
     for the prefix operation).  */
2301
  if (cris_get_operand1 (inst) == REG_PC)
2302
    {
2303
      inst_env->prefix_value += 2;
2304
    }
2305
 
2306
  /* A prefix doesn't change the xflag_found.  But the rest of the flags
2307
     need updating.  */
2308
  inst_env->slot_needed = 0;
2309
  inst_env->xflag_found = 0;
2310
  inst_env->prefix_found = 1;
2311
}
2312
 
2313
/* Calculates the prefix value for the double indirect addressing mode.  */
2314
 
2315
static void
2316
dip_prefix (unsigned short inst, inst_env_type *inst_env)
2317
{
2318
 
2319
  CORE_ADDR address;
2320
 
2321
  /* It's invalid to be in a delay slot.  */
2322
  if (inst_env->slot_needed || inst_env->prefix_found)
2323
    {
2324
      inst_env->invalid = 1;
2325
      return;
2326
    }
2327
 
2328
  /* The prefix value is one dereference of the contents of the operand1
2329
     register.  */
2330
  address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2331
  inst_env->prefix_value = read_memory_unsigned_integer (address, 4);
2332
 
2333
  /* Check if the mode is autoincrement.  */
2334
  if (cris_get_mode (inst) == AUTOINC_MODE)
2335
    {
2336
      inst_env->reg[cris_get_operand1 (inst)] += 4;
2337
    }
2338
 
2339
  /* A prefix doesn't change the xflag_found.  But the rest of the flags
2340
     need updating.  */
2341
  inst_env->slot_needed = 0;
2342
  inst_env->xflag_found = 0;
2343
  inst_env->prefix_found = 1;
2344
}
2345
 
2346
/* Finds the destination for a branch with 8-bits offset.  */
2347
 
2348
static void
2349
eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2350
{
2351
 
2352
  short offset;
2353
 
2354
  /* If we have a prefix or are in a delay slot it's bad.  */
2355
  if (inst_env->slot_needed || inst_env->prefix_found)
2356
    {
2357
      inst_env->invalid = 1;
2358
      return;
2359
    }
2360
 
2361
  /* We have a branch, find out where the branch will land.  */
2362
  offset = cris_get_branch_short_offset (inst);
2363
 
2364
  /* Check if the offset is signed.  */
2365
  if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2366
    {
2367
      offset |= 0xFF00;
2368
    }
2369
 
2370
  /* The offset ends with the sign bit, set it to zero.  The address
2371
     should always be word aligned.  */
2372
  offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2373
 
2374
  inst_env->branch_found = 1;
2375
  inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2376
 
2377
  inst_env->slot_needed = 1;
2378
  inst_env->prefix_found = 0;
2379
  inst_env->xflag_found = 0;
2380
  inst_env->disable_interrupt = 1;
2381
}
2382
 
2383
/* Finds the destination for a branch with 16-bits offset.  */
2384
 
2385
static void
2386
sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2387
{
2388
  short offset;
2389
 
2390
  /* If we have a prefix or is in a delay slot it's bad.  */
2391
  if (inst_env->slot_needed || inst_env->prefix_found)
2392
    {
2393
      inst_env->invalid = 1;
2394
      return;
2395
    }
2396
 
2397
  /* We have a branch, find out the offset for the branch.  */
2398
  offset = read_memory_integer (inst_env->reg[REG_PC], 2);
2399
 
2400
  /* The instruction is one word longer than normal, so add one word
2401
     to the PC.  */
2402
  inst_env->reg[REG_PC] += 2;
2403
 
2404
  inst_env->branch_found = 1;
2405
  inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2406
 
2407
 
2408
  inst_env->slot_needed = 1;
2409
  inst_env->prefix_found = 0;
2410
  inst_env->xflag_found = 0;
2411
  inst_env->disable_interrupt = 1;
2412
}
2413
 
2414
/* Handles the ABS instruction.  */
2415
 
2416
static void
2417
abs_op (unsigned short inst, inst_env_type *inst_env)
2418
{
2419
 
2420
  long value;
2421
 
2422
  /* ABS can't have a prefix, so it's bad if it does.  */
2423
  if (inst_env->prefix_found)
2424
    {
2425
      inst_env->invalid = 1;
2426
      return;
2427
    }
2428
 
2429
  /* Check if the operation affects the PC.  */
2430
  if (cris_get_operand2 (inst) == REG_PC)
2431
    {
2432
 
2433
      /* It's invalid to change to the PC if we are in a delay slot.  */
2434
      if (inst_env->slot_needed)
2435
        {
2436
          inst_env->invalid = 1;
2437
          return;
2438
        }
2439
 
2440
      value = (long) inst_env->reg[REG_PC];
2441
 
2442
      /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK.  */
2443
      if (value != SIGNED_DWORD_MASK)
2444
        {
2445
          value = -value;
2446
          inst_env->reg[REG_PC] = (long) value;
2447
        }
2448
    }
2449
 
2450
  inst_env->slot_needed = 0;
2451
  inst_env->prefix_found = 0;
2452
  inst_env->xflag_found = 0;
2453
  inst_env->disable_interrupt = 0;
2454
}
2455
 
2456
/* Handles the ADDI instruction.  */
2457
 
2458
static void
2459
addi_op (unsigned short inst, inst_env_type *inst_env)
2460
{
2461
  /* It's invalid to have the PC as base register.  And ADDI can't have
2462
     a prefix.  */
2463
  if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2464
    {
2465
      inst_env->invalid = 1;
2466
      return;
2467
    }
2468
 
2469
  inst_env->slot_needed = 0;
2470
  inst_env->prefix_found = 0;
2471
  inst_env->xflag_found = 0;
2472
  inst_env->disable_interrupt = 0;
2473
}
2474
 
2475
/* Handles the ASR instruction.  */
2476
 
2477
static void
2478
asr_op (unsigned short inst, inst_env_type *inst_env)
2479
{
2480
  int shift_steps;
2481
  unsigned long value;
2482
  unsigned long signed_extend_mask = 0;
2483
 
2484
  /* ASR can't have a prefix, so check that it doesn't.  */
2485
  if (inst_env->prefix_found)
2486
    {
2487
      inst_env->invalid = 1;
2488
      return;
2489
    }
2490
 
2491
  /* Check if the PC is the target register.  */
2492
  if (cris_get_operand2 (inst) == REG_PC)
2493
    {
2494
      /* It's invalid to change the PC in a delay slot.  */
2495
      if (inst_env->slot_needed)
2496
        {
2497
          inst_env->invalid = 1;
2498
          return;
2499
        }
2500
      /* Get the number of bits to shift.  */
2501
      shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2502
      value = inst_env->reg[REG_PC];
2503
 
2504
      /* Find out how many bits the operation should apply to.  */
2505
      if (cris_get_size (inst) == INST_BYTE_SIZE)
2506
        {
2507
          if (value & SIGNED_BYTE_MASK)
2508
            {
2509
              signed_extend_mask = 0xFF;
2510
              signed_extend_mask = signed_extend_mask >> shift_steps;
2511
              signed_extend_mask = ~signed_extend_mask;
2512
            }
2513
          value = value >> shift_steps;
2514
          value |= signed_extend_mask;
2515
          value &= 0xFF;
2516
          inst_env->reg[REG_PC] &= 0xFFFFFF00;
2517
          inst_env->reg[REG_PC] |= value;
2518
        }
2519
      else if (cris_get_size (inst) == INST_WORD_SIZE)
2520
        {
2521
          if (value & SIGNED_WORD_MASK)
2522
            {
2523
              signed_extend_mask = 0xFFFF;
2524
              signed_extend_mask = signed_extend_mask >> shift_steps;
2525
              signed_extend_mask = ~signed_extend_mask;
2526
            }
2527
          value = value >> shift_steps;
2528
          value |= signed_extend_mask;
2529
          value &= 0xFFFF;
2530
          inst_env->reg[REG_PC] &= 0xFFFF0000;
2531
          inst_env->reg[REG_PC] |= value;
2532
        }
2533
      else if (cris_get_size (inst) == INST_DWORD_SIZE)
2534
        {
2535
          if (value & SIGNED_DWORD_MASK)
2536
            {
2537
              signed_extend_mask = 0xFFFFFFFF;
2538
              signed_extend_mask = signed_extend_mask >> shift_steps;
2539
              signed_extend_mask = ~signed_extend_mask;
2540
            }
2541
          value = value >> shift_steps;
2542
          value |= signed_extend_mask;
2543
          inst_env->reg[REG_PC]  = value;
2544
        }
2545
    }
2546
  inst_env->slot_needed = 0;
2547
  inst_env->prefix_found = 0;
2548
  inst_env->xflag_found = 0;
2549
  inst_env->disable_interrupt = 0;
2550
}
2551
 
2552
/* Handles the ASRQ instruction.  */
2553
 
2554
static void
2555
asrq_op (unsigned short inst, inst_env_type *inst_env)
2556
{
2557
 
2558
  int shift_steps;
2559
  unsigned long value;
2560
  unsigned long signed_extend_mask = 0;
2561
 
2562
  /* ASRQ can't have a prefix, so check that it doesn't.  */
2563
  if (inst_env->prefix_found)
2564
    {
2565
      inst_env->invalid = 1;
2566
      return;
2567
    }
2568
 
2569
  /* Check if the PC is the target register.  */
2570
  if (cris_get_operand2 (inst) == REG_PC)
2571
    {
2572
 
2573
      /* It's invalid to change the PC in a delay slot.  */
2574
      if (inst_env->slot_needed)
2575
        {
2576
          inst_env->invalid = 1;
2577
          return;
2578
        }
2579
      /* The shift size is given as a 5 bit quick value, i.e. we don't
2580
         want the the sign bit of the quick value.  */
2581
      shift_steps = cris_get_asr_shift_steps (inst);
2582
      value = inst_env->reg[REG_PC];
2583
      if (value & SIGNED_DWORD_MASK)
2584
        {
2585
          signed_extend_mask = 0xFFFFFFFF;
2586
          signed_extend_mask = signed_extend_mask >> shift_steps;
2587
          signed_extend_mask = ~signed_extend_mask;
2588
        }
2589
      value = value >> shift_steps;
2590
      value |= signed_extend_mask;
2591
      inst_env->reg[REG_PC]  = value;
2592
    }
2593
  inst_env->slot_needed = 0;
2594
  inst_env->prefix_found = 0;
2595
  inst_env->xflag_found = 0;
2596
  inst_env->disable_interrupt = 0;
2597
}
2598
 
2599
/* Handles the AX, EI and SETF instruction.  */
2600
 
2601
static void
2602
ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2603
{
2604
  if (inst_env->prefix_found)
2605
    {
2606
      inst_env->invalid = 1;
2607
      return;
2608
    }
2609
  /* Check if the instruction is setting the X flag.  */
2610
  if (cris_is_xflag_bit_on (inst))
2611
    {
2612
      inst_env->xflag_found = 1;
2613
    }
2614
  else
2615
    {
2616
      inst_env->xflag_found = 0;
2617
    }
2618
  inst_env->slot_needed = 0;
2619
  inst_env->prefix_found = 0;
2620
  inst_env->disable_interrupt = 1;
2621
}
2622
 
2623
/* Checks if the instruction is in assign mode.  If so, it updates the assign
2624
   register.  Note that check_assign assumes that the caller has checked that
2625
   there is a prefix to this instruction.  The mode check depends on this.  */
2626
 
2627
static void
2628
check_assign (unsigned short inst, inst_env_type *inst_env)
2629
{
2630
  /* Check if it's an assign addressing mode.  */
2631
  if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2632
    {
2633
      /* Assign the prefix value to operand 1.  */
2634
      inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2635
    }
2636
}
2637
 
2638
/* Handles the 2-operand BOUND instruction.  */
2639
 
2640
static void
2641
two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2642
{
2643
  /* It's invalid to have the PC as the index operand.  */
2644
  if (cris_get_operand2 (inst) == REG_PC)
2645
    {
2646
      inst_env->invalid = 1;
2647
      return;
2648
    }
2649
  /* Check if we have a prefix.  */
2650
  if (inst_env->prefix_found)
2651
    {
2652
      check_assign (inst, inst_env);
2653
    }
2654
  /* Check if this is an autoincrement mode.  */
2655
  else if (cris_get_mode (inst) == AUTOINC_MODE)
2656
    {
2657
      /* It's invalid to change the PC in a delay slot.  */
2658
      if (inst_env->slot_needed)
2659
        {
2660
          inst_env->invalid = 1;
2661
          return;
2662
        }
2663
      process_autoincrement (cris_get_size (inst), inst, inst_env);
2664
    }
2665
  inst_env->slot_needed = 0;
2666
  inst_env->prefix_found = 0;
2667
  inst_env->xflag_found = 0;
2668
  inst_env->disable_interrupt = 0;
2669
}
2670
 
2671
/* Handles the 3-operand BOUND instruction.  */
2672
 
2673
static void
2674
three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2675
{
2676
  /* It's an error if we haven't got a prefix.  And it's also an error
2677
     if the PC is the destination register.  */
2678
  if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2679
    {
2680
      inst_env->invalid = 1;
2681
      return;
2682
    }
2683
  inst_env->slot_needed = 0;
2684
  inst_env->prefix_found = 0;
2685
  inst_env->xflag_found = 0;
2686
  inst_env->disable_interrupt = 0;
2687
}
2688
 
2689
/* Clears the status flags in inst_env.  */
2690
 
2691
static void
2692
btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2693
{
2694
  /* It's an error if we have got a prefix.  */
2695
  if (inst_env->prefix_found)
2696
    {
2697
      inst_env->invalid = 1;
2698
      return;
2699
    }
2700
 
2701
  inst_env->slot_needed = 0;
2702
  inst_env->prefix_found = 0;
2703
  inst_env->xflag_found = 0;
2704
  inst_env->disable_interrupt = 0;
2705
}
2706
 
2707
/* Clears the status flags in inst_env.  */
2708
 
2709
static void
2710
clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2711
{
2712
  /* It's an error if we have got a prefix.  */
2713
  if (inst_env->prefix_found)
2714
    {
2715
      inst_env->invalid = 1;
2716
      return;
2717
    }
2718
 
2719
  inst_env->slot_needed = 0;
2720
  inst_env->prefix_found = 0;
2721
  inst_env->xflag_found = 0;
2722
  inst_env->disable_interrupt = 1;
2723
}
2724
 
2725
/* Handles the CLEAR instruction if it's in register mode.  */
2726
 
2727
static void
2728
reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2729
{
2730
  /* Check if the target is the PC.  */
2731
  if (cris_get_operand2 (inst) == REG_PC)
2732
    {
2733
      /* The instruction will clear the instruction's size bits.  */
2734
      int clear_size = cris_get_clear_size (inst);
2735
      if (clear_size == INST_BYTE_SIZE)
2736
        {
2737
          inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2738
        }
2739
      if (clear_size == INST_WORD_SIZE)
2740
        {
2741
          inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2742
        }
2743
      if (clear_size == INST_DWORD_SIZE)
2744
        {
2745
          inst_env->delay_slot_pc = 0x0;
2746
        }
2747
      /* The jump will be delayed with one delay slot.  So we need a delay
2748
         slot.  */
2749
      inst_env->slot_needed = 1;
2750
      inst_env->delay_slot_pc_active = 1;
2751
    }
2752
  else
2753
    {
2754
      /* The PC will not change => no delay slot.  */
2755
      inst_env->slot_needed = 0;
2756
    }
2757
  inst_env->prefix_found = 0;
2758
  inst_env->xflag_found = 0;
2759
  inst_env->disable_interrupt = 0;
2760
}
2761
 
2762
/* Handles the TEST instruction if it's in register mode.  */
2763
 
2764
static void
2765
reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2766
{
2767
  /* It's an error if we have got a prefix.  */
2768
  if (inst_env->prefix_found)
2769
    {
2770
      inst_env->invalid = 1;
2771
      return;
2772
    }
2773
  inst_env->slot_needed = 0;
2774
  inst_env->prefix_found = 0;
2775
  inst_env->xflag_found = 0;
2776
  inst_env->disable_interrupt = 0;
2777
 
2778
}
2779
 
2780
/* Handles the CLEAR and TEST instruction if the instruction isn't
2781
   in register mode.  */
2782
 
2783
static void
2784
none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2785
{
2786
  /* Check if we are in a prefix mode.  */
2787
  if (inst_env->prefix_found)
2788
    {
2789
      /* The only way the PC can change is if this instruction is in
2790
         assign addressing mode.  */
2791
      check_assign (inst, inst_env);
2792
    }
2793
  /* Indirect mode can't change the PC so just check if the mode is
2794
     autoincrement.  */
2795
  else if (cris_get_mode (inst) == AUTOINC_MODE)
2796
    {
2797
      process_autoincrement (cris_get_size (inst), inst, inst_env);
2798
    }
2799
  inst_env->slot_needed = 0;
2800
  inst_env->prefix_found = 0;
2801
  inst_env->xflag_found = 0;
2802
  inst_env->disable_interrupt = 0;
2803
}
2804
 
2805
/* Checks that the PC isn't the destination register or the instructions has
2806
   a prefix.  */
2807
 
2808
static void
2809
dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2810
{
2811
  /* It's invalid to have the PC as the destination.  The instruction can't
2812
     have a prefix.  */
2813
  if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2814
    {
2815
      inst_env->invalid = 1;
2816
      return;
2817
    }
2818
 
2819
  inst_env->slot_needed = 0;
2820
  inst_env->prefix_found = 0;
2821
  inst_env->xflag_found = 0;
2822
  inst_env->disable_interrupt = 0;
2823
}
2824
 
2825
/* Checks that the instruction doesn't have a prefix.  */
2826
 
2827
static void
2828
break_op (unsigned short inst, inst_env_type *inst_env)
2829
{
2830
  /* The instruction can't have a prefix.  */
2831
  if (inst_env->prefix_found)
2832
    {
2833
      inst_env->invalid = 1;
2834
      return;
2835
    }
2836
 
2837
  inst_env->slot_needed = 0;
2838
  inst_env->prefix_found = 0;
2839
  inst_env->xflag_found = 0;
2840
  inst_env->disable_interrupt = 1;
2841
}
2842
 
2843
/* Checks that the PC isn't the destination register and that the instruction
2844
   doesn't have a prefix.  */
2845
 
2846
static void
2847
scc_op (unsigned short inst, inst_env_type *inst_env)
2848
{
2849
  /* It's invalid to have the PC as the destination.  The instruction can't
2850
     have a prefix.  */
2851
  if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2852
    {
2853
      inst_env->invalid = 1;
2854
      return;
2855
    }
2856
 
2857
  inst_env->slot_needed = 0;
2858
  inst_env->prefix_found = 0;
2859
  inst_env->xflag_found = 0;
2860
  inst_env->disable_interrupt = 1;
2861
}
2862
 
2863
/* Handles the register mode JUMP instruction.  */
2864
 
2865
static void
2866
reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2867
{
2868
  /* It's invalid to do a JUMP in a delay slot.  The mode is register, so
2869
     you can't have a prefix.  */
2870
  if ((inst_env->slot_needed) || (inst_env->prefix_found))
2871
    {
2872
      inst_env->invalid = 1;
2873
      return;
2874
    }
2875
 
2876
  /* Just change the PC.  */
2877
  inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2878
  inst_env->slot_needed = 0;
2879
  inst_env->prefix_found = 0;
2880
  inst_env->xflag_found = 0;
2881
  inst_env->disable_interrupt = 1;
2882
}
2883
 
2884
/* Handles the JUMP instruction for all modes except register.  */
2885
 
2886
static void
2887
none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2888
{
2889
  unsigned long newpc;
2890
  CORE_ADDR address;
2891
 
2892
  /* It's invalid to do a JUMP in a delay slot.  */
2893
  if (inst_env->slot_needed)
2894
    {
2895
      inst_env->invalid = 1;
2896
    }
2897
  else
2898
    {
2899
      /* Check if we have a prefix.  */
2900
      if (inst_env->prefix_found)
2901
        {
2902
          check_assign (inst, inst_env);
2903
 
2904
          /* Get the new value for the the PC.  */
2905
          newpc =
2906
            read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2907
                                          4);
2908
        }
2909
      else
2910
        {
2911
          /* Get the new value for the PC.  */
2912
          address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2913
          newpc = read_memory_unsigned_integer (address, 4);
2914
 
2915
          /* Check if we should increment a register.  */
2916
          if (cris_get_mode (inst) == AUTOINC_MODE)
2917
            {
2918
              inst_env->reg[cris_get_operand1 (inst)] += 4;
2919
            }
2920
        }
2921
      inst_env->reg[REG_PC] = newpc;
2922
    }
2923
  inst_env->slot_needed = 0;
2924
  inst_env->prefix_found = 0;
2925
  inst_env->xflag_found = 0;
2926
  inst_env->disable_interrupt = 1;
2927
}
2928
 
2929
/* Handles moves to special registers (aka P-register) for all modes.  */
2930
 
2931
static void
2932
move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2933
                 inst_env_type *inst_env)
2934
{
2935
  if (inst_env->prefix_found)
2936
    {
2937
      /* The instruction has a prefix that means we are only interested if
2938
         the instruction is in assign mode.  */
2939
      if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2940
        {
2941
          /* The prefix handles the problem if we are in a delay slot.  */
2942
          if (cris_get_operand1 (inst) == REG_PC)
2943
            {
2944
              /* Just take care of the assign.  */
2945
              check_assign (inst, inst_env);
2946
            }
2947
        }
2948
    }
2949
  else if (cris_get_mode (inst) == AUTOINC_MODE)
2950
    {
2951
      /* The instruction doesn't have a prefix, the only case left that we
2952
         are interested in is the autoincrement mode.  */
2953
      if (cris_get_operand1 (inst) == REG_PC)
2954
        {
2955
          /* If the PC is to be incremented it's invalid to be in a
2956
             delay slot.  */
2957
          if (inst_env->slot_needed)
2958
            {
2959
              inst_env->invalid = 1;
2960
              return;
2961
            }
2962
 
2963
          /* The increment depends on the size of the special register.  */
2964
          if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2965
            {
2966
              process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2967
            }
2968
          else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2969
            {
2970
              process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2971
            }
2972
          else
2973
            {
2974
              process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2975
            }
2976
        }
2977
    }
2978
  inst_env->slot_needed = 0;
2979
  inst_env->prefix_found = 0;
2980
  inst_env->xflag_found = 0;
2981
  inst_env->disable_interrupt = 1;
2982
}
2983
 
2984
/* Handles moves from special registers (aka P-register) for all modes
2985
   except register.  */
2986
 
2987
static void
2988
none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2989
                                 inst_env_type *inst_env)
2990
{
2991
  if (inst_env->prefix_found)
2992
    {
2993
      /* The instruction has a prefix that means we are only interested if
2994
         the instruction is in assign mode.  */
2995
      if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2996
        {
2997
          /* The prefix handles the problem if we are in a delay slot.  */
2998
          if (cris_get_operand1 (inst) == REG_PC)
2999
            {
3000
              /* Just take care of the assign.  */
3001
              check_assign (inst, inst_env);
3002
            }
3003
        }
3004
    }
3005
  /* The instruction doesn't have a prefix, the only case left that we
3006
     are interested in is the autoincrement mode.  */
3007
  else if (cris_get_mode (inst) == AUTOINC_MODE)
3008
    {
3009
      if (cris_get_operand1 (inst) == REG_PC)
3010
        {
3011
          /* If the PC is to be incremented it's invalid to be in a
3012
             delay slot.  */
3013
          if (inst_env->slot_needed)
3014
            {
3015
              inst_env->invalid = 1;
3016
              return;
3017
            }
3018
 
3019
          /* The increment depends on the size of the special register.  */
3020
          if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
3021
            {
3022
              process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
3023
            }
3024
          else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
3025
            {
3026
              process_autoincrement (INST_WORD_SIZE, inst, inst_env);
3027
            }
3028
          else
3029
            {
3030
              process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
3031
            }
3032
        }
3033
    }
3034
  inst_env->slot_needed = 0;
3035
  inst_env->prefix_found = 0;
3036
  inst_env->xflag_found = 0;
3037
  inst_env->disable_interrupt = 1;
3038
}
3039
 
3040
/* Handles moves from special registers (aka P-register) when the mode
3041
   is register.  */
3042
 
3043
static void
3044
reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
3045
{
3046
  /* Register mode move from special register can't have a prefix.  */
3047
  if (inst_env->prefix_found)
3048
    {
3049
      inst_env->invalid = 1;
3050
      return;
3051
    }
3052
 
3053
  if (cris_get_operand1 (inst) == REG_PC)
3054
    {
3055
      /* It's invalid to change the PC in a delay slot.  */
3056
      if (inst_env->slot_needed)
3057
        {
3058
          inst_env->invalid = 1;
3059
          return;
3060
        }
3061
      /* The destination is the PC, the jump will have a delay slot.  */
3062
      inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
3063
      inst_env->slot_needed = 1;
3064
      inst_env->delay_slot_pc_active = 1;
3065
    }
3066
  else
3067
    {
3068
      /* If the destination isn't PC, there will be no jump.  */
3069
      inst_env->slot_needed = 0;
3070
    }
3071
  inst_env->prefix_found = 0;
3072
  inst_env->xflag_found = 0;
3073
  inst_env->disable_interrupt = 1;
3074
}
3075
 
3076
/* Handles the MOVEM from memory to general register instruction.  */
3077
 
3078
static void
3079
move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3080
{
3081
  if (inst_env->prefix_found)
3082
    {
3083
      /* The prefix handles the problem if we are in a delay slot.  Is the
3084
         MOVEM instruction going to change the PC?  */
3085
      if (cris_get_operand2 (inst) >= REG_PC)
3086
        {
3087
          inst_env->reg[REG_PC] =
3088
            read_memory_unsigned_integer (inst_env->prefix_value, 4);
3089
        }
3090
      /* The assign value is the value after the increment.  Normally, the
3091
         assign value is the value before the increment.  */
3092
      if ((cris_get_operand1 (inst) == REG_PC)
3093
          && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3094
        {
3095
          inst_env->reg[REG_PC] = inst_env->prefix_value;
3096
          inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3097
        }
3098
    }
3099
  else
3100
    {
3101
      /* Is the MOVEM instruction going to change the PC?  */
3102
      if (cris_get_operand2 (inst) == REG_PC)
3103
        {
3104
          /* It's invalid to change the PC in a delay slot.  */
3105
          if (inst_env->slot_needed)
3106
            {
3107
              inst_env->invalid = 1;
3108
              return;
3109
            }
3110
          inst_env->reg[REG_PC] =
3111
            read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3112
                                          4);
3113
        }
3114
      /* The increment is not depending on the size, instead it's depending
3115
         on the number of registers loaded from memory.  */
3116
      if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3117
        {
3118
          /* It's invalid to change the PC in a delay slot.  */
3119
          if (inst_env->slot_needed)
3120
            {
3121
              inst_env->invalid = 1;
3122
              return;
3123
            }
3124
          inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3125
        }
3126
    }
3127
  inst_env->slot_needed = 0;
3128
  inst_env->prefix_found = 0;
3129
  inst_env->xflag_found = 0;
3130
  inst_env->disable_interrupt = 0;
3131
}
3132
 
3133
/* Handles the MOVEM to memory from general register instruction.  */
3134
 
3135
static void
3136
move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3137
{
3138
  if (inst_env->prefix_found)
3139
    {
3140
      /* The assign value is the value after the increment.  Normally, the
3141
         assign value is the value before the increment.  */
3142
      if ((cris_get_operand1 (inst) == REG_PC) &&
3143
          (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3144
        {
3145
          /* The prefix handles the problem if we are in a delay slot.  */
3146
          inst_env->reg[REG_PC] = inst_env->prefix_value;
3147
          inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3148
        }
3149
    }
3150
  else
3151
    {
3152
      /* The increment is not depending on the size, instead it's depending
3153
         on the number of registers loaded to memory.  */
3154
      if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3155
        {
3156
          /* It's invalid to change the PC in a delay slot.  */
3157
          if (inst_env->slot_needed)
3158
            {
3159
              inst_env->invalid = 1;
3160
              return;
3161
            }
3162
          inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3163
        }
3164
    }
3165
  inst_env->slot_needed = 0;
3166
  inst_env->prefix_found = 0;
3167
  inst_env->xflag_found = 0;
3168
  inst_env->disable_interrupt = 0;
3169
}
3170
 
3171
/* Handles the intructions that's not yet implemented, by setting
3172
   inst_env->invalid to true.  */
3173
 
3174
static void
3175
not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3176
{
3177
  inst_env->invalid = 1;
3178
}
3179
 
3180
/* Handles the XOR instruction.  */
3181
 
3182
static void
3183
xor_op (unsigned short inst, inst_env_type *inst_env)
3184
{
3185
  /* XOR can't have a prefix.  */
3186
  if (inst_env->prefix_found)
3187
    {
3188
      inst_env->invalid = 1;
3189
      return;
3190
    }
3191
 
3192
  /* Check if the PC is the target.  */
3193
  if (cris_get_operand2 (inst) == REG_PC)
3194
    {
3195
      /* It's invalid to change the PC in a delay slot.  */
3196
      if (inst_env->slot_needed)
3197
        {
3198
          inst_env->invalid = 1;
3199
          return;
3200
        }
3201
      inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3202
    }
3203
  inst_env->slot_needed = 0;
3204
  inst_env->prefix_found = 0;
3205
  inst_env->xflag_found = 0;
3206
  inst_env->disable_interrupt = 0;
3207
}
3208
 
3209
/* Handles the MULS instruction.  */
3210
 
3211
static void
3212
muls_op (unsigned short inst, inst_env_type *inst_env)
3213
{
3214
  /* MULS/U can't have a prefix.  */
3215
  if (inst_env->prefix_found)
3216
    {
3217
      inst_env->invalid = 1;
3218
      return;
3219
    }
3220
 
3221
  /* Consider it invalid if the PC is the target.  */
3222
  if (cris_get_operand2 (inst) == REG_PC)
3223
    {
3224
      inst_env->invalid = 1;
3225
      return;
3226
    }
3227
  inst_env->slot_needed = 0;
3228
  inst_env->prefix_found = 0;
3229
  inst_env->xflag_found = 0;
3230
  inst_env->disable_interrupt = 0;
3231
}
3232
 
3233
/* Handles the MULU instruction.  */
3234
 
3235
static void
3236
mulu_op (unsigned short inst, inst_env_type *inst_env)
3237
{
3238
  /* MULS/U can't have a prefix.  */
3239
  if (inst_env->prefix_found)
3240
    {
3241
      inst_env->invalid = 1;
3242
      return;
3243
    }
3244
 
3245
  /* Consider it invalid if the PC is the target.  */
3246
  if (cris_get_operand2 (inst) == REG_PC)
3247
    {
3248
      inst_env->invalid = 1;
3249
      return;
3250
    }
3251
  inst_env->slot_needed = 0;
3252
  inst_env->prefix_found = 0;
3253
  inst_env->xflag_found = 0;
3254
  inst_env->disable_interrupt = 0;
3255
}
3256
 
3257
/* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3258
   The MOVE instruction is the move from source to register.  */
3259
 
3260
static void
3261
add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3262
                                unsigned long source1, unsigned long source2)
3263
{
3264
  unsigned long pc_mask;
3265
  unsigned long operation_mask;
3266
 
3267
  /* Find out how many bits the operation should apply to.  */
3268
  if (cris_get_size (inst) == INST_BYTE_SIZE)
3269
    {
3270
      pc_mask = 0xFFFFFF00;
3271
      operation_mask = 0xFF;
3272
    }
3273
  else if (cris_get_size (inst) == INST_WORD_SIZE)
3274
    {
3275
      pc_mask = 0xFFFF0000;
3276
      operation_mask = 0xFFFF;
3277
    }
3278
  else if (cris_get_size (inst) == INST_DWORD_SIZE)
3279
    {
3280
      pc_mask = 0x0;
3281
      operation_mask = 0xFFFFFFFF;
3282
    }
3283
  else
3284
    {
3285
      /* The size is out of range.  */
3286
      inst_env->invalid = 1;
3287
      return;
3288
    }
3289
 
3290
  /* The instruction just works on uw_operation_mask bits.  */
3291
  source2 &= operation_mask;
3292
  source1 &= operation_mask;
3293
 
3294
  /* Now calculate the result.  The opcode's 3 first bits separates
3295
     the different actions.  */
3296
  switch (cris_get_opcode (inst) & 7)
3297
    {
3298
    case 0:  /* add */
3299
      source1 += source2;
3300
      break;
3301
 
3302
    case 1:  /* move */
3303
      source1 = source2;
3304
      break;
3305
 
3306
    case 2:  /* subtract */
3307
      source1 -= source2;
3308
      break;
3309
 
3310
    case 3:  /* compare */
3311
      break;
3312
 
3313
    case 4:  /* and */
3314
      source1 &= source2;
3315
      break;
3316
 
3317
    case 5:  /* or */
3318
      source1 |= source2;
3319
      break;
3320
 
3321
    default:
3322
      inst_env->invalid = 1;
3323
      return;
3324
 
3325
      break;
3326
    }
3327
 
3328
  /* Make sure that the result doesn't contain more than the instruction
3329
     size bits.  */
3330
  source2 &= operation_mask;
3331
 
3332
  /* Calculate the new breakpoint address.  */
3333
  inst_env->reg[REG_PC] &= pc_mask;
3334
  inst_env->reg[REG_PC] |= source1;
3335
 
3336
}
3337
 
3338
/* Extends the value from either byte or word size to a dword.  If the mode
3339
   is zero extend then the value is extended with zero.  If instead the mode
3340
   is signed extend the sign bit of the value is taken into consideration.  */
3341
 
3342
static unsigned long
3343
do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3344
{
3345
  /* The size can be either byte or word, check which one it is.
3346
     Don't check the highest bit, it's indicating if it's a zero
3347
     or sign extend.  */
3348
  if (cris_get_size (*inst) & INST_WORD_SIZE)
3349
    {
3350
      /* Word size.  */
3351
      value &= 0xFFFF;
3352
 
3353
      /* Check if the instruction is signed extend.  If so, check if value has
3354
         the sign bit on.  */
3355
      if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3356
        {
3357
          value |= SIGNED_WORD_EXTEND_MASK;
3358
        }
3359
    }
3360
  else
3361
    {
3362
      /* Byte size.  */
3363
      value &= 0xFF;
3364
 
3365
      /* Check if the instruction is signed extend.  If so, check if value has
3366
         the sign bit on.  */
3367
      if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3368
        {
3369
          value |= SIGNED_BYTE_EXTEND_MASK;
3370
        }
3371
    }
3372
  /* The size should now be dword.  */
3373
  cris_set_size_to_dword (inst);
3374
  return value;
3375
}
3376
 
3377
/* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3378
   instruction.  The MOVE instruction is the move from source to register.  */
3379
 
3380
static void
3381
reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3382
                                     inst_env_type *inst_env)
3383
{
3384
  unsigned long operand1;
3385
  unsigned long operand2;
3386
 
3387
  /* It's invalid to have a prefix to the instruction.  This is a register
3388
     mode instruction and can't have a prefix.  */
3389
  if (inst_env->prefix_found)
3390
    {
3391
      inst_env->invalid = 1;
3392
      return;
3393
    }
3394
  /* Check if the instruction has PC as its target.  */
3395
  if (cris_get_operand2 (inst) == REG_PC)
3396
    {
3397
      if (inst_env->slot_needed)
3398
        {
3399
          inst_env->invalid = 1;
3400
          return;
3401
        }
3402
      /* The instruction has the PC as its target register.  */
3403
      operand1 = inst_env->reg[cris_get_operand1 (inst)];
3404
      operand2 = inst_env->reg[REG_PC];
3405
 
3406
      /* Check if it's a extend, signed or zero instruction.  */
3407
      if (cris_get_opcode (inst) < 4)
3408
        {
3409
          operand1 = do_sign_or_zero_extend (operand1, &inst);
3410
        }
3411
      /* Calculate the PC value after the instruction, i.e. where the
3412
         breakpoint should be.  The order of the udw_operands is vital.  */
3413
      add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3414
    }
3415
  inst_env->slot_needed = 0;
3416
  inst_env->prefix_found = 0;
3417
  inst_env->xflag_found = 0;
3418
  inst_env->disable_interrupt = 0;
3419
}
3420
 
3421
/* Returns the data contained at address.  The size of the data is derived from
3422
   the size of the operation.  If the instruction is a zero or signed
3423
   extend instruction, the size field is changed in instruction.  */
3424
 
3425
static unsigned long
3426
get_data_from_address (unsigned short *inst, CORE_ADDR address)
3427
{
3428
  int size = cris_get_size (*inst);
3429
  unsigned long value;
3430
 
3431
  /* If it's an extend instruction we don't want the signed extend bit,
3432
     because it influences the size.  */
3433
  if (cris_get_opcode (*inst) < 4)
3434
    {
3435
      size &= ~SIGNED_EXTEND_BIT_MASK;
3436
    }
3437
  /* Is there a need for checking the size?  Size should contain the number of
3438
     bytes to read.  */
3439
  size = 1 << size;
3440
  value = read_memory_unsigned_integer (address, size);
3441
 
3442
  /* Check if it's an extend, signed or zero instruction.  */
3443
  if (cris_get_opcode (*inst) < 4)
3444
    {
3445
      value = do_sign_or_zero_extend (value, inst);
3446
    }
3447
  return value;
3448
}
3449
 
3450
/* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3451
   instructions.  The MOVE instruction is the move from source to register.  */
3452
 
3453
static void
3454
handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3455
                                        inst_env_type *inst_env)
3456
{
3457
  unsigned long operand2;
3458
  unsigned long operand3;
3459
 
3460
  check_assign (inst, inst_env);
3461
  if (cris_get_operand2 (inst) == REG_PC)
3462
    {
3463
      operand2 = inst_env->reg[REG_PC];
3464
 
3465
      /* Get the value of the third operand.  */
3466
      operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3467
 
3468
      /* Calculate the PC value after the instruction, i.e. where the
3469
         breakpoint should be.  The order of the udw_operands is vital.  */
3470
      add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3471
    }
3472
  inst_env->slot_needed = 0;
3473
  inst_env->prefix_found = 0;
3474
  inst_env->xflag_found = 0;
3475
  inst_env->disable_interrupt = 0;
3476
}
3477
 
3478
/* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3479
   OR instructions.  Note that for this to work as expected, the calling
3480
   function must have made sure that there is a prefix to this instruction.  */
3481
 
3482
static void
3483
three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3484
                                     inst_env_type *inst_env)
3485
{
3486
  unsigned long operand2;
3487
  unsigned long operand3;
3488
 
3489
  if (cris_get_operand1 (inst) == REG_PC)
3490
    {
3491
      /* The PC will be changed by the instruction.  */
3492
      operand2 = inst_env->reg[cris_get_operand2 (inst)];
3493
 
3494
      /* Get the value of the third operand.  */
3495
      operand3 = get_data_from_address (&inst, inst_env->prefix_value);
3496
 
3497
      /* Calculate the PC value after the instruction, i.e. where the
3498
         breakpoint should be.  */
3499
      add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3500
    }
3501
  inst_env->slot_needed = 0;
3502
  inst_env->prefix_found = 0;
3503
  inst_env->xflag_found = 0;
3504
  inst_env->disable_interrupt = 0;
3505
}
3506
 
3507
/* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3508
   instructions.  The MOVE instruction is the move from source to register.  */
3509
 
3510
static void
3511
handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3512
                                       inst_env_type *inst_env)
3513
{
3514
  if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3515
    {
3516
      /* If the instruction is MOVE it's invalid.  If the instruction is ADD,
3517
         SUB, AND or OR something weird is going on (if everything works these
3518
         instructions should end up in the three operand version).  */
3519
      inst_env->invalid = 1;
3520
      return;
3521
    }
3522
  else
3523
    {
3524
      /* three_operand_add_sub_cmp_and_or does the same as we should do here
3525
         so use it.  */
3526
      three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3527
    }
3528
  inst_env->slot_needed = 0;
3529
  inst_env->prefix_found = 0;
3530
  inst_env->xflag_found = 0;
3531
  inst_env->disable_interrupt = 0;
3532
}
3533
 
3534
/* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3535
   CMP, AND OR and MOVE instruction.  The MOVE instruction is the move from
3536
   source to register.  */
3537
 
3538
static void
3539
handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3540
                                        inst_env_type *inst_env)
3541
{
3542
  unsigned long operand1;
3543
  unsigned long operand2;
3544
  unsigned long operand3;
3545
  int size;
3546
 
3547
  /* The instruction is either an indirect or autoincrement addressing mode.
3548
     Check if the destination register is the PC.  */
3549
  if (cris_get_operand2 (inst) == REG_PC)
3550
    {
3551
      /* Must be done here, get_data_from_address may change the size
3552
         field.  */
3553
      size = cris_get_size (inst);
3554
      operand2 = inst_env->reg[REG_PC];
3555
 
3556
      /* Get the value of the third operand, i.e. the indirect operand.  */
3557
      operand1 = inst_env->reg[cris_get_operand1 (inst)];
3558
      operand3 = get_data_from_address (&inst, operand1);
3559
 
3560
      /* Calculate the PC value after the instruction, i.e. where the
3561
         breakpoint should be.  The order of the udw_operands is vital.  */
3562
      add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3563
    }
3564
  /* If this is an autoincrement addressing mode, check if the increment
3565
     changes the PC.  */
3566
  if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE))
3567
    {
3568
      /* Get the size field.  */
3569
      size = cris_get_size (inst);
3570
 
3571
      /* If it's an extend instruction we don't want the signed extend bit,
3572
         because it influences the size.  */
3573
      if (cris_get_opcode (inst) < 4)
3574
        {
3575
          size &= ~SIGNED_EXTEND_BIT_MASK;
3576
        }
3577
      process_autoincrement (size, inst, inst_env);
3578
    }
3579
  inst_env->slot_needed = 0;
3580
  inst_env->prefix_found = 0;
3581
  inst_env->xflag_found = 0;
3582
  inst_env->disable_interrupt = 0;
3583
}
3584
 
3585
/* Handles the two-operand addressing mode, all modes except register, for
3586
   the ADD, SUB CMP, AND and OR instruction.  */
3587
 
3588
static void
3589
none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3590
                                          inst_env_type *inst_env)
3591
{
3592
  if (inst_env->prefix_found)
3593
    {
3594
      if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3595
        {
3596
          handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3597
        }
3598
      else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3599
        {
3600
          handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3601
        }
3602
      else
3603
        {
3604
          /* The mode is invalid for a prefixed base instruction.  */
3605
          inst_env->invalid = 1;
3606
          return;
3607
        }
3608
    }
3609
  else
3610
    {
3611
      handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3612
    }
3613
}
3614
 
3615
/* Handles the quick addressing mode for the ADD and SUB instruction.  */
3616
 
3617
static void
3618
quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3619
{
3620
  unsigned long operand1;
3621
  unsigned long operand2;
3622
 
3623
  /* It's a bad idea to be in a prefix instruction now.  This is a quick mode
3624
     instruction and can't have a prefix.  */
3625
  if (inst_env->prefix_found)
3626
    {
3627
      inst_env->invalid = 1;
3628
      return;
3629
    }
3630
 
3631
  /* Check if the instruction has PC as its target.  */
3632
  if (cris_get_operand2 (inst) == REG_PC)
3633
    {
3634
      if (inst_env->slot_needed)
3635
        {
3636
          inst_env->invalid = 1;
3637
          return;
3638
        }
3639
      operand1 = cris_get_quick_value (inst);
3640
      operand2 = inst_env->reg[REG_PC];
3641
 
3642
      /* The size should now be dword.  */
3643
      cris_set_size_to_dword (&inst);
3644
 
3645
      /* Calculate the PC value after the instruction, i.e. where the
3646
         breakpoint should be.  */
3647
      add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3648
    }
3649
  inst_env->slot_needed = 0;
3650
  inst_env->prefix_found = 0;
3651
  inst_env->xflag_found = 0;
3652
  inst_env->disable_interrupt = 0;
3653
}
3654
 
3655
/* Handles the quick addressing mode for the CMP, AND and OR instruction.  */
3656
 
3657
static void
3658
quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3659
{
3660
  unsigned long operand1;
3661
  unsigned long operand2;
3662
 
3663
  /* It's a bad idea to be in a prefix instruction now.  This is a quick mode
3664
     instruction and can't have a prefix.  */
3665
  if (inst_env->prefix_found)
3666
    {
3667
      inst_env->invalid = 1;
3668
      return;
3669
    }
3670
  /* Check if the instruction has PC as its target.  */
3671
  if (cris_get_operand2 (inst) == REG_PC)
3672
    {
3673
      if (inst_env->slot_needed)
3674
        {
3675
          inst_env->invalid = 1;
3676
          return;
3677
        }
3678
      /* The instruction has the PC as its target register.  */
3679
      operand1 = cris_get_quick_value (inst);
3680
      operand2 = inst_env->reg[REG_PC];
3681
 
3682
      /* The quick value is signed, so check if we must do a signed extend.  */
3683
      if (operand1 & SIGNED_QUICK_VALUE_MASK)
3684
        {
3685
          /* sign extend  */
3686
          operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3687
        }
3688
      /* The size should now be dword.  */
3689
      cris_set_size_to_dword (&inst);
3690
 
3691
      /* Calculate the PC value after the instruction, i.e. where the
3692
         breakpoint should be.  */
3693
      add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3694
    }
3695
  inst_env->slot_needed = 0;
3696
  inst_env->prefix_found = 0;
3697
  inst_env->xflag_found = 0;
3698
  inst_env->disable_interrupt = 0;
3699
}
3700
 
3701
/* Translate op_type to a function and call it.  */
3702
 
3703
static void
3704
cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3705
               unsigned short inst, inst_env_type *inst_env)
3706
{
3707
  switch (op_type)
3708
    {
3709
    case cris_not_implemented_op:
3710
      not_implemented_op (inst, inst_env);
3711
      break;
3712
 
3713
    case cris_abs_op:
3714
      abs_op (inst, inst_env);
3715
      break;
3716
 
3717
    case cris_addi_op:
3718
      addi_op (inst, inst_env);
3719
      break;
3720
 
3721
    case cris_asr_op:
3722
      asr_op (inst, inst_env);
3723
      break;
3724
 
3725
    case cris_asrq_op:
3726
      asrq_op (inst, inst_env);
3727
      break;
3728
 
3729
    case cris_ax_ei_setf_op:
3730
      ax_ei_setf_op (inst, inst_env);
3731
      break;
3732
 
3733
    case cris_bdap_prefix:
3734
      bdap_prefix (inst, inst_env);
3735
      break;
3736
 
3737
    case cris_biap_prefix:
3738
      biap_prefix (inst, inst_env);
3739
      break;
3740
 
3741
    case cris_break_op:
3742
      break_op (inst, inst_env);
3743
      break;
3744
 
3745
    case cris_btst_nop_op:
3746
      btst_nop_op (inst, inst_env);
3747
      break;
3748
 
3749
    case cris_clearf_di_op:
3750
      clearf_di_op (inst, inst_env);
3751
      break;
3752
 
3753
    case cris_dip_prefix:
3754
      dip_prefix (inst, inst_env);
3755
      break;
3756
 
3757
    case cris_dstep_logshift_mstep_neg_not_op:
3758
      dstep_logshift_mstep_neg_not_op (inst, inst_env);
3759
      break;
3760
 
3761
    case cris_eight_bit_offset_branch_op:
3762
      eight_bit_offset_branch_op (inst, inst_env);
3763
      break;
3764
 
3765
    case cris_move_mem_to_reg_movem_op:
3766
      move_mem_to_reg_movem_op (inst, inst_env);
3767
      break;
3768
 
3769
    case cris_move_reg_to_mem_movem_op:
3770
      move_reg_to_mem_movem_op (inst, inst_env);
3771
      break;
3772
 
3773
    case cris_move_to_preg_op:
3774
      move_to_preg_op (gdbarch, inst, inst_env);
3775
      break;
3776
 
3777
    case cris_muls_op:
3778
      muls_op (inst, inst_env);
3779
      break;
3780
 
3781
    case cris_mulu_op:
3782
      mulu_op (inst, inst_env);
3783
      break;
3784
 
3785
    case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3786
      none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3787
      break;
3788
 
3789
    case cris_none_reg_mode_clear_test_op:
3790
      none_reg_mode_clear_test_op (inst, inst_env);
3791
      break;
3792
 
3793
    case cris_none_reg_mode_jump_op:
3794
      none_reg_mode_jump_op (inst, inst_env);
3795
      break;
3796
 
3797
    case cris_none_reg_mode_move_from_preg_op:
3798
      none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3799
      break;
3800
 
3801
    case cris_quick_mode_add_sub_op:
3802
      quick_mode_add_sub_op (inst, inst_env);
3803
      break;
3804
 
3805
    case cris_quick_mode_and_cmp_move_or_op:
3806
      quick_mode_and_cmp_move_or_op (inst, inst_env);
3807
      break;
3808
 
3809
    case cris_quick_mode_bdap_prefix:
3810
      quick_mode_bdap_prefix (inst, inst_env);
3811
      break;
3812
 
3813
    case cris_reg_mode_add_sub_cmp_and_or_move_op:
3814
      reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3815
      break;
3816
 
3817
    case cris_reg_mode_clear_op:
3818
      reg_mode_clear_op (inst, inst_env);
3819
      break;
3820
 
3821
    case cris_reg_mode_jump_op:
3822
      reg_mode_jump_op (inst, inst_env);
3823
      break;
3824
 
3825
    case cris_reg_mode_move_from_preg_op:
3826
      reg_mode_move_from_preg_op (inst, inst_env);
3827
      break;
3828
 
3829
    case cris_reg_mode_test_op:
3830
      reg_mode_test_op (inst, inst_env);
3831
      break;
3832
 
3833
    case cris_scc_op:
3834
      scc_op (inst, inst_env);
3835
      break;
3836
 
3837
    case cris_sixteen_bit_offset_branch_op:
3838
      sixteen_bit_offset_branch_op (inst, inst_env);
3839
      break;
3840
 
3841
    case cris_three_operand_add_sub_cmp_and_or_op:
3842
      three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3843
      break;
3844
 
3845
    case cris_three_operand_bound_op:
3846
      three_operand_bound_op (inst, inst_env);
3847
      break;
3848
 
3849
    case cris_two_operand_bound_op:
3850
      two_operand_bound_op (inst, inst_env);
3851
      break;
3852
 
3853
    case cris_xor_op:
3854
      xor_op (inst, inst_env);
3855
      break;
3856
    }
3857
}
3858
 
3859
/* This wrapper is to avoid cris_get_assembler being called before
3860
   exec_bfd has been set.  */
3861
 
3862
static int
3863
cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3864
{
3865
  int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3866
  /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3867
     disassembler, even when there is no BFD.  Does something like
3868
     "gdb; target remote; disassmeble *0x123" work?  */
3869
  gdb_assert (exec_bfd != NULL);
3870
  print_insn = cris_get_disassembler (exec_bfd);
3871
  gdb_assert (print_insn != NULL);
3872
  return print_insn (addr, info);
3873
}
3874
 
3875
/* Copied from <asm/elf.h>.  */
3876
typedef unsigned long elf_greg_t;
3877
 
3878
/* Same as user_regs_struct struct in <asm/user.h>.  */
3879
#define CRISV10_ELF_NGREG 35
3880
typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
3881
 
3882
#define CRISV32_ELF_NGREG 32
3883
typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3884
 
3885
/* Unpack an elf_gregset_t into GDB's register cache.  */
3886
 
3887
static void
3888
cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp)
3889
{
3890
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
3891
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3892
  int i;
3893
  elf_greg_t *regp = *gregsetp;
3894
  static char zerobuf[4] = {0};
3895
 
3896
  /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3897
     knows about the actual size of each register so that's no problem.  */
3898
  for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3899
    {
3900
      regcache_raw_supply (regcache, i, (char *)&regp[i]);
3901
    }
3902
 
3903
  if (tdep->cris_version == 32)
3904
    {
3905
      /* Needed to set pseudo-register PC for CRISv32.  */
3906
      /* FIXME: If ERP is in a delay slot at this point then the PC will
3907
         be wrong.  Issue a warning to alert the user.  */
3908
      regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3909
                           (char *)&regp[ERP_REGNUM]);
3910
 
3911
      if (*(char *)&regp[ERP_REGNUM] & 0x1)
3912
        fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3913
    }
3914
}
3915
 
3916
/*  Use a local version of this function to get the correct types for
3917
    regsets, until multi-arch core support is ready.  */
3918
 
3919
static void
3920
fetch_core_registers (struct regcache *regcache,
3921
                      char *core_reg_sect, unsigned core_reg_size,
3922
                      int which, CORE_ADDR reg_addr)
3923
{
3924
  elf_gregset_t gregset;
3925
 
3926
  switch (which)
3927
    {
3928
    case 0:
3929
      if (core_reg_size != sizeof (elf_gregset_t)
3930
          && core_reg_size != sizeof (crisv32_elf_gregset_t))
3931
        {
3932
          warning (_("wrong size gregset struct in core file"));
3933
        }
3934
      else
3935
        {
3936
          memcpy (&gregset, core_reg_sect, sizeof (gregset));
3937
          cris_supply_gregset (regcache, &gregset);
3938
        }
3939
 
3940
    default:
3941
      /* We've covered all the kinds of registers we know about here,
3942
         so this must be something we wouldn't know what to do with
3943
         anyway.  Just ignore it.  */
3944
      break;
3945
    }
3946
}
3947
 
3948
static struct core_fns cris_elf_core_fns =
3949
{
3950
  bfd_target_elf_flavour,               /* core_flavour */
3951
  default_check_format,                 /* check_format */
3952
  default_core_sniffer,                 /* core_sniffer */
3953
  fetch_core_registers,                 /* core_read_registers */
3954
  NULL                                  /* next */
3955
};
3956
 
3957
extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3958
 
3959
void
3960
_initialize_cris_tdep (void)
3961
{
3962
  static struct cmd_list_element *cris_set_cmdlist;
3963
  static struct cmd_list_element *cris_show_cmdlist;
3964
 
3965
  struct cmd_list_element *c;
3966
 
3967
  gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3968
 
3969
  /* CRIS-specific user-commands.  */
3970
  add_setshow_uinteger_cmd ("cris-version", class_support,
3971
                            &usr_cmd_cris_version,
3972
                            _("Set the current CRIS version."),
3973
                            _("Show the current CRIS version."),
3974
                            _("\
3975
Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3976
Defaults to 10. "),
3977
                            set_cris_version,
3978
                            NULL, /* FIXME: i18n: Current CRIS version is %s.  */
3979
                            &setlist, &showlist);
3980
 
3981
  add_setshow_enum_cmd ("cris-mode", class_support,
3982
                        cris_modes, &usr_cmd_cris_mode,
3983
                        _("Set the current CRIS mode."),
3984
                        _("Show the current CRIS mode."),
3985
                        _("\
3986
Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3987
Makes GDB use the NRP register instead of the ERP register in certain cases."),
3988
                        set_cris_mode,
3989
                        NULL, /* FIXME: i18n: Current CRIS version is %s.  */
3990
                        &setlist, &showlist);
3991
 
3992
  add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3993
                           &usr_cmd_cris_dwarf2_cfi,
3994
                           _("Set the usage of Dwarf-2 CFI for CRIS."),
3995
                           _("Show the usage of Dwarf-2 CFI for CRIS."),
3996
                           _("Set this to \"off\" if using gcc-cris < R59."),
3997
                           set_cris_dwarf2_cfi,
3998
                           NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d.  */
3999
                           &setlist, &showlist);
4000
 
4001
  deprecated_add_core_fns (&cris_elf_core_fns);
4002
}
4003
 
4004
/* Prints out all target specific values.  */
4005
 
4006
static void
4007
cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
4008
{
4009
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4010
  if (tdep != NULL)
4011
    {
4012
      fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
4013
                          tdep->cris_version);
4014
      fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
4015
                          tdep->cris_mode);
4016
      fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
4017
                          tdep->cris_dwarf2_cfi);
4018
    }
4019
}
4020
 
4021
static void
4022
set_cris_version (char *ignore_args, int from_tty,
4023
                  struct cmd_list_element *c)
4024
{
4025
  struct gdbarch_info info;
4026
 
4027
  usr_cmd_cris_version_valid = 1;
4028
 
4029
  /* Update the current architecture, if needed.  */
4030
  gdbarch_info_init (&info);
4031
  if (!gdbarch_update_p (info))
4032
    internal_error (__FILE__, __LINE__,
4033
                    _("cris_gdbarch_update: failed to update architecture."));
4034
}
4035
 
4036
static void
4037
set_cris_mode (char *ignore_args, int from_tty,
4038
               struct cmd_list_element *c)
4039
{
4040
  struct gdbarch_info info;
4041
 
4042
  /* Update the current architecture, if needed.  */
4043
  gdbarch_info_init (&info);
4044
  if (!gdbarch_update_p (info))
4045
    internal_error (__FILE__, __LINE__,
4046
                    "cris_gdbarch_update: failed to update architecture.");
4047
}
4048
 
4049
static void
4050
set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
4051
                     struct cmd_list_element *c)
4052
{
4053
  struct gdbarch_info info;
4054
 
4055
  /* Update the current architecture, if needed.  */
4056
  gdbarch_info_init (&info);
4057
  if (!gdbarch_update_p (info))
4058
    internal_error (__FILE__, __LINE__,
4059
                    _("cris_gdbarch_update: failed to update architecture."));
4060
}
4061
 
4062
static struct gdbarch *
4063
cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4064
{
4065
  struct gdbarch *gdbarch;
4066
  struct gdbarch_tdep *tdep;
4067
  int cris_version;
4068
 
4069
  if (usr_cmd_cris_version_valid)
4070
    {
4071
      /* Trust the user's CRIS version setting.  */
4072
      cris_version = usr_cmd_cris_version;
4073
    }
4074
  else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4075
    {
4076
      cris_version = 32;
4077
    }
4078
  else
4079
    {
4080
      /* Assume it's CRIS version 10.  */
4081
      cris_version = 10;
4082
    }
4083
 
4084
  /* Make the current settings visible to the user.  */
4085
  usr_cmd_cris_version = cris_version;
4086
 
4087
  /* Find a candidate among the list of pre-declared architectures.  */
4088
  for (arches = gdbarch_list_lookup_by_info (arches, &info);
4089
       arches != NULL;
4090
       arches = gdbarch_list_lookup_by_info (arches->next, &info))
4091
    {
4092
      if ((gdbarch_tdep (arches->gdbarch)->cris_version
4093
           == usr_cmd_cris_version)
4094
          && (gdbarch_tdep (arches->gdbarch)->cris_mode
4095
           == usr_cmd_cris_mode)
4096
          && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4097
              == usr_cmd_cris_dwarf2_cfi))
4098
        return arches->gdbarch;
4099
    }
4100
 
4101
  /* No matching architecture was found.  Create a new one.  */
4102
  tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
4103
  gdbarch = gdbarch_alloc (&info, tdep);
4104
 
4105
  tdep->cris_version = usr_cmd_cris_version;
4106
  tdep->cris_mode = usr_cmd_cris_mode;
4107
  tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4108
 
4109
  /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero.  */
4110
  switch (info.byte_order)
4111
    {
4112
    case BFD_ENDIAN_LITTLE:
4113
      /* Ok.  */
4114
      break;
4115
 
4116
    case BFD_ENDIAN_BIG:
4117
      internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info"));
4118
      break;
4119
 
4120
    default:
4121
      internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info"));
4122
    }
4123
 
4124
  set_gdbarch_return_value (gdbarch, cris_return_value);
4125
 
4126
  set_gdbarch_sp_regnum (gdbarch, 14);
4127
 
4128
  /* Length of ordinary registers used in push_word and a few other
4129
     places.  register_size() is the real way to know how big a
4130
     register is.  */
4131
 
4132
  set_gdbarch_double_bit (gdbarch, 64);
4133
  /* The default definition of a long double is 2 * gdbarch_double_bit,
4134
     which means we have to set this explicitly.  */
4135
  set_gdbarch_long_double_bit (gdbarch, 64);
4136
 
4137
  /* The total amount of space needed to store (in an array called registers)
4138
     GDB's copy of the machine's register state.  Note: We can not use
4139
     cris_register_size at this point, since it relies on gdbarch
4140
     being set.  */
4141
  switch (tdep->cris_version)
4142
    {
4143
    case 0:
4144
    case 1:
4145
    case 2:
4146
    case 3:
4147
    case 8:
4148
    case 9:
4149
      /* Old versions; not supported.  */
4150
      internal_error (__FILE__, __LINE__,
4151
                      _("cris_gdbarch_init: unsupported CRIS version"));
4152
      break;
4153
 
4154
    case 10:
4155
    case 11:
4156
      /* CRIS v10 and v11, a.k.a. ETRAX 100LX.  In addition to ETRAX 100,
4157
         P7 (32 bits), and P15 (32 bits) have been implemented.  */
4158
      set_gdbarch_pc_regnum (gdbarch, 15);
4159
      set_gdbarch_register_type (gdbarch, cris_register_type);
4160
      /* There are 32 registers (some of which may not be implemented).  */
4161
      set_gdbarch_num_regs (gdbarch, 32);
4162
      set_gdbarch_register_name (gdbarch, cris_register_name);
4163
      set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4164
      set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4165
 
4166
      set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4167
      break;
4168
 
4169
    case 32:
4170
      /* CRIS v32.  General registers R0 - R15 (32 bits), special registers
4171
         P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4172
         and pseudo-register PC (32 bits).  */
4173
      set_gdbarch_pc_regnum (gdbarch, 32);
4174
      set_gdbarch_register_type (gdbarch, crisv32_register_type);
4175
      /* 32 registers + pseudo-register PC + 16 support registers.  */
4176
      set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4177
      set_gdbarch_register_name (gdbarch, crisv32_register_name);
4178
 
4179
      set_gdbarch_cannot_store_register
4180
        (gdbarch, crisv32_cannot_store_register);
4181
      set_gdbarch_cannot_fetch_register
4182
        (gdbarch, crisv32_cannot_fetch_register);
4183
 
4184
      set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4185
 
4186
      set_gdbarch_single_step_through_delay
4187
        (gdbarch, crisv32_single_step_through_delay);
4188
 
4189
      break;
4190
 
4191
    default:
4192
      internal_error (__FILE__, __LINE__,
4193
                      _("cris_gdbarch_init: unknown CRIS version"));
4194
    }
4195
 
4196
  /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4197
     have the same ABI).  */
4198
  set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4199
  set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4200
  set_gdbarch_frame_align (gdbarch, cris_frame_align);
4201
  set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4202
 
4203
  /* The stack grows downward.  */
4204
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4205
 
4206
  set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4207
 
4208
  set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4209
  set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4210
  set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id);
4211
 
4212
  if (tdep->cris_dwarf2_cfi == 1)
4213
    {
4214
      /* Hook in the Dwarf-2 frame sniffer.  */
4215
      set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4216
      dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4217
      frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
4218
    }
4219
 
4220
  if (tdep->cris_mode != cris_mode_guru)
4221
    {
4222
      frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer);
4223
    }
4224
 
4225
  frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer);
4226
  frame_base_set_default (gdbarch, &cris_frame_base);
4227
 
4228
  set_solib_svr4_fetch_link_map_offsets
4229
    (gdbarch, svr4_ilp32_fetch_link_map_offsets);
4230
 
4231
  /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4232
     disassembler, even when there is no BFD.  Does something like
4233
     "gdb; target remote; disassmeble *0x123" work?  */
4234
  set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);
4235
 
4236
  return gdbarch;
4237
}

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