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1 24 jeremybenn
/* Native-dependent code for the i386.
2
 
3
   Copyright (C) 2001, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
4
 
5
   This file is part of GDB.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#include "defs.h"
21
#include "breakpoint.h"
22
#include "command.h"
23
#include "gdbcmd.h"
24
 
25
/* Support for hardware watchpoints and breakpoints using the i386
26
   debug registers.
27
 
28
   This provides several functions for inserting and removing
29
   hardware-assisted breakpoints and watchpoints, testing if one or
30
   more of the watchpoints triggered and at what address, checking
31
   whether a given region can be watched, etc.
32
 
33
   A target which wants to use these functions should define several
34
   macros, such as `target_insert_watchpoint' and
35
   `target_stopped_data_address', listed in target.h, to call the
36
   appropriate functions below.  It should also define
37
   I386_USE_GENERIC_WATCHPOINTS in its tm.h file.
38
 
39
   In addition, each target should provide several low-level macros
40
   that will be called to insert watchpoints and hardware breakpoints
41
   into the inferior, remove them, and check their status.  These
42
   macros are:
43
 
44
      I386_DR_LOW_SET_CONTROL  -- set the debug control (DR7)
45
                                  register to a given value
46
 
47
      I386_DR_LOW_SET_ADDR     -- put an address into one debug
48
                                  register
49
 
50
      I386_DR_LOW_RESET_ADDR   -- reset the address stored in
51
                                  one debug register
52
 
53
      I386_DR_LOW_GET_STATUS   -- return the value of the debug
54
                                  status (DR6) register.
55
 
56
   The functions below implement debug registers sharing by reference
57
   counts, and allow to watch regions up to 16 bytes long.  */
58
 
59
#ifdef I386_USE_GENERIC_WATCHPOINTS
60
 
61
/* Support for 8-byte wide hw watchpoints.  */
62
#ifndef TARGET_HAS_DR_LEN_8
63
#define TARGET_HAS_DR_LEN_8     0
64
#endif
65
 
66
/* Debug registers' indices.  */
67
#define DR_NADDR        4       /* The number of debug address registers.  */
68
#define DR_STATUS       6       /* Index of debug status register (DR6).  */
69
#define DR_CONTROL      7       /* Index of debug control register (DR7). */
70
 
71
/* DR7 Debug Control register fields.  */
72
 
73
/* How many bits to skip in DR7 to get to R/W and LEN fields.  */
74
#define DR_CONTROL_SHIFT        16
75
/* How many bits in DR7 per R/W and LEN field for each watchpoint.  */
76
#define DR_CONTROL_SIZE         4
77
 
78
/* Watchpoint/breakpoint read/write fields in DR7.  */
79
#define DR_RW_EXECUTE   (0x0)   /* Break on instruction execution.  */
80
#define DR_RW_WRITE     (0x1)   /* Break on data writes.  */
81
#define DR_RW_READ      (0x3)   /* Break on data reads or writes.  */
82
 
83
/* This is here for completeness.  No platform supports this
84
   functionality yet (as of March 2001).  Note that the DE flag in the
85
   CR4 register needs to be set to support this.  */
86
#ifndef DR_RW_IORW
87
#define DR_RW_IORW      (0x2)   /* Break on I/O reads or writes.  */
88
#endif
89
 
90
/* Watchpoint/breakpoint length fields in DR7.  The 2-bit left shift
91
   is so we could OR this with the read/write field defined above.  */
92
#define DR_LEN_1        (0x0 << 2) /* 1-byte region watch or breakpoint.  */
93
#define DR_LEN_2        (0x1 << 2) /* 2-byte region watch.  */
94
#define DR_LEN_4        (0x3 << 2) /* 4-byte region watch.  */
95
#define DR_LEN_8        (0x2 << 2) /* 8-byte region watch (AMD64).  */
96
 
97
/* Local and Global Enable flags in DR7.
98
 
99
   When the Local Enable flag is set, the breakpoint/watchpoint is
100
   enabled only for the current task; the processor automatically
101
   clears this flag on every task switch.  When the Global Enable flag
102
   is set, the breakpoint/watchpoint is enabled for all tasks; the
103
   processor never clears this flag.
104
 
105
   Currently, all watchpoint are locally enabled.  If you need to
106
   enable them globally, read the comment which pertains to this in
107
   i386_insert_aligned_watchpoint below.  */
108
#define DR_LOCAL_ENABLE_SHIFT   0 /* Extra shift to the local enable bit.  */
109
#define DR_GLOBAL_ENABLE_SHIFT  1 /* Extra shift to the global enable bit.  */
110
#define DR_ENABLE_SIZE          2 /* Two enable bits per debug register.  */
111
 
112
/* Local and global exact breakpoint enable flags (a.k.a. slowdown
113
   flags).  These are only required on i386, to allow detection of the
114
   exact instruction which caused a watchpoint to break; i486 and
115
   later processors do that automatically.  We set these flags for
116
   backwards compatibility.  */
117
#define DR_LOCAL_SLOWDOWN       (0x100)
118
#define DR_GLOBAL_SLOWDOWN      (0x200)
119
 
120
/* Fields reserved by Intel.  This includes the GD (General Detect
121
   Enable) flag, which causes a debug exception to be generated when a
122
   MOV instruction accesses one of the debug registers.
123
 
124
   FIXME: My Intel manual says we should use 0xF800, not 0xFC00.  */
125
#define DR_CONTROL_RESERVED     (0xFC00)
126
 
127
/* Auxiliary helper macros.  */
128
 
129
/* A value that masks all fields in DR7 that are reserved by Intel.  */
130
#define I386_DR_CONTROL_MASK    (~DR_CONTROL_RESERVED)
131
 
132
/* The I'th debug register is vacant if its Local and Global Enable
133
   bits are reset in the Debug Control register.  */
134
#define I386_DR_VACANT(i) \
135
  ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
136
 
137
/* Locally enable the break/watchpoint in the I'th debug register.  */
138
#define I386_DR_LOCAL_ENABLE(i) \
139
  dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
140
 
141
/* Globally enable the break/watchpoint in the I'th debug register.  */
142
#define I386_DR_GLOBAL_ENABLE(i) \
143
  dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i)))
144
 
145
/* Disable the break/watchpoint in the I'th debug register.  */
146
#define I386_DR_DISABLE(i) \
147
  dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i)))
148
 
149
/* Set in DR7 the RW and LEN fields for the I'th debug register.  */
150
#define I386_DR_SET_RW_LEN(i,rwlen) \
151
  do { \
152
    dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i)));   \
153
    dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \
154
  } while (0)
155
 
156
/* Get from DR7 the RW and LEN fields for the I'th debug register.  */
157
#define I386_DR_GET_RW_LEN(i) \
158
  ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
159
 
160
/* Did the watchpoint whose address is in the I'th register break?  */
161
#define I386_DR_WATCH_HIT(i)    (dr_status_mirror & (1 << (i)))
162
 
163
/* A macro to loop over all debug registers.  */
164
#define ALL_DEBUG_REGISTERS(i)  for (i = 0; i < DR_NADDR; i++)
165
 
166
/* Mirror the inferior's DRi registers.  We keep the status and
167
   control registers separated because they don't hold addresses.  */
168
static CORE_ADDR dr_mirror[DR_NADDR];
169
static unsigned dr_status_mirror, dr_control_mirror;
170
 
171
/* Reference counts for each debug register.  */
172
static int dr_ref_count[DR_NADDR];
173
 
174
/* Whether or not to print the mirrored debug registers.  */
175
static int maint_show_dr;
176
 
177
/* Types of operations supported by i386_handle_nonaligned_watchpoint.  */
178
typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
179
 
180
/* Internal functions.  */
181
 
182
/* Return the value of a 4-bit field for DR7 suitable for watching a
183
   region of LEN bytes for accesses of type TYPE.  LEN is assumed to
184
   have the value of 1, 2, or 4.  */
185
static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type);
186
 
187
/* Insert a watchpoint at address ADDR, which is assumed to be aligned
188
   according to the length of the region to watch.  LEN_RW_BITS is the
189
   value of the bit-field from DR7 which describes the length and
190
   access type of the region to be watched by this watchpoint.  Return
191
 
192
static int i386_insert_aligned_watchpoint (CORE_ADDR addr,
193
                                           unsigned len_rw_bits);
194
 
195
/* Remove a watchpoint at address ADDR, which is assumed to be aligned
196
   according to the length of the region to watch.  LEN_RW_BITS is the
197
   value of the bits from DR7 which describes the length and access
198
   type of the region watched by this watchpoint.  Return 0 on
199
   success, -1 on failure.  */
200
static int i386_remove_aligned_watchpoint (CORE_ADDR addr,
201
                                           unsigned len_rw_bits);
202
 
203
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
204
   number of debug registers required to watch a region at address
205
   ADDR whose length is LEN for accesses of type TYPE.  Return 0 on
206
   successful insertion or removal, a positive number when queried
207
   about the number of registers, or -1 on failure.  If WHAT is not a
208
   valid value, bombs through internal_error.  */
209
static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what,
210
                                              CORE_ADDR addr, int len,
211
                                              enum target_hw_bp_type type);
212
 
213
/* Implementation.  */
214
 
215
/* Clear the reference counts and forget everything we knew about the
216
   debug registers.  */
217
 
218
void
219
i386_cleanup_dregs (void)
220
{
221
  int i;
222
 
223
  ALL_DEBUG_REGISTERS(i)
224
    {
225
      dr_mirror[i] = 0;
226
      dr_ref_count[i] = 0;
227
    }
228
  dr_control_mirror = 0;
229
  dr_status_mirror  = 0;
230
}
231
 
232
/* Reset all debug registers at each new startup to avoid missing
233
   watchpoints after restart.  */
234
 
235
void
236
child_post_startup_inferior (ptid_t ptid)
237
{
238
  i386_cleanup_dregs ();
239
}
240
 
241
/* Print the values of the mirrored debug registers.  This is called
242
   when maint_show_dr is non-zero.  To set that up, type "maint
243
   show-debug-regs" at GDB's prompt.  */
244
 
245
static void
246
i386_show_dr (const char *func, CORE_ADDR addr,
247
              int len, enum target_hw_bp_type type)
248
{
249
  int i;
250
 
251
  puts_unfiltered (func);
252
  if (addr || len)
253
    printf_unfiltered (" (addr=%lx, len=%d, type=%s)",
254
                       /* This code is for ia32, so casting CORE_ADDR
255
                          to unsigned long should be okay.  */
256
                       (unsigned long)addr, len,
257
                       type == hw_write ? "data-write"
258
                       : (type == hw_read ? "data-read"
259
                          : (type == hw_access ? "data-read/write"
260
                             : (type == hw_execute ? "instruction-execute"
261
                                /* FIXME: if/when I/O read/write
262
                                   watchpoints are supported, add them
263
                                   here.  */
264
                                : "??unknown??"))));
265
  puts_unfiltered (":\n");
266
  printf_unfiltered ("\tCONTROL (DR7): %08x          STATUS (DR6): %08x\n",
267
                     dr_control_mirror, dr_status_mirror);
268
  ALL_DEBUG_REGISTERS(i)
269
    {
270
      printf_unfiltered ("\
271
\tDR%d: addr=0x%s, ref.count=%d  DR%d: addr=0x%s, ref.count=%d\n",
272
                         i, paddr(dr_mirror[i]), dr_ref_count[i],
273
                         i+1, paddr(dr_mirror[i+1]), dr_ref_count[i+1]);
274
      i++;
275
    }
276
}
277
 
278
/* Return the value of a 4-bit field for DR7 suitable for watching a
279
   region of LEN bytes for accesses of type TYPE.  LEN is assumed to
280
   have the value of 1, 2, or 4.  */
281
 
282
static unsigned
283
i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
284
{
285
  unsigned rw;
286
 
287
  switch (type)
288
    {
289
      case hw_execute:
290
        rw = DR_RW_EXECUTE;
291
        break;
292
      case hw_write:
293
        rw = DR_RW_WRITE;
294
        break;
295
      case hw_read:
296
        /* The i386 doesn't support data-read watchpoints.  */
297
      case hw_access:
298
        rw = DR_RW_READ;
299
        break;
300
#if 0
301
        /* Not yet supported.  */
302
      case hw_io_access:
303
        rw = DR_RW_IORW;
304
        break;
305
#endif
306
      default:
307
        internal_error (__FILE__, __LINE__, _("\
308
Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"),
309
                        (int) type);
310
    }
311
 
312
  switch (len)
313
    {
314
      case 1:
315
        return (DR_LEN_1 | rw);
316
      case 2:
317
        return (DR_LEN_2 | rw);
318
      case 4:
319
        return (DR_LEN_4 | rw);
320
      case 8:
321
        if (TARGET_HAS_DR_LEN_8)
322
          return (DR_LEN_8 | rw);
323
      default:
324
        internal_error (__FILE__, __LINE__, _("\
325
Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len);
326
    }
327
}
328
 
329
/* Insert a watchpoint at address ADDR, which is assumed to be aligned
330
   according to the length of the region to watch.  LEN_RW_BITS is the
331
   value of the bits from DR7 which describes the length and access
332
   type of the region to be watched by this watchpoint.  Return 0 on
333
   success, -1 on failure.  */
334
 
335
static int
336
i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits)
337
{
338
  int i;
339
 
340
  /* First, look for an occupied debug register with the same address
341
     and the same RW and LEN definitions.  If we find one, we can
342
     reuse it for this watchpoint as well (and save a register).  */
343
  ALL_DEBUG_REGISTERS(i)
344
    {
345
      if (!I386_DR_VACANT (i)
346
          && dr_mirror[i] == addr
347
          && I386_DR_GET_RW_LEN (i) == len_rw_bits)
348
        {
349
          dr_ref_count[i]++;
350
          return 0;
351
        }
352
    }
353
 
354
  /* Next, look for a vacant debug register.  */
355
  ALL_DEBUG_REGISTERS(i)
356
    {
357
      if (I386_DR_VACANT (i))
358
        break;
359
    }
360
 
361
  /* No more debug registers!  */
362
  if (i >= DR_NADDR)
363
    return -1;
364
 
365
  /* Now set up the register I to watch our region.  */
366
 
367
  /* Record the info in our local mirrored array.  */
368
  dr_mirror[i] = addr;
369
  dr_ref_count[i] = 1;
370
  I386_DR_SET_RW_LEN (i, len_rw_bits);
371
  /* Note: we only enable the watchpoint locally, i.e. in the current
372
     task.  Currently, no i386 target allows or supports global
373
     watchpoints; however, if any target would want that in the
374
     future, GDB should probably provide a command to control whether
375
     to enable watchpoints globally or locally, and the code below
376
     should use global or local enable and slow-down flags as
377
     appropriate.  */
378
  I386_DR_LOCAL_ENABLE (i);
379
  dr_control_mirror |= DR_LOCAL_SLOWDOWN;
380
  dr_control_mirror &= I386_DR_CONTROL_MASK;
381
 
382
  /* Finally, actually pass the info to the inferior.  */
383
  I386_DR_LOW_SET_ADDR (i, addr);
384
  I386_DR_LOW_SET_CONTROL (dr_control_mirror);
385
 
386
  return 0;
387
}
388
 
389
/* Remove a watchpoint at address ADDR, which is assumed to be aligned
390
   according to the length of the region to watch.  LEN_RW_BITS is the
391
   value of the bits from DR7 which describes the length and access
392
   type of the region watched by this watchpoint.  Return 0 on
393
   success, -1 on failure.  */
394
 
395
static int
396
i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits)
397
{
398
  int i, retval = -1;
399
 
400
  ALL_DEBUG_REGISTERS(i)
401
    {
402
      if (!I386_DR_VACANT (i)
403
          && dr_mirror[i] == addr
404
          && I386_DR_GET_RW_LEN (i) == len_rw_bits)
405
        {
406
          if (--dr_ref_count[i] == 0) /* no longer in use? */
407
            {
408
              /* Reset our mirror.  */
409
              dr_mirror[i] = 0;
410
              I386_DR_DISABLE (i);
411
              /* Reset it in the inferior.  */
412
              I386_DR_LOW_SET_CONTROL (dr_control_mirror);
413
              I386_DR_LOW_RESET_ADDR (i);
414
            }
415
          retval = 0;
416
        }
417
    }
418
 
419
  return retval;
420
}
421
 
422
/* Insert or remove a (possibly non-aligned) watchpoint, or count the
423
   number of debug registers required to watch a region at address
424
   ADDR whose length is LEN for accesses of type TYPE.  Return 0 on
425
   successful insertion or removal, a positive number when queried
426
   about the number of registers, or -1 on failure.  If WHAT is not a
427
   valid value, bombs through internal_error.  */
428
 
429
static int
430
i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len,
431
                                   enum target_hw_bp_type type)
432
{
433
  int retval = 0, status = 0;
434
  int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
435
 
436
  static int size_try_array[8][8] =
437
  {
438
    {1, 1, 1, 1, 1, 1, 1, 1},   /* Trying size one.  */
439
    {2, 1, 2, 1, 2, 1, 2, 1},   /* Trying size two.  */
440
    {2, 1, 2, 1, 2, 1, 2, 1},   /* Trying size three.  */
441
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size four.  */
442
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size five.  */
443
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size six.  */
444
    {4, 1, 2, 1, 4, 1, 2, 1},   /* Trying size seven.  */
445
    {8, 1, 2, 1, 4, 1, 2, 1},   /* Trying size eight.  */
446
  };
447
 
448
  while (len > 0)
449
    {
450
      int align = addr % max_wp_len;
451
      /* Four (eight on AMD64) is the maximum length a debug register
452
         can watch.  */
453
      int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
454
      int size = size_try_array[try][align];
455
 
456
      if (what == WP_COUNT)
457
        {
458
          /* size_try_array[] is defined such that each iteration
459
             through the loop is guaranteed to produce an address and a
460
             size that can be watched with a single debug register.
461
             Thus, for counting the registers required to watch a
462
             region, we simply need to increment the count on each
463
             iteration.  */
464
          retval++;
465
        }
466
      else
467
        {
468
          unsigned len_rw = i386_length_and_rw_bits (size, type);
469
 
470
          if (what == WP_INSERT)
471
            status = i386_insert_aligned_watchpoint (addr, len_rw);
472
          else if (what == WP_REMOVE)
473
            status = i386_remove_aligned_watchpoint (addr, len_rw);
474
          else
475
            internal_error (__FILE__, __LINE__, _("\
476
Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"),
477
                            (int)what);
478
          /* We keep the loop going even after a failure, because some
479
             of the other aligned watchpoints might still succeed
480
             (e.g. if they watch addresses that are already watched,
481
             in which case we just increment the reference counts of
482
             occupied debug registers).  If we break out of the loop
483
             too early, we could cause those addresses watched by
484
             other watchpoints to be disabled when breakpoint.c reacts
485
             to our failure to insert this watchpoint and tries to
486
             remove it.  */
487
          if (status)
488
            retval = status;
489
        }
490
 
491
      addr += size;
492
      len -= size;
493
    }
494
 
495
  return retval;
496
}
497
 
498
/* Insert a watchpoint to watch a memory region which starts at
499
   address ADDR and whose length is LEN bytes.  Watch memory accesses
500
   of the type TYPE.  Return 0 on success, -1 on failure.  */
501
 
502
int
503
i386_insert_watchpoint (CORE_ADDR addr, int len, int type)
504
{
505
  int retval;
506
 
507
  if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8))
508
      || addr % len != 0)
509
    retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type);
510
  else
511
    {
512
      unsigned len_rw = i386_length_and_rw_bits (len, type);
513
 
514
      retval = i386_insert_aligned_watchpoint (addr, len_rw);
515
    }
516
 
517
  if (maint_show_dr)
518
    i386_show_dr ("insert_watchpoint", addr, len, type);
519
 
520
  return retval;
521
}
522
 
523
/* Remove a watchpoint that watched the memory region which starts at
524
   address ADDR, whose length is LEN bytes, and for accesses of the
525
   type TYPE.  Return 0 on success, -1 on failure.  */
526
int
527
i386_remove_watchpoint (CORE_ADDR addr, int len, int type)
528
{
529
  int retval;
530
 
531
  if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8))
532
      || addr % len != 0)
533
    retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type);
534
  else
535
    {
536
      unsigned len_rw = i386_length_and_rw_bits (len, type);
537
 
538
      retval = i386_remove_aligned_watchpoint (addr, len_rw);
539
    }
540
 
541
  if (maint_show_dr)
542
    i386_show_dr ("remove_watchpoint", addr, len, type);
543
 
544
  return retval;
545
}
546
 
547
/* Return non-zero if we can watch a memory region that starts at
548
   address ADDR and whose length is LEN bytes.  */
549
 
550
int
551
i386_region_ok_for_watchpoint (CORE_ADDR addr, int len)
552
{
553
  int nregs;
554
 
555
  /* Compute how many aligned watchpoints we would need to cover this
556
     region.  */
557
  nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len, hw_write);
558
  return nregs <= DR_NADDR ? 1 : 0;
559
}
560
 
561
/* If the inferior has some watchpoint that triggered, set the
562
   address associated with that watchpoint and return non-zero.
563
   Otherwise, return zero.  */
564
 
565
int
566
i386_stopped_data_address (CORE_ADDR *addr_p)
567
{
568
  CORE_ADDR addr = 0;
569
  int i;
570
  int rc = 0;
571
 
572
  dr_status_mirror = I386_DR_LOW_GET_STATUS ();
573
 
574
  ALL_DEBUG_REGISTERS(i)
575
    {
576
      if (I386_DR_WATCH_HIT (i)
577
          /* This second condition makes sure DRi is set up for a data
578
             watchpoint, not a hardware breakpoint.  The reason is
579
             that GDB doesn't call the target_stopped_data_address
580
             method except for data watchpoints.  In other words, I'm
581
             being paranoiac.  */
582
          && I386_DR_GET_RW_LEN (i) != 0)
583
        {
584
          addr = dr_mirror[i];
585
          rc = 1;
586
          if (maint_show_dr)
587
            i386_show_dr ("watchpoint_hit", addr, -1, hw_write);
588
        }
589
    }
590
  if (maint_show_dr && addr == 0)
591
    i386_show_dr ("stopped_data_addr", 0, 0, hw_write);
592
 
593
  if (rc)
594
    *addr_p = addr;
595
  return rc;
596
}
597
 
598
int
599
i386_stopped_by_watchpoint (void)
600
{
601
  CORE_ADDR addr = 0;
602
  return i386_stopped_data_address (&addr);
603
}
604
 
605
/* Return non-zero if the inferior has some break/watchpoint that
606
   triggered.  */
607
 
608
int
609
i386_stopped_by_hwbp (void)
610
{
611
  int i;
612
 
613
  dr_status_mirror = I386_DR_LOW_GET_STATUS ();
614
  if (maint_show_dr)
615
    i386_show_dr ("stopped_by_hwbp", 0, 0, hw_execute);
616
 
617
  ALL_DEBUG_REGISTERS(i)
618
    {
619
      if (I386_DR_WATCH_HIT (i))
620
        return 1;
621
    }
622
 
623
  return 0;
624
}
625
 
626
/* Insert a hardware-assisted breakpoint at BP_TGT->placed_address.
627
   Return 0 on success, EBUSY on failure.  */
628
int
629
i386_insert_hw_breakpoint (struct bp_target_info *bp_tgt)
630
{
631
  unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
632
  CORE_ADDR addr = bp_tgt->placed_address;
633
  int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0;
634
 
635
  if (maint_show_dr)
636
    i386_show_dr ("insert_hwbp", addr, 1, hw_execute);
637
 
638
  return retval;
639
}
640
 
641
/* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
642
   Return 0 on success, -1 on failure.  */
643
 
644
int
645
i386_remove_hw_breakpoint (struct bp_target_info *bp_tgt)
646
{
647
  unsigned len_rw = i386_length_and_rw_bits (1, hw_execute);
648
  CORE_ADDR addr = bp_tgt->placed_address;
649
  int retval = i386_remove_aligned_watchpoint (addr, len_rw);
650
 
651
  if (maint_show_dr)
652
    i386_show_dr ("remove_hwbp", addr, 1, hw_execute);
653
 
654
  return retval;
655
}
656
 
657
#endif /* I386_USE_GENERIC_WATCHPOINTS */
658
 
659
 
660
/* Provide a prototype to silence -Wmissing-prototypes.  */
661
void _initialize_i386_nat (void);
662
 
663
void
664
_initialize_i386_nat (void)
665
{
666
#ifdef I386_USE_GENERIC_WATCHPOINTS
667
  /* A maintenance command to enable printing the internal DRi mirror
668
     variables.  */
669
  deprecated_add_set_cmd ("show-debug-regs", class_maintenance,
670
                          var_boolean, (char *) &maint_show_dr, _("\
671
Set whether to show variables that mirror the x86 debug registers.\n\
672
Use \"on\" to enable, \"off\" to disable.\n\
673
If enabled, the debug registers values are shown when GDB inserts\n\
674
or removes a hardware breakpoint or watchpoint, and when the inferior\n\
675
triggers a breakpoint or watchpoint."),
676
                          &maintenancelist);
677
#endif
678
}

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