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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [gdb/] [m32c-tdep.c] - Blame information for rev 840

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1 24 jeremybenn
/* Renesas M32C target-dependent code for GDB, the GNU debugger.
2
 
3
   Copyright 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
4
 
5
   This file is part of GDB.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#include "defs.h"
21
 
22
#include <stdarg.h>
23
 
24
#if defined (HAVE_STRING_H)
25
#include <string.h>
26
#endif
27
 
28
#include "gdb_assert.h"
29
#include "elf-bfd.h"
30
#include "elf/m32c.h"
31
#include "gdb/sim-m32c.h"
32
#include "dis-asm.h"
33
#include "gdbtypes.h"
34
#include "regcache.h"
35
#include "arch-utils.h"
36
#include "frame.h"
37
#include "frame-unwind.h"
38
#include "dwarf2-frame.h"
39
#include "dwarf2expr.h"
40
#include "symtab.h"
41
#include "gdbcore.h"
42
#include "value.h"
43
#include "reggroups.h"
44
#include "prologue-value.h"
45
#include "target.h"
46
 
47
 
48
/* The m32c tdep structure.  */
49
 
50
static struct reggroup *m32c_dma_reggroup;
51
 
52
struct m32c_reg;
53
 
54
/* The type of a function that moves the value of REG between CACHE or
55
   BUF --- in either direction.  */
56
typedef void (m32c_move_reg_t) (struct m32c_reg *reg,
57
                                struct regcache *cache,
58
                                void *buf);
59
 
60
struct m32c_reg
61
{
62
  /* The name of this register.  */
63
  const char *name;
64
 
65
  /* Its type.  */
66
  struct type *type;
67
 
68
  /* The architecture this register belongs to.  */
69
  struct gdbarch *arch;
70
 
71
  /* Its GDB register number.  */
72
  int num;
73
 
74
  /* Its sim register number.  */
75
  int sim_num;
76
 
77
  /* Its DWARF register number, or -1 if it doesn't have one.  */
78
  int dwarf_num;
79
 
80
  /* Register group memberships.  */
81
  unsigned int general_p : 1;
82
  unsigned int dma_p : 1;
83
  unsigned int system_p : 1;
84
  unsigned int save_restore_p : 1;
85
 
86
  /* Functions to read its value from a regcache, and write its value
87
     to a regcache.  */
88
  m32c_move_reg_t *read, *write;
89
 
90
  /* Data for READ and WRITE functions.  The exact meaning depends on
91
     the specific functions selected; see the comments for those
92
     functions.  */
93
  struct m32c_reg *rx, *ry;
94
  int n;
95
};
96
 
97
 
98
/* An overestimate of the number of raw and pseudoregisters we will
99
   have.  The exact answer depends on the variant of the architecture
100
   at hand, but we can use this to declare statically allocated
101
   arrays, and bump it up when needed.  */
102
#define M32C_MAX_NUM_REGS (75)
103
 
104
/* The largest assigned DWARF register number.  */
105
#define M32C_MAX_DWARF_REGNUM (40)
106
 
107
 
108
struct gdbarch_tdep
109
{
110
  /* All the registers for this variant, indexed by GDB register
111
     number, and the number of registers present.  */
112
  struct m32c_reg regs[M32C_MAX_NUM_REGS];
113
 
114
  /* The number of valid registers.  */
115
  int num_regs;
116
 
117
  /* Interesting registers.  These are pointers into REGS.  */
118
  struct m32c_reg *pc, *flg;
119
  struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1;
120
  struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0;
121
  struct m32c_reg *sb, *fb, *sp;
122
 
123
  /* A table indexed by DWARF register numbers, pointing into
124
     REGS.  */
125
  struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1];
126
 
127
  /* Types for this architecture.  We can't use the builtin_type_foo
128
     types, because they're not initialized when building a gdbarch
129
     structure.  */
130
  struct type *voyd, *ptr_voyd, *func_voyd;
131
  struct type *uint8, *uint16;
132
  struct type *int8, *int16, *int32, *int64;
133
 
134
  /* The types for data address and code address registers.  */
135
  struct type *data_addr_reg_type, *code_addr_reg_type;
136
 
137
  /* The number of bytes a return address pushed by a 'jsr' instruction
138
     occupies on the stack.  */
139
  int ret_addr_bytes;
140
 
141
  /* The number of bytes an address register occupies on the stack
142
     when saved by an 'enter' or 'pushm' instruction.  */
143
  int push_addr_bytes;
144
};
145
 
146
 
147
/* Types.  */
148
 
149
static void
150
make_types (struct gdbarch *arch)
151
{
152
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
153
  unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
154
  int data_addr_reg_bits, code_addr_reg_bits;
155
  char type_name[50];
156
 
157
#if 0
158
  /* This is used to clip CORE_ADDR values, so this value is
159
     appropriate both on the m32c, where pointers are 32 bits long,
160
     and on the m16c, where pointers are sixteen bits long, but there
161
     may be code above the 64k boundary.  */
162
  set_gdbarch_addr_bit (arch, 24);
163
#else
164
  /* GCC uses 32 bits for addrs in the dwarf info, even though
165
     only 16/24 bits are used.  Setting addr_bit to 24 causes
166
     errors in reading the dwarf addresses.  */
167
  set_gdbarch_addr_bit (arch, 32);
168
#endif
169
 
170
  set_gdbarch_int_bit (arch, 16);
171
  switch (mach)
172
    {
173
    case bfd_mach_m16c:
174
      data_addr_reg_bits = 16;
175
      code_addr_reg_bits = 24;
176
      set_gdbarch_ptr_bit (arch, 16);
177
      tdep->ret_addr_bytes = 3;
178
      tdep->push_addr_bytes = 2;
179
      break;
180
 
181
    case bfd_mach_m32c:
182
      data_addr_reg_bits = 24;
183
      code_addr_reg_bits = 24;
184
      set_gdbarch_ptr_bit (arch, 32);
185
      tdep->ret_addr_bytes = 4;
186
      tdep->push_addr_bytes = 4;
187
      break;
188
 
189
    default:
190
      gdb_assert (0);
191
    }
192
 
193
  /* The builtin_type_mumble variables are sometimes uninitialized when
194
     this is called, so we avoid using them.  */
195
  tdep->voyd = init_type (TYPE_CODE_VOID, 1, 0, "void", NULL);
196
  tdep->ptr_voyd = init_type (TYPE_CODE_PTR, gdbarch_ptr_bit (arch) / 8,
197
                              TYPE_FLAG_UNSIGNED, NULL, NULL);
198
  TYPE_TARGET_TYPE (tdep->ptr_voyd) = tdep->voyd;
199
  tdep->func_voyd = lookup_function_type (tdep->voyd);
200
 
201
  sprintf (type_name, "%s_data_addr_t",
202
           gdbarch_bfd_arch_info (arch)->printable_name);
203
  tdep->data_addr_reg_type
204
    = init_type (TYPE_CODE_PTR, data_addr_reg_bits / 8,
205
                 TYPE_FLAG_UNSIGNED, xstrdup (type_name), NULL);
206
  TYPE_TARGET_TYPE (tdep->data_addr_reg_type) = tdep->voyd;
207
 
208
  sprintf (type_name, "%s_code_addr_t",
209
           gdbarch_bfd_arch_info (arch)->printable_name);
210
  tdep->code_addr_reg_type
211
    = init_type (TYPE_CODE_PTR, code_addr_reg_bits / 8,
212
                 TYPE_FLAG_UNSIGNED, xstrdup (type_name), NULL);
213
  TYPE_TARGET_TYPE (tdep->code_addr_reg_type) = tdep->func_voyd;
214
 
215
  tdep->uint8  = init_type (TYPE_CODE_INT, 1, TYPE_FLAG_UNSIGNED,
216
                            "uint8_t", NULL);
217
  tdep->uint16 = init_type (TYPE_CODE_INT, 2, TYPE_FLAG_UNSIGNED,
218
                            "uint16_t", NULL);
219
  tdep->int8   = init_type (TYPE_CODE_INT, 1, 0, "int8_t", NULL);
220
  tdep->int16  = init_type (TYPE_CODE_INT, 2, 0, "int16_t", NULL);
221
  tdep->int32  = init_type (TYPE_CODE_INT, 4, 0, "int32_t", NULL);
222
  tdep->int64  = init_type (TYPE_CODE_INT, 8, 0, "int64_t", NULL);
223
}
224
 
225
 
226
 
227
/* Register set.  */
228
 
229
static const char *
230
m32c_register_name (struct gdbarch *gdbarch, int num)
231
{
232
  return gdbarch_tdep (gdbarch)->regs[num].name;
233
}
234
 
235
 
236
static struct type *
237
m32c_register_type (struct gdbarch *arch, int reg_nr)
238
{
239
  return gdbarch_tdep (arch)->regs[reg_nr].type;
240
}
241
 
242
 
243
static int
244
m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr)
245
{
246
  return gdbarch_tdep (gdbarch)->regs[reg_nr].sim_num;
247
}
248
 
249
 
250
static int
251
m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr)
252
{
253
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
254
  if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM
255
      && tdep->dwarf_regs[reg_nr])
256
    return tdep->dwarf_regs[reg_nr]->num;
257
  else
258
    /* The DWARF CFI code expects to see -1 for invalid register
259
       numbers.  */
260
    return -1;
261
}
262
 
263
 
264
int
265
m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
266
                          struct reggroup *group)
267
{
268
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
269
  struct m32c_reg *reg = &tdep->regs[regnum];
270
 
271
  /* The anonymous raw registers aren't in any groups.  */
272
  if (! reg->name)
273
    return 0;
274
 
275
  if (group == all_reggroup)
276
    return 1;
277
 
278
  if (group == general_reggroup
279
      && reg->general_p)
280
    return 1;
281
 
282
  if (group == m32c_dma_reggroup
283
      && reg->dma_p)
284
    return 1;
285
 
286
  if (group == system_reggroup
287
      && reg->system_p)
288
    return 1;
289
 
290
  /* Since the m32c DWARF register numbers refer to cooked registers, not
291
     raw registers, and frame_pop depends on the save and restore groups
292
     containing registers the DWARF CFI will actually mention, our save
293
     and restore groups are cooked registers, not raw registers.  (This is
294
     why we can't use the default reggroup function.)  */
295
  if ((group == save_reggroup
296
       || group == restore_reggroup)
297
      && reg->save_restore_p)
298
    return 1;
299
 
300
  return 0;
301
}
302
 
303
 
304
/* Register move functions.  We declare them here using
305
   m32c_move_reg_t to check the types.  */
306
static m32c_move_reg_t m32c_raw_read,      m32c_raw_write;
307
static m32c_move_reg_t m32c_banked_read,   m32c_banked_write;
308
static m32c_move_reg_t m32c_sb_read,       m32c_sb_write;
309
static m32c_move_reg_t m32c_part_read,     m32c_part_write;
310
static m32c_move_reg_t m32c_cat_read,      m32c_cat_write;
311
static m32c_move_reg_t m32c_r3r2r1r0_read, m32c_r3r2r1r0_write;
312
 
313
 
314
/* Copy the value of the raw register REG from CACHE to BUF.  */
315
static void
316
m32c_raw_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
317
{
318
  regcache_raw_read (cache, reg->num, buf);
319
}
320
 
321
 
322
/* Copy the value of the raw register REG from BUF to CACHE.  */
323
static void
324
m32c_raw_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
325
{
326
  regcache_raw_write (cache, reg->num, (const void *) buf);
327
}
328
 
329
 
330
/* Return the value of the 'flg' register in CACHE.  */
331
static int
332
m32c_read_flg (struct regcache *cache)
333
{
334
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (cache));
335
  ULONGEST flg;
336
  regcache_raw_read_unsigned (cache, tdep->flg->num, &flg);
337
  return flg & 0xffff;
338
}
339
 
340
 
341
/* Evaluate the real register number of a banked register.  */
342
static struct m32c_reg *
343
m32c_banked_register (struct m32c_reg *reg, struct regcache *cache)
344
{
345
  return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx);
346
}
347
 
348
 
349
/* Move the value of a banked register from CACHE to BUF.
350
   If the value of the 'flg' register in CACHE has any of the bits
351
   masked in REG->n set, then read REG->ry.  Otherwise, read
352
   REG->rx.  */
353
static void
354
m32c_banked_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
355
{
356
  struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
357
  regcache_raw_read (cache, bank_reg->num, buf);
358
}
359
 
360
 
361
/* Move the value of a banked register from BUF to CACHE.
362
   If the value of the 'flg' register in CACHE has any of the bits
363
   masked in REG->n set, then write REG->ry.  Otherwise, write
364
   REG->rx.  */
365
static void
366
m32c_banked_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
367
{
368
  struct m32c_reg *bank_reg = m32c_banked_register (reg, cache);
369
  regcache_raw_write (cache, bank_reg->num, (const void *) buf);
370
}
371
 
372
 
373
/* Move the value of SB from CACHE to BUF.  On bfd_mach_m32c, SB is a
374
   banked register; on bfd_mach_m16c, it's not.  */
375
static void
376
m32c_sb_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
377
{
378
  if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
379
    m32c_raw_read (reg->rx, cache, buf);
380
  else
381
    m32c_banked_read (reg, cache, buf);
382
}
383
 
384
 
385
/* Move the value of SB from BUF to CACHE.  On bfd_mach_m32c, SB is a
386
   banked register; on bfd_mach_m16c, it's not.  */
387
static void
388
m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
389
{
390
  if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c)
391
    m32c_raw_write (reg->rx, cache, buf);
392
  else
393
    m32c_banked_write (reg, cache, buf);
394
}
395
 
396
 
397
/* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P
398
   and *LEN_P to the offset and length, in bytes, of the part REG
399
   occupies in its underlying register.  The offset is from the
400
   lower-addressed end, regardless of the architecture's endianness.
401
   (The M32C family is always little-endian, but let's keep those
402
   assumptions out of here.)  */
403
static void
404
m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p)
405
{
406
  /* The length of the containing register, of which REG is one part.  */
407
  int containing_len = TYPE_LENGTH (reg->rx->type);
408
 
409
  /* The length of one "element" in our imaginary array.  */
410
  int elt_len = TYPE_LENGTH (reg->type);
411
 
412
  /* The offset of REG's "element" from the least significant end of
413
     the containing register.  */
414
  int elt_offset = reg->n * elt_len;
415
 
416
  /* If we extend off the end, trim the length of the element.  */
417
  if (elt_offset + elt_len > containing_len)
418
    {
419
      elt_len = containing_len - elt_offset;
420
      /* We shouldn't be declaring partial registers that go off the
421
         end of their containing registers.  */
422
      gdb_assert (elt_len > 0);
423
    }
424
 
425
  /* Flip the offset around if we're big-endian.  */
426
  if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
427
    elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len;
428
 
429
  *offset_p = elt_offset;
430
  *len_p = elt_len;
431
}
432
 
433
 
434
/* Move the value of a partial register (r0h, intbl, etc.) from CACHE
435
   to BUF.  Treating the value of the register REG->rx as an array of
436
   REG->type values, where higher indices refer to more significant
437
   bits, read the value of the REG->n'th element.  */
438
static void
439
m32c_part_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
440
{
441
  int offset, len;
442
  memset (buf, 0, TYPE_LENGTH (reg->type));
443
  m32c_find_part (reg, &offset, &len);
444
  regcache_cooked_read_part (cache, reg->rx->num, offset, len, buf);
445
}
446
 
447
 
448
/* Move the value of a banked register from BUF to CACHE.
449
   Treating the value of the register REG->rx as an array of REG->type
450
   values, where higher indices refer to more significant bits, write
451
   the value of the REG->n'th element.  */
452
static void
453
m32c_part_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
454
{
455
  int offset, len;
456
  m32c_find_part (reg, &offset, &len);
457
  regcache_cooked_write_part (cache, reg->rx->num, offset, len, buf);
458
}
459
 
460
 
461
/* Move the value of REG from CACHE to BUF.  REG's value is the
462
   concatenation of the values of the registers REG->rx and REG->ry,
463
   with REG->rx contributing the more significant bits.  */
464
static void
465
m32c_cat_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
466
{
467
  int high_bytes = TYPE_LENGTH (reg->rx->type);
468
  int low_bytes  = TYPE_LENGTH (reg->ry->type);
469
  /* For address arithmetic.  */
470
  unsigned char *cbuf = buf;
471
 
472
  gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
473
 
474
  if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
475
    {
476
      regcache_cooked_read (cache, reg->rx->num, cbuf);
477
      regcache_cooked_read (cache, reg->ry->num, cbuf + high_bytes);
478
    }
479
  else
480
    {
481
      regcache_cooked_read (cache, reg->rx->num, cbuf + low_bytes);
482
      regcache_cooked_read (cache, reg->ry->num, cbuf);
483
    }
484
}
485
 
486
 
487
/* Move the value of REG from CACHE to BUF.  REG's value is the
488
   concatenation of the values of the registers REG->rx and REG->ry,
489
   with REG->rx contributing the more significant bits.  */
490
static void
491
m32c_cat_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
492
{
493
  int high_bytes = TYPE_LENGTH (reg->rx->type);
494
  int low_bytes  = TYPE_LENGTH (reg->ry->type);
495
  /* For address arithmetic.  */
496
  unsigned char *cbuf = buf;
497
 
498
  gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes);
499
 
500
  if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
501
    {
502
      regcache_cooked_write (cache, reg->rx->num, cbuf);
503
      regcache_cooked_write (cache, reg->ry->num, cbuf + high_bytes);
504
    }
505
  else
506
    {
507
      regcache_cooked_write (cache, reg->rx->num, cbuf + low_bytes);
508
      regcache_cooked_write (cache, reg->ry->num, cbuf);
509
    }
510
}
511
 
512
 
513
/* Copy the value of the raw register REG from CACHE to BUF.  REG is
514
   the concatenation (from most significant to least) of r3, r2, r1,
515
   and r0.  */
516
static void
517
m32c_r3r2r1r0_read (struct m32c_reg *reg, struct regcache *cache, void *buf)
518
{
519
  struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
520
  int len = TYPE_LENGTH (tdep->r0->type);
521
 
522
  /* For address arithmetic.  */
523
  unsigned char *cbuf = buf;
524
 
525
  if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
526
    {
527
      regcache_cooked_read (cache, tdep->r0->num, cbuf + len * 3);
528
      regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 2);
529
      regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 1);
530
      regcache_cooked_read (cache, tdep->r3->num, cbuf);
531
    }
532
  else
533
    {
534
      regcache_cooked_read (cache, tdep->r0->num, cbuf);
535
      regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 1);
536
      regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 2);
537
      regcache_cooked_read (cache, tdep->r3->num, cbuf + len * 3);
538
    }
539
}
540
 
541
 
542
/* Copy the value of the raw register REG from BUF to CACHE.  REG is
543
   the concatenation (from most significant to least) of r3, r2, r1,
544
   and r0.  */
545
static void
546
m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache, void *buf)
547
{
548
  struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch);
549
  int len = TYPE_LENGTH (tdep->r0->type);
550
 
551
  /* For address arithmetic.  */
552
  unsigned char *cbuf = buf;
553
 
554
  if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG)
555
    {
556
      regcache_cooked_write (cache, tdep->r0->num, cbuf + len * 3);
557
      regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 2);
558
      regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 1);
559
      regcache_cooked_write (cache, tdep->r3->num, cbuf);
560
    }
561
  else
562
    {
563
      regcache_cooked_write (cache, tdep->r0->num, cbuf);
564
      regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 1);
565
      regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 2);
566
      regcache_cooked_write (cache, tdep->r3->num, cbuf + len * 3);
567
    }
568
}
569
 
570
 
571
static void
572
m32c_pseudo_register_read (struct gdbarch *arch,
573
                           struct regcache *cache,
574
                           int cookednum,
575
                           gdb_byte *buf)
576
{
577
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
578
  struct m32c_reg *reg;
579
 
580
  gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
581
  gdb_assert (arch == get_regcache_arch (cache));
582
  gdb_assert (arch == tdep->regs[cookednum].arch);
583
  reg = &tdep->regs[cookednum];
584
 
585
  reg->read (reg, cache, buf);
586
}
587
 
588
 
589
static void
590
m32c_pseudo_register_write (struct gdbarch *arch,
591
                            struct regcache *cache,
592
                            int cookednum,
593
                            const gdb_byte *buf)
594
{
595
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
596
  struct m32c_reg *reg;
597
 
598
  gdb_assert (0 <= cookednum && cookednum < tdep->num_regs);
599
  gdb_assert (arch == get_regcache_arch (cache));
600
  gdb_assert (arch == tdep->regs[cookednum].arch);
601
  reg = &tdep->regs[cookednum];
602
 
603
  reg->write (reg, cache, (void *) buf);
604
}
605
 
606
 
607
/* Add a register with the given fields to the end of ARCH's table.
608
   Return a pointer to the newly added register.  */
609
static struct m32c_reg *
610
add_reg (struct gdbarch *arch,
611
         const char *name,
612
         struct type *type,
613
         int sim_num,
614
         m32c_move_reg_t *read,
615
         m32c_move_reg_t *write,
616
         struct m32c_reg *rx,
617
         struct m32c_reg *ry,
618
         int n)
619
{
620
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
621
  struct m32c_reg *r = &tdep->regs[tdep->num_regs];
622
 
623
  gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS);
624
 
625
  r->name           = name;
626
  r->type           = type;
627
  r->arch           = arch;
628
  r->num            = tdep->num_regs;
629
  r->sim_num        = sim_num;
630
  r->dwarf_num      = -1;
631
  r->general_p      = 0;
632
  r->dma_p          = 0;
633
  r->system_p       = 0;
634
  r->save_restore_p = 0;
635
  r->read           = read;
636
  r->write          = write;
637
  r->rx             = rx;
638
  r->ry             = ry;
639
  r->n              = n;
640
 
641
  tdep->num_regs++;
642
 
643
  return r;
644
}
645
 
646
 
647
/* Record NUM as REG's DWARF register number.  */
648
static void
649
set_dwarf_regnum (struct m32c_reg *reg, int num)
650
{
651
  gdb_assert (num < M32C_MAX_NUM_REGS);
652
 
653
  /* Update the reg->DWARF mapping.  Only count the first number
654
     assigned to this register.  */
655
  if (reg->dwarf_num == -1)
656
    reg->dwarf_num = num;
657
 
658
  /* Update the DWARF->reg mapping.  */
659
  gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg;
660
}
661
 
662
 
663
/* Mark REG as a general-purpose register, and return it.  */
664
static struct m32c_reg *
665
mark_general (struct m32c_reg *reg)
666
{
667
  reg->general_p = 1;
668
  return reg;
669
}
670
 
671
 
672
/* Mark REG as a DMA register, and return it.  */
673
static struct m32c_reg *
674
mark_dma (struct m32c_reg *reg)
675
{
676
  reg->dma_p = 1;
677
  return reg;
678
}
679
 
680
 
681
/* Mark REG as a SYSTEM register, and return it.  */
682
static struct m32c_reg *
683
mark_system (struct m32c_reg *reg)
684
{
685
  reg->system_p = 1;
686
  return reg;
687
}
688
 
689
 
690
/* Mark REG as a save-restore register, and return it.  */
691
static struct m32c_reg *
692
mark_save_restore (struct m32c_reg *reg)
693
{
694
  reg->save_restore_p = 1;
695
  return reg;
696
}
697
 
698
 
699
#define FLAGBIT_B       0x0010
700
#define FLAGBIT_U       0x0080
701
 
702
/* Handy macros for declaring registers.  These all evaluate to
703
   pointers to the register declared.  Macros that define two
704
   registers evaluate to a pointer to the first.  */
705
 
706
/* A raw register named NAME, with type TYPE and sim number SIM_NUM.  */
707
#define R(name, type, sim_num)                                  \
708
  (add_reg (arch, (name), (type), (sim_num),                    \
709
            m32c_raw_read, m32c_raw_write, NULL, NULL, 0))
710
 
711
/* The simulator register number for a raw register named NAME.  */
712
#define SIM(name) (m32c_sim_reg_ ## name)
713
 
714
/* A raw unsigned 16-bit data register named NAME.
715
   NAME should be an identifier, not a string.  */
716
#define R16U(name)                                              \
717
  (R(#name, tdep->uint16, SIM (name)))
718
 
719
/* A raw data address register named NAME.
720
   NAME should be an identifier, not a string.  */
721
#define RA(name)                                                \
722
  (R(#name, tdep->data_addr_reg_type, SIM (name)))
723
 
724
/* A raw code address register named NAME.  NAME should
725
   be an identifier, not a string.  */
726
#define RC(name)                                                \
727
  (R(#name, tdep->code_addr_reg_type, SIM (name)))
728
 
729
/* A pair of raw registers named NAME0 and NAME1, with type TYPE.
730
   NAME should be an identifier, not a string.  */
731
#define RP(name, type)                          \
732
  (R(#name "0", (type), SIM (name ## 0)),        \
733
   R(#name "1", (type), SIM (name ## 1)) - 1)
734
 
735
/* A raw banked general-purpose data register named NAME.
736
   NAME should be an identifier, not a string.  */
737
#define RBD(name)                                               \
738
  (R(NULL, tdep->int16, SIM (name ## _bank0)),          \
739
   R(NULL, tdep->int16, SIM (name ## _bank1)) - 1)
740
 
741
/* A raw banked data address register named NAME.
742
   NAME should be an identifier, not a string.  */
743
#define RBA(name)                                               \
744
  (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)),     \
745
   R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1)
746
 
747
/* A cooked register named NAME referring to a raw banked register
748
   from the bank selected by the current value of FLG.  RAW_PAIR
749
   should be a pointer to the first register in the banked pair.
750
   NAME must be an identifier, not a string.  */
751
#define CB(name, raw_pair)                              \
752
  (add_reg (arch, #name, (raw_pair)->type, 0,           \
753
            m32c_banked_read, m32c_banked_write,        \
754
            (raw_pair), (raw_pair + 1), FLAGBIT_B))
755
 
756
/* A pair of registers named NAMEH and NAMEL, of type TYPE, that
757
   access the top and bottom halves of the register pointed to by
758
   NAME.  NAME should be an identifier.  */
759
#define CHL(name, type)                                                 \
760
  (add_reg (arch, #name "h", (type), 0,                                 \
761
            m32c_part_read, m32c_part_write, name, NULL, 1),            \
762
   add_reg (arch, #name "l", (type), 0,                                 \
763
            m32c_part_read, m32c_part_write, name, NULL, 0) - 1)
764
 
765
/* A register constructed by concatenating the two registers HIGH and
766
   LOW, whose name is HIGHLOW and whose type is TYPE.  */
767
#define CCAT(high, low, type)                                   \
768
  (add_reg (arch, #high #low, (type), 0,                        \
769
            m32c_cat_read, m32c_cat_write, (high), (low), 0))
770
 
771
/* Abbreviations for marking register group membership.  */
772
#define G(reg)   (mark_general (reg))
773
#define S(reg)   (mark_system  (reg))
774
#define DMA(reg) (mark_dma     (reg))
775
 
776
 
777
/* Construct the register set for ARCH.  */
778
static void
779
make_regs (struct gdbarch *arch)
780
{
781
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
782
  int mach = gdbarch_bfd_arch_info (arch)->mach;
783
  int num_raw_regs;
784
  int num_cooked_regs;
785
 
786
  struct m32c_reg *r0;
787
  struct m32c_reg *r1;
788
  struct m32c_reg *r2;
789
  struct m32c_reg *r3;
790
  struct m32c_reg *a0;
791
  struct m32c_reg *a1;
792
  struct m32c_reg *fb;
793
  struct m32c_reg *sb;
794
  struct m32c_reg *sp;
795
  struct m32c_reg *r0hl;
796
  struct m32c_reg *r1hl;
797
  struct m32c_reg *r2hl;
798
  struct m32c_reg *r3hl;
799
  struct m32c_reg *intbhl;
800
  struct m32c_reg *r2r0;
801
  struct m32c_reg *r3r1;
802
  struct m32c_reg *r3r1r2r0;
803
  struct m32c_reg *r3r2r1r0;
804
  struct m32c_reg *a1a0;
805
 
806
  struct m32c_reg *raw_r0_pair = RBD (r0);
807
  struct m32c_reg *raw_r1_pair = RBD (r1);
808
  struct m32c_reg *raw_r2_pair = RBD (r2);
809
  struct m32c_reg *raw_r3_pair = RBD (r3);
810
  struct m32c_reg *raw_a0_pair = RBA (a0);
811
  struct m32c_reg *raw_a1_pair = RBA (a1);
812
  struct m32c_reg *raw_fb_pair = RBA (fb);
813
 
814
  /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
815
     We always declare both raw registers, and deal with the distinction
816
     in the pseudoregister.  */
817
  struct m32c_reg *raw_sb_pair = RBA (sb);
818
 
819
  struct m32c_reg *usp         = S (RA (usp));
820
  struct m32c_reg *isp         = S (RA (isp));
821
  struct m32c_reg *intb        = S (RC (intb));
822
  struct m32c_reg *pc          = G (RC (pc));
823
  struct m32c_reg *flg         = G (R16U (flg));
824
 
825
  if (mach == bfd_mach_m32c)
826
    {
827
      struct m32c_reg *svf     = S (R16U (svf));
828
      struct m32c_reg *svp     = S (RC (svp));
829
      struct m32c_reg *vct     = S (RC (vct));
830
 
831
      struct m32c_reg *dmd01   = DMA (RP (dmd, tdep->uint8));
832
      struct m32c_reg *dct01   = DMA (RP (dct, tdep->uint16));
833
      struct m32c_reg *drc01   = DMA (RP (drc, tdep->uint16));
834
      struct m32c_reg *dma01   = DMA (RP (dma, tdep->data_addr_reg_type));
835
      struct m32c_reg *dsa01   = DMA (RP (dsa, tdep->data_addr_reg_type));
836
      struct m32c_reg *dra01   = DMA (RP (dra, tdep->data_addr_reg_type));
837
    }
838
 
839
  num_raw_regs = tdep->num_regs;
840
 
841
  r0          = G (CB (r0, raw_r0_pair));
842
  r1          = G (CB (r1, raw_r1_pair));
843
  r2          = G (CB (r2, raw_r2_pair));
844
  r3          = G (CB (r3, raw_r3_pair));
845
  a0          = G (CB (a0, raw_a0_pair));
846
  a1          = G (CB (a1, raw_a1_pair));
847
  fb          = G (CB (fb, raw_fb_pair));
848
 
849
  /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c.
850
     Specify custom read/write functions that do the right thing.  */
851
  sb          = G (add_reg (arch, "sb", raw_sb_pair->type, 0,
852
                            m32c_sb_read, m32c_sb_write,
853
                            raw_sb_pair, raw_sb_pair + 1, 0));
854
 
855
  /* The current sp is either usp or isp, depending on the value of
856
     the FLG register's U bit.  */
857
  sp          = G (add_reg (arch, "sp", usp->type, 0,
858
                            m32c_banked_read, m32c_banked_write,
859
                            isp, usp, FLAGBIT_U));
860
 
861
  r0hl        = CHL (r0, tdep->int8);
862
  r1hl        = CHL (r1, tdep->int8);
863
  r2hl        = CHL (r2, tdep->int8);
864
  r3hl        = CHL (r3, tdep->int8);
865
  intbhl      = CHL (intb, tdep->int16);
866
 
867
  r2r0        = CCAT (r2,   r0,   tdep->int32);
868
  r3r1        = CCAT (r3,   r1,   tdep->int32);
869
  r3r1r2r0    = CCAT (r3r1, r2r0, tdep->int64);
870
 
871
  r3r2r1r0
872
    = add_reg (arch, "r3r2r1r0", tdep->int64, 0,
873
               m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0);
874
 
875
  if (mach == bfd_mach_m16c)
876
    a1a0 = CCAT (a1, a0, tdep->int32);
877
  else
878
    a1a0 = NULL;
879
 
880
  num_cooked_regs = tdep->num_regs - num_raw_regs;
881
 
882
  tdep->pc       = pc;
883
  tdep->flg      = flg;
884
  tdep->r0       = r0;
885
  tdep->r1       = r1;
886
  tdep->r2       = r2;
887
  tdep->r3       = r3;
888
  tdep->r2r0     = r2r0;
889
  tdep->r3r2r1r0 = r3r2r1r0;
890
  tdep->r3r1r2r0 = r3r1r2r0;
891
  tdep->a0       = a0;
892
  tdep->a1       = a1;
893
  tdep->sb       = sb;
894
  tdep->fb       = fb;
895
  tdep->sp       = sp;
896
 
897
  /* Set up the DWARF register table.  */
898
  memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs));
899
  set_dwarf_regnum (r0hl + 1, 0x01);
900
  set_dwarf_regnum (r0hl + 0, 0x02);
901
  set_dwarf_regnum (r1hl + 1, 0x03);
902
  set_dwarf_regnum (r1hl + 0, 0x04);
903
  set_dwarf_regnum (r0,       0x05);
904
  set_dwarf_regnum (r1,       0x06);
905
  set_dwarf_regnum (r2,       0x07);
906
  set_dwarf_regnum (r3,       0x08);
907
  set_dwarf_regnum (a0,       0x09);
908
  set_dwarf_regnum (a1,       0x0a);
909
  set_dwarf_regnum (fb,       0x0b);
910
  set_dwarf_regnum (sp,       0x0c);
911
  set_dwarf_regnum (pc,       0x0d); /* GCC's invention */
912
  set_dwarf_regnum (sb,       0x13);
913
  set_dwarf_regnum (r2r0,     0x15);
914
  set_dwarf_regnum (r3r1,     0x16);
915
  if (a1a0)
916
    set_dwarf_regnum (a1a0,   0x17);
917
 
918
  /* Enumerate the save/restore register group.
919
 
920
     The regcache_save and regcache_restore functions apply their read
921
     function to each register in this group.
922
 
923
     Since frame_pop supplies frame_unwind_register as its read
924
     function, the registers meaningful to the Dwarf unwinder need to
925
     be in this group.
926
 
927
     On the other hand, when we make inferior calls, save_inferior_status
928
     and restore_inferior_status use them to preserve the current register
929
     values across the inferior call.  For this, you'd kind of like to
930
     preserve all the raw registers, to protect the interrupted code from
931
     any sort of bank switching the callee might have done.  But we handle
932
     those cases so badly anyway --- for example, it matters whether we
933
     restore FLG before or after we restore the general-purpose registers,
934
     but there's no way to express that --- that it isn't worth worrying
935
     about.
936
 
937
     We omit control registers like inthl: if you call a function that
938
     changes those, it's probably because you wanted that change to be
939
     visible to the interrupted code.  */
940
  mark_save_restore (r0);
941
  mark_save_restore (r1);
942
  mark_save_restore (r2);
943
  mark_save_restore (r3);
944
  mark_save_restore (a0);
945
  mark_save_restore (a1);
946
  mark_save_restore (sb);
947
  mark_save_restore (fb);
948
  mark_save_restore (sp);
949
  mark_save_restore (pc);
950
  mark_save_restore (flg);
951
 
952
  set_gdbarch_num_regs (arch, num_raw_regs);
953
  set_gdbarch_num_pseudo_regs (arch, num_cooked_regs);
954
  set_gdbarch_pc_regnum (arch, pc->num);
955
  set_gdbarch_sp_regnum (arch, sp->num);
956
  set_gdbarch_register_name (arch, m32c_register_name);
957
  set_gdbarch_register_type (arch, m32c_register_type);
958
  set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read);
959
  set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write);
960
  set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno);
961
  set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
962
  set_gdbarch_dwarf_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
963
  set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum);
964
  set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p);
965
 
966
  reggroup_add (arch, general_reggroup);
967
  reggroup_add (arch, all_reggroup);
968
  reggroup_add (arch, save_reggroup);
969
  reggroup_add (arch, restore_reggroup);
970
  reggroup_add (arch, system_reggroup);
971
  reggroup_add (arch, m32c_dma_reggroup);
972
}
973
 
974
 
975
 
976
/* Breakpoints.  */
977
 
978
static const unsigned char *
979
m32c_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
980
{
981
  static unsigned char break_insn[] = { 0x00 }; /* brk */
982
 
983
  *len = sizeof (break_insn);
984
  return break_insn;
985
}
986
 
987
 
988
 
989
/* Prologue analysis.  */
990
 
991
struct m32c_prologue
992
{
993
  /* For consistency with the DWARF 2 .debug_frame info generated by
994
     GCC, a frame's CFA is the address immediately after the saved
995
     return address.  */
996
 
997
  /* The architecture for which we generated this prologue info.  */
998
  struct gdbarch *arch;
999
 
1000
  enum {
1001
    /* This function uses a frame pointer.  */
1002
    prologue_with_frame_ptr,
1003
 
1004
    /* This function has no frame pointer.  */
1005
    prologue_sans_frame_ptr,
1006
 
1007
    /* This function sets up the stack, so its frame is the first
1008
       frame on the stack.  */
1009
    prologue_first_frame
1010
 
1011
  } kind;
1012
 
1013
  /* If KIND is prologue_with_frame_ptr, this is the offset from the
1014
     CFA to where the frame pointer points.  This is always zero or
1015
     negative.  */
1016
  LONGEST frame_ptr_offset;
1017
 
1018
  /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to
1019
     the stack pointer --- always zero or negative.
1020
 
1021
     Calling this a "size" is a bit misleading, but given that the
1022
     stack grows downwards, using offsets for everything keeps one
1023
     from going completely sign-crazy: you never change anything's
1024
     sign for an ADD instruction; always change the second operand's
1025
     sign for a SUB instruction; and everything takes care of
1026
     itself.
1027
 
1028
     Functions that use alloca don't have a constant frame size.  But
1029
     they always have frame pointers, so we must use that to find the
1030
     CFA (and perhaps to unwind the stack pointer).  */
1031
  LONGEST frame_size;
1032
 
1033
  /* The address of the first instruction at which the frame has been
1034
     set up and the arguments are where the debug info says they are
1035
     --- as best as we can tell.  */
1036
  CORE_ADDR prologue_end;
1037
 
1038
  /* reg_offset[R] is the offset from the CFA at which register R is
1039
     saved, or 1 if register R has not been saved.  (Real values are
1040
     always zero or negative.)  */
1041
  LONGEST reg_offset[M32C_MAX_NUM_REGS];
1042
};
1043
 
1044
 
1045
/* The longest I've seen, anyway.  */
1046
#define M32C_MAX_INSN_LEN (9)
1047
 
1048
/* Processor state, for the prologue analyzer.  */
1049
struct m32c_pv_state
1050
{
1051
  struct gdbarch *arch;
1052
  pv_t r0, r1, r2, r3;
1053
  pv_t a0, a1;
1054
  pv_t sb, fb, sp;
1055
  pv_t pc;
1056
  struct pv_area *stack;
1057
 
1058
  /* Bytes from the current PC, the address they were read from,
1059
     and the address of the next unconsumed byte.  */
1060
  gdb_byte insn[M32C_MAX_INSN_LEN];
1061
  CORE_ADDR scan_pc, next_addr;
1062
};
1063
 
1064
 
1065
/* Push VALUE on STATE's stack, occupying SIZE bytes.  Return zero if
1066
   all went well, or non-zero if simulating the action would trash our
1067
   state.  */
1068
static int
1069
m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size)
1070
{
1071
  if (pv_area_store_would_trash (state->stack, state->sp))
1072
    return 1;
1073
 
1074
  state->sp = pv_add_constant (state->sp, -size);
1075
  pv_area_store (state->stack, state->sp, size, value);
1076
 
1077
  return 0;
1078
}
1079
 
1080
 
1081
/* A source or destination location for an m16c or m32c
1082
   instruction.  */
1083
struct srcdest
1084
{
1085
  /* If srcdest_reg, the location is a register pointed to by REG.
1086
     If srcdest_partial_reg, the location is part of a register pointed
1087
     to by REG.  We don't try to handle this too well.
1088
     If srcdest_mem, the location is memory whose address is ADDR.  */
1089
  enum { srcdest_reg, srcdest_partial_reg, srcdest_mem } kind;
1090
  pv_t *reg, addr;
1091
};
1092
 
1093
 
1094
/* Return the SIZE-byte value at LOC in STATE.  */
1095
static pv_t
1096
m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size)
1097
{
1098
  if (loc.kind == srcdest_mem)
1099
    return pv_area_fetch (state->stack, loc.addr, size);
1100
  else if (loc.kind == srcdest_partial_reg)
1101
    return pv_unknown ();
1102
  else
1103
    return *loc.reg;
1104
}
1105
 
1106
 
1107
/* Write VALUE, a SIZE-byte value, to LOC in STATE.  Return zero if
1108
   all went well, or non-zero if simulating the store would trash our
1109
   state.  */
1110
static int
1111
m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc,
1112
                    pv_t value, int size)
1113
{
1114
  if (loc.kind == srcdest_mem)
1115
    {
1116
      if (pv_area_store_would_trash (state->stack, loc.addr))
1117
        return 1;
1118
      pv_area_store (state->stack, loc.addr, size, value);
1119
    }
1120
  else if (loc.kind == srcdest_partial_reg)
1121
    *loc.reg = pv_unknown ();
1122
  else
1123
    *loc.reg = value;
1124
 
1125
  return 0;
1126
}
1127
 
1128
 
1129
static int
1130
m32c_sign_ext (int v, int bits)
1131
{
1132
  int mask = 1 << (bits - 1);
1133
  return (v ^ mask) - mask;
1134
}
1135
 
1136
static unsigned int
1137
m32c_next_byte (struct m32c_pv_state *st)
1138
{
1139
  gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn));
1140
  return st->insn[st->next_addr++ - st->scan_pc];
1141
}
1142
 
1143
static int
1144
m32c_udisp8 (struct m32c_pv_state *st)
1145
{
1146
  return m32c_next_byte (st);
1147
}
1148
 
1149
 
1150
static int
1151
m32c_sdisp8 (struct m32c_pv_state *st)
1152
{
1153
  return m32c_sign_ext (m32c_next_byte (st), 8);
1154
}
1155
 
1156
 
1157
static int
1158
m32c_udisp16 (struct m32c_pv_state *st)
1159
{
1160
  int low  = m32c_next_byte (st);
1161
  int high = m32c_next_byte (st);
1162
 
1163
  return low + (high << 8);
1164
}
1165
 
1166
 
1167
static int
1168
m32c_sdisp16 (struct m32c_pv_state *st)
1169
{
1170
  int low  = m32c_next_byte (st);
1171
  int high = m32c_next_byte (st);
1172
 
1173
  return m32c_sign_ext (low + (high << 8), 16);
1174
}
1175
 
1176
 
1177
static int
1178
m32c_udisp24 (struct m32c_pv_state *st)
1179
{
1180
  int low  = m32c_next_byte (st);
1181
  int mid  = m32c_next_byte (st);
1182
  int high = m32c_next_byte (st);
1183
 
1184
  return low + (mid << 8) + (high << 16);
1185
}
1186
 
1187
 
1188
/* Extract the 'source' field from an m32c MOV.size:G-format instruction.  */
1189
static int
1190
m32c_get_src23 (unsigned char *i)
1191
{
1192
  return (((i[0] & 0x70) >> 2)
1193
          | ((i[1] & 0x30) >> 4));
1194
}
1195
 
1196
 
1197
/* Extract the 'dest' field from an m32c MOV.size:G-format instruction.  */
1198
static int
1199
m32c_get_dest23 (unsigned char *i)
1200
{
1201
  return (((i[0] & 0x0e) << 1)
1202
          | ((i[1] & 0xc0) >> 6));
1203
}
1204
 
1205
 
1206
static struct srcdest
1207
m32c_decode_srcdest4 (struct m32c_pv_state *st,
1208
                      int code, int size)
1209
{
1210
  struct srcdest sd;
1211
 
1212
  if (code < 6)
1213
    sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg);
1214
  else
1215
    sd.kind = srcdest_mem;
1216
 
1217
  sd.addr = pv_unknown ();
1218
  sd.reg = 0;
1219
 
1220
  switch (code)
1221
    {
1222
    case 0x0: sd.reg = (size == 1 ? &st->r0 : &st->r0); break;
1223
    case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break;
1224
    case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break;
1225
    case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break;
1226
 
1227
    case 0x4: sd.reg = &st->a0; break;
1228
    case 0x5: sd.reg = &st->a1; break;
1229
 
1230
    case 0x6: sd.addr = st->a0; break;
1231
    case 0x7: sd.addr = st->a1; break;
1232
 
1233
    case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1234
    case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1235
    case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1236
    case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1237
 
1238
    case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1239
    case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1240
    case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1241
    case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1242
 
1243
    default:
1244
      gdb_assert (0);
1245
    }
1246
 
1247
  return sd;
1248
}
1249
 
1250
 
1251
static struct srcdest
1252
m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind)
1253
{
1254
  struct srcdest sd;
1255
 
1256
  sd.addr = pv_unknown ();
1257
  sd.reg = 0;
1258
 
1259
  switch (code)
1260
    {
1261
    case 0x12:
1262
    case 0x13:
1263
    case 0x10:
1264
    case 0x11:
1265
      sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg;
1266
      break;
1267
 
1268
    case 0x02:
1269
    case 0x03:
1270
      sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg;
1271
      break;
1272
 
1273
    default:
1274
      sd.kind = srcdest_mem;
1275
      break;
1276
 
1277
    }
1278
 
1279
  switch (code)
1280
    {
1281
    case 0x12: sd.reg = &st->r0; break;
1282
    case 0x13: sd.reg = &st->r1; break;
1283
    case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break;
1284
    case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break;
1285
    case 0x02: sd.reg = &st->a0; break;
1286
    case 0x03: sd.reg = &st->a1; break;
1287
 
1288
    case 0x00: sd.addr = st->a0; break;
1289
    case 0x01: sd.addr = st->a1; break;
1290
    case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break;
1291
    case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break;
1292
    case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break;
1293
    case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break;
1294
    case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break;
1295
    case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break;
1296
    case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break;
1297
    case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break;
1298
    case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break;
1299
    case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break;
1300
    case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break;
1301
    case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break;
1302
    default:
1303
      gdb_assert (0);
1304
    }
1305
 
1306
  if (ind)
1307
    {
1308
      sd.addr = m32c_srcdest_fetch (st, sd, 4);
1309
      sd.kind = srcdest_mem;
1310
    }
1311
 
1312
  return sd;
1313
}
1314
 
1315
 
1316
/* The r16c and r32c machines have instructions with similar
1317
   semantics, but completely different machine language encodings.  So
1318
   we break out the semantics into their own functions, and leave
1319
   machine-specific decoding in m32c_analyze_prologue.
1320
 
1321
   The following functions all expect their arguments already decoded,
1322
   and they all return zero if analysis should continue past this
1323
   instruction, or non-zero if analysis should stop.  */
1324
 
1325
 
1326
/* Simulate an 'enter SIZE' instruction in STATE.  */
1327
static int
1328
m32c_pv_enter (struct m32c_pv_state *state, int size)
1329
{
1330
  struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1331
 
1332
  /* If simulating this store would require us to forget
1333
     everything we know about the stack frame in the name of
1334
     accuracy, it would be better to just quit now.  */
1335
  if (pv_area_store_would_trash (state->stack, state->sp))
1336
    return 1;
1337
 
1338
  if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes))
1339
    return 1;
1340
  state->fb = state->sp;
1341
  state->sp = pv_add_constant (state->sp, -size);
1342
 
1343
  return 0;
1344
}
1345
 
1346
 
1347
static int
1348
m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg,
1349
                   int bit, int src, int size)
1350
{
1351
  if (bit & src)
1352
    {
1353
      if (m32c_pv_push (state, reg, size))
1354
        return 1;
1355
    }
1356
 
1357
  return 0;
1358
}
1359
 
1360
 
1361
/* Simulate a 'pushm SRC' instruction in STATE.  */
1362
static int
1363
m32c_pv_pushm (struct m32c_pv_state *state, int src)
1364
{
1365
  struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1366
 
1367
  /* The bits in SRC indicating which registers to save are:
1368
     r0 r1 r2 r3 a0 a1 sb fb */
1369
  return
1370
    (   m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes)
1371
     || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes)
1372
     || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes)
1373
     || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes)
1374
     || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2)
1375
     || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2)
1376
     || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2)
1377
     || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2));
1378
}
1379
 
1380
/* Return non-zero if VALUE is the first incoming argument register.  */
1381
 
1382
static int
1383
m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value)
1384
{
1385
  struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1386
  return (value.kind == pvk_register
1387
          && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1388
              ? (value.reg == tdep->r1->num)
1389
              : (value.reg == tdep->r0->num))
1390
          && value.k == 0);
1391
}
1392
 
1393
/* Return non-zero if VALUE is an incoming argument register.  */
1394
 
1395
static int
1396
m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value)
1397
{
1398
  struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch);
1399
  return (value.kind == pvk_register
1400
          && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c
1401
              ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num)
1402
              : (value.reg == tdep->r0->num))
1403
          && value.k == 0);
1404
}
1405
 
1406
/* Return non-zero if a store of VALUE to LOC is probably spilling an
1407
   argument register to its stack slot in STATE.  Such instructions
1408
   should be included in the prologue, if possible.
1409
 
1410
   The store is a spill if:
1411
   - the value being stored is the original value of an argument register;
1412
   - the value has not already been stored somewhere in STACK; and
1413
   - LOC is a stack slot (e.g., a memory location whose address is
1414
     relative to the original value of the SP).  */
1415
 
1416
static int
1417
m32c_is_arg_spill (struct m32c_pv_state *st,
1418
                   struct srcdest loc,
1419
                   pv_t value)
1420
{
1421
  struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1422
 
1423
  return (m32c_is_arg_reg (st, value)
1424
          && loc.kind == srcdest_mem
1425
          && pv_is_register (loc.addr, tdep->sp->num)
1426
          && ! pv_area_find_reg (st->stack, st->arch, value.reg, 0));
1427
}
1428
 
1429
/* Return non-zero if a store of VALUE to LOC is probably
1430
   copying the struct return address into an address register
1431
   for immediate use.  This is basically a "spill" into the
1432
   address register, instead of onto the stack.
1433
 
1434
   The prerequisites are:
1435
   - value being stored is original value of the FIRST arg register;
1436
   - value has not already been stored on stack; and
1437
   - LOC is an address register (a0 or a1).  */
1438
 
1439
static int
1440
m32c_is_struct_return (struct m32c_pv_state *st,
1441
                       struct srcdest loc,
1442
                       pv_t value)
1443
{
1444
  struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1445
 
1446
  return (m32c_is_1st_arg_reg (st, value)
1447
          && !pv_area_find_reg (st->stack, st->arch, value.reg, 0)
1448
          && loc.kind == srcdest_reg
1449
          && (pv_is_register (*loc.reg, tdep->a0->num)
1450
              || pv_is_register (*loc.reg, tdep->a1->num)));
1451
}
1452
 
1453
/* Return non-zero if a 'pushm' saving the registers indicated by SRC
1454
   was a register save:
1455
   - all the named registers should have their original values, and
1456
   - the stack pointer should be at a constant offset from the
1457
     original stack pointer.  */
1458
static int
1459
m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src)
1460
{
1461
  struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch);
1462
  /* The bits in SRC indicating which registers to save are:
1463
     r0 r1 r2 r3 a0 a1 sb fb */
1464
  return
1465
    (pv_is_register (st->sp, tdep->sp->num)
1466
     && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0))
1467
     && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0))
1468
     && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0))
1469
     && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0))
1470
     && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0))
1471
     && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0))
1472
     && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0))
1473
     && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0)));
1474
}
1475
 
1476
 
1477
/* Function for finding saved registers in a 'struct pv_area'; we pass
1478
   this to pv_area_scan.
1479
 
1480
   If VALUE is a saved register, ADDR says it was saved at a constant
1481
   offset from the frame base, and SIZE indicates that the whole
1482
   register was saved, record its offset in RESULT_UNTYPED.  */
1483
static void
1484
check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value)
1485
{
1486
  struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped;
1487
  struct gdbarch *arch = prologue->arch;
1488
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1489
 
1490
  /* Is this the unchanged value of some register being saved on the
1491
     stack?  */
1492
  if (value.kind == pvk_register
1493
      && value.k == 0
1494
      && pv_is_register (addr, tdep->sp->num))
1495
    {
1496
      /* Some registers require special handling: they're saved as a
1497
         larger value than the register itself.  */
1498
      CORE_ADDR saved_size = register_size (arch, value.reg);
1499
 
1500
      if (value.reg == tdep->pc->num)
1501
        saved_size = tdep->ret_addr_bytes;
1502
      else if (register_type (arch, value.reg)
1503
               == tdep->data_addr_reg_type)
1504
        saved_size = tdep->push_addr_bytes;
1505
 
1506
      if (size == saved_size)
1507
        {
1508
          /* Find which end of the saved value corresponds to our
1509
             register.  */
1510
          if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
1511
            prologue->reg_offset[value.reg]
1512
              = (addr.k + saved_size - register_size (arch, value.reg));
1513
          else
1514
            prologue->reg_offset[value.reg] = addr.k;
1515
        }
1516
    }
1517
}
1518
 
1519
 
1520
/* Analyze the function prologue for ARCH at START, going no further
1521
   than LIMIT, and place a description of what we found in
1522
   PROLOGUE.  */
1523
void
1524
m32c_analyze_prologue (struct gdbarch *arch,
1525
                       CORE_ADDR start, CORE_ADDR limit,
1526
                       struct m32c_prologue *prologue)
1527
{
1528
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1529
  unsigned long mach = gdbarch_bfd_arch_info (arch)->mach;
1530
  CORE_ADDR after_last_frame_related_insn;
1531
  struct cleanup *back_to;
1532
  struct m32c_pv_state st;
1533
 
1534
  st.arch = arch;
1535
  st.r0 = pv_register (tdep->r0->num, 0);
1536
  st.r1 = pv_register (tdep->r1->num, 0);
1537
  st.r2 = pv_register (tdep->r2->num, 0);
1538
  st.r3 = pv_register (tdep->r3->num, 0);
1539
  st.a0 = pv_register (tdep->a0->num, 0);
1540
  st.a1 = pv_register (tdep->a1->num, 0);
1541
  st.sb = pv_register (tdep->sb->num, 0);
1542
  st.fb = pv_register (tdep->fb->num, 0);
1543
  st.sp = pv_register (tdep->sp->num, 0);
1544
  st.pc = pv_register (tdep->pc->num, 0);
1545
  st.stack = make_pv_area (tdep->sp->num);
1546
  back_to = make_cleanup_free_pv_area (st.stack);
1547
 
1548
  /* Record that the call instruction has saved the return address on
1549
     the stack.  */
1550
  m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes);
1551
 
1552
  memset (prologue, 0, sizeof (*prologue));
1553
  prologue->arch = arch;
1554
  {
1555
    int i;
1556
    for (i = 0; i < M32C_MAX_NUM_REGS; i++)
1557
      prologue->reg_offset[i] = 1;
1558
  }
1559
 
1560
  st.scan_pc = after_last_frame_related_insn = start;
1561
 
1562
  while (st.scan_pc < limit)
1563
    {
1564
      pv_t pre_insn_fb = st.fb;
1565
      pv_t pre_insn_sp = st.sp;
1566
 
1567
      /* In theory we could get in trouble by trying to read ahead
1568
         here, when we only know we're expecting one byte.  In
1569
         practice I doubt anyone will care, and it makes the rest of
1570
         the code easier.  */
1571
      if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn)))
1572
        /* If we can't fetch the instruction from memory, stop here
1573
           and hope for the best.  */
1574
        break;
1575
      st.next_addr = st.scan_pc;
1576
 
1577
      /* The assembly instructions are written as they appear in the
1578
         section of the processor manuals that describe the
1579
         instruction encodings.
1580
 
1581
         When a single assembly language instruction has several
1582
         different machine-language encodings, the manual
1583
         distinguishes them by a number in parens, before the
1584
         mnemonic.  Those numbers are included, as well.
1585
 
1586
         The srcdest decoding instructions have the same names as the
1587
         analogous functions in the simulator.  */
1588
      if (mach == bfd_mach_m16c)
1589
        {
1590
          /* (1) ENTER #imm8 */
1591
          if (st.insn[0] == 0x7c && st.insn[1] == 0xf2)
1592
            {
1593
              if (m32c_pv_enter (&st, st.insn[2]))
1594
                break;
1595
              st.next_addr += 3;
1596
            }
1597
          /* (1) PUSHM src */
1598
          else if (st.insn[0] == 0xec)
1599
            {
1600
              int src = st.insn[1];
1601
              if (m32c_pv_pushm (&st, src))
1602
                break;
1603
              st.next_addr += 2;
1604
 
1605
              if (m32c_pushm_is_reg_save (&st, src))
1606
                after_last_frame_related_insn = st.next_addr;
1607
            }
1608
 
1609
          /* (6) MOV.size:G src, dest */
1610
          else if ((st.insn[0] & 0xfe) == 0x72)
1611
            {
1612
              int size = (st.insn[0] & 0x01) ? 2 : 1;
1613
              struct srcdest src;
1614
              struct srcdest dest;
1615
              pv_t src_value;
1616
              st.next_addr += 2;
1617
 
1618
              src
1619
                = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size);
1620
              dest
1621
                = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size);
1622
              src_value = m32c_srcdest_fetch (&st, src, size);
1623
 
1624
              if (m32c_is_arg_spill (&st, dest, src_value))
1625
                after_last_frame_related_insn = st.next_addr;
1626
              else if (m32c_is_struct_return (&st, dest, src_value))
1627
                after_last_frame_related_insn = st.next_addr;
1628
 
1629
              if (m32c_srcdest_store (&st, dest, src_value, size))
1630
                break;
1631
            }
1632
 
1633
          /* (1) LDC #IMM16, sp */
1634
          else if (st.insn[0] == 0xeb
1635
                   && st.insn[1] == 0x50)
1636
            {
1637
              st.next_addr += 2;
1638
              st.sp = pv_constant (m32c_udisp16 (&st));
1639
            }
1640
 
1641
          else
1642
            /* We've hit some instruction we don't know how to simulate.
1643
               Strictly speaking, we should set every value we're
1644
               tracking to "unknown".  But we'll be optimistic, assume
1645
               that we have enough information already, and stop
1646
               analysis here.  */
1647
            break;
1648
        }
1649
      else
1650
        {
1651
          int src_indirect = 0;
1652
          int dest_indirect = 0;
1653
          int i = 0;
1654
 
1655
          gdb_assert (mach == bfd_mach_m32c);
1656
 
1657
          /* Check for prefix bytes indicating indirect addressing.  */
1658
          if (st.insn[0] == 0x41)
1659
            {
1660
              src_indirect = 1;
1661
              i++;
1662
            }
1663
          else if (st.insn[0] == 0x09)
1664
            {
1665
              dest_indirect = 1;
1666
              i++;
1667
            }
1668
          else if (st.insn[0] == 0x49)
1669
            {
1670
              src_indirect = dest_indirect = 1;
1671
              i++;
1672
            }
1673
 
1674
          /* (1) ENTER #imm8 */
1675
          if (st.insn[i] == 0xec)
1676
            {
1677
              if (m32c_pv_enter (&st, st.insn[i + 1]))
1678
                break;
1679
              st.next_addr += 2;
1680
            }
1681
 
1682
          /* (1) PUSHM src */
1683
          else if (st.insn[i] == 0x8f)
1684
            {
1685
              int src = st.insn[i + 1];
1686
              if (m32c_pv_pushm (&st, src))
1687
                break;
1688
              st.next_addr += 2;
1689
 
1690
              if (m32c_pushm_is_reg_save (&st, src))
1691
                after_last_frame_related_insn = st.next_addr;
1692
            }
1693
 
1694
          /* (7) MOV.size:G src, dest */
1695
          else if ((st.insn[i] & 0x80) == 0x80
1696
                   && (st.insn[i + 1] & 0x0f) == 0x0b
1697
                   && m32c_get_src23 (&st.insn[i]) < 20
1698
                   && m32c_get_dest23 (&st.insn[i]) < 20)
1699
            {
1700
              struct srcdest src;
1701
              struct srcdest dest;
1702
              pv_t src_value;
1703
              int bw = st.insn[i] & 0x01;
1704
              int size = bw ? 2 : 1;
1705
              st.next_addr += 2;
1706
 
1707
              src
1708
                = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]),
1709
                                    size, src_indirect);
1710
              dest
1711
                = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]),
1712
                                    size, dest_indirect);
1713
              src_value = m32c_srcdest_fetch (&st, src, size);
1714
 
1715
              if (m32c_is_arg_spill (&st, dest, src_value))
1716
                after_last_frame_related_insn = st.next_addr;
1717
 
1718
              if (m32c_srcdest_store (&st, dest, src_value, size))
1719
                break;
1720
            }
1721
          /* (2) LDC #IMM24, sp */
1722
          else if (st.insn[i] == 0xd5
1723
                   && st.insn[i + 1] == 0x29)
1724
            {
1725
              st.next_addr += 2;
1726
              st.sp = pv_constant (m32c_udisp24 (&st));
1727
            }
1728
          else
1729
            /* We've hit some instruction we don't know how to simulate.
1730
               Strictly speaking, we should set every value we're
1731
               tracking to "unknown".  But we'll be optimistic, assume
1732
               that we have enough information already, and stop
1733
               analysis here.  */
1734
            break;
1735
        }
1736
 
1737
      /* If this instruction changed the FB or decreased the SP (i.e.,
1738
         allocated more stack space), then this may be a good place to
1739
         declare the prologue finished.  However, there are some
1740
         exceptions:
1741
 
1742
         - If the instruction just changed the FB back to its original
1743
           value, then that's probably a restore instruction.  The
1744
           prologue should definitely end before that.
1745
 
1746
         - If the instruction increased the value of the SP (that is,
1747
           shrunk the frame), then it's probably part of a frame
1748
           teardown sequence, and the prologue should end before
1749
           that.  */
1750
 
1751
      if (! pv_is_identical (st.fb, pre_insn_fb))
1752
        {
1753
          if (! pv_is_register_k (st.fb, tdep->fb->num, 0))
1754
            after_last_frame_related_insn = st.next_addr;
1755
        }
1756
      else if (! pv_is_identical (st.sp, pre_insn_sp))
1757
        {
1758
          /* The comparison of the constants looks odd, there, because
1759
             .k is unsigned.  All it really means is that the SP is
1760
             lower than it was before the instruction.  */
1761
          if (   pv_is_register (pre_insn_sp, tdep->sp->num)
1762
              && pv_is_register (st.sp,       tdep->sp->num)
1763
              && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k)))
1764
            after_last_frame_related_insn = st.next_addr;
1765
        }
1766
 
1767
      st.scan_pc = st.next_addr;
1768
    }
1769
 
1770
  /* Did we load a constant value into the stack pointer?  */
1771
  if (pv_is_constant (st.sp))
1772
    prologue->kind = prologue_first_frame;
1773
 
1774
  /* Alternatively, did we initialize the frame pointer?  Remember
1775
     that the CFA is the address after the return address.  */
1776
  if (pv_is_register (st.fb, tdep->sp->num))
1777
    {
1778
      prologue->kind = prologue_with_frame_ptr;
1779
      prologue->frame_ptr_offset = st.fb.k;
1780
    }
1781
 
1782
  /* Is the frame size a known constant?  Remember that frame_size is
1783
     actually the offset from the CFA to the SP (i.e., a negative
1784
     value).  */
1785
  else if (pv_is_register (st.sp, tdep->sp->num))
1786
    {
1787
      prologue->kind = prologue_sans_frame_ptr;
1788
      prologue->frame_size = st.sp.k;
1789
    }
1790
 
1791
  /* We haven't been able to make sense of this function's frame.  Treat
1792
     it as the first frame.  */
1793
  else
1794
    prologue->kind = prologue_first_frame;
1795
 
1796
  /* Record where all the registers were saved.  */
1797
  pv_area_scan (st.stack, check_for_saved, (void *) prologue);
1798
 
1799
  prologue->prologue_end = after_last_frame_related_insn;
1800
 
1801
  do_cleanups (back_to);
1802
}
1803
 
1804
 
1805
static CORE_ADDR
1806
m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip)
1807
{
1808
  char *name;
1809
  CORE_ADDR func_addr, func_end, sal_end;
1810
  struct m32c_prologue p;
1811
 
1812
  /* Try to find the extent of the function that contains IP.  */
1813
  if (! find_pc_partial_function (ip, &name, &func_addr, &func_end))
1814
    return ip;
1815
 
1816
  /* Find end by prologue analysis.  */
1817
  m32c_analyze_prologue (gdbarch, ip, func_end, &p);
1818
  /* Find end by line info.  */
1819
  sal_end = skip_prologue_using_sal (ip);
1820
  /* Return whichever is lower.  */
1821
  if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end)
1822
    return sal_end;
1823
  else
1824
    return p.prologue_end;
1825
}
1826
 
1827
 
1828
 
1829
/* Stack unwinding.  */
1830
 
1831
static struct m32c_prologue *
1832
m32c_analyze_frame_prologue (struct frame_info *next_frame,
1833
                             void **this_prologue_cache)
1834
{
1835
  if (! *this_prologue_cache)
1836
    {
1837
      CORE_ADDR func_start = frame_func_unwind (next_frame, NORMAL_FRAME);
1838
      CORE_ADDR stop_addr = frame_pc_unwind (next_frame);
1839
 
1840
      /* If we couldn't find any function containing the PC, then
1841
         just initialize the prologue cache, but don't do anything.  */
1842
      if (! func_start)
1843
        stop_addr = func_start;
1844
 
1845
      *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue);
1846
      m32c_analyze_prologue (get_frame_arch (next_frame),
1847
                             func_start, stop_addr, *this_prologue_cache);
1848
    }
1849
 
1850
  return *this_prologue_cache;
1851
}
1852
 
1853
 
1854
static CORE_ADDR
1855
m32c_frame_base (struct frame_info *next_frame,
1856
                void **this_prologue_cache)
1857
{
1858
  struct m32c_prologue *p
1859
    = m32c_analyze_frame_prologue (next_frame, this_prologue_cache);
1860
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
1861
 
1862
  /* In functions that use alloca, the distance between the stack
1863
     pointer and the frame base varies dynamically, so we can't use
1864
     the SP plus static information like prologue analysis to find the
1865
     frame base.  However, such functions must have a frame pointer,
1866
     to be able to restore the SP on exit.  So whenever we do have a
1867
     frame pointer, use that to find the base.  */
1868
  switch (p->kind)
1869
    {
1870
    case prologue_with_frame_ptr:
1871
      {
1872
        CORE_ADDR fb
1873
          = frame_unwind_register_unsigned (next_frame, tdep->fb->num);
1874
        return fb - p->frame_ptr_offset;
1875
      }
1876
 
1877
    case prologue_sans_frame_ptr:
1878
      {
1879
        CORE_ADDR sp
1880
          = frame_unwind_register_unsigned (next_frame, tdep->sp->num);
1881
        return sp - p->frame_size;
1882
      }
1883
 
1884
    case prologue_first_frame:
1885
      return 0;
1886
 
1887
    default:
1888
      gdb_assert (0);
1889
    }
1890
}
1891
 
1892
 
1893
static void
1894
m32c_this_id (struct frame_info *next_frame,
1895
              void **this_prologue_cache,
1896
              struct frame_id *this_id)
1897
{
1898
  CORE_ADDR base = m32c_frame_base (next_frame, this_prologue_cache);
1899
 
1900
  if (base)
1901
    *this_id = frame_id_build (base,
1902
                               frame_func_unwind (next_frame, NORMAL_FRAME));
1903
  /* Otherwise, leave it unset, and that will terminate the backtrace.  */
1904
}
1905
 
1906
 
1907
static void
1908
m32c_prev_register (struct frame_info *next_frame,
1909
                    void **this_prologue_cache,
1910
                    int regnum, int *optimizedp,
1911
                    enum lval_type *lvalp, CORE_ADDR *addrp,
1912
                    int *realnump, gdb_byte *bufferp)
1913
{
1914
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
1915
  struct m32c_prologue *p
1916
    = m32c_analyze_frame_prologue (next_frame, this_prologue_cache);
1917
  CORE_ADDR frame_base = m32c_frame_base (next_frame, this_prologue_cache);
1918
  int reg_size = register_size (get_frame_arch (next_frame), regnum);
1919
 
1920
  if (regnum == tdep->sp->num)
1921
    {
1922
      *optimizedp = 0;
1923
      *lvalp = not_lval;
1924
      *addrp = 0;
1925
      *realnump = -1;
1926
      if (bufferp)
1927
        store_unsigned_integer (bufferp, reg_size, frame_base);
1928
    }
1929
 
1930
  /* If prologue analysis says we saved this register somewhere,
1931
     return a description of the stack slot holding it.  */
1932
  else if (p->reg_offset[regnum] != 1)
1933
    {
1934
      *optimizedp = 0;
1935
      *lvalp = lval_memory;
1936
      *addrp = frame_base + p->reg_offset[regnum];
1937
      *realnump = -1;
1938
      if (bufferp)
1939
        get_frame_memory (next_frame, *addrp, bufferp, reg_size);
1940
    }
1941
 
1942
  /* Otherwise, presume we haven't changed the value of this
1943
     register, and get it from the next frame.  */
1944
  else
1945
    {
1946
      *optimizedp = 0;
1947
      *lvalp = lval_register;
1948
      *addrp = 0;
1949
      *realnump = regnum;
1950
      if (bufferp)
1951
        frame_unwind_register (next_frame, *realnump, bufferp);
1952
    }
1953
}
1954
 
1955
 
1956
static const struct frame_unwind m32c_unwind = {
1957
  NORMAL_FRAME,
1958
  m32c_this_id,
1959
  m32c_prev_register
1960
};
1961
 
1962
 
1963
static const struct frame_unwind *
1964
m32c_frame_sniffer (struct frame_info *next_frame)
1965
{
1966
  return &m32c_unwind;
1967
}
1968
 
1969
 
1970
static CORE_ADDR
1971
m32c_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1972
{
1973
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1974
  return frame_unwind_register_unsigned (next_frame, tdep->pc->num);
1975
}
1976
 
1977
 
1978
static CORE_ADDR
1979
m32c_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1980
{
1981
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1982
  return frame_unwind_register_unsigned (next_frame, tdep->sp->num);
1983
}
1984
 
1985
 
1986
/* Inferior calls.  */
1987
 
1988
/* The calling conventions, according to GCC:
1989
 
1990
   r8c, m16c
1991
   ---------
1992
   First arg may be passed in r1l or r1 if it (1) fits (QImode or
1993
   HImode), (2) is named, and (3) is an integer or pointer type (no
1994
   structs, floats, etc).  Otherwise, it's passed on the stack.
1995
 
1996
   Second arg may be passed in r2, same restrictions (but not QImode),
1997
   even if the first arg is passed on the stack.
1998
 
1999
   Third and further args are passed on the stack.  No padding is
2000
   used, stack "alignment" is 8 bits.
2001
 
2002
   m32cm, m32c
2003
   -----------
2004
 
2005
   First arg may be passed in r0l or r0, same restrictions as above.
2006
 
2007
   Second and further args are passed on the stack.  Padding is used
2008
   after QImode parameters (i.e. lower-addressed byte is the value,
2009
   higher-addressed byte is the padding), stack "alignment" is 16
2010
   bits.  */
2011
 
2012
 
2013
/* Return true if TYPE is a type that can be passed in registers.  (We
2014
   ignore the size, and pay attention only to the type code;
2015
   acceptable sizes depends on which register is being considered to
2016
   hold it.)  */
2017
static int
2018
m32c_reg_arg_type (struct type *type)
2019
{
2020
  enum type_code code = TYPE_CODE (type);
2021
 
2022
  return (code == TYPE_CODE_INT
2023
          || code == TYPE_CODE_ENUM
2024
          || code == TYPE_CODE_PTR
2025
          || code == TYPE_CODE_REF
2026
          || code == TYPE_CODE_BOOL
2027
          || code == TYPE_CODE_CHAR);
2028
}
2029
 
2030
 
2031
static CORE_ADDR
2032
m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
2033
                      struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
2034
                      struct value **args, CORE_ADDR sp, int struct_return,
2035
                      CORE_ADDR struct_addr)
2036
{
2037
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2038
  unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
2039
  CORE_ADDR cfa;
2040
  int i;
2041
 
2042
  /* The number of arguments given in this function's prototype, or
2043
     zero if it has a non-prototyped function type.  The m32c ABI
2044
     passes arguments mentioned in the prototype differently from
2045
     those in the ellipsis of a varargs function, or from those passed
2046
     to a non-prototyped function.  */
2047
  int num_prototyped_args = 0;
2048
 
2049
  {
2050
    struct type *func_type = value_type (function);
2051
 
2052
    gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC ||
2053
                TYPE_CODE (func_type) == TYPE_CODE_METHOD);
2054
 
2055
#if 0
2056
    /* The ABI description in gcc/config/m32c/m32c.abi says that
2057
       we need to handle prototyped and non-prototyped functions
2058
       separately, but the code in GCC doesn't actually do so.  */
2059
    if (TYPE_PROTOTYPED (func_type))
2060
#endif
2061
      num_prototyped_args = TYPE_NFIELDS (func_type);
2062
  }
2063
 
2064
  /* First, if the function returns an aggregate by value, push a
2065
     pointer to a buffer for it.  This doesn't affect the way
2066
     subsequent arguments are allocated to registers.  */
2067
  if (struct_return)
2068
    {
2069
      int ptr_len = TYPE_LENGTH (tdep->ptr_voyd);
2070
      sp -= ptr_len;
2071
      write_memory_unsigned_integer (sp, ptr_len, struct_addr);
2072
    }
2073
 
2074
  /* Push the arguments.  */
2075
  for (i = nargs - 1; i >= 0; i--)
2076
    {
2077
      struct value *arg = args[i];
2078
      const gdb_byte *arg_bits = value_contents (arg);
2079
      struct type *arg_type = value_type (arg);
2080
      ULONGEST arg_size = TYPE_LENGTH (arg_type);
2081
 
2082
      /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)?  */
2083
      if (i == 0
2084
          && arg_size <= 2
2085
          && i < num_prototyped_args
2086
          && m32c_reg_arg_type (arg_type))
2087
        {
2088
          /* Extract and re-store as an integer as a terse way to make
2089
             sure it ends up in the least significant end of r1.  (GDB
2090
             should avoid assuming endianness, even on uni-endian
2091
             processors.)  */
2092
          ULONGEST u = extract_unsigned_integer (arg_bits, arg_size);
2093
          struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0;
2094
          regcache_cooked_write_unsigned (regcache, reg->num, u);
2095
        }
2096
 
2097
      /* Can it go in r2?  */
2098
      else if (mach == bfd_mach_m16c
2099
               && i == 1
2100
               && arg_size == 2
2101
               && i < num_prototyped_args
2102
               && m32c_reg_arg_type (arg_type))
2103
        regcache_cooked_write (regcache, tdep->r2->num, arg_bits);
2104
 
2105
      /* Everything else goes on the stack.  */
2106
      else
2107
        {
2108
          sp -= arg_size;
2109
 
2110
          /* Align the stack.  */
2111
          if (mach == bfd_mach_m32c)
2112
            sp &= ~1;
2113
 
2114
          write_memory (sp, arg_bits, arg_size);
2115
        }
2116
    }
2117
 
2118
  /* This is the CFA we use to identify the dummy frame.  */
2119
  cfa = sp;
2120
 
2121
  /* Push the return address.  */
2122
  sp -= tdep->ret_addr_bytes;
2123
  write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, bp_addr);
2124
 
2125
  /* Update the stack pointer.  */
2126
  regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp);
2127
 
2128
  /* We need to borrow an odd trick from the i386 target here.
2129
 
2130
     The value we return from this function gets used as the stack
2131
     address (the CFA) for the dummy frame's ID.  The obvious thing is
2132
     to return the new TOS.  However, that points at the return
2133
     address, saved on the stack, which is inconsistent with the CFA's
2134
     described by GCC's DWARF 2 .debug_frame information: DWARF 2
2135
     .debug_frame info uses the address immediately after the saved
2136
     return address.  So you end up with a dummy frame whose CFA
2137
     points at the return address, but the frame for the function
2138
     being called has a CFA pointing after the return address: the
2139
     younger CFA is *greater than* the older CFA.  The sanity checks
2140
     in frame.c don't like that.
2141
 
2142
     So we try to be consistent with the CFA's used by DWARF 2.
2143
     Having a dummy frame and a real frame with the *same* CFA is
2144
     tolerable.  */
2145
  return cfa;
2146
}
2147
 
2148
 
2149
static struct frame_id
2150
m32c_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2151
{
2152
  /* This needs to return a frame ID whose PC is the return address
2153
     passed to m32c_push_dummy_call, and whose stack_addr is the SP
2154
     m32c_push_dummy_call returned.
2155
 
2156
     m32c_unwind_sp gives us the CFA, which is the value the SP had
2157
     before the return address was pushed.  */
2158
  return frame_id_build (m32c_unwind_sp (gdbarch, next_frame),
2159
                         frame_pc_unwind (next_frame));
2160
}
2161
 
2162
 
2163
 
2164
/* Return values.  */
2165
 
2166
/* Return value conventions, according to GCC:
2167
 
2168
   r8c, m16c
2169
   ---------
2170
 
2171
   QImode in r0l
2172
   HImode in r0
2173
   SImode in r2r0
2174
   near pointer in r0
2175
   far pointer in r2r0
2176
 
2177
   Aggregate values (regardless of size) are returned by pushing a
2178
   pointer to a temporary area on the stack after the args are pushed.
2179
   The function fills in this area with the value.  Note that this
2180
   pointer on the stack does not affect how register arguments, if any,
2181
   are configured.
2182
 
2183
   m32cm, m32c
2184
   -----------
2185
   Same.  */
2186
 
2187
/* Return non-zero if values of type TYPE are returned by storing them
2188
   in a buffer whose address is passed on the stack, ahead of the
2189
   other arguments.  */
2190
static int
2191
m32c_return_by_passed_buf (struct type *type)
2192
{
2193
  enum type_code code = TYPE_CODE (type);
2194
 
2195
  return (code == TYPE_CODE_STRUCT
2196
          || code == TYPE_CODE_UNION);
2197
}
2198
 
2199
static enum return_value_convention
2200
m32c_return_value (struct gdbarch *gdbarch,
2201
                   struct type *valtype,
2202
                   struct regcache *regcache,
2203
                   gdb_byte *readbuf,
2204
                   const gdb_byte *writebuf)
2205
{
2206
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2207
  enum return_value_convention conv;
2208
  ULONGEST valtype_len = TYPE_LENGTH (valtype);
2209
 
2210
  if (m32c_return_by_passed_buf (valtype))
2211
    conv = RETURN_VALUE_STRUCT_CONVENTION;
2212
  else
2213
    conv = RETURN_VALUE_REGISTER_CONVENTION;
2214
 
2215
  if (readbuf)
2216
    {
2217
      /* We should never be called to find values being returned by
2218
         RETURN_VALUE_STRUCT_CONVENTION.  Those can't be located,
2219
         unless we made the call ourselves.  */
2220
      gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2221
 
2222
      gdb_assert (valtype_len <= 8);
2223
 
2224
      /* Anything that fits in r0 is returned there.  */
2225
      if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2226
        {
2227
          ULONGEST u;
2228
          regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u);
2229
          store_unsigned_integer (readbuf, valtype_len, u);
2230
        }
2231
      else
2232
        {
2233
          /* Everything else is passed in mem0, using as many bytes as
2234
             needed.  This is not what the Renesas tools do, but it's
2235
             what GCC does at the moment.  */
2236
          struct minimal_symbol *mem0
2237
            = lookup_minimal_symbol ("mem0", NULL, NULL);
2238
 
2239
          if (! mem0)
2240
            error ("The return value is stored in memory at 'mem0', "
2241
                   "but GDB cannot find\n"
2242
                   "its address.");
2243
          read_memory (SYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len);
2244
        }
2245
    }
2246
 
2247
  if (writebuf)
2248
    {
2249
      /* We should never be called to store values to be returned
2250
         using RETURN_VALUE_STRUCT_CONVENTION.  We have no way of
2251
         finding the buffer, unless we made the call ourselves.  */
2252
      gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION);
2253
 
2254
      gdb_assert (valtype_len <= 8);
2255
 
2256
      /* Anything that fits in r0 is returned there.  */
2257
      if (valtype_len <= TYPE_LENGTH (tdep->r0->type))
2258
        {
2259
          ULONGEST u = extract_unsigned_integer (writebuf, valtype_len);
2260
          regcache_cooked_write_unsigned (regcache, tdep->r0->num, u);
2261
        }
2262
      else
2263
        {
2264
          /* Everything else is passed in mem0, using as many bytes as
2265
             needed.  This is not what the Renesas tools do, but it's
2266
             what GCC does at the moment.  */
2267
          struct minimal_symbol *mem0
2268
            = lookup_minimal_symbol ("mem0", NULL, NULL);
2269
 
2270
          if (! mem0)
2271
            error ("The return value is stored in memory at 'mem0', "
2272
                   "but GDB cannot find\n"
2273
                   " its address.");
2274
          write_memory (SYMBOL_VALUE_ADDRESS (mem0),
2275
                        (char *) writebuf, valtype_len);
2276
        }
2277
    }
2278
 
2279
  return conv;
2280
}
2281
 
2282
 
2283
 
2284
/* Trampolines.  */
2285
 
2286
/* The m16c and m32c use a trampoline function for indirect function
2287
   calls.  An indirect call looks like this:
2288
 
2289
             ... push arguments ...
2290
             ... push target function address ...
2291
             jsr.a m32c_jsri16
2292
 
2293
   The code for m32c_jsri16 looks like this:
2294
 
2295
     m32c_jsri16:
2296
 
2297
             # Save return address.
2298
             pop.w      m32c_jsri_ret
2299
             pop.b      m32c_jsri_ret+2
2300
 
2301
             # Store target function address.
2302
             pop.w      m32c_jsri_addr
2303
 
2304
             # Re-push return address.
2305
             push.b     m32c_jsri_ret+2
2306
             push.w     m32c_jsri_ret
2307
 
2308
             # Call the target function.
2309
             jmpi.a     m32c_jsri_addr
2310
 
2311
   Without further information, GDB will treat calls to m32c_jsri16
2312
   like calls to any other function.  Since m32c_jsri16 doesn't have
2313
   debugging information, that normally means that GDB sets a step-
2314
   resume breakpoint and lets the program continue --- which is not
2315
   what the user wanted.  (Giving the trampoline debugging info
2316
   doesn't help: the user expects the program to stop in the function
2317
   their program is calling, not in some trampoline code they've never
2318
   seen before.)
2319
 
2320
   The gdbarch_skip_trampoline_code method tells GDB how to step
2321
   through such trampoline functions transparently to the user.  When
2322
   given the address of a trampoline function's first instruction,
2323
   gdbarch_skip_trampoline_code should return the address of the first
2324
   instruction of the function really being called.  If GDB decides it
2325
   wants to step into that function, it will set a breakpoint there
2326
   and silently continue to it.
2327
 
2328
   We recognize the trampoline by name, and extract the target address
2329
   directly from the stack.  This isn't great, but recognizing by its
2330
   code sequence seems more fragile.  */
2331
 
2332
static CORE_ADDR
2333
m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc)
2334
{
2335
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
2336
 
2337
  /* It would be nicer to simply look up the addresses of known
2338
     trampolines once, and then compare stop_pc with them.  However,
2339
     we'd need to ensure that that cached address got invalidated when
2340
     someone loaded a new executable, and I'm not quite sure of the
2341
     best way to do that.  find_pc_partial_function does do some
2342
     caching, so we'll see how this goes.  */
2343
  char *name;
2344
  CORE_ADDR start, end;
2345
 
2346
  if (find_pc_partial_function (stop_pc, &name, &start, &end))
2347
    {
2348
      /* Are we stopped at the beginning of the trampoline function?  */
2349
      if (strcmp (name, "m32c_jsri16") == 0
2350
          && stop_pc == start)
2351
        {
2352
          /* Get the stack pointer.  The return address is at the top,
2353
             and the target function's address is just below that.  We
2354
             know it's a two-byte address, since the trampoline is
2355
             m32c_jsri*16*.  */
2356
          CORE_ADDR sp = get_frame_sp (get_current_frame ());
2357
          CORE_ADDR target
2358
            = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes, 2);
2359
 
2360
          /* What we have now is the address of a jump instruction.
2361
             What we need is the destination of that jump.
2362
             The opcode is 1 byte, and the destination is the next 3 bytes.
2363
          */
2364
          target = read_memory_unsigned_integer (target + 1, 3);
2365
          return target;
2366
        }
2367
    }
2368
 
2369
  return 0;
2370
}
2371
 
2372
 
2373
/* Address/pointer conversions.  */
2374
 
2375
/* On the m16c, there is a 24-bit address space, but only a very few
2376
   instructions can generate addresses larger than 0xffff: jumps,
2377
   jumps to subroutines, and the lde/std (load/store extended)
2378
   instructions.
2379
 
2380
   Since GCC can only support one size of pointer, we can't have
2381
   distinct 'near' and 'far' pointer types; we have to pick one size
2382
   for everything.  If we wanted to use 24-bit pointers, then GCC
2383
   would have to use lde and ste for all memory references, which
2384
   would be terrible for performance and code size.  So the GNU
2385
   toolchain uses 16-bit pointers for everything, and gives up the
2386
   ability to have pointers point outside the first 64k of memory.
2387
 
2388
   However, as a special hack, we let the linker place functions at
2389
   addresses above 0xffff, as long as it also places a trampoline in
2390
   the low 64k for every function whose address is taken.  Each
2391
   trampoline consists of a single jmp.a instruction that jumps to the
2392
   function's real entry point.  Pointers to functions can be 16 bits
2393
   long, even though the functions themselves are at higher addresses:
2394
   the pointers refer to the trampolines, not the functions.
2395
 
2396
   This complicates things for GDB, however: given the address of a
2397
   function (from debug info or linker symbols, say) which could be
2398
   anywhere in the 24-bit address space, how can we find an
2399
   appropriate 16-bit value to use as a pointer to it?
2400
 
2401
   If the linker has not generated a trampoline for the function,
2402
   we're out of luck.  Well, I guess we could malloc some space and
2403
   write a jmp.a instruction to it, but I'm not going to get into that
2404
   at the moment.
2405
 
2406
   If the linker has generated a trampoline for the function, then it
2407
   also emitted a symbol for the trampoline: if the function's linker
2408
   symbol is named NAME, then the function's trampoline's linker
2409
   symbol is named NAME.plt.
2410
 
2411
   So, given a code address:
2412
   - We try to find a linker symbol at that address.
2413
   - If we find such a symbol named NAME, we look for a linker symbol
2414
     named NAME.plt.
2415
   - If we find such a symbol, we assume it is a trampoline, and use
2416
     its address as the pointer value.
2417
 
2418
   And, given a function pointer:
2419
   - We try to find a linker symbol at that address named NAME.plt.
2420
   - If we find such a symbol, we look for a linker symbol named NAME.
2421
   - If we find that, we provide that as the function's address.
2422
   - If any of the above steps fail, we return the original address
2423
     unchanged; it might really be a function in the low 64k.
2424
 
2425
   See?  You *knew* there was a reason you wanted to be a computer
2426
   programmer!  :)  */
2427
 
2428
static void
2429
m32c_m16c_address_to_pointer (struct type *type, gdb_byte *buf, CORE_ADDR addr)
2430
{
2431
  enum type_code target_code;
2432
  gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR ||
2433
              TYPE_CODE (type) == TYPE_CODE_REF);
2434
 
2435
  target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2436
 
2437
  if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2438
    {
2439
      char *func_name;
2440
      char *tramp_name;
2441
      struct minimal_symbol *tramp_msym;
2442
 
2443
      /* Try to find a linker symbol at this address.  */
2444
      struct minimal_symbol *func_msym = lookup_minimal_symbol_by_pc (addr);
2445
 
2446
      if (! func_msym)
2447
        error ("Cannot convert code address %s to function pointer:\n"
2448
               "couldn't find a symbol at that address, to find trampoline.",
2449
               paddr_nz (addr));
2450
 
2451
      func_name = SYMBOL_LINKAGE_NAME (func_msym);
2452
      tramp_name = xmalloc (strlen (func_name) + 5);
2453
      strcpy (tramp_name, func_name);
2454
      strcat (tramp_name, ".plt");
2455
 
2456
      /* Try to find a linker symbol for the trampoline.  */
2457
      tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL);
2458
 
2459
      /* We've either got another copy of the name now, or don't need
2460
         the name any more.  */
2461
      xfree (tramp_name);
2462
 
2463
      if (! tramp_msym)
2464
        error ("Cannot convert code address %s to function pointer:\n"
2465
               "couldn't find trampoline named '%s.plt'.",
2466
               paddr_nz (addr), func_name);
2467
 
2468
      /* The trampoline's address is our pointer.  */
2469
      addr = SYMBOL_VALUE_ADDRESS (tramp_msym);
2470
    }
2471
 
2472
  store_unsigned_integer (buf, TYPE_LENGTH (type), addr);
2473
}
2474
 
2475
 
2476
static CORE_ADDR
2477
m32c_m16c_pointer_to_address (struct type *type, const gdb_byte *buf)
2478
{
2479
  CORE_ADDR ptr;
2480
  enum type_code target_code;
2481
 
2482
  gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR ||
2483
              TYPE_CODE (type) == TYPE_CODE_REF);
2484
 
2485
  ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type));
2486
 
2487
  target_code = TYPE_CODE (TYPE_TARGET_TYPE (type));
2488
 
2489
  if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD)
2490
    {
2491
      /* See if there is a minimal symbol at that address whose name is
2492
         "NAME.plt".  */
2493
      struct minimal_symbol *ptr_msym = lookup_minimal_symbol_by_pc (ptr);
2494
 
2495
      if (ptr_msym)
2496
        {
2497
          char *ptr_msym_name = SYMBOL_LINKAGE_NAME (ptr_msym);
2498
          int len = strlen (ptr_msym_name);
2499
 
2500
          if (len > 4
2501
              && strcmp (ptr_msym_name + len - 4, ".plt") == 0)
2502
            {
2503
              struct minimal_symbol *func_msym;
2504
              /* We have a .plt symbol; try to find the symbol for the
2505
                 corresponding function.
2506
 
2507
                 Since the trampoline contains a jump instruction, we
2508
                 could also just extract the jump's target address.  I
2509
                 don't see much advantage one way or the other.  */
2510
              char *func_name = xmalloc (len - 4 + 1);
2511
              memcpy (func_name, ptr_msym_name, len - 4);
2512
              func_name[len - 4] = '\0';
2513
              func_msym
2514
                = lookup_minimal_symbol (func_name, NULL, NULL);
2515
 
2516
              /* If we do have such a symbol, return its value as the
2517
                 function's true address.  */
2518
              if (func_msym)
2519
                ptr = SYMBOL_VALUE_ADDRESS (func_msym);
2520
            }
2521
        }
2522
    }
2523
 
2524
  return ptr;
2525
}
2526
 
2527
void
2528
m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
2529
                            int *frame_regnum,
2530
                            LONGEST *frame_offset)
2531
{
2532
  char *name;
2533
  CORE_ADDR func_addr, func_end, sal_end;
2534
  struct m32c_prologue p;
2535
 
2536
  struct regcache *regcache = get_current_regcache ();
2537
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2538
 
2539
  if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
2540
    internal_error (__FILE__, __LINE__, _("No virtual frame pointer available"));
2541
 
2542
  m32c_analyze_prologue (gdbarch, func_addr, pc, &p);
2543
  switch (p.kind)
2544
    {
2545
    case prologue_with_frame_ptr:
2546
      *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num;
2547
      *frame_offset = p.frame_ptr_offset;
2548
      break;
2549
    case prologue_sans_frame_ptr:
2550
      *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num;
2551
      *frame_offset = p.frame_size;
2552
      break;
2553
    default:
2554
      *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num;
2555
      *frame_offset = 0;
2556
      break;
2557
    }
2558
  /* Sanity check */
2559
  if (*frame_regnum > gdbarch_num_regs (gdbarch))
2560
    internal_error (__FILE__, __LINE__, _("No virtual frame pointer available"));
2561
}
2562
 
2563
 
2564
/* Initialization.  */
2565
 
2566
static struct gdbarch *
2567
m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2568
{
2569
  struct gdbarch *arch;
2570
  struct gdbarch_tdep *tdep;
2571
  unsigned long mach = info.bfd_arch_info->mach;
2572
 
2573
  /* Find a candidate among the list of architectures we've created
2574
     already.  */
2575
  for (arches = gdbarch_list_lookup_by_info (arches, &info);
2576
       arches != NULL;
2577
       arches = gdbarch_list_lookup_by_info (arches->next, &info))
2578
    return arches->gdbarch;
2579
 
2580
  tdep = xcalloc (1, sizeof (*tdep));
2581
  arch = gdbarch_alloc (&info, tdep);
2582
 
2583
  /* Essential types.  */
2584
  make_types (arch);
2585
 
2586
  /* Address/pointer conversions.  */
2587
  if (mach == bfd_mach_m16c)
2588
    {
2589
      set_gdbarch_address_to_pointer (arch, m32c_m16c_address_to_pointer);
2590
      set_gdbarch_pointer_to_address (arch, m32c_m16c_pointer_to_address);
2591
    }
2592
 
2593
  /* Register set.  */
2594
  make_regs (arch);
2595
 
2596
  /* Disassembly.  */
2597
  set_gdbarch_print_insn (arch, print_insn_m32c);
2598
 
2599
  /* Breakpoints.  */
2600
  set_gdbarch_breakpoint_from_pc (arch, m32c_breakpoint_from_pc);
2601
 
2602
  /* Prologue analysis and unwinding.  */
2603
  set_gdbarch_inner_than (arch, core_addr_lessthan);
2604
  set_gdbarch_skip_prologue (arch, m32c_skip_prologue);
2605
  set_gdbarch_unwind_pc (arch, m32c_unwind_pc);
2606
  set_gdbarch_unwind_sp (arch, m32c_unwind_sp);
2607
#if 0
2608
  /* I'm dropping the dwarf2 sniffer because it has a few problems.
2609
     They may be in the dwarf2 cfi code in GDB, or they may be in
2610
     the debug info emitted by the upstream toolchain.  I don't
2611
     know which, but I do know that the prologue analyzer works better.
2612
     MVS 04/13/06
2613
  */
2614
  frame_unwind_append_sniffer (arch, dwarf2_frame_sniffer);
2615
#endif
2616
  frame_unwind_append_sniffer (arch, m32c_frame_sniffer);
2617
 
2618
  /* Inferior calls.  */
2619
  set_gdbarch_push_dummy_call (arch, m32c_push_dummy_call);
2620
  set_gdbarch_return_value (arch, m32c_return_value);
2621
  set_gdbarch_unwind_dummy_id (arch, m32c_unwind_dummy_id);
2622
 
2623
  /* Trampolines.  */
2624
  set_gdbarch_skip_trampoline_code (arch, m32c_skip_trampoline_code);
2625
 
2626
  set_gdbarch_virtual_frame_pointer (arch, m32c_virtual_frame_pointer);
2627
 
2628
  return arch;
2629
}
2630
 
2631
 
2632
void
2633
_initialize_m32c_tdep (void)
2634
{
2635
  register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init);
2636
 
2637
  m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP);
2638
}

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