URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [gdb/] [regformats/] [reg-m32r.dat] - Blame information for rev 827

Line No.	Rev	Author	Line
1	24	jeremybenn	`name:m32r`
2			`expedite:pc,lr,sp`
3			`32:r0`
4			`32:r1`
5			`32:r2`
6			`32:r3`
7			`32:r4`
8			`32:r5`
9			`32:r6`
10			`32:r7`
11			`32:r8`
12			`32:r9`
13			`32:r10`
14			`32:r11`
15			`32:r12`
16			`32:fp`
17			`32:lr`
18			`32:sp`
19			`32:psw`
20			`32:cbr`
21			`32:spi`
22			`32:spu`
23			`32:bpc`
24			`32:pc`
25			`32:accl`
26			`32:acch`
27			`32:evb`