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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [gdb/] [rs6000-tdep.c] - Blame information for rev 840

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1 24 jeremybenn
/* Target-dependent code for GDB, the GNU debugger.
2
 
3
   Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4
   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5
   Free Software Foundation, Inc.
6
 
7
   This file is part of GDB.
8
 
9
   This program is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3 of the License, or
12
   (at your option) any later version.
13
 
14
   This program is distributed in the hope that it will be useful,
15
   but WITHOUT ANY WARRANTY; without even the implied warranty of
16
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
   GNU General Public License for more details.
18
 
19
   You should have received a copy of the GNU General Public License
20
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
21
 
22
#include "defs.h"
23
#include "frame.h"
24
#include "inferior.h"
25
#include "symtab.h"
26
#include "target.h"
27
#include "gdbcore.h"
28
#include "gdbcmd.h"
29
#include "objfiles.h"
30
#include "arch-utils.h"
31
#include "regcache.h"
32
#include "regset.h"
33
#include "doublest.h"
34
#include "value.h"
35
#include "parser-defs.h"
36
#include "osabi.h"
37
#include "infcall.h"
38
#include "sim-regno.h"
39
#include "gdb/sim-ppc.h"
40
#include "reggroups.h"
41
#include "dwarf2-frame.h"
42
#include "target-descriptions.h"
43
#include "user-regs.h"
44
 
45
#include "libbfd.h"             /* for bfd_default_set_arch_mach */
46
#include "coff/internal.h"      /* for libcoff.h */
47
#include "libcoff.h"            /* for xcoff_data */
48
#include "coff/xcoff.h"
49
#include "libxcoff.h"
50
 
51
#include "elf-bfd.h"
52
#include "elf/ppc.h"
53
 
54
#include "solib-svr4.h"
55
#include "ppc-tdep.h"
56
 
57
#include "gdb_assert.h"
58
#include "dis-asm.h"
59
 
60
#include "trad-frame.h"
61
#include "frame-unwind.h"
62
#include "frame-base.h"
63
 
64
#include "rs6000-tdep.h"
65
 
66
#include "features/rs6000/powerpc-32.c"
67
#include "features/rs6000/powerpc-403.c"
68
#include "features/rs6000/powerpc-403gc.c"
69
#include "features/rs6000/powerpc-505.c"
70
#include "features/rs6000/powerpc-601.c"
71
#include "features/rs6000/powerpc-602.c"
72
#include "features/rs6000/powerpc-603.c"
73
#include "features/rs6000/powerpc-604.c"
74
#include "features/rs6000/powerpc-64.c"
75
#include "features/rs6000/powerpc-7400.c"
76
#include "features/rs6000/powerpc-750.c"
77
#include "features/rs6000/powerpc-860.c"
78
#include "features/rs6000/powerpc-e500.c"
79
#include "features/rs6000/rs6000.c"
80
 
81
/* Determine if regnum is an SPE pseudo-register.  */
82
#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
83
    && (regnum) >= (tdep)->ppc_ev0_regnum \
84
    && (regnum) < (tdep)->ppc_ev0_regnum + 32)
85
 
86
/* Determine if regnum is a decimal float pseudo-register.  */
87
#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
88
    && (regnum) >= (tdep)->ppc_dl0_regnum \
89
    && (regnum) < (tdep)->ppc_dl0_regnum + 16)
90
 
91
/* The list of available "set powerpc ..." and "show powerpc ..."
92
   commands.  */
93
static struct cmd_list_element *setpowerpccmdlist = NULL;
94
static struct cmd_list_element *showpowerpccmdlist = NULL;
95
 
96
static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
97
 
98
/* The vector ABI to use.  Keep this in sync with powerpc_vector_abi.  */
99
static const char *powerpc_vector_strings[] =
100
{
101
  "auto",
102
  "generic",
103
  "altivec",
104
  "spe",
105
  NULL
106
};
107
 
108
/* A variable that can be configured by the user.  */
109
static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
110
static const char *powerpc_vector_abi_string = "auto";
111
 
112
/* If the kernel has to deliver a signal, it pushes a sigcontext
113
   structure on the stack and then calls the signal handler, passing
114
   the address of the sigcontext in an argument register. Usually
115
   the signal handler doesn't save this register, so we have to
116
   access the sigcontext structure via an offset from the signal handler
117
   frame.
118
   The following constants were determined by experimentation on AIX 3.2.  */
119
#define SIG_FRAME_PC_OFFSET 96
120
#define SIG_FRAME_LR_OFFSET 108
121
#define SIG_FRAME_FP_OFFSET 284
122
 
123
/* To be used by skip_prologue. */
124
 
125
struct rs6000_framedata
126
  {
127
    int offset;                 /* total size of frame --- the distance
128
                                   by which we decrement sp to allocate
129
                                   the frame */
130
    int saved_gpr;              /* smallest # of saved gpr */
131
    int saved_fpr;              /* smallest # of saved fpr */
132
    int saved_vr;               /* smallest # of saved vr */
133
    int saved_ev;               /* smallest # of saved ev */
134
    int alloca_reg;             /* alloca register number (frame ptr) */
135
    char frameless;             /* true if frameless functions. */
136
    char nosavedpc;             /* true if pc not saved. */
137
    int gpr_offset;             /* offset of saved gprs from prev sp */
138
    int fpr_offset;             /* offset of saved fprs from prev sp */
139
    int vr_offset;              /* offset of saved vrs from prev sp */
140
    int ev_offset;              /* offset of saved evs from prev sp */
141
    int lr_offset;              /* offset of saved lr */
142
    int cr_offset;              /* offset of saved cr */
143
    int vrsave_offset;          /* offset of saved vrsave register */
144
  };
145
 
146
/* Description of a single register. */
147
 
148
struct reg
149
  {
150
    char *name;                 /* name of register */
151
    unsigned char sz32;         /* size on 32-bit arch, 0 if nonexistent */
152
    unsigned char sz64;         /* size on 64-bit arch, 0 if nonexistent */
153
    unsigned char fpr;          /* whether register is floating-point */
154
    unsigned char pseudo;       /* whether register is pseudo */
155
    int spr_num;                /* PowerPC SPR number, or -1 if not an SPR.
156
                                   This is an ISA SPR number, not a GDB
157
                                   register number.  */
158
  };
159
 
160
/* Hook for determining the TOC address when calling functions in the
161
   inferior under AIX. The initialization code in rs6000-nat.c sets
162
   this hook to point to find_toc_address.  */
163
 
164
CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
165
 
166
/* Static function prototypes */
167
 
168
static CORE_ADDR branch_dest (struct frame_info *frame, int opcode,
169
                              int instr, CORE_ADDR pc, CORE_ADDR safety);
170
static CORE_ADDR skip_prologue (struct gdbarch *, CORE_ADDR, CORE_ADDR,
171
                                struct rs6000_framedata *);
172
 
173
/* Is REGNO an AltiVec register?  Return 1 if so, 0 otherwise.  */
174
int
175
altivec_register_p (struct gdbarch *gdbarch, int regno)
176
{
177
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
178
  if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
179
    return 0;
180
  else
181
    return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
182
}
183
 
184
 
185
/* Return true if REGNO is an SPE register, false otherwise.  */
186
int
187
spe_register_p (struct gdbarch *gdbarch, int regno)
188
{
189
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
190
 
191
  /* Is it a reference to EV0 -- EV31, and do we have those?  */
192
  if (IS_SPE_PSEUDOREG (tdep, regno))
193
    return 1;
194
 
195
  /* Is it a reference to one of the raw upper GPR halves?  */
196
  if (tdep->ppc_ev0_upper_regnum >= 0
197
      && tdep->ppc_ev0_upper_regnum <= regno
198
      && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
199
    return 1;
200
 
201
  /* Is it a reference to the 64-bit accumulator, and do we have that?  */
202
  if (tdep->ppc_acc_regnum >= 0
203
      && tdep->ppc_acc_regnum == regno)
204
    return 1;
205
 
206
  /* Is it a reference to the SPE floating-point status and control register,
207
     and do we have that?  */
208
  if (tdep->ppc_spefscr_regnum >= 0
209
      && tdep->ppc_spefscr_regnum == regno)
210
    return 1;
211
 
212
  return 0;
213
}
214
 
215
 
216
/* Return non-zero if the architecture described by GDBARCH has
217
   floating-point registers (f0 --- f31 and fpscr).  */
218
int
219
ppc_floating_point_unit_p (struct gdbarch *gdbarch)
220
{
221
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
222
 
223
  return (tdep->ppc_fp0_regnum >= 0
224
          && tdep->ppc_fpscr_regnum >= 0);
225
}
226
 
227
/* Return non-zero if the architecture described by GDBARCH has
228
   Altivec registers (vr0 --- vr31, vrsave and vscr).  */
229
int
230
ppc_altivec_support_p (struct gdbarch *gdbarch)
231
{
232
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
233
 
234
  return (tdep->ppc_vr0_regnum >= 0
235
          && tdep->ppc_vrsave_regnum >= 0);
236
}
237
 
238
/* Check that TABLE[GDB_REGNO] is not already initialized, and then
239
   set it to SIM_REGNO.
240
 
241
   This is a helper function for init_sim_regno_table, constructing
242
   the table mapping GDB register numbers to sim register numbers; we
243
   initialize every element in that table to -1 before we start
244
   filling it in.  */
245
static void
246
set_sim_regno (int *table, int gdb_regno, int sim_regno)
247
{
248
  /* Make sure we don't try to assign any given GDB register a sim
249
     register number more than once.  */
250
  gdb_assert (table[gdb_regno] == -1);
251
  table[gdb_regno] = sim_regno;
252
}
253
 
254
 
255
/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
256
   numbers to simulator register numbers, based on the values placed
257
   in the ARCH->tdep->ppc_foo_regnum members.  */
258
static void
259
init_sim_regno_table (struct gdbarch *arch)
260
{
261
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
262
  int total_regs = gdbarch_num_regs (arch);
263
  int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
264
  int i;
265
  static const char *const segment_regs[] = {
266
    "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
267
    "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
268
  };
269
 
270
  /* Presume that all registers not explicitly mentioned below are
271
     unavailable from the sim.  */
272
  for (i = 0; i < total_regs; i++)
273
    sim_regno[i] = -1;
274
 
275
  /* General-purpose registers.  */
276
  for (i = 0; i < ppc_num_gprs; i++)
277
    set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
278
 
279
  /* Floating-point registers.  */
280
  if (tdep->ppc_fp0_regnum >= 0)
281
    for (i = 0; i < ppc_num_fprs; i++)
282
      set_sim_regno (sim_regno,
283
                     tdep->ppc_fp0_regnum + i,
284
                     sim_ppc_f0_regnum + i);
285
  if (tdep->ppc_fpscr_regnum >= 0)
286
    set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
287
 
288
  set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
289
  set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
290
  set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
291
 
292
  /* Segment registers.  */
293
  for (i = 0; i < ppc_num_srs; i++)
294
    {
295
      int gdb_regno;
296
 
297
      gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
298
      if (gdb_regno >= 0)
299
        set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
300
    }
301
 
302
  /* Altivec registers.  */
303
  if (tdep->ppc_vr0_regnum >= 0)
304
    {
305
      for (i = 0; i < ppc_num_vrs; i++)
306
        set_sim_regno (sim_regno,
307
                       tdep->ppc_vr0_regnum + i,
308
                       sim_ppc_vr0_regnum + i);
309
 
310
      /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
311
         we can treat this more like the other cases.  */
312
      set_sim_regno (sim_regno,
313
                     tdep->ppc_vr0_regnum + ppc_num_vrs,
314
                     sim_ppc_vscr_regnum);
315
    }
316
  /* vsave is a special-purpose register, so the code below handles it.  */
317
 
318
  /* SPE APU (E500) registers.  */
319
  if (tdep->ppc_ev0_upper_regnum >= 0)
320
    for (i = 0; i < ppc_num_gprs; i++)
321
      set_sim_regno (sim_regno,
322
                     tdep->ppc_ev0_upper_regnum + i,
323
                     sim_ppc_rh0_regnum + i);
324
  if (tdep->ppc_acc_regnum >= 0)
325
    set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
326
  /* spefscr is a special-purpose register, so the code below handles it.  */
327
 
328
#ifdef WITH_SIM
329
  /* Now handle all special-purpose registers.  Verify that they
330
     haven't mistakenly been assigned numbers by any of the above
331
     code.  */
332
  for (i = 0; i < sim_ppc_num_sprs; i++)
333
    {
334
      const char *spr_name = sim_spr_register_name (i);
335
      int gdb_regno = -1;
336
 
337
      if (spr_name != NULL)
338
        gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
339
 
340
      if (gdb_regno != -1)
341
        set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
342
    }
343
#endif
344
 
345
  /* Drop the initialized array into place.  */
346
  tdep->sim_regno = sim_regno;
347
}
348
 
349
 
350
/* Given a GDB register number REG, return the corresponding SIM
351
   register number.  */
352
static int
353
rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
354
{
355
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
356
  int sim_regno;
357
 
358
  if (tdep->sim_regno == NULL)
359
    init_sim_regno_table (gdbarch);
360
 
361
  gdb_assert (0 <= reg
362
              && reg <= gdbarch_num_regs (gdbarch)
363
                        + gdbarch_num_pseudo_regs (gdbarch));
364
  sim_regno = tdep->sim_regno[reg];
365
 
366
  if (sim_regno >= 0)
367
    return sim_regno;
368
  else
369
    return LEGACY_SIM_REGNO_IGNORE;
370
}
371
 
372
 
373
 
374
/* Register set support functions.  */
375
 
376
/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
377
   Write the register to REGCACHE.  */
378
 
379
static void
380
ppc_supply_reg (struct regcache *regcache, int regnum,
381
                const gdb_byte *regs, size_t offset, int regsize)
382
{
383
  if (regnum != -1 && offset != -1)
384
    {
385
      if (regsize > 4)
386
        {
387
          struct gdbarch *gdbarch = get_regcache_arch (regcache);
388
          int gdb_regsize = register_size (gdbarch, regnum);
389
          if (gdb_regsize < regsize
390
              && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
391
            offset += regsize - gdb_regsize;
392
        }
393
      regcache_raw_supply (regcache, regnum, regs + offset);
394
    }
395
}
396
 
397
/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
398
   in a field REGSIZE wide.  Zero pad as necessary.  */
399
 
400
static void
401
ppc_collect_reg (const struct regcache *regcache, int regnum,
402
                 gdb_byte *regs, size_t offset, int regsize)
403
{
404
  if (regnum != -1 && offset != -1)
405
    {
406
      if (regsize > 4)
407
        {
408
          struct gdbarch *gdbarch = get_regcache_arch (regcache);
409
          int gdb_regsize = register_size (gdbarch, regnum);
410
          if (gdb_regsize < regsize)
411
            {
412
              if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
413
                {
414
                  memset (regs + offset, 0, regsize - gdb_regsize);
415
                  offset += regsize - gdb_regsize;
416
                }
417
              else
418
                memset (regs + offset + regsize - gdb_regsize, 0,
419
                        regsize - gdb_regsize);
420
            }
421
        }
422
      regcache_raw_collect (regcache, regnum, regs + offset);
423
    }
424
}
425
 
426
static int
427
ppc_greg_offset (struct gdbarch *gdbarch,
428
                 struct gdbarch_tdep *tdep,
429
                 const struct ppc_reg_offsets *offsets,
430
                 int regnum,
431
                 int *regsize)
432
{
433
  *regsize = offsets->gpr_size;
434
  if (regnum >= tdep->ppc_gp0_regnum
435
      && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
436
    return (offsets->r0_offset
437
            + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
438
 
439
  if (regnum == gdbarch_pc_regnum (gdbarch))
440
    return offsets->pc_offset;
441
 
442
  if (regnum == tdep->ppc_ps_regnum)
443
    return offsets->ps_offset;
444
 
445
  if (regnum == tdep->ppc_lr_regnum)
446
    return offsets->lr_offset;
447
 
448
  if (regnum == tdep->ppc_ctr_regnum)
449
    return offsets->ctr_offset;
450
 
451
  *regsize = offsets->xr_size;
452
  if (regnum == tdep->ppc_cr_regnum)
453
    return offsets->cr_offset;
454
 
455
  if (regnum == tdep->ppc_xer_regnum)
456
    return offsets->xer_offset;
457
 
458
  if (regnum == tdep->ppc_mq_regnum)
459
    return offsets->mq_offset;
460
 
461
  return -1;
462
}
463
 
464
static int
465
ppc_fpreg_offset (struct gdbarch_tdep *tdep,
466
                  const struct ppc_reg_offsets *offsets,
467
                  int regnum)
468
{
469
  if (regnum >= tdep->ppc_fp0_regnum
470
      && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
471
    return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
472
 
473
  if (regnum == tdep->ppc_fpscr_regnum)
474
    return offsets->fpscr_offset;
475
 
476
  return -1;
477
}
478
 
479
static int
480
ppc_vrreg_offset (struct gdbarch_tdep *tdep,
481
                  const struct ppc_reg_offsets *offsets,
482
                  int regnum)
483
{
484
  if (regnum >= tdep->ppc_vr0_regnum
485
      && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
486
    return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
487
 
488
  if (regnum == tdep->ppc_vrsave_regnum - 1)
489
    return offsets->vscr_offset;
490
 
491
  if (regnum == tdep->ppc_vrsave_regnum)
492
    return offsets->vrsave_offset;
493
 
494
  return -1;
495
}
496
 
497
/* Supply register REGNUM in the general-purpose register set REGSET
498
   from the buffer specified by GREGS and LEN to register cache
499
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
500
 
501
void
502
ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
503
                    int regnum, const void *gregs, size_t len)
504
{
505
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
506
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
507
  const struct ppc_reg_offsets *offsets = regset->descr;
508
  size_t offset;
509
  int regsize;
510
 
511
  if (regnum == -1)
512
    {
513
      int i;
514
      int gpr_size = offsets->gpr_size;
515
 
516
      for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
517
           i < tdep->ppc_gp0_regnum + ppc_num_gprs;
518
           i++, offset += gpr_size)
519
        ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
520
 
521
      ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
522
                      gregs, offsets->pc_offset, gpr_size);
523
      ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
524
                      gregs, offsets->ps_offset, gpr_size);
525
      ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
526
                      gregs, offsets->lr_offset, gpr_size);
527
      ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
528
                      gregs, offsets->ctr_offset, gpr_size);
529
      ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
530
                      gregs, offsets->cr_offset, offsets->xr_size);
531
      ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
532
                      gregs, offsets->xer_offset, offsets->xr_size);
533
      ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
534
                      gregs, offsets->mq_offset, offsets->xr_size);
535
      return;
536
    }
537
 
538
  offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
539
  ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
540
}
541
 
542
/* Supply register REGNUM in the floating-point register set REGSET
543
   from the buffer specified by FPREGS and LEN to register cache
544
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
545
 
546
void
547
ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
548
                     int regnum, const void *fpregs, size_t len)
549
{
550
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
551
  struct gdbarch_tdep *tdep;
552
  const struct ppc_reg_offsets *offsets;
553
  size_t offset;
554
 
555
  if (!ppc_floating_point_unit_p (gdbarch))
556
    return;
557
 
558
  tdep = gdbarch_tdep (gdbarch);
559
  offsets = regset->descr;
560
  if (regnum == -1)
561
    {
562
      int i;
563
 
564
      for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
565
           i < tdep->ppc_fp0_regnum + ppc_num_fprs;
566
           i++, offset += 8)
567
        ppc_supply_reg (regcache, i, fpregs, offset, 8);
568
 
569
      ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
570
                      fpregs, offsets->fpscr_offset, offsets->fpscr_size);
571
      return;
572
    }
573
 
574
  offset = ppc_fpreg_offset (tdep, offsets, regnum);
575
  ppc_supply_reg (regcache, regnum, fpregs, offset,
576
                  regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
577
}
578
 
579
/* Supply register REGNUM in the Altivec register set REGSET
580
   from the buffer specified by VRREGS and LEN to register cache
581
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
582
 
583
void
584
ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
585
                     int regnum, const void *vrregs, size_t len)
586
{
587
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
588
  struct gdbarch_tdep *tdep;
589
  const struct ppc_reg_offsets *offsets;
590
  size_t offset;
591
 
592
  if (!ppc_altivec_support_p (gdbarch))
593
    return;
594
 
595
  tdep = gdbarch_tdep (gdbarch);
596
  offsets = regset->descr;
597
  if (regnum == -1)
598
    {
599
      int i;
600
 
601
      for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
602
           i < tdep->ppc_vr0_regnum + ppc_num_vrs;
603
           i++, offset += 16)
604
        ppc_supply_reg (regcache, i, vrregs, offset, 16);
605
 
606
      ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
607
                      vrregs, offsets->vscr_offset, 4);
608
 
609
      ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
610
                      vrregs, offsets->vrsave_offset, 4);
611
      return;
612
    }
613
 
614
  offset = ppc_vrreg_offset (tdep, offsets, regnum);
615
  if (regnum != tdep->ppc_vrsave_regnum
616
      && regnum != tdep->ppc_vrsave_regnum - 1)
617
    ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
618
  else
619
    ppc_supply_reg (regcache, regnum,
620
                    vrregs, offset, 4);
621
}
622
 
623
/* Collect register REGNUM in the general-purpose register set
624
   REGSET from register cache REGCACHE into the buffer specified by
625
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
626
   REGSET.  */
627
 
628
void
629
ppc_collect_gregset (const struct regset *regset,
630
                     const struct regcache *regcache,
631
                     int regnum, void *gregs, size_t len)
632
{
633
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
634
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
635
  const struct ppc_reg_offsets *offsets = regset->descr;
636
  size_t offset;
637
  int regsize;
638
 
639
  if (regnum == -1)
640
    {
641
      int i;
642
      int gpr_size = offsets->gpr_size;
643
 
644
      for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
645
           i < tdep->ppc_gp0_regnum + ppc_num_gprs;
646
           i++, offset += gpr_size)
647
        ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
648
 
649
      ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
650
                       gregs, offsets->pc_offset, gpr_size);
651
      ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
652
                       gregs, offsets->ps_offset, gpr_size);
653
      ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
654
                       gregs, offsets->lr_offset, gpr_size);
655
      ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
656
                       gregs, offsets->ctr_offset, gpr_size);
657
      ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
658
                       gregs, offsets->cr_offset, offsets->xr_size);
659
      ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
660
                       gregs, offsets->xer_offset, offsets->xr_size);
661
      ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
662
                       gregs, offsets->mq_offset, offsets->xr_size);
663
      return;
664
    }
665
 
666
  offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
667
  ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
668
}
669
 
670
/* Collect register REGNUM in the floating-point register set
671
   REGSET from register cache REGCACHE into the buffer specified by
672
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
673
   REGSET.  */
674
 
675
void
676
ppc_collect_fpregset (const struct regset *regset,
677
                      const struct regcache *regcache,
678
                      int regnum, void *fpregs, size_t len)
679
{
680
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
681
  struct gdbarch_tdep *tdep;
682
  const struct ppc_reg_offsets *offsets;
683
  size_t offset;
684
 
685
  if (!ppc_floating_point_unit_p (gdbarch))
686
    return;
687
 
688
  tdep = gdbarch_tdep (gdbarch);
689
  offsets = regset->descr;
690
  if (regnum == -1)
691
    {
692
      int i;
693
 
694
      for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
695
           i < tdep->ppc_fp0_regnum + ppc_num_fprs;
696
           i++, offset += 8)
697
        ppc_collect_reg (regcache, i, fpregs, offset, 8);
698
 
699
      ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
700
                       fpregs, offsets->fpscr_offset, offsets->fpscr_size);
701
      return;
702
    }
703
 
704
  offset = ppc_fpreg_offset (tdep, offsets, regnum);
705
  ppc_collect_reg (regcache, regnum, fpregs, offset,
706
                   regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
707
}
708
 
709
/* Collect register REGNUM in the Altivec register set
710
   REGSET from register cache REGCACHE into the buffer specified by
711
   VRREGS and LEN.  If REGNUM is -1, do this for all registers in
712
   REGSET.  */
713
 
714
void
715
ppc_collect_vrregset (const struct regset *regset,
716
                      const struct regcache *regcache,
717
                      int regnum, void *vrregs, size_t len)
718
{
719
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
720
  struct gdbarch_tdep *tdep;
721
  const struct ppc_reg_offsets *offsets;
722
  size_t offset;
723
 
724
  if (!ppc_altivec_support_p (gdbarch))
725
    return;
726
 
727
  tdep = gdbarch_tdep (gdbarch);
728
  offsets = regset->descr;
729
  if (regnum == -1)
730
    {
731
      int i;
732
 
733
      for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
734
           i < tdep->ppc_vr0_regnum + ppc_num_vrs;
735
           i++, offset += 16)
736
        ppc_collect_reg (regcache, i, vrregs, offset, 16);
737
 
738
      ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
739
                       vrregs, offsets->vscr_offset, 4);
740
 
741
      ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
742
                       vrregs, offsets->vrsave_offset, 4);
743
      return;
744
    }
745
 
746
  offset = ppc_vrreg_offset (tdep, offsets, regnum);
747
  if (regnum != tdep->ppc_vrsave_regnum
748
      && regnum != tdep->ppc_vrsave_regnum - 1)
749
    ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
750
  else
751
    ppc_collect_reg (regcache, regnum,
752
                    vrregs, offset, 4);
753
}
754
 
755
 
756
/* Read a LEN-byte address from debugged memory address MEMADDR. */
757
 
758
static CORE_ADDR
759
read_memory_addr (CORE_ADDR memaddr, int len)
760
{
761
  return read_memory_unsigned_integer (memaddr, len);
762
}
763
 
764
static CORE_ADDR
765
rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
766
{
767
  struct rs6000_framedata frame;
768
  CORE_ADDR limit_pc, func_addr;
769
 
770
  /* See if we can determine the end of the prologue via the symbol table.
771
     If so, then return either PC, or the PC after the prologue, whichever
772
     is greater.  */
773
  if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
774
    {
775
      CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
776
      if (post_prologue_pc != 0)
777
        return max (pc, post_prologue_pc);
778
    }
779
 
780
  /* Can't determine prologue from the symbol table, need to examine
781
     instructions.  */
782
 
783
  /* Find an upper limit on the function prologue using the debug
784
     information.  If the debug information could not be used to provide
785
     that bound, then use an arbitrary large number as the upper bound.  */
786
  limit_pc = skip_prologue_using_sal (pc);
787
  if (limit_pc == 0)
788
    limit_pc = pc + 100;          /* Magic.  */
789
 
790
  pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
791
  return pc;
792
}
793
 
794
static int
795
insn_changes_sp_or_jumps (unsigned long insn)
796
{
797
  int opcode = (insn >> 26) & 0x03f;
798
  int sd = (insn >> 21) & 0x01f;
799
  int a = (insn >> 16) & 0x01f;
800
  int subcode = (insn >> 1) & 0x3ff;
801
 
802
  /* Changes the stack pointer.  */
803
 
804
  /* NOTE: There are many ways to change the value of a given register.
805
           The ways below are those used when the register is R1, the SP,
806
           in a funtion's epilogue.  */
807
 
808
  if (opcode == 31 && subcode == 444 && a == 1)
809
    return 1;  /* mr R1,Rn */
810
  if (opcode == 14 && sd == 1)
811
    return 1;  /* addi R1,Rn,simm */
812
  if (opcode == 58 && sd == 1)
813
    return 1;  /* ld R1,ds(Rn) */
814
 
815
  /* Transfers control.  */
816
 
817
  if (opcode == 18)
818
    return 1;  /* b */
819
  if (opcode == 16)
820
    return 1;  /* bc */
821
  if (opcode == 19 && subcode == 16)
822
    return 1;  /* bclr */
823
  if (opcode == 19 && subcode == 528)
824
    return 1;  /* bcctr */
825
 
826
  return 0;
827
}
828
 
829
/* Return true if we are in the function's epilogue, i.e. after the
830
   instruction that destroyed the function's stack frame.
831
 
832
   1) scan forward from the point of execution:
833
       a) If you find an instruction that modifies the stack pointer
834
          or transfers control (except a return), execution is not in
835
          an epilogue, return.
836
       b) Stop scanning if you find a return instruction or reach the
837
          end of the function or reach the hard limit for the size of
838
          an epilogue.
839
   2) scan backward from the point of execution:
840
        a) If you find an instruction that modifies the stack pointer,
841
            execution *is* in an epilogue, return.
842
        b) Stop scanning if you reach an instruction that transfers
843
           control or the beginning of the function or reach the hard
844
           limit for the size of an epilogue.  */
845
 
846
static int
847
rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
848
{
849
  bfd_byte insn_buf[PPC_INSN_SIZE];
850
  CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
851
  unsigned long insn;
852
  struct frame_info *curfrm;
853
 
854
  /* Find the search limits based on function boundaries and hard limit.  */
855
 
856
  if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
857
    return 0;
858
 
859
  epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
860
  if (epilogue_start < func_start) epilogue_start = func_start;
861
 
862
  epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
863
  if (epilogue_end > func_end) epilogue_end = func_end;
864
 
865
  curfrm = get_current_frame ();
866
 
867
  /* Scan forward until next 'blr'.  */
868
 
869
  for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
870
    {
871
      if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
872
        return 0;
873
      insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
874
      if (insn == 0x4e800020)
875
        break;
876
      if (insn_changes_sp_or_jumps (insn))
877
        return 0;
878
    }
879
 
880
  /* Scan backward until adjustment to stack pointer (R1).  */
881
 
882
  for (scan_pc = pc - PPC_INSN_SIZE;
883
       scan_pc >= epilogue_start;
884
       scan_pc -= PPC_INSN_SIZE)
885
    {
886
      if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
887
        return 0;
888
      insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
889
      if (insn_changes_sp_or_jumps (insn))
890
        return 1;
891
    }
892
 
893
  return 0;
894
}
895
 
896
/* Get the ith function argument for the current function.  */
897
static CORE_ADDR
898
rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
899
                               struct type *type)
900
{
901
  return get_frame_register_unsigned (frame, 3 + argi);
902
}
903
 
904
/* Calculate the destination of a branch/jump.  Return -1 if not a branch.  */
905
 
906
static CORE_ADDR
907
branch_dest (struct frame_info *frame, int opcode, int instr,
908
             CORE_ADDR pc, CORE_ADDR safety)
909
{
910
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
911
  CORE_ADDR dest;
912
  int immediate;
913
  int absolute;
914
  int ext_op;
915
 
916
  absolute = (int) ((instr >> 1) & 1);
917
 
918
  switch (opcode)
919
    {
920
    case 18:
921
      immediate = ((instr & ~3) << 6) >> 6;     /* br unconditional */
922
      if (absolute)
923
        dest = immediate;
924
      else
925
        dest = pc + immediate;
926
      break;
927
 
928
    case 16:
929
      immediate = ((instr & ~3) << 16) >> 16;   /* br conditional */
930
      if (absolute)
931
        dest = immediate;
932
      else
933
        dest = pc + immediate;
934
      break;
935
 
936
    case 19:
937
      ext_op = (instr >> 1) & 0x3ff;
938
 
939
      if (ext_op == 16)         /* br conditional register */
940
        {
941
          dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3;
942
 
943
          /* If we are about to return from a signal handler, dest is
944
             something like 0x3c90.  The current frame is a signal handler
945
             caller frame, upon completion of the sigreturn system call
946
             execution will return to the saved PC in the frame.  */
947
          if (dest < tdep->text_segment_base)
948
            dest = read_memory_addr (get_frame_base (frame) + SIG_FRAME_PC_OFFSET,
949
                                     tdep->wordsize);
950
        }
951
 
952
      else if (ext_op == 528)   /* br cond to count reg */
953
        {
954
          dest = get_frame_register_unsigned (frame, tdep->ppc_ctr_regnum) & ~3;
955
 
956
          /* If we are about to execute a system call, dest is something
957
             like 0x22fc or 0x3b00.  Upon completion the system call
958
             will return to the address in the link register.  */
959
          if (dest < tdep->text_segment_base)
960
            dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3;
961
        }
962
      else
963
        return -1;
964
      break;
965
 
966
    default:
967
      return -1;
968
    }
969
  return (dest < tdep->text_segment_base) ? safety : dest;
970
}
971
 
972
 
973
/* Sequence of bytes for breakpoint instruction.  */
974
 
975
const static unsigned char *
976
rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
977
                           int *bp_size)
978
{
979
  static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
980
  static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
981
  *bp_size = 4;
982
  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
983
    return big_breakpoint;
984
  else
985
    return little_breakpoint;
986
}
987
 
988
 
989
/* Instruction masks used during single-stepping of atomic sequences.  */
990
#define LWARX_MASK 0xfc0007fe
991
#define LWARX_INSTRUCTION 0x7c000028
992
#define LDARX_INSTRUCTION 0x7c0000A8
993
#define STWCX_MASK 0xfc0007ff
994
#define STWCX_INSTRUCTION 0x7c00012d
995
#define STDCX_INSTRUCTION 0x7c0001ad
996
#define BC_MASK 0xfc000000
997
#define BC_INSTRUCTION 0x40000000
998
 
999
/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1000
   instruction and ending with a STWCX/STDCX instruction.  If such a sequence
1001
   is found, attempt to step through it.  A breakpoint is placed at the end of
1002
   the sequence.  */
1003
 
1004
static int
1005
deal_with_atomic_sequence (struct frame_info *frame)
1006
{
1007
  CORE_ADDR pc = get_frame_pc (frame);
1008
  CORE_ADDR breaks[2] = {-1, -1};
1009
  CORE_ADDR loc = pc;
1010
  CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination.  */
1011
  CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence.  */
1012
  int insn = read_memory_integer (loc, PPC_INSN_SIZE);
1013
  int insn_count;
1014
  int index;
1015
  int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed).  */
1016
  const int atomic_sequence_length = 16; /* Instruction sequence length.  */
1017
  int opcode; /* Branch instruction's OPcode.  */
1018
  int bc_insn_count = 0; /* Conditional branch instruction count.  */
1019
 
1020
  /* Assume all atomic sequences start with a lwarx/ldarx instruction.  */
1021
  if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1022
      && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1023
    return 0;
1024
 
1025
  /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1026
     instructions.  */
1027
  for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1028
    {
1029
      loc += PPC_INSN_SIZE;
1030
      insn = read_memory_integer (loc, PPC_INSN_SIZE);
1031
 
1032
      /* Assume that there is at most one conditional branch in the atomic
1033
         sequence.  If a conditional branch is found, put a breakpoint in
1034
         its destination address.  */
1035
      if ((insn & BC_MASK) == BC_INSTRUCTION)
1036
        {
1037
          if (bc_insn_count >= 1)
1038
            return 0; /* More than one conditional branch found, fallback
1039
                         to the standard single-step code.  */
1040
 
1041
          opcode = insn >> 26;
1042
          branch_bp = branch_dest (frame, opcode, insn, pc, breaks[0]);
1043
 
1044
          if (branch_bp != -1)
1045
            {
1046
              breaks[1] = branch_bp;
1047
              bc_insn_count++;
1048
              last_breakpoint++;
1049
            }
1050
        }
1051
 
1052
      if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1053
          || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1054
        break;
1055
    }
1056
 
1057
  /* Assume that the atomic sequence ends with a stwcx/stdcx instruction.  */
1058
  if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1059
      && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1060
    return 0;
1061
 
1062
  closing_insn = loc;
1063
  loc += PPC_INSN_SIZE;
1064
  insn = read_memory_integer (loc, PPC_INSN_SIZE);
1065
 
1066
  /* Insert a breakpoint right after the end of the atomic sequence.  */
1067
  breaks[0] = loc;
1068
 
1069
  /* Check for duplicated breakpoints.  Check also for a breakpoint
1070
     placed (branch instruction's destination) at the stwcx/stdcx
1071
     instruction, this resets the reservation and take us back to the
1072
     lwarx/ldarx instruction at the beginning of the atomic sequence.  */
1073
  if (last_breakpoint && ((breaks[1] == breaks[0])
1074
      || (breaks[1] == closing_insn)))
1075
    last_breakpoint = 0;
1076
 
1077
  /* Effectively inserts the breakpoints.  */
1078
  for (index = 0; index <= last_breakpoint; index++)
1079
    insert_single_step_breakpoint (breaks[index]);
1080
 
1081
  return 1;
1082
}
1083
 
1084
/* AIX does not support PT_STEP.  Simulate it.  */
1085
 
1086
int
1087
rs6000_software_single_step (struct frame_info *frame)
1088
{
1089
  CORE_ADDR dummy;
1090
  int breakp_sz;
1091
  const gdb_byte *breakp
1092
    = rs6000_breakpoint_from_pc (get_frame_arch (frame), &dummy, &breakp_sz);
1093
  int ii, insn;
1094
  CORE_ADDR loc;
1095
  CORE_ADDR breaks[2];
1096
  int opcode;
1097
 
1098
  loc = get_frame_pc (frame);
1099
 
1100
  insn = read_memory_integer (loc, 4);
1101
 
1102
  if (deal_with_atomic_sequence (frame))
1103
    return 1;
1104
 
1105
  breaks[0] = loc + breakp_sz;
1106
  opcode = insn >> 26;
1107
  breaks[1] = branch_dest (frame, opcode, insn, loc, breaks[0]);
1108
 
1109
  /* Don't put two breakpoints on the same address. */
1110
  if (breaks[1] == breaks[0])
1111
    breaks[1] = -1;
1112
 
1113
  for (ii = 0; ii < 2; ++ii)
1114
    {
1115
      /* ignore invalid breakpoint. */
1116
      if (breaks[ii] == -1)
1117
        continue;
1118
      insert_single_step_breakpoint (breaks[ii]);
1119
    }
1120
 
1121
  errno = 0;                     /* FIXME, don't ignore errors! */
1122
  /* What errors?  {read,write}_memory call error().  */
1123
  return 1;
1124
}
1125
 
1126
 
1127
#define SIGNED_SHORT(x)                                                 \
1128
  ((sizeof (short) == 2)                                                \
1129
   ? ((int)(short)(x))                                                  \
1130
   : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1131
 
1132
#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1133
 
1134
/* Limit the number of skipped non-prologue instructions, as the examining
1135
   of the prologue is expensive.  */
1136
static int max_skip_non_prologue_insns = 10;
1137
 
1138
/* Return nonzero if the given instruction OP can be part of the prologue
1139
   of a function and saves a parameter on the stack.  FRAMEP should be
1140
   set if one of the previous instructions in the function has set the
1141
   Frame Pointer.  */
1142
 
1143
static int
1144
store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1145
{
1146
  /* Move parameters from argument registers to temporary register.  */
1147
  if ((op & 0xfc0007fe) == 0x7c000378)         /* mr(.)  Rx,Ry */
1148
    {
1149
      /* Rx must be scratch register r0.  */
1150
      const int rx_regno = (op >> 16) & 31;
1151
      /* Ry: Only r3 - r10 are used for parameter passing.  */
1152
      const int ry_regno = GET_SRC_REG (op);
1153
 
1154
      if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1155
        {
1156
          *r0_contains_arg = 1;
1157
          return 1;
1158
        }
1159
      else
1160
        return 0;
1161
    }
1162
 
1163
  /* Save a General Purpose Register on stack.  */
1164
 
1165
  if ((op & 0xfc1f0003) == 0xf8010000 ||       /* std  Rx,NUM(r1) */
1166
      (op & 0xfc1f0000) == 0xd8010000)         /* stfd Rx,NUM(r1) */
1167
    {
1168
      /* Rx: Only r3 - r10 are used for parameter passing.  */
1169
      const int rx_regno = GET_SRC_REG (op);
1170
 
1171
      return (rx_regno >= 3 && rx_regno <= 10);
1172
    }
1173
 
1174
  /* Save a General Purpose Register on stack via the Frame Pointer.  */
1175
 
1176
  if (framep &&
1177
      ((op & 0xfc1f0000) == 0x901f0000 ||     /* st rx,NUM(r31) */
1178
       (op & 0xfc1f0000) == 0x981f0000 ||     /* stb Rx,NUM(r31) */
1179
       (op & 0xfc1f0000) == 0xd81f0000))      /* stfd Rx,NUM(r31) */
1180
    {
1181
      /* Rx: Usually, only r3 - r10 are used for parameter passing.
1182
         However, the compiler sometimes uses r0 to hold an argument.  */
1183
      const int rx_regno = GET_SRC_REG (op);
1184
 
1185
      return ((rx_regno >= 3 && rx_regno <= 10)
1186
              || (rx_regno == 0 && *r0_contains_arg));
1187
    }
1188
 
1189
  if ((op & 0xfc1f0000) == 0xfc010000)         /* frsp, fp?,NUM(r1) */
1190
    {
1191
      /* Only f2 - f8 are used for parameter passing.  */
1192
      const int src_regno = GET_SRC_REG (op);
1193
 
1194
      return (src_regno >= 2 && src_regno <= 8);
1195
    }
1196
 
1197
  if (framep && ((op & 0xfc1f0000) == 0xfc1f0000))  /* frsp, fp?,NUM(r31) */
1198
    {
1199
      /* Only f2 - f8 are used for parameter passing.  */
1200
      const int src_regno = GET_SRC_REG (op);
1201
 
1202
      return (src_regno >= 2 && src_regno <= 8);
1203
    }
1204
 
1205
  /* Not an insn that saves a parameter on stack.  */
1206
  return 0;
1207
}
1208
 
1209
/* Assuming that INSN is a "bl" instruction located at PC, return
1210
   nonzero if the destination of the branch is a "blrl" instruction.
1211
 
1212
   This sequence is sometimes found in certain function prologues.
1213
   It allows the function to load the LR register with a value that
1214
   they can use to access PIC data using PC-relative offsets.  */
1215
 
1216
static int
1217
bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
1218
{
1219
  CORE_ADDR dest;
1220
  int immediate;
1221
  int absolute;
1222
  int dest_insn;
1223
 
1224
  absolute = (int) ((insn >> 1) & 1);
1225
  immediate = ((insn & ~3) << 6) >> 6;
1226
  if (absolute)
1227
    dest = immediate;
1228
  else
1229
    dest = pc + immediate;
1230
 
1231
  dest_insn = read_memory_integer (dest, 4);
1232
  if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1233
    return 1;
1234
 
1235
  return 0;
1236
}
1237
 
1238
/* return pc value after skipping a function prologue and also return
1239
   information about a function frame.
1240
 
1241
   in struct rs6000_framedata fdata:
1242
   - frameless is TRUE, if function does not have a frame.
1243
   - nosavedpc is TRUE, if function does not save %pc value in its frame.
1244
   - offset is the initial size of this stack frame --- the amount by
1245
   which we decrement the sp to allocate the frame.
1246
   - saved_gpr is the number of the first saved gpr.
1247
   - saved_fpr is the number of the first saved fpr.
1248
   - saved_vr is the number of the first saved vr.
1249
   - saved_ev is the number of the first saved ev.
1250
   - alloca_reg is the number of the register used for alloca() handling.
1251
   Otherwise -1.
1252
   - gpr_offset is the offset of the first saved gpr from the previous frame.
1253
   - fpr_offset is the offset of the first saved fpr from the previous frame.
1254
   - vr_offset is the offset of the first saved vr from the previous frame.
1255
   - ev_offset is the offset of the first saved ev from the previous frame.
1256
   - lr_offset is the offset of the saved lr
1257
   - cr_offset is the offset of the saved cr
1258
   - vrsave_offset is the offset of the saved vrsave register
1259
 */
1260
 
1261
static CORE_ADDR
1262
skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1263
               struct rs6000_framedata *fdata)
1264
{
1265
  CORE_ADDR orig_pc = pc;
1266
  CORE_ADDR last_prologue_pc = pc;
1267
  CORE_ADDR li_found_pc = 0;
1268
  gdb_byte buf[4];
1269
  unsigned long op;
1270
  long offset = 0;
1271
  long vr_saved_offset = 0;
1272
  int lr_reg = -1;
1273
  int cr_reg = -1;
1274
  int vr_reg = -1;
1275
  int ev_reg = -1;
1276
  long ev_offset = 0;
1277
  int vrsave_reg = -1;
1278
  int reg;
1279
  int framep = 0;
1280
  int minimal_toc_loaded = 0;
1281
  int prev_insn_was_prologue_insn = 1;
1282
  int num_skip_non_prologue_insns = 0;
1283
  int r0_contains_arg = 0;
1284
  const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1285
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1286
 
1287
  memset (fdata, 0, sizeof (struct rs6000_framedata));
1288
  fdata->saved_gpr = -1;
1289
  fdata->saved_fpr = -1;
1290
  fdata->saved_vr = -1;
1291
  fdata->saved_ev = -1;
1292
  fdata->alloca_reg = -1;
1293
  fdata->frameless = 1;
1294
  fdata->nosavedpc = 1;
1295
 
1296
  for (;; pc += 4)
1297
    {
1298
      /* Sometimes it isn't clear if an instruction is a prologue
1299
         instruction or not.  When we encounter one of these ambiguous
1300
         cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1301
         Otherwise, we'll assume that it really is a prologue instruction. */
1302
      if (prev_insn_was_prologue_insn)
1303
        last_prologue_pc = pc;
1304
 
1305
      /* Stop scanning if we've hit the limit.  */
1306
      if (pc >= lim_pc)
1307
        break;
1308
 
1309
      prev_insn_was_prologue_insn = 1;
1310
 
1311
      /* Fetch the instruction and convert it to an integer.  */
1312
      if (target_read_memory (pc, buf, 4))
1313
        break;
1314
      op = extract_unsigned_integer (buf, 4);
1315
 
1316
      if ((op & 0xfc1fffff) == 0x7c0802a6)
1317
        {                       /* mflr Rx */
1318
          /* Since shared library / PIC code, which needs to get its
1319
             address at runtime, can appear to save more than one link
1320
             register vis:
1321
 
1322
             *INDENT-OFF*
1323
             stwu r1,-304(r1)
1324
             mflr r3
1325
             bl 0xff570d0 (blrl)
1326
             stw r30,296(r1)
1327
             mflr r30
1328
             stw r31,300(r1)
1329
             stw r3,308(r1);
1330
             ...
1331
             *INDENT-ON*
1332
 
1333
             remember just the first one, but skip over additional
1334
             ones.  */
1335
          if (lr_reg == -1)
1336
            lr_reg = (op & 0x03e00000);
1337
          if (lr_reg == 0)
1338
            r0_contains_arg = 0;
1339
          continue;
1340
        }
1341
      else if ((op & 0xfc1fffff) == 0x7c000026)
1342
        {                       /* mfcr Rx */
1343
          cr_reg = (op & 0x03e00000);
1344
          if (cr_reg == 0)
1345
            r0_contains_arg = 0;
1346
          continue;
1347
 
1348
        }
1349
      else if ((op & 0xfc1f0000) == 0xd8010000)
1350
        {                       /* stfd Rx,NUM(r1) */
1351
          reg = GET_SRC_REG (op);
1352
          if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1353
            {
1354
              fdata->saved_fpr = reg;
1355
              fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1356
            }
1357
          continue;
1358
 
1359
        }
1360
      else if (((op & 0xfc1f0000) == 0xbc010000) ||     /* stm Rx, NUM(r1) */
1361
               (((op & 0xfc1f0000) == 0x90010000 ||     /* st rx,NUM(r1) */
1362
                 (op & 0xfc1f0003) == 0xf8010000) &&    /* std rx,NUM(r1) */
1363
                (op & 0x03e00000) >= 0x01a00000))       /* rx >= r13 */
1364
        {
1365
 
1366
          reg = GET_SRC_REG (op);
1367
          if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1368
            {
1369
              fdata->saved_gpr = reg;
1370
              if ((op & 0xfc1f0003) == 0xf8010000)
1371
                op &= ~3UL;
1372
              fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1373
            }
1374
          continue;
1375
 
1376
        }
1377
      else if ((op & 0xffff0000) == 0x60000000)
1378
        {
1379
          /* nop */
1380
          /* Allow nops in the prologue, but do not consider them to
1381
             be part of the prologue unless followed by other prologue
1382
             instructions. */
1383
          prev_insn_was_prologue_insn = 0;
1384
          continue;
1385
 
1386
        }
1387
      else if ((op & 0xffff0000) == 0x3c000000)
1388
        {                       /* addis 0,0,NUM, used
1389
                                   for >= 32k frames */
1390
          fdata->offset = (op & 0x0000ffff) << 16;
1391
          fdata->frameless = 0;
1392
          r0_contains_arg = 0;
1393
          continue;
1394
 
1395
        }
1396
      else if ((op & 0xffff0000) == 0x60000000)
1397
        {                       /* ori 0,0,NUM, 2nd ha
1398
                                   lf of >= 32k frames */
1399
          fdata->offset |= (op & 0x0000ffff);
1400
          fdata->frameless = 0;
1401
          r0_contains_arg = 0;
1402
          continue;
1403
 
1404
        }
1405
      else if (lr_reg >= 0 &&
1406
               /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1407
               (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1408
                /* stw Rx, NUM(r1) */
1409
                ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1410
                /* stwu Rx, NUM(r1) */
1411
                ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1412
        {       /* where Rx == lr */
1413
          fdata->lr_offset = offset;
1414
          fdata->nosavedpc = 0;
1415
          /* Invalidate lr_reg, but don't set it to -1.
1416
             That would mean that it had never been set.  */
1417
          lr_reg = -2;
1418
          if ((op & 0xfc000003) == 0xf8000000 ||        /* std */
1419
              (op & 0xfc000000) == 0x90000000)          /* stw */
1420
            {
1421
              /* Does not update r1, so add displacement to lr_offset.  */
1422
              fdata->lr_offset += SIGNED_SHORT (op);
1423
            }
1424
          continue;
1425
 
1426
        }
1427
      else if (cr_reg >= 0 &&
1428
               /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1429
               (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1430
                /* stw Rx, NUM(r1) */
1431
                ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1432
                /* stwu Rx, NUM(r1) */
1433
                ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1434
        {       /* where Rx == cr */
1435
          fdata->cr_offset = offset;
1436
          /* Invalidate cr_reg, but don't set it to -1.
1437
             That would mean that it had never been set.  */
1438
          cr_reg = -2;
1439
          if ((op & 0xfc000003) == 0xf8000000 ||
1440
              (op & 0xfc000000) == 0x90000000)
1441
            {
1442
              /* Does not update r1, so add displacement to cr_offset.  */
1443
              fdata->cr_offset += SIGNED_SHORT (op);
1444
            }
1445
          continue;
1446
 
1447
        }
1448
      else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1449
        {
1450
          /* bcl 20,xx,.+4 is used to get the current PC, with or without
1451
             prediction bits.  If the LR has already been saved, we can
1452
             skip it.  */
1453
          continue;
1454
        }
1455
      else if (op == 0x48000005)
1456
        {                       /* bl .+4 used in
1457
                                   -mrelocatable */
1458
          continue;
1459
 
1460
        }
1461
      else if (op == 0x48000004)
1462
        {                       /* b .+4 (xlc) */
1463
          break;
1464
 
1465
        }
1466
      else if ((op & 0xffff0000) == 0x3fc00000 ||  /* addis 30,0,foo@ha, used
1467
                                                      in V.4 -mminimal-toc */
1468
               (op & 0xffff0000) == 0x3bde0000)
1469
        {                       /* addi 30,30,foo@l */
1470
          continue;
1471
 
1472
        }
1473
      else if ((op & 0xfc000001) == 0x48000001)
1474
        {                       /* bl foo,
1475
                                   to save fprs??? */
1476
 
1477
          fdata->frameless = 0;
1478
 
1479
          /* If the return address has already been saved, we can skip
1480
             calls to blrl (for PIC).  */
1481
          if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1482
            continue;
1483
 
1484
          /* Don't skip over the subroutine call if it is not within
1485
             the first three instructions of the prologue and either
1486
             we have no line table information or the line info tells
1487
             us that the subroutine call is not part of the line
1488
             associated with the prologue.  */
1489
          if ((pc - orig_pc) > 8)
1490
            {
1491
              struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1492
              struct symtab_and_line this_sal = find_pc_line (pc, 0);
1493
 
1494
              if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1495
                break;
1496
            }
1497
 
1498
          op = read_memory_integer (pc + 4, 4);
1499
 
1500
          /* At this point, make sure this is not a trampoline
1501
             function (a function that simply calls another functions,
1502
             and nothing else).  If the next is not a nop, this branch
1503
             was part of the function prologue. */
1504
 
1505
          if (op == 0x4def7b82 || op == 0)       /* crorc 15, 15, 15 */
1506
            break;              /* don't skip over
1507
                                   this branch */
1508
          continue;
1509
 
1510
        }
1511
      /* update stack pointer */
1512
      else if ((op & 0xfc1f0000) == 0x94010000)
1513
        {               /* stu rX,NUM(r1) ||  stwu rX,NUM(r1) */
1514
          fdata->frameless = 0;
1515
          fdata->offset = SIGNED_SHORT (op);
1516
          offset = fdata->offset;
1517
          continue;
1518
        }
1519
      else if ((op & 0xfc1f016a) == 0x7c01016e)
1520
        {                       /* stwux rX,r1,rY */
1521
          /* no way to figure out what r1 is going to be */
1522
          fdata->frameless = 0;
1523
          offset = fdata->offset;
1524
          continue;
1525
        }
1526
      else if ((op & 0xfc1f0003) == 0xf8010001)
1527
        {                       /* stdu rX,NUM(r1) */
1528
          fdata->frameless = 0;
1529
          fdata->offset = SIGNED_SHORT (op & ~3UL);
1530
          offset = fdata->offset;
1531
          continue;
1532
        }
1533
      else if ((op & 0xfc1f016a) == 0x7c01016a)
1534
        {                       /* stdux rX,r1,rY */
1535
          /* no way to figure out what r1 is going to be */
1536
          fdata->frameless = 0;
1537
          offset = fdata->offset;
1538
          continue;
1539
        }
1540
      else if ((op & 0xffff0000) == 0x38210000)
1541
        {                       /* addi r1,r1,SIMM */
1542
          fdata->frameless = 0;
1543
          fdata->offset += SIGNED_SHORT (op);
1544
          offset = fdata->offset;
1545
          continue;
1546
        }
1547
      /* Load up minimal toc pointer.  Do not treat an epilogue restore
1548
         of r31 as a minimal TOC load.  */
1549
      else if (((op >> 22) == 0x20f     ||      /* l r31,... or l r30,... */
1550
               (op >> 22) == 0x3af)             /* ld r31,... or ld r30,... */
1551
               && !framep
1552
               && !minimal_toc_loaded)
1553
        {
1554
          minimal_toc_loaded = 1;
1555
          continue;
1556
 
1557
          /* move parameters from argument registers to local variable
1558
             registers */
1559
        }
1560
      else if ((op & 0xfc0007fe) == 0x7c000378 &&       /* mr(.)  Rx,Ry */
1561
               (((op >> 21) & 31) >= 3) &&              /* R3 >= Ry >= R10 */
1562
               (((op >> 21) & 31) <= 10) &&
1563
               ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1564
        {
1565
          continue;
1566
 
1567
          /* store parameters in stack */
1568
        }
1569
      /* Move parameters from argument registers to temporary register.  */
1570
      else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1571
        {
1572
          continue;
1573
 
1574
          /* Set up frame pointer */
1575
        }
1576
      else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1577
               || op == 0x7c3f0b78)
1578
        {                       /* mr r31, r1 */
1579
          fdata->frameless = 0;
1580
          framep = 1;
1581
          fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1582
          continue;
1583
 
1584
          /* Another way to set up the frame pointer.  */
1585
        }
1586
      else if ((op & 0xfc1fffff) == 0x38010000)
1587
        {                       /* addi rX, r1, 0x0 */
1588
          fdata->frameless = 0;
1589
          framep = 1;
1590
          fdata->alloca_reg = (tdep->ppc_gp0_regnum
1591
                               + ((op & ~0x38010000) >> 21));
1592
          continue;
1593
        }
1594
      /* AltiVec related instructions.  */
1595
      /* Store the vrsave register (spr 256) in another register for
1596
         later manipulation, or load a register into the vrsave
1597
         register.  2 instructions are used: mfvrsave and
1598
         mtvrsave.  They are shorthand notation for mfspr Rn, SPR256
1599
         and mtspr SPR256, Rn.  */
1600
      /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1601
         mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110  */
1602
      else if ((op & 0xfc1fffff) == 0x7c0042a6)    /* mfvrsave Rn */
1603
        {
1604
          vrsave_reg = GET_SRC_REG (op);
1605
          continue;
1606
        }
1607
      else if ((op & 0xfc1fffff) == 0x7c0043a6)     /* mtvrsave Rn */
1608
        {
1609
          continue;
1610
        }
1611
      /* Store the register where vrsave was saved to onto the stack:
1612
         rS is the register where vrsave was stored in a previous
1613
         instruction.  */
1614
      /* 100100 sssss 00001 dddddddd dddddddd */
1615
      else if ((op & 0xfc1f0000) == 0x90010000)     /* stw rS, d(r1) */
1616
        {
1617
          if (vrsave_reg == GET_SRC_REG (op))
1618
            {
1619
              fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1620
              vrsave_reg = -1;
1621
            }
1622
          continue;
1623
        }
1624
      /* Compute the new value of vrsave, by modifying the register
1625
         where vrsave was saved to.  */
1626
      else if (((op & 0xfc000000) == 0x64000000)    /* oris Ra, Rs, UIMM */
1627
               || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1628
        {
1629
          continue;
1630
        }
1631
      /* li r0, SIMM (short for addi r0, 0, SIMM).  This is the first
1632
         in a pair of insns to save the vector registers on the
1633
         stack.  */
1634
      /* 001110 00000 00000 iiii iiii iiii iiii  */
1635
      /* 001110 01110 00000 iiii iiii iiii iiii  */
1636
      else if ((op & 0xffff0000) == 0x38000000         /* li r0, SIMM */
1637
               || (op & 0xffff0000) == 0x39c00000)     /* li r14, SIMM */
1638
        {
1639
          if ((op & 0xffff0000) == 0x38000000)
1640
            r0_contains_arg = 0;
1641
          li_found_pc = pc;
1642
          vr_saved_offset = SIGNED_SHORT (op);
1643
 
1644
          /* This insn by itself is not part of the prologue, unless
1645
             if part of the pair of insns mentioned above. So do not
1646
             record this insn as part of the prologue yet.  */
1647
          prev_insn_was_prologue_insn = 0;
1648
        }
1649
      /* Store vector register S at (r31+r0) aligned to 16 bytes.  */
1650
      /* 011111 sssss 11111 00000 00111001110 */
1651
      else if ((op & 0xfc1fffff) == 0x7c1f01ce)   /* stvx Vs, R31, R0 */
1652
        {
1653
          if (pc == (li_found_pc + 4))
1654
            {
1655
              vr_reg = GET_SRC_REG (op);
1656
              /* If this is the first vector reg to be saved, or if
1657
                 it has a lower number than others previously seen,
1658
                 reupdate the frame info.  */
1659
              if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1660
                {
1661
                  fdata->saved_vr = vr_reg;
1662
                  fdata->vr_offset = vr_saved_offset + offset;
1663
                }
1664
              vr_saved_offset = -1;
1665
              vr_reg = -1;
1666
              li_found_pc = 0;
1667
            }
1668
        }
1669
      /* End AltiVec related instructions.  */
1670
 
1671
      /* Start BookE related instructions.  */
1672
      /* Store gen register S at (r31+uimm).
1673
         Any register less than r13 is volatile, so we don't care.  */
1674
      /* 000100 sssss 11111 iiiii 01100100001 */
1675
      else if (arch_info->mach == bfd_mach_ppc_e500
1676
               && (op & 0xfc1f07ff) == 0x101f0321)    /* evstdd Rs,uimm(R31) */
1677
        {
1678
          if ((op & 0x03e00000) >= 0x01a00000)  /* Rs >= r13 */
1679
            {
1680
              unsigned int imm;
1681
              ev_reg = GET_SRC_REG (op);
1682
              imm = (op >> 11) & 0x1f;
1683
              ev_offset = imm * 8;
1684
              /* If this is the first vector reg to be saved, or if
1685
                 it has a lower number than others previously seen,
1686
                 reupdate the frame info.  */
1687
              if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1688
                {
1689
                  fdata->saved_ev = ev_reg;
1690
                  fdata->ev_offset = ev_offset + offset;
1691
                }
1692
            }
1693
          continue;
1694
        }
1695
      /* Store gen register rS at (r1+rB).  */
1696
      /* 000100 sssss 00001 bbbbb 01100100000 */
1697
      else if (arch_info->mach == bfd_mach_ppc_e500
1698
               && (op & 0xffe007ff) == 0x13e00320)     /* evstddx RS,R1,Rb */
1699
        {
1700
          if (pc == (li_found_pc + 4))
1701
            {
1702
              ev_reg = GET_SRC_REG (op);
1703
              /* If this is the first vector reg to be saved, or if
1704
                 it has a lower number than others previously seen,
1705
                 reupdate the frame info.  */
1706
              /* We know the contents of rB from the previous instruction.  */
1707
              if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1708
                {
1709
                  fdata->saved_ev = ev_reg;
1710
                  fdata->ev_offset = vr_saved_offset + offset;
1711
                }
1712
              vr_saved_offset = -1;
1713
              ev_reg = -1;
1714
              li_found_pc = 0;
1715
            }
1716
          continue;
1717
        }
1718
      /* Store gen register r31 at (rA+uimm).  */
1719
      /* 000100 11111 aaaaa iiiii 01100100001 */
1720
      else if (arch_info->mach == bfd_mach_ppc_e500
1721
               && (op & 0xffe007ff) == 0x13e00321)   /* evstdd R31,Ra,UIMM */
1722
        {
1723
          /* Wwe know that the source register is 31 already, but
1724
             it can't hurt to compute it.  */
1725
          ev_reg = GET_SRC_REG (op);
1726
          ev_offset = ((op >> 11) & 0x1f) * 8;
1727
          /* If this is the first vector reg to be saved, or if
1728
             it has a lower number than others previously seen,
1729
             reupdate the frame info.  */
1730
          if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1731
            {
1732
              fdata->saved_ev = ev_reg;
1733
              fdata->ev_offset = ev_offset + offset;
1734
            }
1735
 
1736
          continue;
1737
        }
1738
      /* Store gen register S at (r31+r0).
1739
         Store param on stack when offset from SP bigger than 4 bytes.  */
1740
      /* 000100 sssss 11111 00000 01100100000 */
1741
      else if (arch_info->mach == bfd_mach_ppc_e500
1742
               && (op & 0xfc1fffff) == 0x101f0320)     /* evstddx Rs,R31,R0 */
1743
        {
1744
          if (pc == (li_found_pc + 4))
1745
            {
1746
              if ((op & 0x03e00000) >= 0x01a00000)
1747
                {
1748
                  ev_reg = GET_SRC_REG (op);
1749
                  /* If this is the first vector reg to be saved, or if
1750
                     it has a lower number than others previously seen,
1751
                     reupdate the frame info.  */
1752
                  /* We know the contents of r0 from the previous
1753
                     instruction.  */
1754
                  if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1755
                    {
1756
                      fdata->saved_ev = ev_reg;
1757
                      fdata->ev_offset = vr_saved_offset + offset;
1758
                    }
1759
                  ev_reg = -1;
1760
                }
1761
              vr_saved_offset = -1;
1762
              li_found_pc = 0;
1763
              continue;
1764
            }
1765
        }
1766
      /* End BookE related instructions.  */
1767
 
1768
      else
1769
        {
1770
          /* Not a recognized prologue instruction.
1771
             Handle optimizer code motions into the prologue by continuing
1772
             the search if we have no valid frame yet or if the return
1773
             address is not yet saved in the frame.  */
1774
          if (fdata->frameless == 0 && fdata->nosavedpc == 0)
1775
            break;
1776
 
1777
          if (op == 0x4e800020          /* blr */
1778
              || op == 0x4e800420)      /* bctr */
1779
            /* Do not scan past epilogue in frameless functions or
1780
               trampolines.  */
1781
            break;
1782
          if ((op & 0xf4000000) == 0x40000000) /* bxx */
1783
            /* Never skip branches.  */
1784
            break;
1785
 
1786
          if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1787
            /* Do not scan too many insns, scanning insns is expensive with
1788
               remote targets.  */
1789
            break;
1790
 
1791
          /* Continue scanning.  */
1792
          prev_insn_was_prologue_insn = 0;
1793
          continue;
1794
        }
1795
    }
1796
 
1797
#if 0
1798
/* I have problems with skipping over __main() that I need to address
1799
 * sometime. Previously, I used to use misc_function_vector which
1800
 * didn't work as well as I wanted to be.  -MGO */
1801
 
1802
  /* If the first thing after skipping a prolog is a branch to a function,
1803
     this might be a call to an initializer in main(), introduced by gcc2.
1804
     We'd like to skip over it as well.  Fortunately, xlc does some extra
1805
     work before calling a function right after a prologue, thus we can
1806
     single out such gcc2 behaviour.  */
1807
 
1808
 
1809
  if ((op & 0xfc000001) == 0x48000001)
1810
    {                           /* bl foo, an initializer function? */
1811
      op = read_memory_integer (pc + 4, 4);
1812
 
1813
      if (op == 0x4def7b82)
1814
        {                       /* cror 0xf, 0xf, 0xf (nop) */
1815
 
1816
          /* Check and see if we are in main.  If so, skip over this
1817
             initializer function as well.  */
1818
 
1819
          tmp = find_pc_misc_function (pc);
1820
          if (tmp >= 0
1821
              && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1822
            return pc + 8;
1823
        }
1824
    }
1825
#endif /* 0 */
1826
 
1827
  fdata->offset = -fdata->offset;
1828
  return last_prologue_pc;
1829
}
1830
 
1831
 
1832
/*************************************************************************
1833
  Support for creating pushing a dummy frame into the stack, and popping
1834
  frames, etc.
1835
*************************************************************************/
1836
 
1837
 
1838
/* All the ABI's require 16 byte alignment.  */
1839
static CORE_ADDR
1840
rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1841
{
1842
  return (addr & -16);
1843
}
1844
 
1845
/* Pass the arguments in either registers, or in the stack. In RS/6000,
1846
   the first eight words of the argument list (that might be less than
1847
   eight parameters if some parameters occupy more than one word) are
1848
   passed in r3..r10 registers.  float and double parameters are
1849
   passed in fpr's, in addition to that.  Rest of the parameters if any
1850
   are passed in user stack.  There might be cases in which half of the
1851
   parameter is copied into registers, the other half is pushed into
1852
   stack.
1853
 
1854
   Stack must be aligned on 64-bit boundaries when synthesizing
1855
   function calls.
1856
 
1857
   If the function is returning a structure, then the return address is passed
1858
   in r3, then the first 7 words of the parameters can be passed in registers,
1859
   starting from r4.  */
1860
 
1861
static CORE_ADDR
1862
rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1863
                        struct regcache *regcache, CORE_ADDR bp_addr,
1864
                        int nargs, struct value **args, CORE_ADDR sp,
1865
                        int struct_return, CORE_ADDR struct_addr)
1866
{
1867
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1868
  int ii;
1869
  int len = 0;
1870
  int argno;                    /* current argument number */
1871
  int argbytes;                 /* current argument byte */
1872
  gdb_byte tmp_buffer[50];
1873
  int f_argno = 0;               /* current floating point argno */
1874
  int wordsize = gdbarch_tdep (gdbarch)->wordsize;
1875
  CORE_ADDR func_addr = find_function_addr (function, NULL);
1876
 
1877
  struct value *arg = 0;
1878
  struct type *type;
1879
 
1880
  ULONGEST saved_sp;
1881
 
1882
  /* The calling convention this function implements assumes the
1883
     processor has floating-point registers.  We shouldn't be using it
1884
     on PPC variants that lack them.  */
1885
  gdb_assert (ppc_floating_point_unit_p (gdbarch));
1886
 
1887
  /* The first eight words of ther arguments are passed in registers.
1888
     Copy them appropriately.  */
1889
  ii = 0;
1890
 
1891
  /* If the function is returning a `struct', then the first word
1892
     (which will be passed in r3) is used for struct return address.
1893
     In that case we should advance one word and start from r4
1894
     register to copy parameters.  */
1895
  if (struct_return)
1896
    {
1897
      regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1898
                                   struct_addr);
1899
      ii++;
1900
    }
1901
 
1902
/*
1903
   effectively indirect call... gcc does...
1904
 
1905
   return_val example( float, int);
1906
 
1907
   eabi:
1908
   float in fp0, int in r3
1909
   offset of stack on overflow 8/16
1910
   for varargs, must go by type.
1911
   power open:
1912
   float in r3&r4, int in r5
1913
   offset of stack on overflow different
1914
   both:
1915
   return in r3 or f0.  If no float, must study how gcc emulates floats;
1916
   pay attention to arg promotion.
1917
   User may have to cast\args to handle promotion correctly
1918
   since gdb won't know if prototype supplied or not.
1919
 */
1920
 
1921
  for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1922
    {
1923
      int reg_size = register_size (gdbarch, ii + 3);
1924
 
1925
      arg = args[argno];
1926
      type = check_typedef (value_type (arg));
1927
      len = TYPE_LENGTH (type);
1928
 
1929
      if (TYPE_CODE (type) == TYPE_CODE_FLT)
1930
        {
1931
 
1932
          /* Floating point arguments are passed in fpr's, as well as gpr's.
1933
             There are 13 fpr's reserved for passing parameters. At this point
1934
             there is no way we would run out of them.  */
1935
 
1936
          gdb_assert (len <= 8);
1937
 
1938
          regcache_cooked_write (regcache,
1939
                                 tdep->ppc_fp0_regnum + 1 + f_argno,
1940
                                 value_contents (arg));
1941
          ++f_argno;
1942
        }
1943
 
1944
      if (len > reg_size)
1945
        {
1946
 
1947
          /* Argument takes more than one register.  */
1948
          while (argbytes < len)
1949
            {
1950
              gdb_byte word[MAX_REGISTER_SIZE];
1951
              memset (word, 0, reg_size);
1952
              memcpy (word,
1953
                      ((char *) value_contents (arg)) + argbytes,
1954
                      (len - argbytes) > reg_size
1955
                        ? reg_size : len - argbytes);
1956
              regcache_cooked_write (regcache,
1957
                                    tdep->ppc_gp0_regnum + 3 + ii,
1958
                                    word);
1959
              ++ii, argbytes += reg_size;
1960
 
1961
              if (ii >= 8)
1962
                goto ran_out_of_registers_for_arguments;
1963
            }
1964
          argbytes = 0;
1965
          --ii;
1966
        }
1967
      else
1968
        {
1969
          /* Argument can fit in one register.  No problem.  */
1970
          int adj = gdbarch_byte_order (gdbarch)
1971
                    == BFD_ENDIAN_BIG ? reg_size - len : 0;
1972
          gdb_byte word[MAX_REGISTER_SIZE];
1973
 
1974
          memset (word, 0, reg_size);
1975
          memcpy (word, value_contents (arg), len);
1976
          regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1977
        }
1978
      ++argno;
1979
    }
1980
 
1981
ran_out_of_registers_for_arguments:
1982
 
1983
  regcache_cooked_read_unsigned (regcache,
1984
                                 gdbarch_sp_regnum (gdbarch),
1985
                                 &saved_sp);
1986
 
1987
  /* Location for 8 parameters are always reserved.  */
1988
  sp -= wordsize * 8;
1989
 
1990
  /* Another six words for back chain, TOC register, link register, etc.  */
1991
  sp -= wordsize * 6;
1992
 
1993
  /* Stack pointer must be quadword aligned.  */
1994
  sp &= -16;
1995
 
1996
  /* If there are more arguments, allocate space for them in
1997
     the stack, then push them starting from the ninth one.  */
1998
 
1999
  if ((argno < nargs) || argbytes)
2000
    {
2001
      int space = 0, jj;
2002
 
2003
      if (argbytes)
2004
        {
2005
          space += ((len - argbytes + 3) & -4);
2006
          jj = argno + 1;
2007
        }
2008
      else
2009
        jj = argno;
2010
 
2011
      for (; jj < nargs; ++jj)
2012
        {
2013
          struct value *val = args[jj];
2014
          space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
2015
        }
2016
 
2017
      /* Add location required for the rest of the parameters.  */
2018
      space = (space + 15) & -16;
2019
      sp -= space;
2020
 
2021
      /* This is another instance we need to be concerned about
2022
         securing our stack space. If we write anything underneath %sp
2023
         (r1), we might conflict with the kernel who thinks he is free
2024
         to use this area.  So, update %sp first before doing anything
2025
         else.  */
2026
 
2027
      regcache_raw_write_signed (regcache,
2028
                                 gdbarch_sp_regnum (gdbarch), sp);
2029
 
2030
      /* If the last argument copied into the registers didn't fit there
2031
         completely, push the rest of it into stack.  */
2032
 
2033
      if (argbytes)
2034
        {
2035
          write_memory (sp + 24 + (ii * 4),
2036
                        value_contents (arg) + argbytes,
2037
                        len - argbytes);
2038
          ++argno;
2039
          ii += ((len - argbytes + 3) & -4) / 4;
2040
        }
2041
 
2042
      /* Push the rest of the arguments into stack.  */
2043
      for (; argno < nargs; ++argno)
2044
        {
2045
 
2046
          arg = args[argno];
2047
          type = check_typedef (value_type (arg));
2048
          len = TYPE_LENGTH (type);
2049
 
2050
 
2051
          /* Float types should be passed in fpr's, as well as in the
2052
             stack.  */
2053
          if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
2054
            {
2055
 
2056
              gdb_assert (len <= 8);
2057
 
2058
              regcache_cooked_write (regcache,
2059
                                     tdep->ppc_fp0_regnum + 1 + f_argno,
2060
                                     value_contents (arg));
2061
              ++f_argno;
2062
            }
2063
 
2064
          write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
2065
          ii += ((len + 3) & -4) / 4;
2066
        }
2067
    }
2068
 
2069
  /* Set the stack pointer.  According to the ABI, the SP is meant to
2070
     be set _before_ the corresponding stack space is used.  On AIX,
2071
     this even applies when the target has been completely stopped!
2072
     Not doing this can lead to conflicts with the kernel which thinks
2073
     that it still has control over this not-yet-allocated stack
2074
     region.  */
2075
  regcache_raw_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
2076
 
2077
  /* Set back chain properly.  */
2078
  store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
2079
  write_memory (sp, tmp_buffer, wordsize);
2080
 
2081
  /* Point the inferior function call's return address at the dummy's
2082
     breakpoint.  */
2083
  regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
2084
 
2085
  /* Set the TOC register, get the value from the objfile reader
2086
     which, in turn, gets it from the VMAP table.  */
2087
  if (rs6000_find_toc_address_hook != NULL)
2088
    {
2089
      CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
2090
      regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
2091
    }
2092
 
2093
  target_store_registers (regcache, -1);
2094
  return sp;
2095
}
2096
 
2097
static enum return_value_convention
2098
rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype,
2099
                     struct regcache *regcache, gdb_byte *readbuf,
2100
                     const gdb_byte *writebuf)
2101
{
2102
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2103
  gdb_byte buf[8];
2104
 
2105
  /* The calling convention this function implements assumes the
2106
     processor has floating-point registers.  We shouldn't be using it
2107
     on PowerPC variants that lack them.  */
2108
  gdb_assert (ppc_floating_point_unit_p (gdbarch));
2109
 
2110
  /* AltiVec extension: Functions that declare a vector data type as a
2111
     return value place that return value in VR2.  */
2112
  if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype)
2113
      && TYPE_LENGTH (valtype) == 16)
2114
    {
2115
      if (readbuf)
2116
        regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
2117
      if (writebuf)
2118
        regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
2119
 
2120
      return RETURN_VALUE_REGISTER_CONVENTION;
2121
    }
2122
 
2123
  /* If the called subprogram returns an aggregate, there exists an
2124
     implicit first argument, whose value is the address of a caller-
2125
     allocated buffer into which the callee is assumed to store its
2126
     return value. All explicit parameters are appropriately
2127
     relabeled.  */
2128
  if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2129
      || TYPE_CODE (valtype) == TYPE_CODE_UNION
2130
      || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2131
    return RETURN_VALUE_STRUCT_CONVENTION;
2132
 
2133
  /* Scalar floating-point values are returned in FPR1 for float or
2134
     double, and in FPR1:FPR2 for quadword precision.  Fortran
2135
     complex*8 and complex*16 are returned in FPR1:FPR2, and
2136
     complex*32 is returned in FPR1:FPR4.  */
2137
  if (TYPE_CODE (valtype) == TYPE_CODE_FLT
2138
      && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8))
2139
    {
2140
      struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
2141
      gdb_byte regval[8];
2142
 
2143
      /* FIXME: kettenis/2007-01-01: Add support for quadword
2144
         precision and complex.  */
2145
 
2146
      if (readbuf)
2147
        {
2148
          regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
2149
          convert_typed_floating (regval, regtype, readbuf, valtype);
2150
        }
2151
      if (writebuf)
2152
        {
2153
          convert_typed_floating (writebuf, valtype, regval, regtype);
2154
          regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
2155
        }
2156
 
2157
      return RETURN_VALUE_REGISTER_CONVENTION;
2158
  }
2159
 
2160
  /* Values of the types int, long, short, pointer, and char (length
2161
     is less than or equal to four bytes), as well as bit values of
2162
     lengths less than or equal to 32 bits, must be returned right
2163
     justified in GPR3 with signed values sign extended and unsigned
2164
     values zero extended, as necessary.  */
2165
  if (TYPE_LENGTH (valtype) <= tdep->wordsize)
2166
    {
2167
      if (readbuf)
2168
        {
2169
          ULONGEST regval;
2170
 
2171
          /* For reading we don't have to worry about sign extension.  */
2172
          regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
2173
                                         &regval);
2174
          store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
2175
        }
2176
      if (writebuf)
2177
        {
2178
          /* For writing, use unpack_long since that should handle any
2179
             required sign extension.  */
2180
          regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
2181
                                          unpack_long (valtype, writebuf));
2182
        }
2183
 
2184
      return RETURN_VALUE_REGISTER_CONVENTION;
2185
    }
2186
 
2187
  /* Eight-byte non-floating-point scalar values must be returned in
2188
     GPR3:GPR4.  */
2189
 
2190
  if (TYPE_LENGTH (valtype) == 8)
2191
    {
2192
      gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT);
2193
      gdb_assert (tdep->wordsize == 4);
2194
 
2195
      if (readbuf)
2196
        {
2197
          gdb_byte regval[8];
2198
 
2199
          regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval);
2200
          regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
2201
                                regval + 4);
2202
          memcpy (readbuf, regval, 8);
2203
        }
2204
      if (writebuf)
2205
        {
2206
          regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
2207
          regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
2208
                                 writebuf + 4);
2209
        }
2210
 
2211
      return RETURN_VALUE_REGISTER_CONVENTION;
2212
    }
2213
 
2214
  return RETURN_VALUE_STRUCT_CONVENTION;
2215
}
2216
 
2217
/* Return whether handle_inferior_event() should proceed through code
2218
   starting at PC in function NAME when stepping.
2219
 
2220
   The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2221
   handle memory references that are too distant to fit in instructions
2222
   generated by the compiler.  For example, if 'foo' in the following
2223
   instruction:
2224
 
2225
     lwz r9,foo(r2)
2226
 
2227
   is greater than 32767, the linker might replace the lwz with a branch to
2228
   somewhere in @FIX1 that does the load in 2 instructions and then branches
2229
   back to where execution should continue.
2230
 
2231
   GDB should silently step over @FIX code, just like AIX dbx does.
2232
   Unfortunately, the linker uses the "b" instruction for the
2233
   branches, meaning that the link register doesn't get set.
2234
   Therefore, GDB's usual step_over_function () mechanism won't work.
2235
 
2236
   Instead, use the gdbarch_skip_trampoline_code and
2237
   gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2238
   @FIX code.  */
2239
 
2240
int
2241
rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
2242
{
2243
  return name && !strncmp (name, "@FIX", 4);
2244
}
2245
 
2246
/* Skip code that the user doesn't want to see when stepping:
2247
 
2248
   1. Indirect function calls use a piece of trampoline code to do context
2249
   switching, i.e. to set the new TOC table.  Skip such code if we are on
2250
   its first instruction (as when we have single-stepped to here).
2251
 
2252
   2. Skip shared library trampoline code (which is different from
2253
   indirect function call trampolines).
2254
 
2255
   3. Skip bigtoc fixup code.
2256
 
2257
   Result is desired PC to step until, or NULL if we are not in
2258
   code that should be skipped.  */
2259
 
2260
CORE_ADDR
2261
rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
2262
{
2263
  unsigned int ii, op;
2264
  int rel;
2265
  CORE_ADDR solib_target_pc;
2266
  struct minimal_symbol *msymbol;
2267
 
2268
  static unsigned trampoline_code[] =
2269
  {
2270
    0x800b0000,                 /*     l   r0,0x0(r11)  */
2271
    0x90410014,                 /*    st   r2,0x14(r1)  */
2272
    0x7c0903a6,                 /* mtctr   r0           */
2273
    0x804b0004,                 /*     l   r2,0x4(r11)  */
2274
    0x816b0008,                 /*     l  r11,0x8(r11)  */
2275
    0x4e800420,                 /*  bctr                */
2276
    0x4e800020,                 /*    br                */
2277
 
2278
  };
2279
 
2280
  /* Check for bigtoc fixup code.  */
2281
  msymbol = lookup_minimal_symbol_by_pc (pc);
2282
  if (msymbol
2283
      && rs6000_in_solib_return_trampoline (pc,
2284
                                            DEPRECATED_SYMBOL_NAME (msymbol)))
2285
    {
2286
      /* Double-check that the third instruction from PC is relative "b".  */
2287
      op = read_memory_integer (pc + 8, 4);
2288
      if ((op & 0xfc000003) == 0x48000000)
2289
        {
2290
          /* Extract bits 6-29 as a signed 24-bit relative word address and
2291
             add it to the containing PC.  */
2292
          rel = ((int)(op << 6) >> 6);
2293
          return pc + 8 + rel;
2294
        }
2295
    }
2296
 
2297
  /* If pc is in a shared library trampoline, return its target.  */
2298
  solib_target_pc = find_solib_trampoline_target (frame, pc);
2299
  if (solib_target_pc)
2300
    return solib_target_pc;
2301
 
2302
  for (ii = 0; trampoline_code[ii]; ++ii)
2303
    {
2304
      op = read_memory_integer (pc + (ii * 4), 4);
2305
      if (op != trampoline_code[ii])
2306
        return 0;
2307
    }
2308
  ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr   */
2309
  pc = read_memory_addr (ii,
2310
                         gdbarch_tdep (get_frame_arch (frame))->wordsize); /* (r11) value */
2311
  return pc;
2312
}
2313
 
2314
/* ISA-specific vector types.  */
2315
 
2316
static struct type *
2317
rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2318
{
2319
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2320
 
2321
  if (!tdep->ppc_builtin_type_vec64)
2322
    {
2323
      /* The type we're building is this: */
2324
#if 0
2325
      union __gdb_builtin_type_vec64
2326
        {
2327
          int64_t uint64;
2328
          float v2_float[2];
2329
          int32_t v2_int32[2];
2330
          int16_t v4_int16[4];
2331
          int8_t v8_int8[8];
2332
        };
2333
#endif
2334
 
2335
      struct type *t;
2336
 
2337
      t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2338
      append_composite_type_field (t, "uint64", builtin_type_int64);
2339
      append_composite_type_field (t, "v2_float",
2340
                                   init_vector_type (builtin_type_float, 2));
2341
      append_composite_type_field (t, "v2_int32",
2342
                                   init_vector_type (builtin_type_int32, 2));
2343
      append_composite_type_field (t, "v4_int16",
2344
                                   init_vector_type (builtin_type_int16, 4));
2345
      append_composite_type_field (t, "v8_int8",
2346
                                   init_vector_type (builtin_type_int8, 8));
2347
 
2348
      TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
2349
      TYPE_NAME (t) = "ppc_builtin_type_vec64";
2350
      tdep->ppc_builtin_type_vec64 = t;
2351
    }
2352
 
2353
  return tdep->ppc_builtin_type_vec64;
2354
}
2355
 
2356
/* Return the size of register REG when words are WORDSIZE bytes long.  If REG
2357
   isn't available with that word size, return 0.  */
2358
 
2359
static int
2360
regsize (const struct reg *reg, int wordsize)
2361
{
2362
  return wordsize == 8 ? reg->sz64 : reg->sz32;
2363
}
2364
 
2365
/* Return the name of register number REGNO, or the empty string if it
2366
   is an anonymous register.  */
2367
 
2368
static const char *
2369
rs6000_register_name (struct gdbarch *gdbarch, int regno)
2370
{
2371
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2372
 
2373
  /* The upper half "registers" have names in the XML description,
2374
     but we present only the low GPRs and the full 64-bit registers
2375
     to the user.  */
2376
  if (tdep->ppc_ev0_upper_regnum >= 0
2377
      && tdep->ppc_ev0_upper_regnum <= regno
2378
      && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2379
    return "";
2380
 
2381
  /* Check if the SPE pseudo registers are available.  */
2382
  if (IS_SPE_PSEUDOREG (tdep, regno))
2383
    {
2384
      static const char *const spe_regnames[] = {
2385
        "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2386
        "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2387
        "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2388
        "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2389
      };
2390
      return spe_regnames[regno - tdep->ppc_ev0_regnum];
2391
    }
2392
 
2393
  /* Check if the decimal128 pseudo-registers are available.  */
2394
  if (IS_DFP_PSEUDOREG (tdep, regno))
2395
    {
2396
      static const char *const dfp128_regnames[] = {
2397
        "dl0", "dl1", "dl2", "dl3",
2398
        "dl4", "dl5", "dl6", "dl7",
2399
        "dl8", "dl9", "dl10", "dl11",
2400
        "dl12", "dl13", "dl14", "dl15"
2401
      };
2402
      return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2403
    }
2404
 
2405
  return tdesc_register_name (gdbarch, regno);
2406
}
2407
 
2408
/* Return the GDB type object for the "standard" data type of data in
2409
   register N.  */
2410
 
2411
static struct type *
2412
rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2413
{
2414
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2415
 
2416
  /* These are the only pseudo-registers we support.  */
2417
  gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2418
              || IS_DFP_PSEUDOREG (tdep, regnum));
2419
 
2420
  /* These are the e500 pseudo-registers.  */
2421
  if (IS_SPE_PSEUDOREG (tdep, regnum))
2422
    return rs6000_builtin_type_vec64 (gdbarch);
2423
  else
2424
    /* Could only be the ppc decimal128 pseudo-registers.  */
2425
    return builtin_type (gdbarch)->builtin_declong;
2426
}
2427
 
2428
/* Is REGNUM a member of REGGROUP?  */
2429
static int
2430
rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2431
                                   struct reggroup *group)
2432
{
2433
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2434
 
2435
  /* These are the only pseudo-registers we support.  */
2436
  gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2437
              || IS_DFP_PSEUDOREG (tdep, regnum));
2438
 
2439
  /* These are the e500 pseudo-registers.  */
2440
  if (IS_SPE_PSEUDOREG (tdep, regnum))
2441
    return group == all_reggroup || group == vector_reggroup;
2442
  else
2443
    /* Could only be the ppc decimal128 pseudo-registers.  */
2444
    return group == all_reggroup || group == float_reggroup;
2445
}
2446
 
2447
/* The register format for RS/6000 floating point registers is always
2448
   double, we need a conversion if the memory format is float.  */
2449
 
2450
static int
2451
rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2452
                           struct type *type)
2453
{
2454
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2455
 
2456
  return (tdep->ppc_fp0_regnum >= 0
2457
          && regnum >= tdep->ppc_fp0_regnum
2458
          && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2459
          && TYPE_CODE (type) == TYPE_CODE_FLT
2460
          && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2461
}
2462
 
2463
static void
2464
rs6000_register_to_value (struct frame_info *frame,
2465
                          int regnum,
2466
                          struct type *type,
2467
                          gdb_byte *to)
2468
{
2469
  gdb_byte from[MAX_REGISTER_SIZE];
2470
 
2471
  gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2472
 
2473
  get_frame_register (frame, regnum, from);
2474
  convert_typed_floating (from, builtin_type_double, to, type);
2475
}
2476
 
2477
static void
2478
rs6000_value_to_register (struct frame_info *frame,
2479
                          int regnum,
2480
                          struct type *type,
2481
                          const gdb_byte *from)
2482
{
2483
  gdb_byte to[MAX_REGISTER_SIZE];
2484
 
2485
  gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2486
 
2487
  convert_typed_floating (from, type, to, builtin_type_double);
2488
  put_frame_register (frame, regnum, to);
2489
}
2490
 
2491
/* Move SPE vector register values between a 64-bit buffer and the two
2492
   32-bit raw register halves in a regcache.  This function handles
2493
   both splitting a 64-bit value into two 32-bit halves, and joining
2494
   two halves into a whole 64-bit value, depending on the function
2495
   passed as the MOVE argument.
2496
 
2497
   EV_REG must be the number of an SPE evN vector register --- a
2498
   pseudoregister.  REGCACHE must be a regcache, and BUFFER must be a
2499
   64-bit buffer.
2500
 
2501
   Call MOVE once for each 32-bit half of that register, passing
2502
   REGCACHE, the number of the raw register corresponding to that
2503
   half, and the address of the appropriate half of BUFFER.
2504
 
2505
   For example, passing 'regcache_raw_read' as the MOVE function will
2506
   fill BUFFER with the full 64-bit contents of EV_REG.  Or, passing
2507
   'regcache_raw_supply' will supply the contents of BUFFER to the
2508
   appropriate pair of raw registers in REGCACHE.
2509
 
2510
   You may need to cast away some 'const' qualifiers when passing
2511
   MOVE, since this function can't tell at compile-time which of
2512
   REGCACHE or BUFFER is acting as the source of the data.  If C had
2513
   co-variant type qualifiers, ...  */
2514
static void
2515
e500_move_ev_register (void (*move) (struct regcache *regcache,
2516
                                     int regnum, gdb_byte *buf),
2517
                       struct regcache *regcache, int ev_reg,
2518
                       gdb_byte *buffer)
2519
{
2520
  struct gdbarch *arch = get_regcache_arch (regcache);
2521
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2522
  int reg_index;
2523
  gdb_byte *byte_buffer = buffer;
2524
 
2525
  gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2526
 
2527
  reg_index = ev_reg - tdep->ppc_ev0_regnum;
2528
 
2529
  if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2530
    {
2531
      move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2532
      move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2533
    }
2534
  else
2535
    {
2536
      move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2537
      move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2538
    }
2539
}
2540
 
2541
static void
2542
e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2543
                           int reg_nr, gdb_byte *buffer)
2544
{
2545
  e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2546
}
2547
 
2548
static void
2549
e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2550
                            int reg_nr, const gdb_byte *buffer)
2551
{
2552
  e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2553
                         regcache_raw_write,
2554
                         regcache, reg_nr, (gdb_byte *) buffer);
2555
}
2556
 
2557
/* Read method for PPC pseudo-registers. Currently this is handling the
2558
   16 decimal128 registers that map into 16 pairs of FP registers.  */
2559
static void
2560
ppc_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2561
                           int reg_nr, gdb_byte *buffer)
2562
{
2563
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2564
  int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2565
 
2566
  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2567
    {
2568
      /* Read two FP registers to form a whole dl register.  */
2569
      regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2570
                         2 * reg_index, buffer);
2571
      regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2572
                         2 * reg_index + 1, buffer + 8);
2573
    }
2574
  else
2575
    {
2576
      regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2577
                         2 * reg_index + 1, buffer + 8);
2578
      regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2579
                         2 * reg_index, buffer);
2580
    }
2581
}
2582
 
2583
/* Write method for PPC pseudo-registers. Currently this is handling the
2584
   16 decimal128 registers that map into 16 pairs of FP registers.  */
2585
static void
2586
ppc_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2587
                            int reg_nr, const gdb_byte *buffer)
2588
{
2589
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2590
  int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2591
 
2592
  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2593
    {
2594
      /* Write each half of the dl register into a separate
2595
      FP register.  */
2596
      regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2597
                          2 * reg_index, buffer);
2598
      regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2599
                          2 * reg_index + 1, buffer + 8);
2600
    }
2601
  else
2602
    {
2603
      regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2604
                          2 * reg_index + 1, buffer + 8);
2605
      regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2606
                          2 * reg_index, buffer);
2607
    }
2608
}
2609
 
2610
static void
2611
rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2612
                             int reg_nr, gdb_byte *buffer)
2613
{
2614
  struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2615
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2616
 
2617
  gdb_assert (regcache_arch == gdbarch);
2618
 
2619
  if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2620
    e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2621
  else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2622
    ppc_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2623
  else
2624
    internal_error (__FILE__, __LINE__,
2625
                    _("rs6000_pseudo_register_read: "
2626
                    "called on unexpected register '%s' (%d)"),
2627
                    gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2628
}
2629
 
2630
static void
2631
rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2632
                              struct regcache *regcache,
2633
                              int reg_nr, const gdb_byte *buffer)
2634
{
2635
  struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2636
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2637
 
2638
  gdb_assert (regcache_arch == gdbarch);
2639
 
2640
  if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2641
    e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2642
  else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2643
    ppc_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2644
  else
2645
    internal_error (__FILE__, __LINE__,
2646
                    _("rs6000_pseudo_register_write: "
2647
                    "called on unexpected register '%s' (%d)"),
2648
                    gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2649
}
2650
 
2651
/* Convert a DBX STABS register number to a GDB register number.  */
2652
static int
2653
rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2654
{
2655
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2656
 
2657
  if (0 <= num && num <= 31)
2658
    return tdep->ppc_gp0_regnum + num;
2659
  else if (32 <= num && num <= 63)
2660
    /* FIXME: jimb/2004-05-05: What should we do when the debug info
2661
       specifies registers the architecture doesn't have?  Our
2662
       callers don't check the value we return.  */
2663
    return tdep->ppc_fp0_regnum + (num - 32);
2664
  else if (77 <= num && num <= 108)
2665
    return tdep->ppc_vr0_regnum + (num - 77);
2666
  else if (1200 <= num && num < 1200 + 32)
2667
    return tdep->ppc_ev0_regnum + (num - 1200);
2668
  else
2669
    switch (num)
2670
      {
2671
      case 64:
2672
        return tdep->ppc_mq_regnum;
2673
      case 65:
2674
        return tdep->ppc_lr_regnum;
2675
      case 66:
2676
        return tdep->ppc_ctr_regnum;
2677
      case 76:
2678
        return tdep->ppc_xer_regnum;
2679
      case 109:
2680
        return tdep->ppc_vrsave_regnum;
2681
      case 110:
2682
        return tdep->ppc_vrsave_regnum - 1; /* vscr */
2683
      case 111:
2684
        return tdep->ppc_acc_regnum;
2685
      case 112:
2686
        return tdep->ppc_spefscr_regnum;
2687
      default:
2688
        return num;
2689
      }
2690
}
2691
 
2692
 
2693
/* Convert a Dwarf 2 register number to a GDB register number.  */
2694
static int
2695
rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
2696
{
2697
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2698
 
2699
  if (0 <= num && num <= 31)
2700
    return tdep->ppc_gp0_regnum + num;
2701
  else if (32 <= num && num <= 63)
2702
    /* FIXME: jimb/2004-05-05: What should we do when the debug info
2703
       specifies registers the architecture doesn't have?  Our
2704
       callers don't check the value we return.  */
2705
    return tdep->ppc_fp0_regnum + (num - 32);
2706
  else if (1124 <= num && num < 1124 + 32)
2707
    return tdep->ppc_vr0_regnum + (num - 1124);
2708
  else if (1200 <= num && num < 1200 + 32)
2709
    return tdep->ppc_ev0_regnum + (num - 1200);
2710
  else
2711
    switch (num)
2712
      {
2713
      case 64:
2714
        return tdep->ppc_cr_regnum;
2715
      case 67:
2716
        return tdep->ppc_vrsave_regnum - 1; /* vscr */
2717
      case 99:
2718
        return tdep->ppc_acc_regnum;
2719
      case 100:
2720
        return tdep->ppc_mq_regnum;
2721
      case 101:
2722
        return tdep->ppc_xer_regnum;
2723
      case 108:
2724
        return tdep->ppc_lr_regnum;
2725
      case 109:
2726
        return tdep->ppc_ctr_regnum;
2727
      case 356:
2728
        return tdep->ppc_vrsave_regnum;
2729
      case 612:
2730
        return tdep->ppc_spefscr_regnum;
2731
      default:
2732
        return num;
2733
      }
2734
}
2735
 
2736
/* Translate a .eh_frame register to DWARF register, or adjust a
2737
   .debug_frame register.  */
2738
 
2739
static int
2740
rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2741
{
2742
  /* GCC releases before 3.4 use GCC internal register numbering in
2743
     .debug_frame (and .debug_info, et cetera).  The numbering is
2744
     different from the standard SysV numbering for everything except
2745
     for GPRs and FPRs.  We can not detect this problem in most cases
2746
     - to get accurate debug info for variables living in lr, ctr, v0,
2747
     et cetera, use a newer version of GCC.  But we must detect
2748
     one important case - lr is in column 65 in .debug_frame output,
2749
     instead of 108.
2750
 
2751
     GCC 3.4, and the "hammer" branch, have a related problem.  They
2752
     record lr register saves in .debug_frame as 108, but still record
2753
     the return column as 65.  We fix that up too.
2754
 
2755
     We can do this because 65 is assigned to fpsr, and GCC never
2756
     generates debug info referring to it.  To add support for
2757
     handwritten debug info that restores fpsr, we would need to add a
2758
     producer version check to this.  */
2759
  if (!eh_frame_p)
2760
    {
2761
      if (num == 65)
2762
        return 108;
2763
      else
2764
        return num;
2765
    }
2766
 
2767
  /* .eh_frame is GCC specific.  For binary compatibility, it uses GCC
2768
     internal register numbering; translate that to the standard DWARF2
2769
     register numbering.  */
2770
  if (0 <= num && num <= 63)     /* r0-r31,fp0-fp31 */
2771
    return num;
2772
  else if (68 <= num && num <= 75) /* cr0-cr8 */
2773
    return num - 68 + 86;
2774
  else if (77 <= num && num <= 108) /* vr0-vr31 */
2775
    return num - 77 + 1124;
2776
  else
2777
    switch (num)
2778
      {
2779
      case 64: /* mq */
2780
        return 100;
2781
      case 65: /* lr */
2782
        return 108;
2783
      case 66: /* ctr */
2784
        return 109;
2785
      case 76: /* xer */
2786
        return 101;
2787
      case 109: /* vrsave */
2788
        return 356;
2789
      case 110: /* vscr */
2790
        return 67;
2791
      case 111: /* spe_acc */
2792
        return 99;
2793
      case 112: /* spefscr */
2794
        return 612;
2795
      default:
2796
        return num;
2797
      }
2798
}
2799
 
2800
/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2801
 
2802
   Usually a function pointer's representation is simply the address
2803
   of the function. On the RS/6000 however, a function pointer is
2804
   represented by a pointer to an OPD entry. This OPD entry contains
2805
   three words, the first word is the address of the function, the
2806
   second word is the TOC pointer (r2), and the third word is the
2807
   static chain value.  Throughout GDB it is currently assumed that a
2808
   function pointer contains the address of the function, which is not
2809
   easy to fix.  In addition, the conversion of a function address to
2810
   a function pointer would require allocation of an OPD entry in the
2811
   inferior's memory space, with all its drawbacks.  To be able to
2812
   call C++ virtual methods in the inferior (which are called via
2813
   function pointers), find_function_addr uses this function to get the
2814
   function address from a function pointer.  */
2815
 
2816
/* Return real function address if ADDR (a function pointer) is in the data
2817
   space and is therefore a special function pointer.  */
2818
 
2819
static CORE_ADDR
2820
rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2821
                                   CORE_ADDR addr,
2822
                                   struct target_ops *targ)
2823
{
2824
  struct obj_section *s;
2825
 
2826
  s = find_pc_section (addr);
2827
  if (s && s->the_bfd_section->flags & SEC_CODE)
2828
    return addr;
2829
 
2830
  /* ADDR is in the data space, so it's a special function pointer. */
2831
  return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize);
2832
}
2833
 
2834
 
2835
/* Handling the various POWER/PowerPC variants.  */
2836
 
2837
/* Information about a particular processor variant.  */
2838
 
2839
struct variant
2840
  {
2841
    /* Name of this variant.  */
2842
    char *name;
2843
 
2844
    /* English description of the variant.  */
2845
    char *description;
2846
 
2847
    /* bfd_arch_info.arch corresponding to variant.  */
2848
    enum bfd_architecture arch;
2849
 
2850
    /* bfd_arch_info.mach corresponding to variant.  */
2851
    unsigned long mach;
2852
 
2853
    /* Target description for this variant.  */
2854
    struct target_desc **tdesc;
2855
  };
2856
 
2857
static struct variant variants[] =
2858
{
2859
  {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2860
   bfd_mach_ppc, &tdesc_powerpc_32},
2861
  {"power", "POWER user-level", bfd_arch_rs6000,
2862
   bfd_mach_rs6k, &tdesc_rs6000},
2863
  {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2864
   bfd_mach_ppc_403, &tdesc_powerpc_403},
2865
  {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2866
   bfd_mach_ppc_601, &tdesc_powerpc_601},
2867
  {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2868
   bfd_mach_ppc_602, &tdesc_powerpc_602},
2869
  {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2870
   bfd_mach_ppc_603, &tdesc_powerpc_603},
2871
  {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2872
   604, &tdesc_powerpc_604},
2873
  {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2874
   bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
2875
  {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2876
   bfd_mach_ppc_505, &tdesc_powerpc_505},
2877
  {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2878
   bfd_mach_ppc_860, &tdesc_powerpc_860},
2879
  {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2880
   bfd_mach_ppc_750, &tdesc_powerpc_750},
2881
  {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2882
   bfd_mach_ppc_7400, &tdesc_powerpc_7400},
2883
  {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2884
   bfd_mach_ppc_e500, &tdesc_powerpc_e500},
2885
 
2886
  /* 64-bit */
2887
  {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2888
   bfd_mach_ppc64, &tdesc_powerpc_64},
2889
  {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2890
   bfd_mach_ppc_620, &tdesc_powerpc_64},
2891
  {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2892
   bfd_mach_ppc_630, &tdesc_powerpc_64},
2893
  {"a35", "PowerPC A35", bfd_arch_powerpc,
2894
   bfd_mach_ppc_a35, &tdesc_powerpc_64},
2895
  {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2896
   bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
2897
  {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2898
   bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
2899
 
2900
  /* FIXME: I haven't checked the register sets of the following.  */
2901
  {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2902
   bfd_mach_rs6k_rs1, &tdesc_rs6000},
2903
  {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2904
   bfd_mach_rs6k_rsc, &tdesc_rs6000},
2905
  {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2906
   bfd_mach_rs6k_rs2, &tdesc_rs6000},
2907
 
2908
  {0, 0, 0, 0, 0}
2909
};
2910
 
2911
/* Return the variant corresponding to architecture ARCH and machine number
2912
   MACH.  If no such variant exists, return null.  */
2913
 
2914
static const struct variant *
2915
find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2916
{
2917
  const struct variant *v;
2918
 
2919
  for (v = variants; v->name; v++)
2920
    if (arch == v->arch && mach == v->mach)
2921
      return v;
2922
 
2923
  return NULL;
2924
}
2925
 
2926
static int
2927
gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2928
{
2929
  if (!info->disassembler_options)
2930
    info->disassembler_options = "any";
2931
 
2932
  if (info->endian == BFD_ENDIAN_BIG)
2933
    return print_insn_big_powerpc (memaddr, info);
2934
  else
2935
    return print_insn_little_powerpc (memaddr, info);
2936
}
2937
 
2938
static CORE_ADDR
2939
rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2940
{
2941
  return frame_unwind_register_unsigned (next_frame,
2942
                                         gdbarch_pc_regnum (gdbarch));
2943
}
2944
 
2945
static struct frame_id
2946
rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2947
{
2948
  return frame_id_build (frame_unwind_register_unsigned
2949
                         (next_frame, gdbarch_sp_regnum (gdbarch)),
2950
                        frame_pc_unwind (next_frame));
2951
}
2952
 
2953
struct rs6000_frame_cache
2954
{
2955
  CORE_ADDR base;
2956
  CORE_ADDR initial_sp;
2957
  struct trad_frame_saved_reg *saved_regs;
2958
};
2959
 
2960
static struct rs6000_frame_cache *
2961
rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2962
{
2963
  struct rs6000_frame_cache *cache;
2964
  struct gdbarch *gdbarch = get_frame_arch (next_frame);
2965
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2966
  struct rs6000_framedata fdata;
2967
  int wordsize = tdep->wordsize;
2968
  CORE_ADDR func, pc;
2969
 
2970
  if ((*this_cache) != NULL)
2971
    return (*this_cache);
2972
  cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2973
  (*this_cache) = cache;
2974
  cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2975
 
2976
  func = frame_func_unwind (next_frame, NORMAL_FRAME);
2977
  pc = frame_pc_unwind (next_frame);
2978
  skip_prologue (gdbarch, func, pc, &fdata);
2979
 
2980
  /* Figure out the parent's stack pointer.  */
2981
 
2982
  /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2983
     address of the current frame.  Things might be easier if the
2984
     ->frame pointed to the outer-most address of the frame.  In
2985
     the mean time, the address of the prev frame is used as the
2986
     base address of this frame.  */
2987
  cache->base = frame_unwind_register_unsigned
2988
                (next_frame, gdbarch_sp_regnum (gdbarch));
2989
 
2990
  /* If the function appears to be frameless, check a couple of likely
2991
     indicators that we have simply failed to find the frame setup.
2992
     Two common cases of this are missing symbols (i.e.
2993
     frame_func_unwind returns the wrong address or 0), and assembly
2994
     stubs which have a fast exit path but set up a frame on the slow
2995
     path.
2996
 
2997
     If the LR appears to return to this function, then presume that
2998
     we have an ABI compliant frame that we failed to find.  */
2999
  if (fdata.frameless && fdata.lr_offset == 0)
3000
    {
3001
      CORE_ADDR saved_lr;
3002
      int make_frame = 0;
3003
 
3004
      saved_lr = frame_unwind_register_unsigned (next_frame,
3005
                                                 tdep->ppc_lr_regnum);
3006
      if (func == 0 && saved_lr == pc)
3007
        make_frame = 1;
3008
      else if (func != 0)
3009
        {
3010
          CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3011
          if (func == saved_func)
3012
            make_frame = 1;
3013
        }
3014
 
3015
      if (make_frame)
3016
        {
3017
          fdata.frameless = 0;
3018
          fdata.lr_offset = tdep->lr_frame_offset;
3019
        }
3020
    }
3021
 
3022
  if (!fdata.frameless)
3023
    /* Frameless really means stackless.  */
3024
    cache->base = read_memory_addr (cache->base, wordsize);
3025
 
3026
  trad_frame_set_value (cache->saved_regs,
3027
                        gdbarch_sp_regnum (gdbarch), cache->base);
3028
 
3029
  /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3030
     All fpr's from saved_fpr to fp31 are saved.  */
3031
 
3032
  if (fdata.saved_fpr >= 0)
3033
    {
3034
      int i;
3035
      CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3036
 
3037
      /* If skip_prologue says floating-point registers were saved,
3038
         but the current architecture has no floating-point registers,
3039
         then that's strange.  But we have no indices to even record
3040
         the addresses under, so we just ignore it.  */
3041
      if (ppc_floating_point_unit_p (gdbarch))
3042
        for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3043
          {
3044
            cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3045
            fpr_addr += 8;
3046
          }
3047
    }
3048
 
3049
  /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3050
     All gpr's from saved_gpr to gpr31 are saved.  */
3051
 
3052
  if (fdata.saved_gpr >= 0)
3053
    {
3054
      int i;
3055
      CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3056
      for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3057
        {
3058
          cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3059
          gpr_addr += wordsize;
3060
        }
3061
    }
3062
 
3063
  /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3064
     All vr's from saved_vr to vr31 are saved.  */
3065
  if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3066
    {
3067
      if (fdata.saved_vr >= 0)
3068
        {
3069
          int i;
3070
          CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3071
          for (i = fdata.saved_vr; i < 32; i++)
3072
            {
3073
              cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3074
              vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3075
            }
3076
        }
3077
    }
3078
 
3079
  /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3080
     All vr's from saved_ev to ev31 are saved. ????? */
3081
  if (tdep->ppc_ev0_regnum != -1)
3082
    {
3083
      if (fdata.saved_ev >= 0)
3084
        {
3085
          int i;
3086
          CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3087
          for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3088
            {
3089
              cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3090
              cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3091
              ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3092
            }
3093
        }
3094
    }
3095
 
3096
  /* If != 0, fdata.cr_offset is the offset from the frame that
3097
     holds the CR.  */
3098
  if (fdata.cr_offset != 0)
3099
    cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3100
 
3101
  /* If != 0, fdata.lr_offset is the offset from the frame that
3102
     holds the LR.  */
3103
  if (fdata.lr_offset != 0)
3104
    cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3105
  /* The PC is found in the link register.  */
3106
  cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3107
    cache->saved_regs[tdep->ppc_lr_regnum];
3108
 
3109
  /* If != 0, fdata.vrsave_offset is the offset from the frame that
3110
     holds the VRSAVE.  */
3111
  if (fdata.vrsave_offset != 0)
3112
    cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3113
 
3114
  if (fdata.alloca_reg < 0)
3115
    /* If no alloca register used, then fi->frame is the value of the
3116
       %sp for this frame, and it is good enough.  */
3117
    cache->initial_sp = frame_unwind_register_unsigned
3118
                        (next_frame, gdbarch_sp_regnum (gdbarch));
3119
  else
3120
    cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3121
                                                        fdata.alloca_reg);
3122
 
3123
  return cache;
3124
}
3125
 
3126
static void
3127
rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3128
                      struct frame_id *this_id)
3129
{
3130
  struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3131
                                                        this_cache);
3132
  (*this_id) = frame_id_build (info->base,
3133
                               frame_func_unwind (next_frame, NORMAL_FRAME));
3134
}
3135
 
3136
static void
3137
rs6000_frame_prev_register (struct frame_info *next_frame,
3138
                                 void **this_cache,
3139
                                 int regnum, int *optimizedp,
3140
                                 enum lval_type *lvalp, CORE_ADDR *addrp,
3141
                                 int *realnump, gdb_byte *valuep)
3142
{
3143
  struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3144
                                                        this_cache);
3145
  trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3146
                                optimizedp, lvalp, addrp, realnump, valuep);
3147
}
3148
 
3149
static const struct frame_unwind rs6000_frame_unwind =
3150
{
3151
  NORMAL_FRAME,
3152
  rs6000_frame_this_id,
3153
  rs6000_frame_prev_register
3154
};
3155
 
3156
static const struct frame_unwind *
3157
rs6000_frame_sniffer (struct frame_info *next_frame)
3158
{
3159
  return &rs6000_frame_unwind;
3160
}
3161
 
3162
 
3163
 
3164
static CORE_ADDR
3165
rs6000_frame_base_address (struct frame_info *next_frame,
3166
                                void **this_cache)
3167
{
3168
  struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3169
                                                        this_cache);
3170
  return info->initial_sp;
3171
}
3172
 
3173
static const struct frame_base rs6000_frame_base = {
3174
  &rs6000_frame_unwind,
3175
  rs6000_frame_base_address,
3176
  rs6000_frame_base_address,
3177
  rs6000_frame_base_address
3178
};
3179
 
3180
static const struct frame_base *
3181
rs6000_frame_base_sniffer (struct frame_info *next_frame)
3182
{
3183
  return &rs6000_frame_base;
3184
}
3185
 
3186
/* DWARF-2 frame support.  Used to handle the detection of
3187
  clobbered registers during function calls.  */
3188
 
3189
static void
3190
ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3191
                            struct dwarf2_frame_state_reg *reg,
3192
                            struct frame_info *next_frame)
3193
{
3194
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3195
 
3196
  /* PPC32 and PPC64 ABI's are the same regarding volatile and
3197
     non-volatile registers.  We will use the same code for both.  */
3198
 
3199
  /* Call-saved GP registers.  */
3200
  if ((regnum >= tdep->ppc_gp0_regnum + 14
3201
      && regnum <= tdep->ppc_gp0_regnum + 31)
3202
      || (regnum == tdep->ppc_gp0_regnum + 1))
3203
    reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3204
 
3205
  /* Call-clobbered GP registers.  */
3206
  if ((regnum >= tdep->ppc_gp0_regnum + 3
3207
      && regnum <= tdep->ppc_gp0_regnum + 12)
3208
      || (regnum == tdep->ppc_gp0_regnum))
3209
    reg->how = DWARF2_FRAME_REG_UNDEFINED;
3210
 
3211
  /* Deal with FP registers, if supported.  */
3212
  if (tdep->ppc_fp0_regnum >= 0)
3213
    {
3214
      /* Call-saved FP registers.  */
3215
      if ((regnum >= tdep->ppc_fp0_regnum + 14
3216
          && regnum <= tdep->ppc_fp0_regnum + 31))
3217
        reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3218
 
3219
      /* Call-clobbered FP registers.  */
3220
      if ((regnum >= tdep->ppc_fp0_regnum
3221
          && regnum <= tdep->ppc_fp0_regnum + 13))
3222
        reg->how = DWARF2_FRAME_REG_UNDEFINED;
3223
    }
3224
 
3225
  /* Deal with ALTIVEC registers, if supported.  */
3226
  if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3227
    {
3228
      /* Call-saved Altivec registers.  */
3229
      if ((regnum >= tdep->ppc_vr0_regnum + 20
3230
          && regnum <= tdep->ppc_vr0_regnum + 31)
3231
          || regnum == tdep->ppc_vrsave_regnum)
3232
        reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3233
 
3234
      /* Call-clobbered Altivec registers.  */
3235
      if ((regnum >= tdep->ppc_vr0_regnum
3236
          && regnum <= tdep->ppc_vr0_regnum + 19))
3237
        reg->how = DWARF2_FRAME_REG_UNDEFINED;
3238
    }
3239
 
3240
  /* Handle PC register and Stack Pointer correctly.  */
3241
  if (regnum == gdbarch_pc_regnum (gdbarch))
3242
    reg->how = DWARF2_FRAME_REG_RA;
3243
  else if (regnum == gdbarch_sp_regnum (gdbarch))
3244
    reg->how = DWARF2_FRAME_REG_CFA;
3245
}
3246
 
3247
 
3248
/* Initialize the current architecture based on INFO.  If possible, re-use an
3249
   architecture from ARCHES, which is a list of architectures already created
3250
   during this debugging session.
3251
 
3252
   Called e.g. at program startup, when reading a core file, and when reading
3253
   a binary file.  */
3254
 
3255
static struct gdbarch *
3256
rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3257
{
3258
  struct gdbarch *gdbarch;
3259
  struct gdbarch_tdep *tdep;
3260
  int wordsize, from_xcoff_exec, from_elf_exec;
3261
  enum bfd_architecture arch;
3262
  unsigned long mach;
3263
  bfd abfd;
3264
  int sysv_abi;
3265
  asection *sect;
3266
  enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3267
  int soft_float;
3268
  enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
3269
  int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0;
3270
  int tdesc_wordsize = -1;
3271
  const struct target_desc *tdesc = info.target_desc;
3272
  struct tdesc_arch_data *tdesc_data = NULL;
3273
  int num_pseudoregs = 0;
3274
 
3275
  from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3276
    bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3277
 
3278
  from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3279
    bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3280
 
3281
  sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3282
 
3283
  /* Check word size.  If INFO is from a binary file, infer it from
3284
     that, else choose a likely default.  */
3285
  if (from_xcoff_exec)
3286
    {
3287
      if (bfd_xcoff_is_xcoff64 (info.abfd))
3288
        wordsize = 8;
3289
      else
3290
        wordsize = 4;
3291
    }
3292
  else if (from_elf_exec)
3293
    {
3294
      if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3295
        wordsize = 8;
3296
      else
3297
        wordsize = 4;
3298
    }
3299
  else if (tdesc_has_registers (tdesc))
3300
    wordsize = -1;
3301
  else
3302
    {
3303
      if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3304
        wordsize = info.bfd_arch_info->bits_per_word /
3305
          info.bfd_arch_info->bits_per_byte;
3306
      else
3307
        wordsize = 4;
3308
    }
3309
 
3310
  if (!from_xcoff_exec)
3311
    {
3312
      arch = info.bfd_arch_info->arch;
3313
      mach = info.bfd_arch_info->mach;
3314
    }
3315
  else
3316
    {
3317
      arch = bfd_arch_powerpc;
3318
      bfd_default_set_arch_mach (&abfd, arch, 0);
3319
      info.bfd_arch_info = bfd_get_arch_info (&abfd);
3320
      mach = info.bfd_arch_info->mach;
3321
    }
3322
 
3323
  /* For e500 executables, the apuinfo section is of help here.  Such
3324
     section contains the identifier and revision number of each
3325
     Application-specific Processing Unit that is present on the
3326
     chip.  The content of the section is determined by the assembler
3327
     which looks at each instruction and determines which unit (and
3328
     which version of it) can execute it. In our case we just look for
3329
     the existance of the section.  */
3330
 
3331
  if (info.abfd)
3332
    {
3333
      sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3334
      if (sect)
3335
        {
3336
          arch = info.bfd_arch_info->arch;
3337
          mach = bfd_mach_ppc_e500;
3338
          bfd_default_set_arch_mach (&abfd, arch, mach);
3339
          info.bfd_arch_info = bfd_get_arch_info (&abfd);
3340
        }
3341
    }
3342
 
3343
  /* Find a default target description which describes our register
3344
     layout, if we do not already have one.  */
3345
  if (! tdesc_has_registers (tdesc))
3346
    {
3347
      const struct variant *v;
3348
 
3349
      /* Choose variant.  */
3350
      v = find_variant_by_arch (arch, mach);
3351
      if (!v)
3352
        return NULL;
3353
 
3354
      tdesc = *v->tdesc;
3355
    }
3356
 
3357
  gdb_assert (tdesc_has_registers (tdesc));
3358
 
3359
  /* Check any target description for validity.  */
3360
  if (tdesc_has_registers (tdesc))
3361
    {
3362
      static const char *const gprs[] = {
3363
        "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3364
        "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3365
        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3366
        "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3367
      };
3368
      static const char *const segment_regs[] = {
3369
        "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3370
        "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3371
      };
3372
      const struct tdesc_feature *feature;
3373
      int i, valid_p;
3374
      static const char *const msr_names[] = { "msr", "ps" };
3375
      static const char *const cr_names[] = { "cr", "cnd" };
3376
      static const char *const ctr_names[] = { "ctr", "cnt" };
3377
 
3378
      feature = tdesc_find_feature (tdesc,
3379
                                    "org.gnu.gdb.power.core");
3380
      if (feature == NULL)
3381
        return NULL;
3382
 
3383
      tdesc_data = tdesc_data_alloc ();
3384
 
3385
      valid_p = 1;
3386
      for (i = 0; i < ppc_num_gprs; i++)
3387
        valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3388
      valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3389
                                          "pc");
3390
      valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3391
                                          "lr");
3392
      valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3393
                                          "xer");
3394
 
3395
      /* Allow alternate names for these registers, to accomodate GDB's
3396
         historic naming.  */
3397
      valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3398
                                                  PPC_MSR_REGNUM, msr_names);
3399
      valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3400
                                                  PPC_CR_REGNUM, cr_names);
3401
      valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3402
                                                  PPC_CTR_REGNUM, ctr_names);
3403
 
3404
      if (!valid_p)
3405
        {
3406
          tdesc_data_cleanup (tdesc_data);
3407
          return NULL;
3408
        }
3409
 
3410
      have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3411
                                         "mq");
3412
 
3413
      tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3414
      if (wordsize == -1)
3415
        wordsize = tdesc_wordsize;
3416
 
3417
      feature = tdesc_find_feature (tdesc,
3418
                                    "org.gnu.gdb.power.fpu");
3419
      if (feature != NULL)
3420
        {
3421
          static const char *const fprs[] = {
3422
            "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3423
            "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3424
            "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3425
            "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3426
          };
3427
          valid_p = 1;
3428
          for (i = 0; i < ppc_num_fprs; i++)
3429
            valid_p &= tdesc_numbered_register (feature, tdesc_data,
3430
                                                PPC_F0_REGNUM + i, fprs[i]);
3431
          valid_p &= tdesc_numbered_register (feature, tdesc_data,
3432
                                              PPC_FPSCR_REGNUM, "fpscr");
3433
 
3434
          if (!valid_p)
3435
            {
3436
              tdesc_data_cleanup (tdesc_data);
3437
              return NULL;
3438
            }
3439
          have_fpu = 1;
3440
        }
3441
      else
3442
        have_fpu = 0;
3443
 
3444
      /* The DFP pseudo-registers will be available when there are floating
3445
         point registers.  */
3446
      have_dfp = have_fpu;
3447
 
3448
      feature = tdesc_find_feature (tdesc,
3449
                                    "org.gnu.gdb.power.altivec");
3450
      if (feature != NULL)
3451
        {
3452
          static const char *const vector_regs[] = {
3453
            "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3454
            "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3455
            "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3456
            "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3457
          };
3458
 
3459
          valid_p = 1;
3460
          for (i = 0; i < ppc_num_gprs; i++)
3461
            valid_p &= tdesc_numbered_register (feature, tdesc_data,
3462
                                                PPC_VR0_REGNUM + i,
3463
                                                vector_regs[i]);
3464
          valid_p &= tdesc_numbered_register (feature, tdesc_data,
3465
                                              PPC_VSCR_REGNUM, "vscr");
3466
          valid_p &= tdesc_numbered_register (feature, tdesc_data,
3467
                                              PPC_VRSAVE_REGNUM, "vrsave");
3468
 
3469
          if (have_spe || !valid_p)
3470
            {
3471
              tdesc_data_cleanup (tdesc_data);
3472
              return NULL;
3473
            }
3474
          have_altivec = 1;
3475
        }
3476
      else
3477
        have_altivec = 0;
3478
 
3479
      /* On machines supporting the SPE APU, the general-purpose registers
3480
         are 64 bits long.  There are SIMD vector instructions to treat them
3481
         as pairs of floats, but the rest of the instruction set treats them
3482
         as 32-bit registers, and only operates on their lower halves.
3483
 
3484
         In the GDB regcache, we treat their high and low halves as separate
3485
         registers.  The low halves we present as the general-purpose
3486
         registers, and then we have pseudo-registers that stitch together
3487
         the upper and lower halves and present them as pseudo-registers.
3488
 
3489
         Thus, the target description is expected to supply the upper
3490
         halves separately.  */
3491
 
3492
      feature = tdesc_find_feature (tdesc,
3493
                                    "org.gnu.gdb.power.spe");
3494
      if (feature != NULL)
3495
        {
3496
          static const char *const upper_spe[] = {
3497
            "ev0h", "ev1h", "ev2h", "ev3h",
3498
            "ev4h", "ev5h", "ev6h", "ev7h",
3499
            "ev8h", "ev9h", "ev10h", "ev11h",
3500
            "ev12h", "ev13h", "ev14h", "ev15h",
3501
            "ev16h", "ev17h", "ev18h", "ev19h",
3502
            "ev20h", "ev21h", "ev22h", "ev23h",
3503
            "ev24h", "ev25h", "ev26h", "ev27h",
3504
            "ev28h", "ev29h", "ev30h", "ev31h"
3505
          };
3506
 
3507
          valid_p = 1;
3508
          for (i = 0; i < ppc_num_gprs; i++)
3509
            valid_p &= tdesc_numbered_register (feature, tdesc_data,
3510
                                                PPC_SPE_UPPER_GP0_REGNUM + i,
3511
                                                upper_spe[i]);
3512
          valid_p &= tdesc_numbered_register (feature, tdesc_data,
3513
                                              PPC_SPE_ACC_REGNUM, "acc");
3514
          valid_p &= tdesc_numbered_register (feature, tdesc_data,
3515
                                              PPC_SPE_FSCR_REGNUM, "spefscr");
3516
 
3517
          if (have_mq || have_fpu || !valid_p)
3518
            {
3519
              tdesc_data_cleanup (tdesc_data);
3520
              return NULL;
3521
            }
3522
          have_spe = 1;
3523
        }
3524
      else
3525
        have_spe = 0;
3526
    }
3527
 
3528
  /* If we have a 64-bit binary on a 32-bit target, complain.  Also
3529
     complain for a 32-bit binary on a 64-bit target; we do not yet
3530
     support that.  For instance, the 32-bit ABI routines expect
3531
     32-bit GPRs.
3532
 
3533
     As long as there isn't an explicit target description, we'll
3534
     choose one based on the BFD architecture and get a word size
3535
     matching the binary (probably powerpc:common or
3536
     powerpc:common64).  So there is only trouble if a 64-bit target
3537
     supplies a 64-bit description while debugging a 32-bit
3538
     binary.  */
3539
  if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3540
    {
3541
      tdesc_data_cleanup (tdesc_data);
3542
      return NULL;
3543
    }
3544
 
3545
#ifdef HAVE_ELF
3546
  if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3547
    {
3548
      switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3549
                                        Tag_GNU_Power_ABI_FP))
3550
        {
3551
        case 1:
3552
          soft_float_flag = AUTO_BOOLEAN_FALSE;
3553
          break;
3554
        case 2:
3555
          soft_float_flag = AUTO_BOOLEAN_TRUE;
3556
          break;
3557
        default:
3558
          break;
3559
        }
3560
    }
3561
 
3562
  if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3563
    {
3564
      switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3565
                                        Tag_GNU_Power_ABI_Vector))
3566
        {
3567
        case 1:
3568
          vector_abi = POWERPC_VEC_GENERIC;
3569
          break;
3570
        case 2:
3571
          vector_abi = POWERPC_VEC_ALTIVEC;
3572
          break;
3573
        case 3:
3574
          vector_abi = POWERPC_VEC_SPE;
3575
          break;
3576
        default:
3577
          break;
3578
        }
3579
    }
3580
#endif
3581
 
3582
  if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3583
    soft_float = 1;
3584
  else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3585
    soft_float = 0;
3586
  else
3587
    soft_float = !have_fpu;
3588
 
3589
  /* If we have a hard float binary or setting but no floating point
3590
     registers, downgrade to soft float anyway.  We're still somewhat
3591
     useful in this scenario.  */
3592
  if (!soft_float && !have_fpu)
3593
    soft_float = 1;
3594
 
3595
  /* Similarly for vector registers.  */
3596
  if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3597
    vector_abi = POWERPC_VEC_GENERIC;
3598
 
3599
  if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3600
    vector_abi = POWERPC_VEC_GENERIC;
3601
 
3602
  if (vector_abi == POWERPC_VEC_AUTO)
3603
    {
3604
      if (have_altivec)
3605
        vector_abi = POWERPC_VEC_ALTIVEC;
3606
      else if (have_spe)
3607
        vector_abi = POWERPC_VEC_SPE;
3608
      else
3609
        vector_abi = POWERPC_VEC_GENERIC;
3610
    }
3611
 
3612
  /* Do not limit the vector ABI based on available hardware, since we
3613
     do not yet know what hardware we'll decide we have.  Yuck!  FIXME!  */
3614
 
3615
  /* Find a candidate among extant architectures.  */
3616
  for (arches = gdbarch_list_lookup_by_info (arches, &info);
3617
       arches != NULL;
3618
       arches = gdbarch_list_lookup_by_info (arches->next, &info))
3619
    {
3620
      /* Word size in the various PowerPC bfd_arch_info structs isn't
3621
         meaningful, because 64-bit CPUs can run in 32-bit mode.  So, perform
3622
         separate word size check.  */
3623
      tdep = gdbarch_tdep (arches->gdbarch);
3624
      if (tdep && tdep->soft_float != soft_float)
3625
        continue;
3626
      if (tdep && tdep->vector_abi != vector_abi)
3627
        continue;
3628
      if (tdep && tdep->wordsize == wordsize)
3629
        {
3630
          if (tdesc_data != NULL)
3631
            tdesc_data_cleanup (tdesc_data);
3632
          return arches->gdbarch;
3633
        }
3634
    }
3635
 
3636
  /* None found, create a new architecture from INFO, whose bfd_arch_info
3637
     validity depends on the source:
3638
       - executable             useless
3639
       - rs6000_host_arch()     good
3640
       - core file              good
3641
       - "set arch"             trust blindly
3642
       - GDB startup            useless but harmless */
3643
 
3644
  tdep = XCALLOC (1, struct gdbarch_tdep);
3645
  tdep->wordsize = wordsize;
3646
  tdep->soft_float = soft_float;
3647
  tdep->vector_abi = vector_abi;
3648
 
3649
  gdbarch = gdbarch_alloc (&info, tdep);
3650
 
3651
  tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3652
  tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3653
  tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3654
  tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3655
  tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3656
  tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3657
  tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3658
  tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3659
 
3660
  tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3661
  tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
3662
  tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3663
  tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3664
  tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3665
  tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3666
  tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3667
 
3668
  set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3669
  set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3670
  set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3671
  set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
3672
  set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3673
 
3674
  /* The XML specification for PowerPC sensibly calls the MSR "msr".
3675
     GDB traditionally called it "ps", though, so let GDB add an
3676
     alias.  */
3677
  set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3678
 
3679
  if (sysv_abi && wordsize == 8)
3680
    set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3681
  else if (sysv_abi && wordsize == 4)
3682
    set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3683
  else
3684
    set_gdbarch_return_value (gdbarch, rs6000_return_value);
3685
 
3686
  /* Set lr_frame_offset.  */
3687
  if (wordsize == 8)
3688
    tdep->lr_frame_offset = 16;
3689
  else if (sysv_abi)
3690
    tdep->lr_frame_offset = 4;
3691
  else
3692
    tdep->lr_frame_offset = 8;
3693
 
3694
  if (have_spe || have_dfp)
3695
    {
3696
      set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3697
      set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write);
3698
    }
3699
 
3700
  set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3701
 
3702
  /* Select instruction printer.  */
3703
  if (arch == bfd_arch_rs6000)
3704
    set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3705
  else
3706
    set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3707
 
3708
  set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
3709
 
3710
  if (have_spe)
3711
    num_pseudoregs += 32;
3712
  if (have_dfp)
3713
    num_pseudoregs += 16;
3714
 
3715
  set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
3716
 
3717
  set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3718
  set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3719
  set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3720
  set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3721
  set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3722
  set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3723
  set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3724
  if (sysv_abi)
3725
    set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3726
  else
3727
    set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3728
  set_gdbarch_char_signed (gdbarch, 0);
3729
 
3730
  set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3731
  if (sysv_abi && wordsize == 8)
3732
    /* PPC64 SYSV.  */
3733
    set_gdbarch_frame_red_zone_size (gdbarch, 288);
3734
  else if (!sysv_abi && wordsize == 4)
3735
    /* PowerOpen / AIX 32 bit.  The saved area or red zone consists of
3736
       19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3737
       Problem is, 220 isn't frame (16 byte) aligned.  Round it up to
3738
       224.  */
3739
    set_gdbarch_frame_red_zone_size (gdbarch, 224);
3740
 
3741
  set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3742
  set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3743
  set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3744
 
3745
  set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3746
  set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3747
 
3748
  if (sysv_abi && wordsize == 4)
3749
    set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3750
  else if (sysv_abi && wordsize == 8)
3751
    set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3752
  else
3753
    set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3754
 
3755
  set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3756
  set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3757
 
3758
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3759
  set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3760
 
3761
  /* The value of symbols of type N_SO and N_FUN maybe null when
3762
     it shouldn't be. */
3763
  set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3764
 
3765
  /* Handles single stepping of atomic sequences.  */
3766
  set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence);
3767
 
3768
  /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3769
     for the descriptor and ".FN" for the entry-point -- a user
3770
     specifying "break FN" will unexpectedly end up with a breakpoint
3771
     on the descriptor and not the function.  This architecture method
3772
     transforms any breakpoints on descriptors into breakpoints on the
3773
     corresponding entry point.  */
3774
  if (sysv_abi && wordsize == 8)
3775
    set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3776
 
3777
  /* Not sure on this. FIXMEmgo */
3778
  set_gdbarch_frame_args_skip (gdbarch, 8);
3779
 
3780
  if (!sysv_abi)
3781
    {
3782
      /* Handle RS/6000 function pointers (which are really function
3783
         descriptors).  */
3784
      set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3785
        rs6000_convert_from_func_ptr_addr);
3786
    }
3787
 
3788
  /* Helpers for function argument information.  */
3789
  set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3790
 
3791
  /* Trampoline.  */
3792
  set_gdbarch_in_solib_return_trampoline
3793
    (gdbarch, rs6000_in_solib_return_trampoline);
3794
  set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3795
 
3796
  /* Hook in the DWARF CFI frame unwinder.  */
3797
  frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3798
  dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3799
 
3800
  /* Frame handling.  */
3801
  dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3802
 
3803
  /* Hook in ABI-specific overrides, if they have been registered.  */
3804
  gdbarch_init_osabi (info, gdbarch);
3805
 
3806
  switch (info.osabi)
3807
    {
3808
    case GDB_OSABI_LINUX:
3809
    case GDB_OSABI_NETBSD_AOUT:
3810
    case GDB_OSABI_NETBSD_ELF:
3811
    case GDB_OSABI_UNKNOWN:
3812
      set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3813
      frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3814
      set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3815
      frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3816
      break;
3817
    default:
3818
      set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3819
 
3820
      set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3821
      frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3822
      set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3823
      frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3824
    }
3825
 
3826
  set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3827
  set_tdesc_pseudo_register_reggroup_p (gdbarch,
3828
                                        rs6000_pseudo_register_reggroup_p);
3829
  tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3830
 
3831
  /* Override the normal target description method to make the SPE upper
3832
     halves anonymous.  */
3833
  set_gdbarch_register_name (gdbarch, rs6000_register_name);
3834
 
3835
  /* Recording the numbering of pseudo registers.  */
3836
  tdep->ppc_ev0_regnum = have_spe ? gdbarch_num_regs (gdbarch) : -1;
3837
 
3838
  /* Set the register number for _Decimal128 pseudo-registers.  */
3839
  tdep->ppc_dl0_regnum = have_dfp? gdbarch_num_regs (gdbarch) : -1;
3840
 
3841
  if (have_dfp && have_spe)
3842
    /* Put the _Decimal128 pseudo-registers after the SPE registers.  */
3843
    tdep->ppc_dl0_regnum += 32;
3844
 
3845
  return gdbarch;
3846
}
3847
 
3848
static void
3849
rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3850
{
3851
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3852
 
3853
  if (tdep == NULL)
3854
    return;
3855
 
3856
  /* FIXME: Dump gdbarch_tdep.  */
3857
}
3858
 
3859
/* PowerPC-specific commands.  */
3860
 
3861
static void
3862
set_powerpc_command (char *args, int from_tty)
3863
{
3864
  printf_unfiltered (_("\
3865
\"set powerpc\" must be followed by an appropriate subcommand.\n"));
3866
  help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
3867
}
3868
 
3869
static void
3870
show_powerpc_command (char *args, int from_tty)
3871
{
3872
  cmd_show_list (showpowerpccmdlist, from_tty, "");
3873
}
3874
 
3875
static void
3876
powerpc_set_soft_float (char *args, int from_tty,
3877
                        struct cmd_list_element *c)
3878
{
3879
  struct gdbarch_info info;
3880
 
3881
  /* Update the architecture.  */
3882
  gdbarch_info_init (&info);
3883
  if (!gdbarch_update_p (info))
3884
    internal_error (__FILE__, __LINE__, "could not update architecture");
3885
}
3886
 
3887
static void
3888
powerpc_set_vector_abi (char *args, int from_tty,
3889
                        struct cmd_list_element *c)
3890
{
3891
  struct gdbarch_info info;
3892
  enum powerpc_vector_abi vector_abi;
3893
 
3894
  for (vector_abi = POWERPC_VEC_AUTO;
3895
       vector_abi != POWERPC_VEC_LAST;
3896
       vector_abi++)
3897
    if (strcmp (powerpc_vector_abi_string,
3898
                powerpc_vector_strings[vector_abi]) == 0)
3899
      {
3900
        powerpc_vector_abi_global = vector_abi;
3901
        break;
3902
      }
3903
 
3904
  if (vector_abi == POWERPC_VEC_LAST)
3905
    internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
3906
                    powerpc_vector_abi_string);
3907
 
3908
  /* Update the architecture.  */
3909
  gdbarch_info_init (&info);
3910
  if (!gdbarch_update_p (info))
3911
    internal_error (__FILE__, __LINE__, "could not update architecture");
3912
}
3913
 
3914
/* Initialization code.  */
3915
 
3916
extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3917
 
3918
void
3919
_initialize_rs6000_tdep (void)
3920
{
3921
  gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3922
  gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
3923
 
3924
  /* Initialize the standard target descriptions.  */
3925
  initialize_tdesc_powerpc_32 ();
3926
  initialize_tdesc_powerpc_403 ();
3927
  initialize_tdesc_powerpc_403gc ();
3928
  initialize_tdesc_powerpc_505 ();
3929
  initialize_tdesc_powerpc_601 ();
3930
  initialize_tdesc_powerpc_602 ();
3931
  initialize_tdesc_powerpc_603 ();
3932
  initialize_tdesc_powerpc_604 ();
3933
  initialize_tdesc_powerpc_64 ();
3934
  initialize_tdesc_powerpc_7400 ();
3935
  initialize_tdesc_powerpc_750 ();
3936
  initialize_tdesc_powerpc_860 ();
3937
  initialize_tdesc_powerpc_e500 ();
3938
  initialize_tdesc_rs6000 ();
3939
 
3940
  /* Add root prefix command for all "set powerpc"/"show powerpc"
3941
     commands.  */
3942
  add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
3943
                  _("Various PowerPC-specific commands."),
3944
                  &setpowerpccmdlist, "set powerpc ", 0, &setlist);
3945
 
3946
  add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
3947
                  _("Various PowerPC-specific commands."),
3948
                  &showpowerpccmdlist, "show powerpc ", 0, &showlist);
3949
 
3950
  /* Add a command to allow the user to force the ABI.  */
3951
  add_setshow_auto_boolean_cmd ("soft-float", class_support,
3952
                                &powerpc_soft_float_global,
3953
                                _("Set whether to use a soft-float ABI."),
3954
                                _("Show whether to use a soft-float ABI."),
3955
                                NULL,
3956
                                powerpc_set_soft_float, NULL,
3957
                                &setpowerpccmdlist, &showpowerpccmdlist);
3958
 
3959
  add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
3960
                        &powerpc_vector_abi_string,
3961
                        _("Set the vector ABI."),
3962
                        _("Show the vector ABI."),
3963
                        NULL, powerpc_set_vector_abi, NULL,
3964
                        &setpowerpccmdlist, &showpowerpccmdlist);
3965
}

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