OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [include/] [coff/] [arm.h] - Blame information for rev 840

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* ARM COFF support for BFD.
2
   Copyright 1998, 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
3
 
4
   This file is part of BFD, the Binary File Descriptor library.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software Foundation,
18
   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
19
 
20
#define COFFARM 1
21
 
22
#define L_LNNO_SIZE 2
23
#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
24
#include "coff/external.h"
25
 
26
/* Bits for f_flags:
27
        F_RELFLG        relocation info stripped from file
28
        F_EXEC          file is executable (no unresolved external references)
29
        F_LNNO          line numbers stripped from file
30
        F_LSYMS         local symbols stripped from file
31
        F_INTERWORK     file supports switching between ARM and Thumb instruction sets
32
        F_INTERWORK_SET the F_INTERWORK bit is valid
33
        F_APCS_FLOAT    code passes float arguments in float registers
34
        F_PIC           code is reentrant/position-independent
35
        F_AR32WR        file has byte ordering of an AR32WR machine (e.g. vax)
36
        F_APCS_26       file uses 26 bit ARM Procedure Calling Standard
37
        F_APCS_SET      the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised
38
        F_SOFT_FLOAT    code does not use floating point instructions.  */
39
 
40
#define F_RELFLG        (0x0001)
41
#define F_EXEC          (0x0002)
42
#define F_LNNO          (0x0004)
43
#define F_LSYMS         (0x0008)
44
#define F_INTERWORK     (0x0010)
45
#define F_INTERWORK_SET (0x0020)
46
#define F_APCS_FLOAT    (0x0040)
47
#undef  F_AR16WR
48
#define F_PIC           (0x0080)
49
#define F_AR32WR        (0x0100)
50
#define F_APCS_26       (0x0400)
51
#define F_APCS_SET      (0x0800)
52
#define F_SOFT_FLOAT    (0x2000)
53
#define F_VFP_FLOAT     (0x4000)
54
 
55
/* Bits stored in flags field of the internal_f structure */
56
 
57
#define F_INTERWORK     (0x0010)
58
#define F_APCS_FLOAT    (0x0040)
59
#define F_PIC           (0x0080)
60
#define F_APCS26        (0x1000)
61
#define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400)
62
#define F_ARM_2         (0x0400)
63
#define F_ARM_2a        (0x0800)
64
#define F_ARM_3         (0x0c00)
65
#define F_ARM_3M        (0x4000)
66
#define F_ARM_4         (0x4400)
67
#define F_ARM_4T        (0x4800)
68
#define F_ARM_5         (0x4c00)
69
 
70
/*
71
  ARMMAGIC ought to encoded the procesor type,
72
  but it is too late to change it now, instead
73
  the flags field of the internal_f structure
74
  is used as shown above.
75
 
76
  XXX - NC 5/6/97.  */
77
 
78
#define ARMMAGIC        0xa00  /* I just made this up */
79
 
80
#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC))
81
 
82
#define ARMPEMAGIC      0x1c0
83
#define THUMBPEMAGIC    0x1c2
84
 
85
#undef  ARMBADMAG
86
#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC) && ((x).f_magic != ARMPEMAGIC) && ((x).f_magic != THUMBPEMAGIC))
87
 
88
#define OMAGIC          0404    /* object files, eg as output */
89
#define ZMAGIC          0413    /* demand load format, eg normal ld output */
90
#define STMAGIC         0401    /* target shlib */
91
#define SHMAGIC         0443    /* host   shlib */
92
 
93
/* define some NT default values */
94
/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h */
95
#define NT_SECTION_ALIGNMENT 0x1000
96
#define NT_FILE_ALIGNMENT    0x200  
97
#define NT_DEF_RESERVE       0x100000
98
#define NT_DEF_COMMIT        0x1000
99
 
100
/* We use the .rdata section to hold read only data.  */
101
#define _LIT    ".rdata"
102
 
103
/********************** RELOCATION DIRECTIVES **********************/
104
#ifdef ARM_WINCE
105
struct external_reloc
106
{
107
  char r_vaddr[4];
108
  char r_symndx[4];
109
  char r_type[2];
110
};
111
 
112
#define RELOC struct external_reloc
113
#define RELSZ 10
114
 
115
#else
116
struct external_reloc
117
{
118
  char r_vaddr[4];
119
  char r_symndx[4];
120
  char r_type[2];
121
  char r_offset[4];
122
};
123
 
124
#define RELOC struct external_reloc
125
#define RELSZ 14
126
#endif
127
 
128
#define ARM_NOTE_SECTION ".note"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.