OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [opcodes/] [i386-opc.h] - Blame information for rev 827

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/* Declarations for Intel 80386 opcode table
2 225 jeremybenn
   Copyright 2007, 2008, 2009
3 24 jeremybenn
   Free Software Foundation, Inc.
4
 
5
   This file is part of the GNU opcodes library.
6
 
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
#include "opcode/i386.h"
23
#ifdef HAVE_LIMITS_H
24
#include <limits.h>
25
#endif
26
 
27
#ifndef CHAR_BIT
28
#define CHAR_BIT 8
29
#endif
30
 
31
/* Position of cpu flags bitfiled.  */
32
 
33
/* i186 or better required */
34
#define Cpu186          0
35
/* i286 or better required */
36
#define Cpu286          (Cpu186 + 1)
37
/* i386 or better required */
38
#define Cpu386          (Cpu286 + 1)
39
/* i486 or better required */
40
#define Cpu486          (Cpu386 + 1)
41
/* i585 or better required */
42
#define Cpu586          (Cpu486 + 1)
43
/* i686 or better required */
44
#define Cpu686          (Cpu586 + 1)
45 225 jeremybenn
/* CLFLUSH Instuction support required */
46
#define CpuClflush      (Cpu686 + 1)
47
/* SYSCALL Instuctions support required */
48
#define CpuSYSCALL      (CpuClflush + 1)
49
/* Floating point support required */
50
#define Cpu8087         (CpuSYSCALL + 1)
51
/* i287 support required */
52
#define Cpu287          (Cpu8087 + 1)
53
/* i387 support required */
54
#define Cpu387          (Cpu287 + 1)
55
/* i686 and floating point support required */
56
#define Cpu687          (Cpu387 + 1)
57
/* SSE3 and floating point support required */
58
#define CpuFISTTP               (Cpu687 + 1)
59 24 jeremybenn
/* MMX support required */
60 225 jeremybenn
#define CpuMMX          (CpuFISTTP + 1)
61 24 jeremybenn
/* SSE support required */
62
#define CpuSSE          (CpuMMX + 1)
63
/* SSE2 support required */
64
#define CpuSSE2         (CpuSSE + 1)
65
/* 3dnow! support required */
66
#define Cpu3dnow        (CpuSSE2 + 1)
67
/* 3dnow! Extensions support required */
68
#define Cpu3dnowA       (Cpu3dnow + 1)
69
/* SSE3 support required */
70
#define CpuSSE3         (Cpu3dnowA + 1)
71
/* VIA PadLock required */
72
#define CpuPadLock      (CpuSSE3 + 1)
73
/* AMD Secure Virtual Machine Ext-s required */
74
#define CpuSVME         (CpuPadLock + 1)
75
/* VMX Instructions required */
76
#define CpuVMX          (CpuSVME + 1)
77
/* SMX Instructions required */
78
#define CpuSMX          (CpuVMX + 1)
79
/* SSSE3 support required */
80
#define CpuSSSE3        (CpuSMX + 1)
81
/* SSE4a support required */
82
#define CpuSSE4a        (CpuSSSE3 + 1)
83
/* ABM New Instructions required */
84
#define CpuABM          (CpuSSE4a + 1)
85
/* SSE4.1 support required */
86
#define CpuSSE4_1       (CpuABM + 1)
87
/* SSE4.2 support required */
88
#define CpuSSE4_2       (CpuSSE4_1 + 1)
89 225 jeremybenn
/* AVX support required */
90
#define CpuAVX          (CpuSSE4_2 + 1)
91
/* Intel L1OM support required */
92
#define CpuL1OM         (CpuAVX + 1)
93 24 jeremybenn
/* Xsave/xrstor New Instuctions support required */
94 225 jeremybenn
#define CpuXsave        (CpuL1OM + 1)
95
/* AES support required */
96
#define CpuAES          (CpuXsave + 1)
97
/* PCLMUL support required */
98
#define CpuPCLMUL       (CpuAES + 1)
99
/* FMA support required */
100
#define CpuFMA          (CpuPCLMUL + 1)
101
/* FMA4 support required */
102
#define CpuFMA4         (CpuFMA + 1)
103
/* MOVBE Instuction support required */
104
#define CpuMovbe        (CpuFMA4 + 1)
105
/* EPT Instructions required */
106
#define CpuEPT          (CpuMovbe + 1)
107
/* RDTSCP Instuction support required */
108
#define CpuRdtscp       (CpuEPT + 1)
109 24 jeremybenn
/* 64bit support available, used by -march= in assembler.  */
110 225 jeremybenn
#define CpuLM           (CpuRdtscp + 1)
111 24 jeremybenn
/* 64bit support required  */
112
#define Cpu64           (CpuLM + 1)
113
/* Not supported in the 64bit mode  */
114
#define CpuNo64         (Cpu64 + 1)
115
/* The last bitfield in i386_cpu_flags.  */
116
#define CpuMax          CpuNo64
117
 
118
#define CpuNumOfUints \
119
  (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
120
#define CpuNumOfBits \
121
  (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
122
 
123
/* If you get a compiler error for zero width of the unused field,
124
   comment it out.  */
125
#define CpuUnused       (CpuMax + 1)
126
 
127
/* We can check if an instruction is available with array instead
128
   of bitfield. */
129
typedef union i386_cpu_flags
130
{
131
  struct
132
    {
133
      unsigned int cpui186:1;
134
      unsigned int cpui286:1;
135
      unsigned int cpui386:1;
136
      unsigned int cpui486:1;
137
      unsigned int cpui586:1;
138
      unsigned int cpui686:1;
139 225 jeremybenn
      unsigned int cpuclflush:1;
140
      unsigned int cpusyscall:1;
141
      unsigned int cpu8087:1;
142
      unsigned int cpu287:1;
143
      unsigned int cpu387:1;
144
      unsigned int cpu687:1;
145
      unsigned int cpufisttp:1;
146 24 jeremybenn
      unsigned int cpummx:1;
147
      unsigned int cpusse:1;
148
      unsigned int cpusse2:1;
149
      unsigned int cpua3dnow:1;
150
      unsigned int cpua3dnowa:1;
151
      unsigned int cpusse3:1;
152
      unsigned int cpupadlock:1;
153
      unsigned int cpusvme:1;
154
      unsigned int cpuvmx:1;
155
      unsigned int cpusmx:1;
156
      unsigned int cpussse3:1;
157
      unsigned int cpusse4a:1;
158
      unsigned int cpuabm:1;
159
      unsigned int cpusse4_1:1;
160
      unsigned int cpusse4_2:1;
161 225 jeremybenn
      unsigned int cpuavx:1;
162
      unsigned int cpul1om:1;
163 24 jeremybenn
      unsigned int cpuxsave:1;
164 225 jeremybenn
      unsigned int cpuaes:1;
165
      unsigned int cpupclmul:1;
166
      unsigned int cpufma:1;
167
      unsigned int cpufma4:1;
168
      unsigned int cpumovbe:1;
169
      unsigned int cpuept:1;
170
      unsigned int cpurdtscp:1;
171 24 jeremybenn
      unsigned int cpulm:1;
172
      unsigned int cpu64:1;
173
      unsigned int cpuno64:1;
174
#ifdef CpuUnused
175
      unsigned int unused:(CpuNumOfBits - CpuUnused);
176
#endif
177
    } bitfield;
178
  unsigned int array[CpuNumOfUints];
179
} i386_cpu_flags;
180
 
181
/* Position of opcode_modifier bits.  */
182
 
183
/* has direction bit. */
184
#define D                       0
185
/* set if operands can be words or dwords encoded the canonical way */
186
#define W                       (D + 1)
187 225 jeremybenn
/* Skip the current insn and use the next insn in i386-opc.tbl to swap
188
   operand in encoding.  */
189
#define S                       (W + 1)
190 24 jeremybenn
/* insn has a modrm byte. */
191 225 jeremybenn
#define Modrm                   (S + 1)
192 24 jeremybenn
/* register is in low 3 bits of opcode */
193
#define ShortForm               (Modrm + 1)
194
/* special case for jump insns.  */
195
#define Jump                    (ShortForm + 1)
196
/* call and jump */
197
#define JumpDword               (Jump + 1)
198
/* loop and jecxz */
199
#define JumpByte                (JumpDword + 1)
200
/* special case for intersegment leaps/calls */
201
#define JumpInterSegment        (JumpByte + 1)
202
/* FP insn memory format bit, sized by 0x4 */
203
#define FloatMF                 (JumpInterSegment + 1)
204
/* src/dest swap for floats. */
205
#define FloatR                  (FloatMF + 1)
206
/* has float insn direction bit. */
207
#define FloatD                  (FloatR + 1)
208
/* needs size prefix if in 32-bit mode */
209
#define Size16                  (FloatD + 1)
210
/* needs size prefix if in 16-bit mode */
211
#define Size32                  (Size16 + 1)
212
/* needs size prefix if in 64-bit mode */
213
#define Size64                  (Size32 + 1)
214
/* instruction ignores operand size prefix and in Intel mode ignores
215
   mnemonic size suffix check.  */
216
#define IgnoreSize              (Size64 + 1)
217
/* default insn size depends on mode */
218
#define DefaultSize             (IgnoreSize + 1)
219
/* b suffix on instruction illegal */
220
#define No_bSuf                 (DefaultSize + 1)
221
/* w suffix on instruction illegal */
222
#define No_wSuf                 (No_bSuf + 1)
223
/* l suffix on instruction illegal */
224
#define No_lSuf                 (No_wSuf + 1)
225
/* s suffix on instruction illegal */
226
#define No_sSuf                 (No_lSuf + 1)
227
/* q suffix on instruction illegal */
228
#define No_qSuf                 (No_sSuf + 1)
229
/* long double suffix on instruction illegal */
230
#define No_ldSuf                (No_qSuf + 1)
231
/* instruction needs FWAIT */
232
#define FWait                   (No_ldSuf + 1)
233
/* quick test for string instructions */
234
#define IsString                (FWait + 1)
235
/* fake an extra reg operand for clr, imul and special register
236
   processing for some instructions.  */
237
#define RegKludge               (IsString + 1)
238
/* The first operand must be xmm0 */
239
#define FirstXmm0               (RegKludge + 1)
240 225 jeremybenn
/* An implicit xmm0 as the first operand */
241
#define Implicit1stXmm0         (FirstXmm0 + 1)
242 24 jeremybenn
/* BYTE is OK in Intel syntax. */
243 225 jeremybenn
#define ByteOkIntel             (Implicit1stXmm0 + 1)
244 24 jeremybenn
/* Convert to DWORD */
245
#define ToDword                 (ByteOkIntel + 1)
246
/* Convert to QWORD */
247
#define ToQword                 (ToDword + 1)
248
/* Address prefix changes operand 0 */
249
#define AddrPrefixOp0           (ToQword + 1)
250
/* opcode is a prefix */
251
#define IsPrefix                (AddrPrefixOp0 + 1)
252
/* instruction has extension in 8 bit imm */
253
#define ImmExt                  (IsPrefix + 1)
254
/* instruction don't need Rex64 prefix.  */
255
#define NoRex64                 (ImmExt + 1)
256
/* instruction require Rex64 prefix.  */
257
#define Rex64                   (NoRex64 + 1)
258
/* deprecated fp insn, gets a warning */
259
#define Ugh                     (Rex64 + 1)
260 225 jeremybenn
/* insn has VEX prefix. */
261
#define Vex                     (Ugh + 1)
262
/* insn has 256bit VEX prefix. */
263
#define Vex256                  (Vex + 1)
264
/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
265
   We use VexNDS on insns with VEX DDS since the register-only source
266
   is the second source register.  */
267
#define VexNDS                  (Vex256 + 1)
268
/* insn has VEX NDD. Register destination is encoded in Vex
269
   prefix. */
270
#define VexNDD                  (VexNDS + 1)
271
/* insn has VEX W0. */
272
#define VexW0                   (VexNDD + 1)
273
/* insn has VEX W1. */
274
#define VexW1                   (VexW0 + 1)
275
/* insn has VEX 0x0F opcode prefix. */
276
#define Vex0F                   (VexW1 + 1)
277
/* insn has VEX 0x0F38 opcode prefix. */
278
#define Vex0F38                 (Vex0F + 1)
279
/* insn has VEX 0x0F3A opcode prefix. */
280
#define Vex0F3A                 (Vex0F38 + 1)
281
/* insn has VEX prefix with 3 soures. */
282
#define Vex3Sources             (Vex0F3A + 1)
283
/* instruction has VEX 8 bit imm */
284
#define VexImmExt               (Vex3Sources + 1)
285
/* SSE to AVX support required */
286
#define SSE2AVX                 (VexImmExt + 1)
287
/* No AVX equivalent */
288
#define NoAVX                   (SSE2AVX + 1)
289 24 jeremybenn
/* Compatible with old (<= 2.8.1) versions of gcc  */
290 225 jeremybenn
#define OldGcc                  (NoAVX + 1)
291 24 jeremybenn
/* AT&T mnemonic.  */
292
#define ATTMnemonic             (OldGcc + 1)
293
/* AT&T syntax.  */
294
#define ATTSyntax               (ATTMnemonic + 1)
295
/* Intel syntax.  */
296
#define IntelSyntax             (ATTSyntax + 1)
297
/* The last bitfield in i386_opcode_modifier.  */
298
#define Opcode_Modifier_Max     IntelSyntax
299
 
300
typedef struct i386_opcode_modifier
301
{
302
  unsigned int d:1;
303
  unsigned int w:1;
304 225 jeremybenn
  unsigned int s:1;
305 24 jeremybenn
  unsigned int modrm:1;
306
  unsigned int shortform:1;
307
  unsigned int jump:1;
308
  unsigned int jumpdword:1;
309
  unsigned int jumpbyte:1;
310
  unsigned int jumpintersegment:1;
311
  unsigned int floatmf:1;
312
  unsigned int floatr:1;
313
  unsigned int floatd:1;
314
  unsigned int size16:1;
315
  unsigned int size32:1;
316
  unsigned int size64:1;
317
  unsigned int ignoresize:1;
318
  unsigned int defaultsize:1;
319
  unsigned int no_bsuf:1;
320
  unsigned int no_wsuf:1;
321
  unsigned int no_lsuf:1;
322
  unsigned int no_ssuf:1;
323
  unsigned int no_qsuf:1;
324
  unsigned int no_ldsuf:1;
325
  unsigned int fwait:1;
326
  unsigned int isstring:1;
327
  unsigned int regkludge:1;
328
  unsigned int firstxmm0:1;
329 225 jeremybenn
  unsigned int implicit1stxmm0:1;
330 24 jeremybenn
  unsigned int byteokintel:1;
331
  unsigned int todword:1;
332
  unsigned int toqword:1;
333
  unsigned int addrprefixop0:1;
334
  unsigned int isprefix:1;
335
  unsigned int immext:1;
336
  unsigned int norex64:1;
337
  unsigned int rex64:1;
338
  unsigned int ugh:1;
339 225 jeremybenn
  unsigned int vex:1;
340
  unsigned int vex256:1;
341
  unsigned int vexnds:1;
342
  unsigned int vexndd:1;
343
  unsigned int vexw0:1;
344
  unsigned int vexw1:1;
345
  unsigned int vex0f:1;
346
  unsigned int vex0f38:1;
347
  unsigned int vex0f3a:1;
348
  unsigned int vex3sources:1;
349
  unsigned int veximmext:1;
350
  unsigned int sse2avx:1;
351
  unsigned int noavx:1;
352 24 jeremybenn
  unsigned int oldgcc:1;
353
  unsigned int attmnemonic:1;
354
  unsigned int attsyntax:1;
355
  unsigned int intelsyntax:1;
356
} i386_opcode_modifier;
357
 
358
/* Position of operand_type bits.  */
359
 
360
/* 8bit register */
361
#define Reg8                    0
362
/* 16bit register */
363
#define Reg16                   (Reg8 + 1)
364
/* 32bit register */
365
#define Reg32                   (Reg16 + 1)
366
/* 64bit register */
367
#define Reg64                   (Reg32 + 1)
368
/* Floating pointer stack register */
369
#define FloatReg                (Reg64 + 1)
370
/* MMX register */
371
#define RegMMX                  (FloatReg + 1)
372
/* SSE register */
373
#define RegXMM                  (RegMMX + 1)
374 225 jeremybenn
/* AVX registers */
375
#define RegYMM                  (RegXMM + 1)
376 24 jeremybenn
/* Control register */
377 225 jeremybenn
#define Control                 (RegYMM + 1)
378 24 jeremybenn
/* Debug register */
379
#define Debug                   (Control + 1)
380
/* Test register */
381
#define Test                    (Debug + 1)
382
/* 2 bit segment register */
383
#define SReg2                   (Test + 1)
384
/* 3 bit segment register */
385
#define SReg3                   (SReg2 + 1)
386
/* 1 bit immediate */
387
#define Imm1                    (SReg3 + 1)
388
/* 8 bit immediate */
389
#define Imm8                    (Imm1 + 1)
390
/* 8 bit immediate sign extended */
391
#define Imm8S                   (Imm8 + 1)
392
/* 16 bit immediate */
393
#define Imm16                   (Imm8S + 1)
394
/* 32 bit immediate */
395
#define Imm32                   (Imm16 + 1)
396
/* 32 bit immediate sign extended */
397
#define Imm32S                  (Imm32 + 1)
398
/* 64 bit immediate */
399
#define Imm64                   (Imm32S + 1)
400
/* 8bit/16bit/32bit displacements are used in different ways,
401
   depending on the instruction.  For jumps, they specify the
402
   size of the PC relative displacement, for instructions with
403
   memory operand, they specify the size of the offset relative
404
   to the base register, and for instructions with memory offset
405
   such as `mov 1234,%al' they specify the size of the offset
406
   relative to the segment base.  */
407
/* 8 bit displacement */
408
#define Disp8                   (Imm64 + 1)
409
/* 16 bit displacement */
410
#define Disp16                  (Disp8 + 1)
411
/* 32 bit displacement */
412
#define Disp32                  (Disp16 + 1)
413
/* 32 bit signed displacement */
414
#define Disp32S                 (Disp32 + 1)
415
/* 64 bit displacement */
416
#define Disp64                  (Disp32S + 1)
417
/* Accumulator %al/%ax/%eax/%rax */
418
#define Acc                     (Disp64 + 1)
419
/* Floating pointer top stack register %st(0) */
420
#define FloatAcc                (Acc + 1)
421
/* Register which can be used for base or index in memory operand.  */
422
#define BaseIndex               (FloatAcc + 1)
423
/* Register to hold in/out port addr = dx */
424
#define InOutPortReg            (BaseIndex + 1)
425
/* Register to hold shift count = cl */
426
#define ShiftCount              (InOutPortReg + 1)
427
/* Absolute address for jump.  */
428
#define JumpAbsolute            (ShiftCount + 1)
429
/* String insn operand with fixed es segment */
430
#define EsSeg                   (JumpAbsolute + 1)
431
/* RegMem is for instructions with a modrm byte where the register
432
   destination operand should be encoded in the mod and regmem fields.
433
   Normally, it will be encoded in the reg field. We add a RegMem
434
   flag to the destination register operand to indicate that it should
435
   be encoded in the regmem field.  */
436
#define RegMem                  (EsSeg + 1)
437
/* Memory.  */
438
#define Mem                     (RegMem + 1)
439
/* BYTE memory. */
440
#define Byte                    (Mem + 1)
441
/* WORD memory. 2 byte */
442
#define Word                    (Byte + 1)
443
/* DWORD memory. 4 byte */
444
#define Dword                   (Word + 1)
445
/* FWORD memory. 6 byte */
446
#define Fword                   (Dword + 1)
447
/* QWORD memory. 8 byte */
448
#define Qword                   (Fword + 1)
449
/* TBYTE memory. 10 byte */
450
#define Tbyte                   (Qword + 1)
451
/* XMMWORD memory. */
452
#define Xmmword                 (Tbyte + 1)
453 225 jeremybenn
/* YMMWORD memory. */
454
#define Ymmword                 (Xmmword + 1)
455 24 jeremybenn
/* Unspecified memory size.  */
456 225 jeremybenn
#define Unspecified             (Ymmword + 1)
457 24 jeremybenn
/* Any memory size.  */
458
#define Anysize                 (Unspecified  + 1)
459
 
460
/* The last bitfield in i386_operand_type.  */
461
#define OTMax                   Anysize
462
 
463
#define OTNumOfUints \
464
  (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
465
#define OTNumOfBits \
466
  (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
467
 
468
/* If you get a compiler error for zero width of the unused field,
469
   comment it out.  */
470
#define OTUnused                (OTMax + 1)
471
 
472
typedef union i386_operand_type
473
{
474
  struct
475
    {
476
      unsigned int reg8:1;
477
      unsigned int reg16:1;
478
      unsigned int reg32:1;
479
      unsigned int reg64:1;
480
      unsigned int floatreg:1;
481
      unsigned int regmmx:1;
482
      unsigned int regxmm:1;
483 225 jeremybenn
      unsigned int regymm:1;
484 24 jeremybenn
      unsigned int control:1;
485
      unsigned int debug:1;
486
      unsigned int test:1;
487
      unsigned int sreg2:1;
488
      unsigned int sreg3:1;
489
      unsigned int imm1:1;
490
      unsigned int imm8:1;
491
      unsigned int imm8s:1;
492
      unsigned int imm16:1;
493
      unsigned int imm32:1;
494
      unsigned int imm32s:1;
495
      unsigned int imm64:1;
496
      unsigned int disp8:1;
497
      unsigned int disp16:1;
498
      unsigned int disp32:1;
499
      unsigned int disp32s:1;
500
      unsigned int disp64:1;
501
      unsigned int acc:1;
502
      unsigned int floatacc:1;
503
      unsigned int baseindex:1;
504
      unsigned int inoutportreg:1;
505
      unsigned int shiftcount:1;
506
      unsigned int jumpabsolute:1;
507
      unsigned int esseg:1;
508
      unsigned int regmem:1;
509
      unsigned int mem:1;
510
      unsigned int byte:1;
511
      unsigned int word:1;
512
      unsigned int dword:1;
513
      unsigned int fword:1;
514
      unsigned int qword:1;
515
      unsigned int tbyte:1;
516
      unsigned int xmmword:1;
517 225 jeremybenn
      unsigned int ymmword:1;
518 24 jeremybenn
      unsigned int unspecified:1;
519
      unsigned int anysize:1;
520
#ifdef OTUnused
521
      unsigned int unused:(OTNumOfBits - OTUnused);
522
#endif
523
    } bitfield;
524
  unsigned int array[OTNumOfUints];
525
} i386_operand_type;
526
 
527 225 jeremybenn
typedef struct insn_template
528 24 jeremybenn
{
529
  /* instruction name sans width suffix ("mov" for movl insns) */
530
  char *name;
531
 
532
  /* how many operands */
533
  unsigned int operands;
534
 
535
  /* base_opcode is the fundamental opcode byte without optional
536
     prefix(es).  */
537
  unsigned int base_opcode;
538
#define Opcode_D        0x2 /* Direction bit:
539
                               set if Reg --> Regmem;
540
                               unset if Regmem --> Reg. */
541
#define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
542
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
543
 
544
  /* extension_opcode is the 3 bit extension for group <n> insns.
545
     This field is also used to store the 8-bit opcode suffix for the
546
     AMD 3DNow! instructions.
547
     If this template has no extension opcode (the usual case) use None
548 225 jeremybenn
     Instructions */
549 24 jeremybenn
  unsigned int extension_opcode;
550
#define None 0xffff             /* If no extension_opcode is possible.  */
551
 
552
  /* Opcode length.  */
553
  unsigned char opcode_length;
554
 
555
  /* cpu feature flags */
556
  i386_cpu_flags cpu_flags;
557
 
558
  /* the bits in opcode_modifier are used to generate the final opcode from
559
     the base_opcode.  These bits also are used to detect alternate forms of
560
     the same instruction */
561
  i386_opcode_modifier opcode_modifier;
562
 
563
  /* operand_types[i] describes the type of operand i.  This is made
564
     by OR'ing together all of the possible type masks.  (e.g.
565
     'operand_types[i] = Reg|Imm' specifies that operand i can be
566
     either a register or an immediate operand.  */
567
  i386_operand_type operand_types[MAX_OPERANDS];
568
}
569 225 jeremybenn
insn_template;
570 24 jeremybenn
 
571 225 jeremybenn
extern const insn_template i386_optab[];
572 24 jeremybenn
 
573
/* these are for register name --> number & type hash lookup */
574
typedef struct
575
{
576
  char *reg_name;
577
  i386_operand_type reg_type;
578
  unsigned char reg_flags;
579
#define RegRex      0x1  /* Extended register.  */
580
#define RegRex64    0x2  /* Extended 8 bit register.  */
581
  unsigned char reg_num;
582
#define RegRip  ((unsigned char ) ~0)
583
#define RegEip  (RegRip - 1)
584
/* EIZ and RIZ are fake index registers.  */
585
#define RegEiz  (RegEip - 1)
586
#define RegRiz  (RegEiz - 1)
587
/* FLAT is a fake segment register (Intel mode).  */
588
#define RegFlat     ((unsigned char) ~0)
589
  signed char dw2_regnum[2];
590
#define Dw2Inval (-1)
591
}
592
reg_entry;
593
 
594
/* Entries in i386_regtab.  */
595
#define REGNAM_AL 1
596
#define REGNAM_AX 25
597
#define REGNAM_EAX 41
598
 
599
extern const reg_entry i386_regtab[];
600
extern const unsigned int i386_regtab_size;
601
 
602
typedef struct
603
{
604
  char *seg_name;
605
  unsigned int seg_prefix;
606
}
607
seg_entry;
608
 
609
extern const seg_entry cs;
610
extern const seg_entry ds;
611
extern const seg_entry ss;
612
extern const seg_entry es;
613
extern const seg_entry fs;
614
extern const seg_entry gs;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.